1 /*
2 * Copyright (c) 2000, 2025, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/macroAssembler.inline.hpp"
27 #include "asm/assembler.hpp"
28 #include "c1/c1_CodeStubs.hpp"
29 #include "c1/c1_Compilation.hpp"
30 #include "c1/c1_LIRAssembler.hpp"
31 #include "c1/c1_MacroAssembler.hpp"
32 #include "c1/c1_Runtime1.hpp"
33 #include "c1/c1_ValueStack.hpp"
34 #include "ci/ciArrayKlass.hpp"
35 #include "ci/ciInstance.hpp"
36 #include "ci/ciUtilities.hpp"
37 #include "code/aotCodeCache.hpp"
38 #include "code/compiledIC.hpp"
39 #include "gc/shared/collectedHeap.hpp"
40 #include "gc/shared/gc_globals.hpp"
41 #include "nativeInst_aarch64.hpp"
42 #include "oops/objArrayKlass.hpp"
43 #include "runtime/frame.inline.hpp"
44 #include "runtime/sharedRuntime.hpp"
45 #include "runtime/stubRoutines.hpp"
46 #include "utilities/powerOfTwo.hpp"
47 #include "vmreg_aarch64.inline.hpp"
48
49
50 #ifndef PRODUCT
51 #define COMMENT(x) do { __ block_comment(x); } while (0)
52 #else
53 #define COMMENT(x)
54 #endif
55
56 NEEDS_CLEANUP // remove this definitions ?
57 const Register SYNC_header = r0; // synchronization header
58 const Register SHIFT_count = r0; // where count for shift operations must be
59
60 #define __ _masm->
61
62
63 static void select_different_registers(Register preserve,
64 Register extra,
65 Register &tmp1,
66 Register &tmp2) {
67 if (tmp1 == preserve) {
68 assert_different_registers(tmp1, tmp2, extra);
69 tmp1 = extra;
70 } else if (tmp2 == preserve) {
71 assert_different_registers(tmp1, tmp2, extra);
72 tmp2 = extra;
73 }
74 assert_different_registers(preserve, tmp1, tmp2);
75 }
76
77
78
79 static void select_different_registers(Register preserve,
80 Register extra,
81 Register &tmp1,
82 Register &tmp2,
83 Register &tmp3) {
84 if (tmp1 == preserve) {
85 assert_different_registers(tmp1, tmp2, tmp3, extra);
86 tmp1 = extra;
87 } else if (tmp2 == preserve) {
88 assert_different_registers(tmp1, tmp2, tmp3, extra);
89 tmp2 = extra;
90 } else if (tmp3 == preserve) {
91 assert_different_registers(tmp1, tmp2, tmp3, extra);
92 tmp3 = extra;
93 }
94 assert_different_registers(preserve, tmp1, tmp2, tmp3);
95 }
96
97
98 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
99
100
101 LIR_Opr LIR_Assembler::receiverOpr() {
102 return FrameMap::receiver_opr;
103 }
104
105 LIR_Opr LIR_Assembler::osrBufferPointer() {
106 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
107 }
108
109 //--------------fpu register translations-----------------------
110
111
112 address LIR_Assembler::float_constant(float f) {
113 address const_addr = __ float_constant(f);
114 if (const_addr == nullptr) {
115 bailout("const section overflow");
116 return __ code()->consts()->start();
117 } else {
118 return const_addr;
119 }
120 }
121
122
123 address LIR_Assembler::double_constant(double d) {
124 address const_addr = __ double_constant(d);
125 if (const_addr == nullptr) {
126 bailout("const section overflow");
127 return __ code()->consts()->start();
128 } else {
129 return const_addr;
130 }
131 }
132
133 address LIR_Assembler::int_constant(jlong n) {
134 address const_addr = __ long_constant(n);
135 if (const_addr == nullptr) {
136 bailout("const section overflow");
137 return __ code()->consts()->start();
138 } else {
139 return const_addr;
140 }
141 }
142
143 void LIR_Assembler::breakpoint() { Unimplemented(); }
144
145 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
146
147 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
148
149 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
150 //-------------------------------------------
151
152 static Register as_reg(LIR_Opr op) {
153 return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
154 }
155
156 static jlong as_long(LIR_Opr data) {
157 jlong result;
158 switch (data->type()) {
159 case T_INT:
160 result = (data->as_jint());
161 break;
162 case T_LONG:
163 result = (data->as_jlong());
164 break;
165 default:
166 ShouldNotReachHere();
167 result = 0; // unreachable
168 }
169 return result;
170 }
171
172 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
173 Register base = addr->base()->as_pointer_register();
174 LIR_Opr opr = addr->index();
175 if (opr->is_cpu_register()) {
176 Register index;
177 if (opr->is_single_cpu())
178 index = opr->as_register();
179 else
180 index = opr->as_register_lo();
181 assert(addr->disp() == 0, "must be");
182 switch(opr->type()) {
183 case T_INT:
184 return Address(base, index, Address::sxtw(addr->scale()));
185 case T_LONG:
186 return Address(base, index, Address::lsl(addr->scale()));
187 default:
188 ShouldNotReachHere();
189 }
190 } else {
191 assert(addr->scale() == 0,
192 "expected for immediate operand, was: %d", addr->scale());
193 ptrdiff_t offset = ptrdiff_t(addr->disp());
194 // NOTE: Does not handle any 16 byte vector access.
195 const uint type_size = type2aelembytes(addr->type(), true);
196 return __ legitimize_address(Address(base, offset), type_size, tmp);
197 }
198 return Address();
199 }
200
201 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
202 ShouldNotReachHere();
203 return Address();
204 }
205
206 Address LIR_Assembler::as_Address(LIR_Address* addr) {
207 return as_Address(addr, rscratch1);
208 }
209
210 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
211 return as_Address(addr, rscratch1); // Ouch
212 // FIXME: This needs to be much more clever. See x86.
213 }
214
215 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is
216 // not encodable as a base + (immediate) offset, generate an explicit address
217 // calculation to hold the address in a temporary register.
218 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
219 precond(size == 4 || size == 8);
220 Address addr = frame_map()->address_for_slot(index, adjust);
221 precond(addr.getMode() == Address::base_plus_offset);
222 precond(addr.base() == sp);
223 precond(addr.offset() > 0);
224 uint mask = size - 1;
225 assert((addr.offset() & mask) == 0, "scaled offsets only");
226 return __ legitimize_address(addr, size, tmp);
227 }
228
229 void LIR_Assembler::osr_entry() {
230 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
231 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
232 ValueStack* entry_state = osr_entry->state();
233 int number_of_locks = entry_state->locks_size();
234
235 // we jump here if osr happens with the interpreter
236 // state set up to continue at the beginning of the
237 // loop that triggered osr - in particular, we have
238 // the following registers setup:
239 //
240 // r2: osr buffer
241 //
242
243 // build frame
244 ciMethod* m = compilation()->method();
245 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
246
247 // OSR buffer is
248 //
249 // locals[nlocals-1..0]
250 // monitors[0..number_of_locks]
251 //
252 // locals is a direct copy of the interpreter frame so in the osr buffer
253 // so first slot in the local array is the last local from the interpreter
254 // and last slot is local[0] (receiver) from the interpreter
255 //
256 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
257 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
258 // in the interpreter frame (the method lock if a sync method)
259
260 // Initialize monitors in the compiled activation.
261 // r2: pointer to osr buffer
262 //
263 // All other registers are dead at this point and the locals will be
264 // copied into place by code emitted in the IR.
265
266 Register OSR_buf = osrBufferPointer()->as_pointer_register();
267 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
268 int monitor_offset = BytesPerWord * method()->max_locals() +
269 (2 * BytesPerWord) * (number_of_locks - 1);
270 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
271 // the OSR buffer using 2 word entries: first the lock and then
272 // the oop.
273 for (int i = 0; i < number_of_locks; i++) {
274 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
275 #ifdef ASSERT
276 // verify the interpreter's monitor has a non-null object
277 {
278 Label L;
279 __ ldr(rscratch1, __ form_address(rscratch1, OSR_buf, slot_offset + 1*BytesPerWord, 0));
280 __ cbnz(rscratch1, L);
281 __ stop("locked object is null");
282 __ bind(L);
283 }
284 #endif
285 __ ldr(r19, __ form_address(rscratch1, OSR_buf, slot_offset, 0));
286 __ ldr(r20, __ form_address(rscratch1, OSR_buf, slot_offset + BytesPerWord, 0));
287 __ str(r19, frame_map()->address_for_monitor_lock(i));
288 __ str(r20, frame_map()->address_for_monitor_object(i));
289 }
290 }
291 }
292
293
294 // inline cache check; done before the frame is built.
295 int LIR_Assembler::check_icache() {
296 return __ ic_check(CodeEntryAlignment);
297 }
298
299 void LIR_Assembler::clinit_barrier(ciMethod* method) {
300 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
301 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
302
303 Label L_skip_barrier;
304
305 __ mov_metadata(rscratch2, method->holder()->constant_encoding());
306 __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/);
307 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
308 __ bind(L_skip_barrier);
309 }
310
311 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
312 if (o == nullptr) {
313 __ mov(reg, zr);
314 } else {
315 __ movoop(reg, o);
316 }
317 }
318
319 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
320 address target = nullptr;
321 relocInfo::relocType reloc_type = relocInfo::none;
322
323 switch (patching_id(info)) {
324 case PatchingStub::access_field_id:
325 target = Runtime1::entry_for(C1StubId::access_field_patching_id);
326 reloc_type = relocInfo::section_word_type;
327 break;
328 case PatchingStub::load_klass_id:
329 target = Runtime1::entry_for(C1StubId::load_klass_patching_id);
330 reloc_type = relocInfo::metadata_type;
331 break;
332 case PatchingStub::load_mirror_id:
333 target = Runtime1::entry_for(C1StubId::load_mirror_patching_id);
334 reloc_type = relocInfo::oop_type;
335 break;
336 case PatchingStub::load_appendix_id:
337 target = Runtime1::entry_for(C1StubId::load_appendix_patching_id);
338 reloc_type = relocInfo::oop_type;
339 break;
340 default: ShouldNotReachHere();
341 }
342
343 __ far_call(RuntimeAddress(target));
344 add_call_info_here(info);
345 }
346
347 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
348 deoptimize_trap(info);
349 }
350
351
352 // This specifies the rsp decrement needed to build the frame
353 int LIR_Assembler::initial_frame_size_in_bytes() const {
354 // if rounding, must let FrameMap know!
355
356 return in_bytes(frame_map()->framesize_in_bytes());
357 }
358
359
360 int LIR_Assembler::emit_exception_handler() {
361 // generate code for exception handler
362 address handler_base = __ start_a_stub(exception_handler_size());
363 if (handler_base == nullptr) {
364 // not enough space left for the handler
365 bailout("exception handler overflow");
366 return -1;
367 }
368
369 int offset = code_offset();
370
371 // the exception oop and pc are in r0, and r3
372 // no other registers need to be preserved, so invalidate them
373 __ invalidate_registers(false, true, true, false, true, true);
374
375 // check that there is really an exception
376 __ verify_not_null_oop(r0);
377
378 // search an exception handler (r0: exception oop, r3: throwing pc)
379 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::handle_exception_from_callee_id)));
380 __ should_not_reach_here();
381 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
382 __ end_a_stub();
383
384 return offset;
385 }
386
387
388 // Emit the code to remove the frame from the stack in the exception
389 // unwind path.
390 int LIR_Assembler::emit_unwind_handler() {
391 #ifndef PRODUCT
392 if (CommentedAssembly) {
393 _masm->block_comment("Unwind handler");
394 }
395 #endif
396
397 int offset = code_offset();
398
399 // Fetch the exception from TLS and clear out exception related thread state
400 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
401 __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
402 __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
403
404 __ bind(_unwind_handler_entry);
405 __ verify_not_null_oop(r0);
406 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
407 __ mov(r19, r0); // Preserve the exception
408 }
409
410 // Perform needed unlocking
411 MonitorExitStub* stub = nullptr;
412 if (method()->is_synchronized()) {
413 monitor_address(0, FrameMap::r0_opr);
414 stub = new MonitorExitStub(FrameMap::r0_opr, true, 0);
415 if (LockingMode == LM_MONITOR) {
416 __ b(*stub->entry());
417 } else {
418 __ unlock_object(r5, r4, r0, r6, *stub->entry());
419 }
420 __ bind(*stub->continuation());
421 }
422
423 if (compilation()->env()->dtrace_method_probes()) {
424 __ mov(c_rarg0, rthread);
425 __ mov_metadata(c_rarg1, method()->constant_encoding());
426 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
427 }
428
429 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
430 __ mov(r0, r19); // Restore the exception
431 }
432
433 // remove the activation and dispatch to the unwind handler
434 __ block_comment("remove_frame and dispatch to the unwind handler");
435 __ remove_frame(initial_frame_size_in_bytes());
436 __ far_jump(RuntimeAddress(Runtime1::entry_for(C1StubId::unwind_exception_id)));
437
438 // Emit the slow path assembly
439 if (stub != nullptr) {
440 stub->emit_code(this);
441 }
442
443 return offset;
444 }
445
446
447 int LIR_Assembler::emit_deopt_handler() {
448 // generate code for exception handler
449 address handler_base = __ start_a_stub(deopt_handler_size());
450 if (handler_base == nullptr) {
451 // not enough space left for the handler
452 bailout("deopt handler overflow");
453 return -1;
454 }
455
456 int offset = code_offset();
457
458 __ adr(lr, pc());
459 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
460 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
461 __ end_a_stub();
462
463 return offset;
464 }
465
466 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
467 _masm->code_section()->relocate(adr, relocInfo::poll_type);
468 int pc_offset = code_offset();
469 flush_debug_info(pc_offset);
470 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
471 if (info->exception_handlers() != nullptr) {
472 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
473 }
474 }
475
476 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
477 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
478
479 // Pop the stack before the safepoint code
480 __ remove_frame(initial_frame_size_in_bytes());
481
482 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
483 __ reserved_stack_check();
484 }
485
486 code_stub->set_safepoint_offset(__ offset());
487 __ relocate(relocInfo::poll_return_type);
488 __ safepoint_poll(*code_stub->entry(), true /* at_return */, false /* acquire */, true /* in_nmethod */);
489 __ ret(lr);
490 }
491
492 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
493 guarantee(info != nullptr, "Shouldn't be null");
494 __ get_polling_page(rscratch1, relocInfo::poll_type);
495 add_debug_info_for_branch(info); // This isn't just debug info:
496 // it's the oop map
497 __ read_polling_page(rscratch1, relocInfo::poll_type);
498 return __ offset();
499 }
500
501
502 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
503 if (from_reg == r31_sp)
504 from_reg = sp;
505 if (to_reg == r31_sp)
506 to_reg = sp;
507 __ mov(to_reg, from_reg);
508 }
509
510 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
511
512
513 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
514 assert(src->is_constant(), "should not call otherwise");
515 assert(dest->is_register(), "should not call otherwise");
516 LIR_Const* c = src->as_constant_ptr();
517
518 switch (c->type()) {
519 case T_INT: {
520 assert(patch_code == lir_patch_none, "no patching handled here");
521 __ movw(dest->as_register(), c->as_jint());
522 break;
523 }
524
525 case T_ADDRESS: {
526 assert(patch_code == lir_patch_none, "no patching handled here");
527 __ mov(dest->as_register(), c->as_jint());
528 break;
529 }
530
531 case T_LONG: {
532 assert(patch_code == lir_patch_none, "no patching handled here");
533 if (AOTCodeCache::is_on_for_write()) {
534 // AOT code needs relocation info for card table base
535 address b = c->as_pointer();
536 if (is_card_table_address(b)) {
537 __ lea(dest->as_register_lo(), ExternalAddress(b));
538 break;
539 }
540 #if INCLUDE_CDS
541 if (AOTRuntimeConstants::contains(b)) {
542 __ load_aotrc_address(dest->as_register_lo(), b);
543 break;
544 }
545 #endif
546 }
547 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
548 break;
549 }
550
551 case T_OBJECT: {
552 if (patch_code == lir_patch_none) {
553 jobject2reg(c->as_jobject(), dest->as_register());
554 } else {
555 jobject2reg_with_patching(dest->as_register(), info);
556 }
557 break;
558 }
559
560 case T_METADATA: {
561 if (patch_code != lir_patch_none) {
562 klass2reg_with_patching(dest->as_register(), info);
563 } else {
564 __ mov_metadata(dest->as_register(), c->as_metadata());
565 }
566 break;
567 }
568
569 case T_FLOAT: {
570 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
571 __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
572 } else {
573 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
574 __ ldrs(dest->as_float_reg(), Address(rscratch1));
575 }
576 break;
577 }
578
579 case T_DOUBLE: {
580 if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
581 __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
582 } else {
583 __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
584 __ ldrd(dest->as_double_reg(), Address(rscratch1));
585 }
586 break;
587 }
588
589 default:
590 ShouldNotReachHere();
591 }
592 }
593
594 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
595 LIR_Const* c = src->as_constant_ptr();
596 switch (c->type()) {
597 case T_OBJECT:
598 {
599 if (! c->as_jobject())
600 __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
601 else {
602 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
603 reg2stack(FrameMap::rscratch1_opr, dest, c->type());
604 }
605 }
606 break;
607 case T_ADDRESS:
608 {
609 const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, nullptr);
610 reg2stack(FrameMap::rscratch1_opr, dest, c->type());
611 }
612 case T_INT:
613 case T_FLOAT:
614 {
615 Register reg = zr;
616 if (c->as_jint_bits() == 0)
617 __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
618 else {
619 __ movw(rscratch1, c->as_jint_bits());
620 __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
621 }
622 }
623 break;
624 case T_LONG:
625 case T_DOUBLE:
626 {
627 Register reg = zr;
628 if (c->as_jlong_bits() == 0)
629 __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
630 lo_word_offset_in_bytes));
631 else {
632 __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
633 __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
634 lo_word_offset_in_bytes));
635 }
636 }
637 break;
638 default:
639 ShouldNotReachHere();
640 }
641 }
642
643 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
644 assert(src->is_constant(), "should not call otherwise");
645 LIR_Const* c = src->as_constant_ptr();
646 LIR_Address* to_addr = dest->as_address_ptr();
647
648 void (Assembler::* insn)(Register Rt, const Address &adr);
649
650 switch (type) {
651 case T_ADDRESS:
652 assert(c->as_jint() == 0, "should be");
653 insn = &Assembler::str;
654 break;
655 case T_LONG:
656 assert(c->as_jlong() == 0, "should be");
657 insn = &Assembler::str;
658 break;
659 case T_INT:
660 assert(c->as_jint() == 0, "should be");
661 insn = &Assembler::strw;
662 break;
663 case T_OBJECT:
664 case T_ARRAY:
665 assert(c->as_jobject() == nullptr, "should be");
666 if (UseCompressedOops && !wide) {
667 insn = &Assembler::strw;
668 } else {
669 insn = &Assembler::str;
670 }
671 break;
672 case T_CHAR:
673 case T_SHORT:
674 assert(c->as_jint() == 0, "should be");
675 insn = &Assembler::strh;
676 break;
677 case T_BOOLEAN:
678 case T_BYTE:
679 assert(c->as_jint() == 0, "should be");
680 insn = &Assembler::strb;
681 break;
682 default:
683 ShouldNotReachHere();
684 insn = &Assembler::str; // unreachable
685 }
686
687 if (info) add_debug_info_for_null_check_here(info);
688 (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
689 }
690
691 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
692 assert(src->is_register(), "should not call otherwise");
693 assert(dest->is_register(), "should not call otherwise");
694
695 // move between cpu-registers
696 if (dest->is_single_cpu()) {
697 if (src->type() == T_LONG) {
698 // Can do LONG -> OBJECT
699 move_regs(src->as_register_lo(), dest->as_register());
700 return;
701 }
702 assert(src->is_single_cpu(), "must match");
703 if (src->type() == T_OBJECT) {
704 __ verify_oop(src->as_register());
705 }
706 move_regs(src->as_register(), dest->as_register());
707
708 } else if (dest->is_double_cpu()) {
709 if (is_reference_type(src->type())) {
710 // Surprising to me but we can see move of a long to t_object
711 __ verify_oop(src->as_register());
712 move_regs(src->as_register(), dest->as_register_lo());
713 return;
714 }
715 assert(src->is_double_cpu(), "must match");
716 Register f_lo = src->as_register_lo();
717 Register f_hi = src->as_register_hi();
718 Register t_lo = dest->as_register_lo();
719 Register t_hi = dest->as_register_hi();
720 assert(f_hi == f_lo, "must be same");
721 assert(t_hi == t_lo, "must be same");
722 move_regs(f_lo, t_lo);
723
724 } else if (dest->is_single_fpu()) {
725 __ fmovs(dest->as_float_reg(), src->as_float_reg());
726
727 } else if (dest->is_double_fpu()) {
728 __ fmovd(dest->as_double_reg(), src->as_double_reg());
729
730 } else {
731 ShouldNotReachHere();
732 }
733 }
734
735 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
736 precond(src->is_register() && dest->is_stack());
737
738 uint const c_sz32 = sizeof(uint32_t);
739 uint const c_sz64 = sizeof(uint64_t);
740
741 if (src->is_single_cpu()) {
742 int index = dest->single_stack_ix();
743 if (is_reference_type(type)) {
744 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
745 __ verify_oop(src->as_register());
746 } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
747 __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
748 } else {
749 __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
750 }
751
752 } else if (src->is_double_cpu()) {
753 int index = dest->double_stack_ix();
754 Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
755 __ str(src->as_register_lo(), dest_addr_LO);
756
757 } else if (src->is_single_fpu()) {
758 int index = dest->single_stack_ix();
759 __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
760
761 } else if (src->is_double_fpu()) {
762 int index = dest->double_stack_ix();
763 __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
764
765 } else {
766 ShouldNotReachHere();
767 }
768 }
769
770
771 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
772 LIR_Address* to_addr = dest->as_address_ptr();
773 PatchingStub* patch = nullptr;
774 Register compressed_src = rscratch1;
775
776 if (patch_code != lir_patch_none) {
777 deoptimize_trap(info);
778 return;
779 }
780
781 if (is_reference_type(type)) {
782 __ verify_oop(src->as_register());
783
784 if (UseCompressedOops && !wide) {
785 __ encode_heap_oop(compressed_src, src->as_register());
786 } else {
787 compressed_src = src->as_register();
788 }
789 }
790
791 int null_check_here = code_offset();
792 switch (type) {
793 case T_FLOAT: {
794 __ strs(src->as_float_reg(), as_Address(to_addr));
795 break;
796 }
797
798 case T_DOUBLE: {
799 __ strd(src->as_double_reg(), as_Address(to_addr));
800 break;
801 }
802
803 case T_ARRAY: // fall through
804 case T_OBJECT: // fall through
805 if (UseCompressedOops && !wide) {
806 __ strw(compressed_src, as_Address(to_addr, rscratch2));
807 } else {
808 __ str(compressed_src, as_Address(to_addr));
809 }
810 break;
811 case T_METADATA:
812 // We get here to store a method pointer to the stack to pass to
813 // a dtrace runtime call. This can't work on 64 bit with
814 // compressed klass ptrs: T_METADATA can be a compressed klass
815 // ptr or a 64 bit method pointer.
816 ShouldNotReachHere();
817 __ str(src->as_register(), as_Address(to_addr));
818 break;
819 case T_ADDRESS:
820 __ str(src->as_register(), as_Address(to_addr));
821 break;
822 case T_INT:
823 __ strw(src->as_register(), as_Address(to_addr));
824 break;
825
826 case T_LONG: {
827 __ str(src->as_register_lo(), as_Address_lo(to_addr));
828 break;
829 }
830
831 case T_BYTE: // fall through
832 case T_BOOLEAN: {
833 __ strb(src->as_register(), as_Address(to_addr));
834 break;
835 }
836
837 case T_CHAR: // fall through
838 case T_SHORT:
839 __ strh(src->as_register(), as_Address(to_addr));
840 break;
841
842 default:
843 ShouldNotReachHere();
844 }
845 if (info != nullptr) {
846 add_debug_info_for_null_check(null_check_here, info);
847 }
848 }
849
850
851 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
852 precond(src->is_stack() && dest->is_register());
853
854 uint const c_sz32 = sizeof(uint32_t);
855 uint const c_sz64 = sizeof(uint64_t);
856
857 if (dest->is_single_cpu()) {
858 int index = src->single_stack_ix();
859 if (is_reference_type(type)) {
860 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
861 __ verify_oop(dest->as_register());
862 } else if (type == T_METADATA || type == T_ADDRESS) {
863 __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
864 } else {
865 __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
866 }
867
868 } else if (dest->is_double_cpu()) {
869 int index = src->double_stack_ix();
870 Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
871 __ ldr(dest->as_register_lo(), src_addr_LO);
872
873 } else if (dest->is_single_fpu()) {
874 int index = src->single_stack_ix();
875 __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
876
877 } else if (dest->is_double_fpu()) {
878 int index = src->double_stack_ix();
879 __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
880
881 } else {
882 ShouldNotReachHere();
883 }
884 }
885
886
887 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
888 address target = nullptr;
889 relocInfo::relocType reloc_type = relocInfo::none;
890
891 switch (patching_id(info)) {
892 case PatchingStub::access_field_id:
893 target = Runtime1::entry_for(C1StubId::access_field_patching_id);
894 reloc_type = relocInfo::section_word_type;
895 break;
896 case PatchingStub::load_klass_id:
897 target = Runtime1::entry_for(C1StubId::load_klass_patching_id);
898 reloc_type = relocInfo::metadata_type;
899 break;
900 case PatchingStub::load_mirror_id:
901 target = Runtime1::entry_for(C1StubId::load_mirror_patching_id);
902 reloc_type = relocInfo::oop_type;
903 break;
904 case PatchingStub::load_appendix_id:
905 target = Runtime1::entry_for(C1StubId::load_appendix_patching_id);
906 reloc_type = relocInfo::oop_type;
907 break;
908 default: ShouldNotReachHere();
909 }
910
911 __ far_call(RuntimeAddress(target));
912 add_call_info_here(info);
913 }
914
915 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
916
917 LIR_Opr temp;
918 if (type == T_LONG || type == T_DOUBLE)
919 temp = FrameMap::rscratch1_long_opr;
920 else
921 temp = FrameMap::rscratch1_opr;
922
923 stack2reg(src, temp, src->type());
924 reg2stack(temp, dest, dest->type());
925 }
926
927
928 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
929 LIR_Address* addr = src->as_address_ptr();
930 LIR_Address* from_addr = src->as_address_ptr();
931
932 if (addr->base()->type() == T_OBJECT) {
933 __ verify_oop(addr->base()->as_pointer_register());
934 }
935
936 if (patch_code != lir_patch_none) {
937 deoptimize_trap(info);
938 return;
939 }
940
941 if (info != nullptr) {
942 add_debug_info_for_null_check_here(info);
943 }
944 int null_check_here = code_offset();
945 switch (type) {
946 case T_FLOAT: {
947 __ ldrs(dest->as_float_reg(), as_Address(from_addr));
948 break;
949 }
950
951 case T_DOUBLE: {
952 __ ldrd(dest->as_double_reg(), as_Address(from_addr));
953 break;
954 }
955
956 case T_ARRAY: // fall through
957 case T_OBJECT: // fall through
958 if (UseCompressedOops && !wide) {
959 __ ldrw(dest->as_register(), as_Address(from_addr));
960 } else {
961 __ ldr(dest->as_register(), as_Address(from_addr));
962 }
963 break;
964 case T_METADATA:
965 // We get here to store a method pointer to the stack to pass to
966 // a dtrace runtime call. This can't work on 64 bit with
967 // compressed klass ptrs: T_METADATA can be a compressed klass
968 // ptr or a 64 bit method pointer.
969 ShouldNotReachHere();
970 __ ldr(dest->as_register(), as_Address(from_addr));
971 break;
972 case T_ADDRESS:
973 __ ldr(dest->as_register(), as_Address(from_addr));
974 break;
975 case T_INT:
976 __ ldrw(dest->as_register(), as_Address(from_addr));
977 break;
978
979 case T_LONG: {
980 __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
981 break;
982 }
983
984 case T_BYTE:
985 __ ldrsb(dest->as_register(), as_Address(from_addr));
986 break;
987 case T_BOOLEAN: {
988 __ ldrb(dest->as_register(), as_Address(from_addr));
989 break;
990 }
991
992 case T_CHAR:
993 __ ldrh(dest->as_register(), as_Address(from_addr));
994 break;
995 case T_SHORT:
996 __ ldrsh(dest->as_register(), as_Address(from_addr));
997 break;
998
999 default:
1000 ShouldNotReachHere();
1001 }
1002
1003 if (is_reference_type(type)) {
1004 if (UseCompressedOops && !wide) {
1005 __ decode_heap_oop(dest->as_register());
1006 }
1007
1008 __ verify_oop(dest->as_register());
1009 }
1010 }
1011
1012
1013 int LIR_Assembler::array_element_size(BasicType type) const {
1014 int elem_size = type2aelembytes(type);
1015 return exact_log2(elem_size);
1016 }
1017
1018
1019 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1020 switch (op->code()) {
1021 case lir_idiv:
1022 case lir_irem:
1023 arithmetic_idiv(op->code(),
1024 op->in_opr1(),
1025 op->in_opr2(),
1026 op->in_opr3(),
1027 op->result_opr(),
1028 op->info());
1029 break;
1030 case lir_fmad:
1031 __ fmaddd(op->result_opr()->as_double_reg(),
1032 op->in_opr1()->as_double_reg(),
1033 op->in_opr2()->as_double_reg(),
1034 op->in_opr3()->as_double_reg());
1035 break;
1036 case lir_fmaf:
1037 __ fmadds(op->result_opr()->as_float_reg(),
1038 op->in_opr1()->as_float_reg(),
1039 op->in_opr2()->as_float_reg(),
1040 op->in_opr3()->as_float_reg());
1041 break;
1042 default: ShouldNotReachHere(); break;
1043 }
1044 }
1045
1046 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1047 #ifdef ASSERT
1048 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1049 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1050 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1051 #endif
1052
1053 if (op->cond() == lir_cond_always) {
1054 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1055 __ b(*(op->label()));
1056 } else {
1057 Assembler::Condition acond;
1058 if (op->code() == lir_cond_float_branch) {
1059 bool is_unordered = (op->ublock() == op->block());
1060 // Assembler::EQ does not permit unordered branches, so we add
1061 // another branch here. Likewise, Assembler::NE does not permit
1062 // ordered branches.
1063 if ((is_unordered && op->cond() == lir_cond_equal)
1064 || (!is_unordered && op->cond() == lir_cond_notEqual))
1065 __ br(Assembler::VS, *(op->ublock()->label()));
1066 switch(op->cond()) {
1067 case lir_cond_equal: acond = Assembler::EQ; break;
1068 case lir_cond_notEqual: acond = Assembler::NE; break;
1069 case lir_cond_less: acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1070 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1071 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1072 case lir_cond_greater: acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1073 default: ShouldNotReachHere();
1074 acond = Assembler::EQ; // unreachable
1075 }
1076 } else {
1077 switch (op->cond()) {
1078 case lir_cond_equal: acond = Assembler::EQ; break;
1079 case lir_cond_notEqual: acond = Assembler::NE; break;
1080 case lir_cond_less: acond = Assembler::LT; break;
1081 case lir_cond_lessEqual: acond = Assembler::LE; break;
1082 case lir_cond_greaterEqual: acond = Assembler::GE; break;
1083 case lir_cond_greater: acond = Assembler::GT; break;
1084 case lir_cond_belowEqual: acond = Assembler::LS; break;
1085 case lir_cond_aboveEqual: acond = Assembler::HS; break;
1086 default: ShouldNotReachHere();
1087 acond = Assembler::EQ; // unreachable
1088 }
1089 }
1090 __ br(acond,*(op->label()));
1091 }
1092 }
1093
1094
1095
1096 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1097 LIR_Opr src = op->in_opr();
1098 LIR_Opr dest = op->result_opr();
1099
1100 switch (op->bytecode()) {
1101 case Bytecodes::_i2f:
1102 {
1103 __ scvtfws(dest->as_float_reg(), src->as_register());
1104 break;
1105 }
1106 case Bytecodes::_i2d:
1107 {
1108 __ scvtfwd(dest->as_double_reg(), src->as_register());
1109 break;
1110 }
1111 case Bytecodes::_l2d:
1112 {
1113 __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1114 break;
1115 }
1116 case Bytecodes::_l2f:
1117 {
1118 __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1119 break;
1120 }
1121 case Bytecodes::_f2d:
1122 {
1123 __ fcvts(dest->as_double_reg(), src->as_float_reg());
1124 break;
1125 }
1126 case Bytecodes::_d2f:
1127 {
1128 __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1129 break;
1130 }
1131 case Bytecodes::_i2c:
1132 {
1133 __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1134 break;
1135 }
1136 case Bytecodes::_i2l:
1137 {
1138 __ sxtw(dest->as_register_lo(), src->as_register());
1139 break;
1140 }
1141 case Bytecodes::_i2s:
1142 {
1143 __ sxth(dest->as_register(), src->as_register());
1144 break;
1145 }
1146 case Bytecodes::_i2b:
1147 {
1148 __ sxtb(dest->as_register(), src->as_register());
1149 break;
1150 }
1151 case Bytecodes::_l2i:
1152 {
1153 _masm->block_comment("FIXME: This could be a no-op");
1154 __ uxtw(dest->as_register(), src->as_register_lo());
1155 break;
1156 }
1157 case Bytecodes::_d2l:
1158 {
1159 __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1160 break;
1161 }
1162 case Bytecodes::_f2i:
1163 {
1164 __ fcvtzsw(dest->as_register(), src->as_float_reg());
1165 break;
1166 }
1167 case Bytecodes::_f2l:
1168 {
1169 __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1170 break;
1171 }
1172 case Bytecodes::_d2i:
1173 {
1174 __ fcvtzdw(dest->as_register(), src->as_double_reg());
1175 break;
1176 }
1177 default: ShouldNotReachHere();
1178 }
1179 }
1180
1181 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1182 if (op->init_check()) {
1183 __ lea(rscratch1, Address(op->klass()->as_register(), InstanceKlass::init_state_offset()));
1184 __ ldarb(rscratch1, rscratch1);
1185 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1186 add_debug_info_for_null_check_here(op->stub()->info());
1187 __ br(Assembler::NE, *op->stub()->entry());
1188 }
1189 __ allocate_object(op->obj()->as_register(),
1190 op->tmp1()->as_register(),
1191 op->tmp2()->as_register(),
1192 op->header_size(),
1193 op->object_size(),
1194 op->klass()->as_register(),
1195 *op->stub()->entry());
1196 __ bind(*op->stub()->continuation());
1197 }
1198
1199 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1200 Register len = op->len()->as_register();
1201 __ uxtw(len, len);
1202
1203 if (UseSlowPath ||
1204 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1205 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1206 __ b(*op->stub()->entry());
1207 } else {
1208 Register tmp1 = op->tmp1()->as_register();
1209 Register tmp2 = op->tmp2()->as_register();
1210 Register tmp3 = op->tmp3()->as_register();
1211 if (len == tmp1) {
1212 tmp1 = tmp3;
1213 } else if (len == tmp2) {
1214 tmp2 = tmp3;
1215 } else if (len == tmp3) {
1216 // everything is ok
1217 } else {
1218 __ mov(tmp3, len);
1219 }
1220 __ allocate_array(op->obj()->as_register(),
1221 len,
1222 tmp1,
1223 tmp2,
1224 arrayOopDesc::base_offset_in_bytes(op->type()),
1225 array_element_size(op->type()),
1226 op->klass()->as_register(),
1227 *op->stub()->entry(),
1228 op->zero_array());
1229 }
1230 __ bind(*op->stub()->continuation());
1231 }
1232
1233 void LIR_Assembler::type_profile_helper(Register mdo,
1234 ciMethodData *md, ciProfileData *data,
1235 Register recv, Label* update_done) {
1236
1237 // Given a profile data offset, generate an Address which points to
1238 // the corresponding slot in mdo->data().
1239 // Clobbers rscratch2.
1240 auto slot_at = [=](ByteSize offset) -> Address {
1241 return __ form_address(rscratch2, mdo,
1242 md->byte_offset_of_slot(data, offset),
1243 LogBytesPerWord);
1244 };
1245
1246 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1247 Label next_test;
1248 // See if the receiver is receiver[n].
1249 __ ldr(rscratch1, slot_at(ReceiverTypeData::receiver_offset(i)));
1250 __ cmp(recv, rscratch1);
1251 __ br(Assembler::NE, next_test);
1252 __ addptr(slot_at(ReceiverTypeData::receiver_count_offset(i)),
1253 DataLayout::counter_increment);
1254 __ b(*update_done);
1255 __ bind(next_test);
1256 }
1257
1258 // Didn't find receiver; find next empty slot and fill it in
1259 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1260 Label next_test;
1261 Address recv_addr(slot_at(ReceiverTypeData::receiver_offset(i)));
1262 __ ldr(rscratch1, recv_addr);
1263 __ cbnz(rscratch1, next_test);
1264 __ str(recv, recv_addr);
1265 __ mov(rscratch1, DataLayout::counter_increment);
1266 __ str(rscratch1, slot_at(ReceiverTypeData::receiver_count_offset(i)));
1267 __ b(*update_done);
1268 __ bind(next_test);
1269 }
1270 }
1271
1272 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1273 // we always need a stub for the failure case.
1274 CodeStub* stub = op->stub();
1275 Register obj = op->object()->as_register();
1276 Register k_RInfo = op->tmp1()->as_register();
1277 Register klass_RInfo = op->tmp2()->as_register();
1278 Register dst = op->result_opr()->as_register();
1279 ciKlass* k = op->klass();
1280 Register Rtmp1 = noreg;
1281
1282 // check if it needs to be profiled
1283 ciMethodData* md;
1284 ciProfileData* data;
1285
1286 const bool should_profile = op->should_profile();
1287
1288 if (should_profile) {
1289 ciMethod* method = op->profiled_method();
1290 assert(method != nullptr, "Should have method");
1291 int bci = op->profiled_bci();
1292 md = method->method_data_or_null();
1293 assert(md != nullptr, "Sanity");
1294 data = md->bci_to_data(bci);
1295 assert(data != nullptr, "need data for type check");
1296 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1297 }
1298 Label* success_target = success;
1299 Label* failure_target = failure;
1300
1301 if (obj == k_RInfo) {
1302 k_RInfo = dst;
1303 } else if (obj == klass_RInfo) {
1304 klass_RInfo = dst;
1305 }
1306 if (k->is_loaded() && !UseCompressedClassPointers) {
1307 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1308 } else {
1309 Rtmp1 = op->tmp3()->as_register();
1310 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1311 }
1312
1313 assert_different_registers(obj, k_RInfo, klass_RInfo);
1314
1315 if (should_profile) {
1316 Register mdo = klass_RInfo;
1317 __ mov_metadata(mdo, md->constant_encoding());
1318 Label not_null;
1319 __ cbnz(obj, not_null);
1320 // Object is null; update MDO and exit
1321 Address data_addr
1322 = __ form_address(rscratch2, mdo,
1323 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1324 0);
1325 __ ldrb(rscratch1, data_addr);
1326 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1327 __ strb(rscratch1, data_addr);
1328 __ b(*obj_is_null);
1329 __ bind(not_null);
1330
1331 Label update_done;
1332 Register recv = k_RInfo;
1333 __ load_klass(recv, obj);
1334 type_profile_helper(mdo, md, data, recv, &update_done);
1335 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1336 __ addptr(counter_addr, DataLayout::counter_increment);
1337
1338 __ bind(update_done);
1339 } else {
1340 __ cbz(obj, *obj_is_null);
1341 }
1342
1343 if (!k->is_loaded()) {
1344 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1345 } else {
1346 __ mov_metadata(k_RInfo, k->constant_encoding());
1347 }
1348 __ verify_oop(obj);
1349
1350 if (op->fast_check()) {
1351 // get object class
1352 // not a safepoint as obj null check happens earlier
1353 __ load_klass(rscratch1, obj);
1354 __ cmp( rscratch1, k_RInfo);
1355
1356 __ br(Assembler::NE, *failure_target);
1357 // successful cast, fall through to profile or jump
1358 } else {
1359 // get object class
1360 // not a safepoint as obj null check happens earlier
1361 __ load_klass(klass_RInfo, obj);
1362 if (k->is_loaded()) {
1363 // See if we get an immediate positive hit
1364 __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
1365 __ cmp(k_RInfo, rscratch1);
1366 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1367 __ br(Assembler::NE, *failure_target);
1368 // successful cast, fall through to profile or jump
1369 } else {
1370 // See if we get an immediate positive hit
1371 __ br(Assembler::EQ, *success_target);
1372 // check for self
1373 __ cmp(klass_RInfo, k_RInfo);
1374 __ br(Assembler::EQ, *success_target);
1375
1376 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1377 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1378 __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1379 // result is a boolean
1380 __ cbzw(klass_RInfo, *failure_target);
1381 // successful cast, fall through to profile or jump
1382 }
1383 } else {
1384 // perform the fast part of the checking logic
1385 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1386 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1387 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1388 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1389 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1390 // result is a boolean
1391 __ cbz(k_RInfo, *failure_target);
1392 // successful cast, fall through to profile or jump
1393 }
1394 }
1395 __ b(*success);
1396 }
1397
1398
1399 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1400 const bool should_profile = op->should_profile();
1401
1402 LIR_Code code = op->code();
1403 if (code == lir_store_check) {
1404 Register value = op->object()->as_register();
1405 Register array = op->array()->as_register();
1406 Register k_RInfo = op->tmp1()->as_register();
1407 Register klass_RInfo = op->tmp2()->as_register();
1408 Register Rtmp1 = op->tmp3()->as_register();
1409
1410 CodeStub* stub = op->stub();
1411
1412 // check if it needs to be profiled
1413 ciMethodData* md;
1414 ciProfileData* data;
1415
1416 if (should_profile) {
1417 ciMethod* method = op->profiled_method();
1418 assert(method != nullptr, "Should have method");
1419 int bci = op->profiled_bci();
1420 md = method->method_data_or_null();
1421 assert(md != nullptr, "Sanity");
1422 data = md->bci_to_data(bci);
1423 assert(data != nullptr, "need data for type check");
1424 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1425 }
1426 Label done;
1427 Label* success_target = &done;
1428 Label* failure_target = stub->entry();
1429
1430 if (should_profile) {
1431 Label not_null;
1432 Register mdo = klass_RInfo;
1433 __ mov_metadata(mdo, md->constant_encoding());
1434 __ cbnz(value, not_null);
1435 // Object is null; update MDO and exit
1436 Address data_addr
1437 = __ form_address(rscratch2, mdo,
1438 md->byte_offset_of_slot(data, DataLayout::flags_offset()), 0);
1439 __ ldrb(rscratch1, data_addr);
1440 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1441 __ strb(rscratch1, data_addr);
1442 __ b(done);
1443 __ bind(not_null);
1444
1445 Label update_done;
1446 Register recv = k_RInfo;
1447 __ load_klass(recv, value);
1448 type_profile_helper(mdo, md, data, recv, &update_done);
1449 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1450 __ addptr(counter_addr, DataLayout::counter_increment);
1451 __ bind(update_done);
1452 } else {
1453 __ cbz(value, done);
1454 }
1455
1456 add_debug_info_for_null_check_here(op->info_for_exception());
1457 __ load_klass(k_RInfo, array);
1458 __ load_klass(klass_RInfo, value);
1459
1460 // get instance klass (it's already uncompressed)
1461 __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1462 // perform the fast part of the checking logic
1463 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1464 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1465 __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1466 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1467 __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1468 // result is a boolean
1469 __ cbzw(k_RInfo, *failure_target);
1470 // fall through to the success case
1471
1472 __ bind(done);
1473 } else if (code == lir_checkcast) {
1474 Register obj = op->object()->as_register();
1475 Register dst = op->result_opr()->as_register();
1476 Label success;
1477 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1478 __ bind(success);
1479 if (dst != obj) {
1480 __ mov(dst, obj);
1481 }
1482 } else if (code == lir_instanceof) {
1483 Register obj = op->object()->as_register();
1484 Register dst = op->result_opr()->as_register();
1485 Label success, failure, done;
1486 emit_typecheck_helper(op, &success, &failure, &failure);
1487 __ bind(failure);
1488 __ mov(dst, zr);
1489 __ b(done);
1490 __ bind(success);
1491 __ mov(dst, 1);
1492 __ bind(done);
1493 } else {
1494 ShouldNotReachHere();
1495 }
1496 }
1497
1498 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1499 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1500 __ cset(rscratch1, Assembler::NE);
1501 __ membar(__ AnyAny);
1502 }
1503
1504 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1505 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1506 __ cset(rscratch1, Assembler::NE);
1507 __ membar(__ AnyAny);
1508 }
1509
1510
1511 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1512 Register addr;
1513 if (op->addr()->is_register()) {
1514 addr = as_reg(op->addr());
1515 } else {
1516 assert(op->addr()->is_address(), "what else?");
1517 LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1518 assert(addr_ptr->disp() == 0, "need 0 disp");
1519 assert(addr_ptr->index() == LIR_Opr::illegalOpr(), "need 0 index");
1520 addr = as_reg(addr_ptr->base());
1521 }
1522 Register newval = as_reg(op->new_value());
1523 Register cmpval = as_reg(op->cmp_value());
1524
1525 if (op->code() == lir_cas_obj) {
1526 if (UseCompressedOops) {
1527 Register t1 = op->tmp1()->as_register();
1528 assert(op->tmp1()->is_valid(), "must be");
1529 __ encode_heap_oop(t1, cmpval);
1530 cmpval = t1;
1531 __ encode_heap_oop(rscratch2, newval);
1532 newval = rscratch2;
1533 casw(addr, newval, cmpval);
1534 } else {
1535 casl(addr, newval, cmpval);
1536 }
1537 } else if (op->code() == lir_cas_int) {
1538 casw(addr, newval, cmpval);
1539 } else {
1540 casl(addr, newval, cmpval);
1541 }
1542 }
1543
1544
1545 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1546 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1547 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on aarch64");
1548
1549 Assembler::Condition acond, ncond;
1550 switch (condition) {
1551 case lir_cond_equal: acond = Assembler::EQ; ncond = Assembler::NE; break;
1552 case lir_cond_notEqual: acond = Assembler::NE; ncond = Assembler::EQ; break;
1553 case lir_cond_less: acond = Assembler::LT; ncond = Assembler::GE; break;
1554 case lir_cond_lessEqual: acond = Assembler::LE; ncond = Assembler::GT; break;
1555 case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1556 case lir_cond_greater: acond = Assembler::GT; ncond = Assembler::LE; break;
1557 case lir_cond_belowEqual:
1558 case lir_cond_aboveEqual:
1559 default: ShouldNotReachHere();
1560 acond = Assembler::EQ; ncond = Assembler::NE; // unreachable
1561 }
1562
1563 assert(result->is_single_cpu() || result->is_double_cpu(),
1564 "expect single register for result");
1565 if (opr1->is_constant() && opr2->is_constant()
1566 && opr1->type() == T_INT && opr2->type() == T_INT) {
1567 jint val1 = opr1->as_jint();
1568 jint val2 = opr2->as_jint();
1569 if (val1 == 0 && val2 == 1) {
1570 __ cset(result->as_register(), ncond);
1571 return;
1572 } else if (val1 == 1 && val2 == 0) {
1573 __ cset(result->as_register(), acond);
1574 return;
1575 }
1576 }
1577
1578 if (opr1->is_constant() && opr2->is_constant()
1579 && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1580 jlong val1 = opr1->as_jlong();
1581 jlong val2 = opr2->as_jlong();
1582 if (val1 == 0 && val2 == 1) {
1583 __ cset(result->as_register_lo(), ncond);
1584 return;
1585 } else if (val1 == 1 && val2 == 0) {
1586 __ cset(result->as_register_lo(), acond);
1587 return;
1588 }
1589 }
1590
1591 if (opr1->is_stack()) {
1592 stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1593 opr1 = FrameMap::rscratch1_opr;
1594 } else if (opr1->is_constant()) {
1595 LIR_Opr tmp
1596 = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1597 const2reg(opr1, tmp, lir_patch_none, nullptr);
1598 opr1 = tmp;
1599 }
1600
1601 if (opr2->is_stack()) {
1602 stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1603 opr2 = FrameMap::rscratch2_opr;
1604 } else if (opr2->is_constant()) {
1605 LIR_Opr tmp
1606 = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1607 const2reg(opr2, tmp, lir_patch_none, nullptr);
1608 opr2 = tmp;
1609 }
1610
1611 if (result->type() == T_LONG)
1612 __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1613 else
1614 __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1615 }
1616
1617 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info) {
1618 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1619
1620 if (left->is_single_cpu()) {
1621 Register lreg = left->as_register();
1622 Register dreg = as_reg(dest);
1623
1624 if (right->is_single_cpu()) {
1625 // cpu register - cpu register
1626
1627 assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1628 "should be");
1629 Register rreg = right->as_register();
1630 switch (code) {
1631 case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1632 case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1633 case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1634 default: ShouldNotReachHere();
1635 }
1636
1637 } else if (right->is_double_cpu()) {
1638 Register rreg = right->as_register_lo();
1639 // single_cpu + double_cpu: can happen with obj+long
1640 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1641 switch (code) {
1642 case lir_add: __ add(dreg, lreg, rreg); break;
1643 case lir_sub: __ sub(dreg, lreg, rreg); break;
1644 default: ShouldNotReachHere();
1645 }
1646 } else if (right->is_constant()) {
1647 // cpu register - constant
1648 jlong c;
1649
1650 // FIXME. This is fugly: we really need to factor all this logic.
1651 switch(right->type()) {
1652 case T_LONG:
1653 c = right->as_constant_ptr()->as_jlong();
1654 break;
1655 case T_INT:
1656 case T_ADDRESS:
1657 c = right->as_constant_ptr()->as_jint();
1658 break;
1659 default:
1660 ShouldNotReachHere();
1661 c = 0; // unreachable
1662 break;
1663 }
1664
1665 assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1666 if (c == 0 && dreg == lreg) {
1667 COMMENT("effective nop elided");
1668 return;
1669 }
1670 switch(left->type()) {
1671 case T_INT:
1672 switch (code) {
1673 case lir_add: __ addw(dreg, lreg, c); break;
1674 case lir_sub: __ subw(dreg, lreg, c); break;
1675 default: ShouldNotReachHere();
1676 }
1677 break;
1678 case T_OBJECT:
1679 case T_ADDRESS:
1680 switch (code) {
1681 case lir_add: __ add(dreg, lreg, c); break;
1682 case lir_sub: __ sub(dreg, lreg, c); break;
1683 default: ShouldNotReachHere();
1684 }
1685 break;
1686 default:
1687 ShouldNotReachHere();
1688 }
1689 } else {
1690 ShouldNotReachHere();
1691 }
1692
1693 } else if (left->is_double_cpu()) {
1694 Register lreg_lo = left->as_register_lo();
1695
1696 if (right->is_double_cpu()) {
1697 // cpu register - cpu register
1698 Register rreg_lo = right->as_register_lo();
1699 switch (code) {
1700 case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1701 case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1702 case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1703 case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1704 case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1705 default:
1706 ShouldNotReachHere();
1707 }
1708
1709 } else if (right->is_constant()) {
1710 jlong c = right->as_constant_ptr()->as_jlong();
1711 Register dreg = as_reg(dest);
1712 switch (code) {
1713 case lir_add:
1714 case lir_sub:
1715 if (c == 0 && dreg == lreg_lo) {
1716 COMMENT("effective nop elided");
1717 return;
1718 }
1719 code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1720 break;
1721 case lir_div:
1722 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1723 if (c == 1) {
1724 // move lreg_lo to dreg if divisor is 1
1725 __ mov(dreg, lreg_lo);
1726 } else {
1727 unsigned int shift = log2i_exact(c);
1728 // use rscratch1 as intermediate result register
1729 __ asr(rscratch1, lreg_lo, 63);
1730 __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1731 __ asr(dreg, rscratch1, shift);
1732 }
1733 break;
1734 case lir_rem:
1735 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1736 if (c == 1) {
1737 // move 0 to dreg if divisor is 1
1738 __ mov(dreg, zr);
1739 } else {
1740 // use rscratch1 as intermediate result register
1741 __ negs(rscratch1, lreg_lo);
1742 __ andr(dreg, lreg_lo, c - 1);
1743 __ andr(rscratch1, rscratch1, c - 1);
1744 __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1745 }
1746 break;
1747 default:
1748 ShouldNotReachHere();
1749 }
1750 } else {
1751 ShouldNotReachHere();
1752 }
1753 } else if (left->is_single_fpu()) {
1754 assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1755 switch (code) {
1756 case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1757 case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1758 case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1759 case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1760 default:
1761 ShouldNotReachHere();
1762 }
1763 } else if (left->is_double_fpu()) {
1764 if (right->is_double_fpu()) {
1765 // fpu register - fpu register
1766 switch (code) {
1767 case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1768 case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1769 case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1770 case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1771 default:
1772 ShouldNotReachHere();
1773 }
1774 } else {
1775 if (right->is_constant()) {
1776 ShouldNotReachHere();
1777 }
1778 ShouldNotReachHere();
1779 }
1780 } else if (left->is_single_stack() || left->is_address()) {
1781 assert(left == dest, "left and dest must be equal");
1782 ShouldNotReachHere();
1783 } else {
1784 ShouldNotReachHere();
1785 }
1786 }
1787
1788 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1789 switch(code) {
1790 case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1791 case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1792 case lir_f2hf: __ flt_to_flt16(dest->as_register(), value->as_float_reg(), tmp->as_float_reg()); break;
1793 case lir_hf2f: __ flt16_to_flt(dest->as_float_reg(), value->as_register(), tmp->as_float_reg()); break;
1794 default : ShouldNotReachHere();
1795 }
1796 }
1797
1798 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1799
1800 assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1801 Register Rleft = left->is_single_cpu() ? left->as_register() :
1802 left->as_register_lo();
1803 if (dst->is_single_cpu()) {
1804 Register Rdst = dst->as_register();
1805 if (right->is_constant()) {
1806 switch (code) {
1807 case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1808 case lir_logic_or: __ orrw (Rdst, Rleft, right->as_jint()); break;
1809 case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1810 default: ShouldNotReachHere(); break;
1811 }
1812 } else {
1813 Register Rright = right->is_single_cpu() ? right->as_register() :
1814 right->as_register_lo();
1815 switch (code) {
1816 case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1817 case lir_logic_or: __ orrw (Rdst, Rleft, Rright); break;
1818 case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1819 default: ShouldNotReachHere(); break;
1820 }
1821 }
1822 } else {
1823 Register Rdst = dst->as_register_lo();
1824 if (right->is_constant()) {
1825 switch (code) {
1826 case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1827 case lir_logic_or: __ orr (Rdst, Rleft, right->as_jlong()); break;
1828 case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1829 default: ShouldNotReachHere(); break;
1830 }
1831 } else {
1832 Register Rright = right->is_single_cpu() ? right->as_register() :
1833 right->as_register_lo();
1834 switch (code) {
1835 case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1836 case lir_logic_or: __ orr (Rdst, Rleft, Rright); break;
1837 case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1838 default: ShouldNotReachHere(); break;
1839 }
1840 }
1841 }
1842 }
1843
1844
1845
1846 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
1847
1848 // opcode check
1849 assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
1850 bool is_irem = (code == lir_irem);
1851
1852 // operand check
1853 assert(left->is_single_cpu(), "left must be register");
1854 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
1855 assert(result->is_single_cpu(), "result must be register");
1856 Register lreg = left->as_register();
1857 Register dreg = result->as_register();
1858
1859 // power-of-2 constant check and codegen
1860 if (right->is_constant()) {
1861 int c = right->as_constant_ptr()->as_jint();
1862 assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1863 if (is_irem) {
1864 if (c == 1) {
1865 // move 0 to dreg if divisor is 1
1866 __ movw(dreg, zr);
1867 } else {
1868 // use rscratch1 as intermediate result register
1869 __ negsw(rscratch1, lreg);
1870 __ andw(dreg, lreg, c - 1);
1871 __ andw(rscratch1, rscratch1, c - 1);
1872 __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
1873 }
1874 } else {
1875 if (c == 1) {
1876 // move lreg to dreg if divisor is 1
1877 __ movw(dreg, lreg);
1878 } else {
1879 unsigned int shift = exact_log2(c);
1880 // use rscratch1 as intermediate result register
1881 __ asrw(rscratch1, lreg, 31);
1882 __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
1883 __ asrw(dreg, rscratch1, shift);
1884 }
1885 }
1886 } else {
1887 Register rreg = right->as_register();
1888 __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
1889 }
1890 }
1891
1892
1893 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1894 if (opr1->is_constant() && opr2->is_single_cpu()) {
1895 // tableswitch
1896 Register reg = as_reg(opr2);
1897 struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
1898 __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
1899 } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
1900 Register reg1 = as_reg(opr1);
1901 if (opr2->is_single_cpu()) {
1902 // cpu register - cpu register
1903 Register reg2 = opr2->as_register();
1904 if (is_reference_type(opr1->type())) {
1905 __ cmpoop(reg1, reg2);
1906 } else {
1907 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
1908 __ cmpw(reg1, reg2);
1909 }
1910 return;
1911 }
1912 if (opr2->is_double_cpu()) {
1913 // cpu register - cpu register
1914 Register reg2 = opr2->as_register_lo();
1915 __ cmp(reg1, reg2);
1916 return;
1917 }
1918
1919 if (opr2->is_constant()) {
1920 bool is_32bit = false; // width of register operand
1921 jlong imm;
1922
1923 switch(opr2->type()) {
1924 case T_INT:
1925 imm = opr2->as_constant_ptr()->as_jint();
1926 is_32bit = true;
1927 break;
1928 case T_LONG:
1929 imm = opr2->as_constant_ptr()->as_jlong();
1930 break;
1931 case T_ADDRESS:
1932 imm = opr2->as_constant_ptr()->as_jint();
1933 break;
1934 case T_METADATA:
1935 imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata());
1936 break;
1937 case T_OBJECT:
1938 case T_ARRAY:
1939 jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
1940 __ cmpoop(reg1, rscratch1);
1941 return;
1942 default:
1943 ShouldNotReachHere();
1944 imm = 0; // unreachable
1945 break;
1946 }
1947
1948 if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
1949 if (is_32bit)
1950 __ cmpw(reg1, imm);
1951 else
1952 __ subs(zr, reg1, imm);
1953 return;
1954 } else {
1955 __ mov(rscratch1, imm);
1956 if (is_32bit)
1957 __ cmpw(reg1, rscratch1);
1958 else
1959 __ cmp(reg1, rscratch1);
1960 return;
1961 }
1962 } else
1963 ShouldNotReachHere();
1964 } else if (opr1->is_single_fpu()) {
1965 FloatRegister reg1 = opr1->as_float_reg();
1966 assert(opr2->is_single_fpu(), "expect single float register");
1967 FloatRegister reg2 = opr2->as_float_reg();
1968 __ fcmps(reg1, reg2);
1969 } else if (opr1->is_double_fpu()) {
1970 FloatRegister reg1 = opr1->as_double_reg();
1971 assert(opr2->is_double_fpu(), "expect double float register");
1972 FloatRegister reg2 = opr2->as_double_reg();
1973 __ fcmpd(reg1, reg2);
1974 } else {
1975 ShouldNotReachHere();
1976 }
1977 }
1978
1979 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1980 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1981 bool is_unordered_less = (code == lir_ucmp_fd2i);
1982 if (left->is_single_fpu()) {
1983 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
1984 } else if (left->is_double_fpu()) {
1985 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
1986 } else {
1987 ShouldNotReachHere();
1988 }
1989 } else if (code == lir_cmp_l2i) {
1990 Label done;
1991 __ cmp(left->as_register_lo(), right->as_register_lo());
1992 __ mov(dst->as_register(), (uint64_t)-1L);
1993 __ br(Assembler::LT, done);
1994 __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
1995 __ bind(done);
1996 } else {
1997 ShouldNotReachHere();
1998 }
1999 }
2000
2001
2002 void LIR_Assembler::align_call(LIR_Code code) { }
2003
2004
2005 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2006 address call = __ trampoline_call(Address(op->addr(), rtype));
2007 if (call == nullptr) {
2008 bailout("trampoline stub overflow");
2009 return;
2010 }
2011 add_call_info(code_offset(), op->info());
2012 __ post_call_nop();
2013 }
2014
2015
2016 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2017 address call = __ ic_call(op->addr());
2018 if (call == nullptr) {
2019 bailout("trampoline stub overflow");
2020 return;
2021 }
2022 add_call_info(code_offset(), op->info());
2023 __ post_call_nop();
2024 }
2025
2026 void LIR_Assembler::emit_static_call_stub() {
2027 address call_pc = __ pc();
2028 address stub = __ start_a_stub(call_stub_size());
2029 if (stub == nullptr) {
2030 bailout("static call stub overflow");
2031 return;
2032 }
2033
2034 int start = __ offset();
2035
2036 __ relocate(static_stub_Relocation::spec(call_pc));
2037 __ emit_static_call_stub();
2038
2039 assert(__ offset() - start + CompiledDirectCall::to_trampoline_stub_size()
2040 <= call_stub_size(), "stub too big");
2041 __ end_a_stub();
2042 }
2043
2044
2045 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2046 assert(exceptionOop->as_register() == r0, "must match");
2047 assert(exceptionPC->as_register() == r3, "must match");
2048
2049 // exception object is not added to oop map by LinearScan
2050 // (LinearScan assumes that no oops are in fixed registers)
2051 info->add_register_oop(exceptionOop);
2052 C1StubId unwind_id;
2053
2054 // get current pc information
2055 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2056 if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) {
2057 // As no instructions have been generated yet for this LIR node it's
2058 // possible that an oop map already exists for the current offset.
2059 // In that case insert an dummy NOP here to ensure all oop map PCs
2060 // are unique. See JDK-8237483.
2061 __ nop();
2062 }
2063 int pc_for_athrow_offset = __ offset();
2064 InternalAddress pc_for_athrow(__ pc());
2065 __ adr(exceptionPC->as_register(), pc_for_athrow);
2066 add_call_info(pc_for_athrow_offset, info); // for exception handler
2067
2068 __ verify_not_null_oop(r0);
2069 // search an exception handler (r0: exception oop, r3: throwing pc)
2070 if (compilation()->has_fpu_code()) {
2071 unwind_id = C1StubId::handle_exception_id;
2072 } else {
2073 unwind_id = C1StubId::handle_exception_nofpu_id;
2074 }
2075 __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2076
2077 // FIXME: enough room for two byte trap ????
2078 __ nop();
2079 }
2080
2081
2082 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2083 assert(exceptionOop->as_register() == r0, "must match");
2084
2085 __ b(_unwind_handler_entry);
2086 }
2087
2088
2089 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2090 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2091 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2092
2093 switch (left->type()) {
2094 case T_INT: {
2095 switch (code) {
2096 case lir_shl: __ lslvw (dreg, lreg, count->as_register()); break;
2097 case lir_shr: __ asrvw (dreg, lreg, count->as_register()); break;
2098 case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2099 default:
2100 ShouldNotReachHere();
2101 break;
2102 }
2103 break;
2104 case T_LONG:
2105 case T_ADDRESS:
2106 case T_OBJECT:
2107 switch (code) {
2108 case lir_shl: __ lslv (dreg, lreg, count->as_register()); break;
2109 case lir_shr: __ asrv (dreg, lreg, count->as_register()); break;
2110 case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2111 default:
2112 ShouldNotReachHere();
2113 break;
2114 }
2115 break;
2116 default:
2117 ShouldNotReachHere();
2118 break;
2119 }
2120 }
2121 }
2122
2123
2124 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2125 Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2126 Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2127
2128 switch (left->type()) {
2129 case T_INT: {
2130 switch (code) {
2131 case lir_shl: __ lslw (dreg, lreg, count); break;
2132 case lir_shr: __ asrw (dreg, lreg, count); break;
2133 case lir_ushr: __ lsrw (dreg, lreg, count); break;
2134 default:
2135 ShouldNotReachHere();
2136 break;
2137 }
2138 break;
2139 case T_LONG:
2140 case T_ADDRESS:
2141 case T_OBJECT:
2142 switch (code) {
2143 case lir_shl: __ lsl (dreg, lreg, count); break;
2144 case lir_shr: __ asr (dreg, lreg, count); break;
2145 case lir_ushr: __ lsr (dreg, lreg, count); break;
2146 default:
2147 ShouldNotReachHere();
2148 break;
2149 }
2150 break;
2151 default:
2152 ShouldNotReachHere();
2153 break;
2154 }
2155 }
2156 }
2157
2158
2159 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2160 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2161 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2162 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2163 __ str (r, Address(sp, offset_from_rsp_in_bytes));
2164 }
2165
2166
2167 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2168 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2169 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2170 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2171 __ mov (rscratch1, c);
2172 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2173 }
2174
2175
2176 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2177 ShouldNotReachHere();
2178 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2179 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2180 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2181 __ lea(rscratch1, __ constant_oop_address(o));
2182 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2183 }
2184
2185
2186 // This code replaces a call to arraycopy; no exception may
2187 // be thrown in this code, they must be thrown in the System.arraycopy
2188 // activation frame; we could save some checks if this would not be the case
2189 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2190 ciArrayKlass* default_type = op->expected_type();
2191 Register src = op->src()->as_register();
2192 Register dst = op->dst()->as_register();
2193 Register src_pos = op->src_pos()->as_register();
2194 Register dst_pos = op->dst_pos()->as_register();
2195 Register length = op->length()->as_register();
2196 Register tmp = op->tmp()->as_register();
2197
2198 CodeStub* stub = op->stub();
2199 int flags = op->flags();
2200 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
2201 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2202
2203 // if we don't know anything, just go through the generic arraycopy
2204 if (default_type == nullptr // || basic_type == T_OBJECT
2205 ) {
2206 Label done;
2207 assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2208
2209 // Save the arguments in case the generic arraycopy fails and we
2210 // have to fall back to the JNI stub
2211 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2212 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2213 __ str(src, Address(sp, 4*BytesPerWord));
2214
2215 address copyfunc_addr = StubRoutines::generic_arraycopy();
2216 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
2217
2218 // The arguments are in java calling convention so we shift them
2219 // to C convention
2220 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2221 __ mov(c_rarg0, j_rarg0);
2222 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2223 __ mov(c_rarg1, j_rarg1);
2224 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2225 __ mov(c_rarg2, j_rarg2);
2226 assert_different_registers(c_rarg3, j_rarg4);
2227 __ mov(c_rarg3, j_rarg3);
2228 __ mov(c_rarg4, j_rarg4);
2229 #ifndef PRODUCT
2230 if (PrintC1Statistics) {
2231 __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2232 }
2233 #endif
2234 __ far_call(RuntimeAddress(copyfunc_addr));
2235
2236 __ cbz(r0, *stub->continuation());
2237
2238 // Reload values from the stack so they are where the stub
2239 // expects them.
2240 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2241 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2242 __ ldr(src, Address(sp, 4*BytesPerWord));
2243
2244 // r0 is -1^K where K == partial copied count
2245 __ eonw(rscratch1, r0, zr);
2246 // adjust length down and src/end pos up by partial copied count
2247 __ subw(length, length, rscratch1);
2248 __ addw(src_pos, src_pos, rscratch1);
2249 __ addw(dst_pos, dst_pos, rscratch1);
2250 __ b(*stub->entry());
2251
2252 __ bind(*stub->continuation());
2253 return;
2254 }
2255
2256 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2257
2258 int elem_size = type2aelembytes(basic_type);
2259 int scale = exact_log2(elem_size);
2260
2261 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2262 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2263
2264 // test for null
2265 if (flags & LIR_OpArrayCopy::src_null_check) {
2266 __ cbz(src, *stub->entry());
2267 }
2268 if (flags & LIR_OpArrayCopy::dst_null_check) {
2269 __ cbz(dst, *stub->entry());
2270 }
2271
2272 // If the compiler was not able to prove that exact type of the source or the destination
2273 // of the arraycopy is an array type, check at runtime if the source or the destination is
2274 // an instance type.
2275 if (flags & LIR_OpArrayCopy::type_check) {
2276 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2277 __ load_klass(tmp, dst);
2278 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2279 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2280 __ br(Assembler::GE, *stub->entry());
2281 }
2282
2283 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2284 __ load_klass(tmp, src);
2285 __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2286 __ cmpw(rscratch1, Klass::_lh_neutral_value);
2287 __ br(Assembler::GE, *stub->entry());
2288 }
2289 }
2290
2291 // check if negative
2292 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2293 __ cmpw(src_pos, 0);
2294 __ br(Assembler::LT, *stub->entry());
2295 }
2296 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2297 __ cmpw(dst_pos, 0);
2298 __ br(Assembler::LT, *stub->entry());
2299 }
2300
2301 if (flags & LIR_OpArrayCopy::length_positive_check) {
2302 __ cmpw(length, 0);
2303 __ br(Assembler::LT, *stub->entry());
2304 }
2305
2306 if (flags & LIR_OpArrayCopy::src_range_check) {
2307 __ addw(tmp, src_pos, length);
2308 __ ldrw(rscratch1, src_length_addr);
2309 __ cmpw(tmp, rscratch1);
2310 __ br(Assembler::HI, *stub->entry());
2311 }
2312 if (flags & LIR_OpArrayCopy::dst_range_check) {
2313 __ addw(tmp, dst_pos, length);
2314 __ ldrw(rscratch1, dst_length_addr);
2315 __ cmpw(tmp, rscratch1);
2316 __ br(Assembler::HI, *stub->entry());
2317 }
2318
2319 if (flags & LIR_OpArrayCopy::type_check) {
2320 // We don't know the array types are compatible
2321 if (basic_type != T_OBJECT) {
2322 // Simple test for basic type arrays
2323 __ cmp_klasses_from_objects(src, dst, tmp, rscratch1);
2324 __ br(Assembler::NE, *stub->entry());
2325 } else {
2326 // For object arrays, if src is a sub class of dst then we can
2327 // safely do the copy.
2328 Label cont, slow;
2329
2330 #define PUSH(r1, r2) \
2331 stp(r1, r2, __ pre(sp, -2 * wordSize));
2332
2333 #define POP(r1, r2) \
2334 ldp(r1, r2, __ post(sp, 2 * wordSize));
2335
2336 __ PUSH(src, dst);
2337
2338 __ load_klass(src, src);
2339 __ load_klass(dst, dst);
2340
2341 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
2342
2343 __ PUSH(src, dst);
2344 __ far_call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
2345 __ POP(src, dst);
2346
2347 __ cbnz(src, cont);
2348
2349 __ bind(slow);
2350 __ POP(src, dst);
2351
2352 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2353 if (copyfunc_addr != nullptr) { // use stub if available
2354 // src is not a sub class of dst so we have to do a
2355 // per-element check.
2356
2357 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2358 if ((flags & mask) != mask) {
2359 // Check that at least both of them object arrays.
2360 assert(flags & mask, "one of the two should be known to be an object array");
2361
2362 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2363 __ load_klass(tmp, src);
2364 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2365 __ load_klass(tmp, dst);
2366 }
2367 int lh_offset = in_bytes(Klass::layout_helper_offset());
2368 Address klass_lh_addr(tmp, lh_offset);
2369 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2370 __ ldrw(rscratch1, klass_lh_addr);
2371 __ mov(rscratch2, objArray_lh);
2372 __ eorw(rscratch1, rscratch1, rscratch2);
2373 __ cbnzw(rscratch1, *stub->entry());
2374 }
2375
2376 // Spill because stubs can use any register they like and it's
2377 // easier to restore just those that we care about.
2378 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2379 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2380 __ str(src, Address(sp, 4*BytesPerWord));
2381
2382 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2383 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2384 assert_different_registers(c_rarg0, dst, dst_pos, length);
2385 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2386 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2387 assert_different_registers(c_rarg1, dst, length);
2388 __ uxtw(c_rarg2, length);
2389 assert_different_registers(c_rarg2, dst);
2390
2391 __ load_klass(c_rarg4, dst);
2392 __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2393 __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2394 __ far_call(RuntimeAddress(copyfunc_addr));
2395
2396 #ifndef PRODUCT
2397 if (PrintC1Statistics) {
2398 Label failed;
2399 __ cbnz(r0, failed);
2400 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2401 __ bind(failed);
2402 }
2403 #endif
2404
2405 __ cbz(r0, *stub->continuation());
2406
2407 #ifndef PRODUCT
2408 if (PrintC1Statistics) {
2409 __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2410 }
2411 #endif
2412 assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2413
2414 // Restore previously spilled arguments
2415 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2416 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2417 __ ldr(src, Address(sp, 4*BytesPerWord));
2418
2419 // return value is -1^K where K is partial copied count
2420 __ eonw(rscratch1, r0, zr);
2421 // adjust length down and src/end pos up by partial copied count
2422 __ subw(length, length, rscratch1);
2423 __ addw(src_pos, src_pos, rscratch1);
2424 __ addw(dst_pos, dst_pos, rscratch1);
2425 }
2426
2427 __ b(*stub->entry());
2428
2429 __ bind(cont);
2430 __ POP(src, dst);
2431 }
2432 }
2433
2434 #ifdef ASSERT
2435 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2436 // Sanity check the known type with the incoming class. For the
2437 // primitive case the types must match exactly with src.klass and
2438 // dst.klass each exactly matching the default type. For the
2439 // object array case, if no type check is needed then either the
2440 // dst type is exactly the expected type and the src type is a
2441 // subtype which we can't check or src is the same array as dst
2442 // but not necessarily exactly of type default_type.
2443 Label known_ok, halt;
2444 __ mov_metadata(tmp, default_type->constant_encoding());
2445
2446 if (basic_type != T_OBJECT) {
2447 __ cmp_klass(dst, tmp, rscratch1);
2448 __ br(Assembler::NE, halt);
2449 __ cmp_klass(src, tmp, rscratch1);
2450 __ br(Assembler::EQ, known_ok);
2451 } else {
2452 __ cmp_klass(dst, tmp, rscratch1);
2453 __ br(Assembler::EQ, known_ok);
2454 __ cmp(src, dst);
2455 __ br(Assembler::EQ, known_ok);
2456 }
2457 __ bind(halt);
2458 __ stop("incorrect type information in arraycopy");
2459 __ bind(known_ok);
2460 }
2461 #endif
2462
2463 #ifndef PRODUCT
2464 if (PrintC1Statistics) {
2465 __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2466 }
2467 #endif
2468
2469 __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2470 __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2471 assert_different_registers(c_rarg0, dst, dst_pos, length);
2472 __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2473 __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2474 assert_different_registers(c_rarg1, dst, length);
2475 __ uxtw(c_rarg2, length);
2476 assert_different_registers(c_rarg2, dst);
2477
2478 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2479 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2480 const char *name;
2481 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2482
2483 CodeBlob *cb = CodeCache::find_blob(entry);
2484 if (cb) {
2485 __ far_call(RuntimeAddress(entry));
2486 } else {
2487 __ call_VM_leaf(entry, 3);
2488 }
2489
2490 if (stub != nullptr) {
2491 __ bind(*stub->continuation());
2492 }
2493 }
2494
2495
2496
2497
2498 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2499 Register obj = op->obj_opr()->as_register(); // may not be an oop
2500 Register hdr = op->hdr_opr()->as_register();
2501 Register lock = op->lock_opr()->as_register();
2502 Register temp = op->scratch_opr()->as_register();
2503 if (LockingMode == LM_MONITOR) {
2504 if (op->info() != nullptr) {
2505 add_debug_info_for_null_check_here(op->info());
2506 __ null_check(obj, -1);
2507 }
2508 __ b(*op->stub()->entry());
2509 } else if (op->code() == lir_lock) {
2510 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2511 // add debug info for NullPointerException only if one is possible
2512 int null_check_offset = __ lock_object(hdr, obj, lock, temp, *op->stub()->entry());
2513 if (op->info() != nullptr) {
2514 add_debug_info_for_null_check(null_check_offset, op->info());
2515 }
2516 // done
2517 } else if (op->code() == lir_unlock) {
2518 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2519 __ unlock_object(hdr, obj, lock, temp, *op->stub()->entry());
2520 } else {
2521 Unimplemented();
2522 }
2523 __ bind(*op->stub()->continuation());
2524 }
2525
2526 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2527 Register obj = op->obj()->as_pointer_register();
2528 Register result = op->result_opr()->as_pointer_register();
2529
2530 CodeEmitInfo* info = op->info();
2531 if (info != nullptr) {
2532 add_debug_info_for_null_check_here(info);
2533 }
2534
2535 __ load_klass(result, obj);
2536 }
2537
2538 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2539 ciMethod* method = op->profiled_method();
2540 int bci = op->profiled_bci();
2541 ciMethod* callee = op->profiled_callee();
2542
2543 // Update counter for all call types
2544 ciMethodData* md = method->method_data_or_null();
2545 assert(md != nullptr, "Sanity");
2546 ciProfileData* data = md->bci_to_data(bci);
2547 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2548 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2549 Register mdo = op->mdo()->as_register();
2550 __ mov_metadata(mdo, md->constant_encoding());
2551 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2552 // Perform additional virtual call profiling for invokevirtual and
2553 // invokeinterface bytecodes
2554 if (op->should_profile_receiver_type()) {
2555 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2556 Register recv = op->recv()->as_register();
2557 assert_different_registers(mdo, recv);
2558 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2559 ciKlass* known_klass = op->known_holder();
2560 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2561 // We know the type that will be seen at this call site; we can
2562 // statically update the MethodData* rather than needing to do
2563 // dynamic tests on the receiver type
2564
2565 // NOTE: we should probably put a lock around this search to
2566 // avoid collisions by concurrent compilations
2567 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2568 uint i;
2569 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2570 ciKlass* receiver = vc_data->receiver(i);
2571 if (known_klass->equals(receiver)) {
2572 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2573 __ addptr(data_addr, DataLayout::counter_increment);
2574 return;
2575 }
2576 }
2577
2578 // Receiver type not found in profile data; select an empty slot
2579
2580 // Note that this is less efficient than it should be because it
2581 // always does a write to the receiver part of the
2582 // VirtualCallData rather than just the first time
2583 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2584 ciKlass* receiver = vc_data->receiver(i);
2585 if (receiver == nullptr) {
2586 __ mov_metadata(rscratch1, known_klass->constant_encoding());
2587 Address recv_addr =
2588 __ form_address(rscratch2, mdo,
2589 md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)),
2590 LogBytesPerWord);
2591 __ str(rscratch1, recv_addr);
2592 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2593 __ addptr(data_addr, DataLayout::counter_increment);
2594 return;
2595 }
2596 }
2597 } else {
2598 __ load_klass(recv, recv);
2599 Label update_done;
2600 type_profile_helper(mdo, md, data, recv, &update_done);
2601 // Receiver did not match any saved receiver and there is no empty row for it.
2602 // Increment total counter to indicate polymorphic case.
2603 __ addptr(counter_addr, DataLayout::counter_increment);
2604
2605 __ bind(update_done);
2606 }
2607 } else {
2608 // Static call
2609 __ addptr(counter_addr, DataLayout::counter_increment);
2610 }
2611 }
2612
2613
2614 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
2615 Unimplemented();
2616 }
2617
2618
2619 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2620 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2621 }
2622
2623 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2624 assert(op->crc()->is_single_cpu(), "crc must be register");
2625 assert(op->val()->is_single_cpu(), "byte value must be register");
2626 assert(op->result_opr()->is_single_cpu(), "result must be register");
2627 Register crc = op->crc()->as_register();
2628 Register val = op->val()->as_register();
2629 Register res = op->result_opr()->as_register();
2630
2631 assert_different_registers(val, crc, res);
2632 uint64_t offset;
2633 __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2634 __ add(res, res, offset);
2635
2636 __ mvnw(crc, crc); // ~crc
2637 __ update_byte_crc32(crc, val, res);
2638 __ mvnw(res, crc); // ~crc
2639 }
2640
2641 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2642 COMMENT("emit_profile_type {");
2643 Register obj = op->obj()->as_register();
2644 Register tmp = op->tmp()->as_pointer_register();
2645 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2646 ciKlass* exact_klass = op->exact_klass();
2647 intptr_t current_klass = op->current_klass();
2648 bool not_null = op->not_null();
2649 bool no_conflict = op->no_conflict();
2650
2651 Label update, next, none;
2652
2653 bool do_null = !not_null;
2654 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2655 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2656
2657 assert(do_null || do_update, "why are we here?");
2658 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2659 assert(mdo_addr.base() != rscratch1, "wrong register");
2660
2661 __ verify_oop(obj);
2662
2663 if (tmp != obj) {
2664 assert_different_registers(obj, tmp, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2665 __ mov(tmp, obj);
2666 } else {
2667 assert_different_registers(obj, rscratch1, rscratch2, mdo_addr.base(), mdo_addr.index());
2668 }
2669 if (do_null) {
2670 __ cbnz(tmp, update);
2671 if (!TypeEntries::was_null_seen(current_klass)) {
2672 __ ldr(rscratch2, mdo_addr);
2673 __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2674 __ str(rscratch2, mdo_addr);
2675 }
2676 if (do_update) {
2677 #ifndef ASSERT
2678 __ b(next);
2679 }
2680 #else
2681 __ b(next);
2682 }
2683 } else {
2684 __ cbnz(tmp, update);
2685 __ stop("unexpected null obj");
2686 #endif
2687 }
2688
2689 __ bind(update);
2690
2691 if (do_update) {
2692 #ifdef ASSERT
2693 if (exact_klass != nullptr) {
2694 Label ok;
2695 __ load_klass(tmp, tmp);
2696 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2697 __ eor(rscratch1, tmp, rscratch1);
2698 __ cbz(rscratch1, ok);
2699 __ stop("exact klass and actual klass differ");
2700 __ bind(ok);
2701 }
2702 #endif
2703 if (!no_conflict) {
2704 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
2705 if (exact_klass != nullptr) {
2706 __ mov_metadata(tmp, exact_klass->constant_encoding());
2707 } else {
2708 __ load_klass(tmp, tmp);
2709 }
2710
2711 __ ldr(rscratch2, mdo_addr);
2712 __ eor(tmp, tmp, rscratch2);
2713 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2714 // klass seen before, nothing to do. The unknown bit may have been
2715 // set already but no need to check.
2716 __ cbz(rscratch1, next);
2717
2718 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2719
2720 if (TypeEntries::is_type_none(current_klass)) {
2721 __ cbz(rscratch2, none);
2722 __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2723 __ br(Assembler::EQ, none);
2724 // There is a chance that the checks above
2725 // fail if another thread has just set the
2726 // profiling to this obj's klass
2727 __ dmb(Assembler::ISHLD);
2728 __ eor(tmp, tmp, rscratch2); // get back original value before XOR
2729 __ ldr(rscratch2, mdo_addr);
2730 __ eor(tmp, tmp, rscratch2);
2731 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2732 __ cbz(rscratch1, next);
2733 }
2734 } else {
2735 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2736 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2737
2738 __ ldr(tmp, mdo_addr);
2739 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2740 }
2741
2742 // different than before. Cannot keep accurate profile.
2743 __ ldr(rscratch2, mdo_addr);
2744 __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2745 __ str(rscratch2, mdo_addr);
2746
2747 if (TypeEntries::is_type_none(current_klass)) {
2748 __ b(next);
2749
2750 __ bind(none);
2751 // first time here. Set profile type.
2752 __ str(tmp, mdo_addr);
2753 #ifdef ASSERT
2754 __ andr(tmp, tmp, TypeEntries::type_mask);
2755 __ verify_klass_ptr(tmp);
2756 #endif
2757 }
2758 } else {
2759 // There's a single possible klass at this profile point
2760 assert(exact_klass != nullptr, "should be");
2761 if (TypeEntries::is_type_none(current_klass)) {
2762 __ mov_metadata(tmp, exact_klass->constant_encoding());
2763 __ ldr(rscratch2, mdo_addr);
2764 __ eor(tmp, tmp, rscratch2);
2765 __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2766 __ cbz(rscratch1, next);
2767 #ifdef ASSERT
2768 {
2769 Label ok;
2770 __ ldr(rscratch1, mdo_addr);
2771 __ cbz(rscratch1, ok);
2772 __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2773 __ br(Assembler::EQ, ok);
2774 // may have been set by another thread
2775 __ dmb(Assembler::ISHLD);
2776 __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2777 __ ldr(rscratch2, mdo_addr);
2778 __ eor(rscratch2, rscratch1, rscratch2);
2779 __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2780 __ cbz(rscratch2, ok);
2781
2782 __ stop("unexpected profiling mismatch");
2783 __ bind(ok);
2784 }
2785 #endif
2786 // first time here. Set profile type.
2787 __ str(tmp, mdo_addr);
2788 #ifdef ASSERT
2789 __ andr(tmp, tmp, TypeEntries::type_mask);
2790 __ verify_klass_ptr(tmp);
2791 #endif
2792 } else {
2793 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2794 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2795
2796 __ ldr(tmp, mdo_addr);
2797 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2798
2799 __ orr(tmp, tmp, TypeEntries::type_unknown);
2800 __ str(tmp, mdo_addr);
2801 // FIXME: Write barrier needed here?
2802 }
2803 }
2804
2805 __ bind(next);
2806 }
2807 COMMENT("} emit_profile_type");
2808 }
2809
2810
2811 void LIR_Assembler::align_backward_branch_target() {
2812 }
2813
2814
2815 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2816 // tmp must be unused
2817 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2818
2819 if (left->is_single_cpu()) {
2820 assert(dest->is_single_cpu(), "expect single result reg");
2821 __ negw(dest->as_register(), left->as_register());
2822 } else if (left->is_double_cpu()) {
2823 assert(dest->is_double_cpu(), "expect double result reg");
2824 __ neg(dest->as_register_lo(), left->as_register_lo());
2825 } else if (left->is_single_fpu()) {
2826 assert(dest->is_single_fpu(), "expect single float result reg");
2827 __ fnegs(dest->as_float_reg(), left->as_float_reg());
2828 } else {
2829 assert(left->is_double_fpu(), "expect double float operand reg");
2830 assert(dest->is_double_fpu(), "expect double float result reg");
2831 __ fnegd(dest->as_double_reg(), left->as_double_reg());
2832 }
2833 }
2834
2835
2836 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2837 if (patch_code != lir_patch_none) {
2838 deoptimize_trap(info);
2839 return;
2840 }
2841
2842 __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
2843 }
2844
2845
2846 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2847 assert(!tmp->is_valid(), "don't need temporary");
2848
2849 CodeBlob *cb = CodeCache::find_blob(dest);
2850 if (cb) {
2851 __ far_call(RuntimeAddress(dest));
2852 } else {
2853 __ mov(rscratch1, RuntimeAddress(dest));
2854 __ blr(rscratch1);
2855 }
2856
2857 if (info != nullptr) {
2858 add_call_info_here(info);
2859 }
2860 __ post_call_nop();
2861 }
2862
2863 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2864 if (dest->is_address() || src->is_address()) {
2865 move_op(src, dest, type, lir_patch_none, info, /*wide*/false);
2866 } else {
2867 ShouldNotReachHere();
2868 }
2869 }
2870
2871 #ifdef ASSERT
2872 // emit run-time assertion
2873 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2874 assert(op->code() == lir_assert, "must be");
2875
2876 if (op->in_opr1()->is_valid()) {
2877 assert(op->in_opr2()->is_valid(), "both operands must be valid");
2878 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2879 } else {
2880 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2881 assert(op->condition() == lir_cond_always, "no other conditions allowed");
2882 }
2883
2884 Label ok;
2885 if (op->condition() != lir_cond_always) {
2886 Assembler::Condition acond = Assembler::AL;
2887 switch (op->condition()) {
2888 case lir_cond_equal: acond = Assembler::EQ; break;
2889 case lir_cond_notEqual: acond = Assembler::NE; break;
2890 case lir_cond_less: acond = Assembler::LT; break;
2891 case lir_cond_lessEqual: acond = Assembler::LE; break;
2892 case lir_cond_greaterEqual: acond = Assembler::GE; break;
2893 case lir_cond_greater: acond = Assembler::GT; break;
2894 case lir_cond_belowEqual: acond = Assembler::LS; break;
2895 case lir_cond_aboveEqual: acond = Assembler::HS; break;
2896 default: ShouldNotReachHere();
2897 }
2898 __ br(acond, ok);
2899 }
2900 if (op->halt()) {
2901 const char* str = __ code_string(op->msg());
2902 __ stop(str);
2903 } else {
2904 breakpoint();
2905 }
2906 __ bind(ok);
2907 }
2908 #endif
2909
2910 #ifndef PRODUCT
2911 #define COMMENT(x) do { __ block_comment(x); } while (0)
2912 #else
2913 #define COMMENT(x)
2914 #endif
2915
2916 void LIR_Assembler::membar() {
2917 COMMENT("membar");
2918 __ membar(MacroAssembler::AnyAny);
2919 }
2920
2921 void LIR_Assembler::membar_acquire() {
2922 __ membar(Assembler::LoadLoad|Assembler::LoadStore);
2923 }
2924
2925 void LIR_Assembler::membar_release() {
2926 __ membar(Assembler::LoadStore|Assembler::StoreStore);
2927 }
2928
2929 void LIR_Assembler::membar_loadload() {
2930 __ membar(Assembler::LoadLoad);
2931 }
2932
2933 void LIR_Assembler::membar_storestore() {
2934 __ membar(MacroAssembler::StoreStore);
2935 }
2936
2937 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
2938
2939 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
2940
2941 void LIR_Assembler::on_spin_wait() {
2942 __ spin_wait();
2943 }
2944
2945 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2946 __ mov(result_reg->as_register(), rthread);
2947 }
2948
2949
2950 void LIR_Assembler::peephole(LIR_List *lir) {
2951 #if 0
2952 if (tableswitch_count >= max_tableswitches)
2953 return;
2954
2955 /*
2956 This finite-state automaton recognizes sequences of compare-and-
2957 branch instructions. We will turn them into a tableswitch. You
2958 could argue that C1 really shouldn't be doing this sort of
2959 optimization, but without it the code is really horrible.
2960 */
2961
2962 enum { start_s, cmp1_s, beq_s, cmp_s } state;
2963 int first_key, last_key = -2147483648;
2964 int next_key = 0;
2965 int start_insn = -1;
2966 int last_insn = -1;
2967 Register reg = noreg;
2968 LIR_Opr reg_opr;
2969 state = start_s;
2970
2971 LIR_OpList* inst = lir->instructions_list();
2972 for (int i = 0; i < inst->length(); i++) {
2973 LIR_Op* op = inst->at(i);
2974 switch (state) {
2975 case start_s:
2976 first_key = -1;
2977 start_insn = i;
2978 switch (op->code()) {
2979 case lir_cmp:
2980 LIR_Opr opr1 = op->as_Op2()->in_opr1();
2981 LIR_Opr opr2 = op->as_Op2()->in_opr2();
2982 if (opr1->is_cpu_register() && opr1->is_single_cpu()
2983 && opr2->is_constant()
2984 && opr2->type() == T_INT) {
2985 reg_opr = opr1;
2986 reg = opr1->as_register();
2987 first_key = opr2->as_constant_ptr()->as_jint();
2988 next_key = first_key + 1;
2989 state = cmp_s;
2990 goto next_state;
2991 }
2992 break;
2993 }
2994 break;
2995 case cmp_s:
2996 switch (op->code()) {
2997 case lir_branch:
2998 if (op->as_OpBranch()->cond() == lir_cond_equal) {
2999 state = beq_s;
3000 last_insn = i;
3001 goto next_state;
3002 }
3003 }
3004 state = start_s;
3005 break;
3006 case beq_s:
3007 switch (op->code()) {
3008 case lir_cmp: {
3009 LIR_Opr opr1 = op->as_Op2()->in_opr1();
3010 LIR_Opr opr2 = op->as_Op2()->in_opr2();
3011 if (opr1->is_cpu_register() && opr1->is_single_cpu()
3012 && opr1->as_register() == reg
3013 && opr2->is_constant()
3014 && opr2->type() == T_INT
3015 && opr2->as_constant_ptr()->as_jint() == next_key) {
3016 last_key = next_key;
3017 next_key++;
3018 state = cmp_s;
3019 goto next_state;
3020 }
3021 }
3022 }
3023 last_key = next_key;
3024 state = start_s;
3025 break;
3026 default:
3027 assert(false, "impossible state");
3028 }
3029 if (state == start_s) {
3030 if (first_key < last_key - 5L && reg != noreg) {
3031 {
3032 // printf("found run register %d starting at insn %d low value %d high value %d\n",
3033 // reg->encoding(),
3034 // start_insn, first_key, last_key);
3035 // for (int i = 0; i < inst->length(); i++) {
3036 // inst->at(i)->print();
3037 // tty->print("\n");
3038 // }
3039 // tty->print("\n");
3040 }
3041
3042 struct tableswitch *sw = &switches[tableswitch_count];
3043 sw->_insn_index = start_insn, sw->_first_key = first_key,
3044 sw->_last_key = last_key, sw->_reg = reg;
3045 inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3046 {
3047 // Insert the new table of branches
3048 int offset = last_insn;
3049 for (int n = first_key; n < last_key; n++) {
3050 inst->insert_before
3051 (last_insn + 1,
3052 new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3053 inst->at(offset)->as_OpBranch()->label()));
3054 offset -= 2, i++;
3055 }
3056 }
3057 // Delete all the old compare-and-branch instructions
3058 for (int n = first_key; n < last_key; n++) {
3059 inst->remove_at(start_insn);
3060 inst->remove_at(start_insn);
3061 }
3062 // Insert the tableswitch instruction
3063 inst->insert_before(start_insn,
3064 new LIR_Op2(lir_cmp, lir_cond_always,
3065 LIR_OprFact::intConst(tableswitch_count),
3066 reg_opr));
3067 inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3068 tableswitch_count++;
3069 }
3070 reg = noreg;
3071 last_key = -2147483648;
3072 }
3073 next_state:
3074 ;
3075 }
3076 #endif
3077 }
3078
3079 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3080 Address addr = as_Address(src->as_address_ptr());
3081 BasicType type = src->type();
3082 bool is_oop = is_reference_type(type);
3083
3084 void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3085 void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3086
3087 switch(type) {
3088 case T_INT:
3089 xchg = &MacroAssembler::atomic_xchgalw;
3090 add = &MacroAssembler::atomic_addalw;
3091 break;
3092 case T_LONG:
3093 xchg = &MacroAssembler::atomic_xchgal;
3094 add = &MacroAssembler::atomic_addal;
3095 break;
3096 case T_OBJECT:
3097 case T_ARRAY:
3098 if (UseCompressedOops) {
3099 xchg = &MacroAssembler::atomic_xchgalw;
3100 add = &MacroAssembler::atomic_addalw;
3101 } else {
3102 xchg = &MacroAssembler::atomic_xchgal;
3103 add = &MacroAssembler::atomic_addal;
3104 }
3105 break;
3106 default:
3107 ShouldNotReachHere();
3108 xchg = &MacroAssembler::atomic_xchgal;
3109 add = &MacroAssembler::atomic_addal; // unreachable
3110 }
3111
3112 switch (code) {
3113 case lir_xadd:
3114 {
3115 RegisterOrConstant inc;
3116 Register tmp = as_reg(tmp_op);
3117 Register dst = as_reg(dest);
3118 if (data->is_constant()) {
3119 inc = RegisterOrConstant(as_long(data));
3120 assert_different_registers(dst, addr.base(), tmp,
3121 rscratch1, rscratch2);
3122 } else {
3123 inc = RegisterOrConstant(as_reg(data));
3124 assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3125 rscratch1, rscratch2);
3126 }
3127 __ lea(tmp, addr);
3128 (_masm->*add)(dst, inc, tmp);
3129 break;
3130 }
3131 case lir_xchg:
3132 {
3133 Register tmp = tmp_op->as_register();
3134 Register obj = as_reg(data);
3135 Register dst = as_reg(dest);
3136 if (is_oop && UseCompressedOops) {
3137 __ encode_heap_oop(rscratch2, obj);
3138 obj = rscratch2;
3139 }
3140 assert_different_registers(obj, addr.base(), tmp, rscratch1);
3141 assert_different_registers(dst, addr.base(), tmp, rscratch1);
3142 __ lea(tmp, addr);
3143 (_masm->*xchg)(dst, obj, tmp);
3144 if (is_oop && UseCompressedOops) {
3145 __ decode_heap_oop(dst);
3146 }
3147 }
3148 break;
3149 default:
3150 ShouldNotReachHere();
3151 }
3152 __ membar(__ AnyAny);
3153 }
3154
3155 #undef __