1 /*
2 * Copyright (c) 2000, 2025, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "asm/macroAssembler.hpp"
26 #include "asm/macroAssembler.inline.hpp"
27 #include "c1/c1_CodeStubs.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_Runtime1.hpp"
32 #include "c1/c1_ValueStack.hpp"
33 #include "ci/ciArrayKlass.hpp"
34 #include "ci/ciInstance.hpp"
35 #include "ci/ciUtilities.hpp"
36 #include "code/aotCodeCache.hpp"
37 #include "compiler/oopMap.hpp"
38 #include "gc/shared/collectedHeap.hpp"
39 #include "gc/shared/gc_globals.hpp"
40 #include "nativeInst_x86.hpp"
41 #include "oops/objArrayKlass.hpp"
42 #include "runtime/frame.inline.hpp"
43 #include "runtime/safepointMechanism.hpp"
44 #include "runtime/sharedRuntime.hpp"
45 #include "runtime/stubRoutines.hpp"
46 #include "utilities/powerOfTwo.hpp"
47 #include "vmreg_x86.inline.hpp"
48
49
50 // These masks are used to provide 128-bit aligned bitmasks to the XMM
51 // instructions, to allow sign-masking or sign-bit flipping. They allow
52 // fast versions of NegF/NegD and AbsF/AbsD.
53
54 // Note: 'double' and 'long long' have 32-bits alignment on x86.
55 static address double_quadword(jlong *adr, jlong lo, jlong hi) {
56 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
57 // of 128-bits operands for SSE instructions.
58 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
59 // Store the value to a 128-bits operand.
60 operand[0] = lo;
61 operand[1] = hi;
62 return (address)operand;
63 }
64
65 // Buffer for 128-bits masks used by SSE instructions.
66 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
67
68 // Static initialization during VM startup.
69 address LIR_Assembler::float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
70 address LIR_Assembler::double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
71 address LIR_Assembler::float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
72 address LIR_Assembler::double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
73
74
75 NEEDS_CLEANUP // remove this definitions ?
76 const Register SYNC_header = rax; // synchronization header
77 const Register SHIFT_count = rcx; // where count for shift operations must be
78
79 #define __ _masm->
80
81
82 static void select_different_registers(Register preserve,
83 Register extra,
84 Register &tmp1,
85 Register &tmp2) {
86 if (tmp1 == preserve) {
87 assert_different_registers(tmp1, tmp2, extra);
88 tmp1 = extra;
89 } else if (tmp2 == preserve) {
90 assert_different_registers(tmp1, tmp2, extra);
91 tmp2 = extra;
92 }
93 assert_different_registers(preserve, tmp1, tmp2);
94 }
95
96
97
98 static void select_different_registers(Register preserve,
99 Register extra,
100 Register &tmp1,
101 Register &tmp2,
102 Register &tmp3) {
103 if (tmp1 == preserve) {
104 assert_different_registers(tmp1, tmp2, tmp3, extra);
105 tmp1 = extra;
106 } else if (tmp2 == preserve) {
107 assert_different_registers(tmp1, tmp2, tmp3, extra);
108 tmp2 = extra;
109 } else if (tmp3 == preserve) {
110 assert_different_registers(tmp1, tmp2, tmp3, extra);
111 tmp3 = extra;
112 }
113 assert_different_registers(preserve, tmp1, tmp2, tmp3);
114 }
115
116
117
118 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
119 if (opr->is_constant()) {
120 LIR_Const* constant = opr->as_constant_ptr();
121 switch (constant->type()) {
122 case T_INT: {
123 return true;
124 }
125
126 default:
127 return false;
128 }
129 }
130 return false;
131 }
132
133
134 LIR_Opr LIR_Assembler::receiverOpr() {
135 return FrameMap::receiver_opr;
136 }
137
138 LIR_Opr LIR_Assembler::osrBufferPointer() {
139 return FrameMap::as_pointer_opr(receiverOpr()->as_register());
140 }
141
142 //--------------fpu register translations-----------------------
143
144
145 address LIR_Assembler::float_constant(float f) {
146 address const_addr = __ float_constant(f);
147 if (const_addr == nullptr) {
148 bailout("const section overflow");
149 return __ code()->consts()->start();
150 } else {
151 return const_addr;
152 }
153 }
154
155
156 address LIR_Assembler::double_constant(double d) {
157 address const_addr = __ double_constant(d);
158 if (const_addr == nullptr) {
159 bailout("const section overflow");
160 return __ code()->consts()->start();
161 } else {
162 return const_addr;
163 }
164 }
165
166 void LIR_Assembler::breakpoint() {
167 __ int3();
168 }
169
170 void LIR_Assembler::push(LIR_Opr opr) {
171 if (opr->is_single_cpu()) {
172 __ push_reg(opr->as_register());
173 } else if (opr->is_double_cpu()) {
174 __ push_reg(opr->as_register_lo());
175 } else if (opr->is_stack()) {
176 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
177 } else if (opr->is_constant()) {
178 LIR_Const* const_opr = opr->as_constant_ptr();
179 if (const_opr->type() == T_OBJECT) {
180 __ push_oop(const_opr->as_jobject(), rscratch1);
181 } else if (const_opr->type() == T_INT) {
182 __ push_jint(const_opr->as_jint());
183 } else {
184 ShouldNotReachHere();
185 }
186
187 } else {
188 ShouldNotReachHere();
189 }
190 }
191
192 void LIR_Assembler::pop(LIR_Opr opr) {
193 if (opr->is_single_cpu()) {
194 __ pop_reg(opr->as_register());
195 } else {
196 ShouldNotReachHere();
197 }
198 }
199
200 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
201 return addr->base()->is_illegal() && addr->index()->is_illegal();
202 }
203
204 //-------------------------------------------
205
206 Address LIR_Assembler::as_Address(LIR_Address* addr) {
207 return as_Address(addr, rscratch1);
208 }
209
210 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
211 if (addr->base()->is_illegal()) {
212 assert(addr->index()->is_illegal(), "must be illegal too");
213 AddressLiteral laddr((address)addr->disp(), relocInfo::none);
214 if (! __ reachable(laddr)) {
215 __ movptr(tmp, laddr.addr());
216 Address res(tmp, 0);
217 return res;
218 } else {
219 return __ as_Address(laddr);
220 }
221 }
222
223 Register base = addr->base()->as_pointer_register();
224
225 if (addr->index()->is_illegal()) {
226 return Address( base, addr->disp());
227 } else if (addr->index()->is_cpu_register()) {
228 Register index = addr->index()->as_pointer_register();
229 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
230 } else if (addr->index()->is_constant()) {
231 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
232 assert(Assembler::is_simm32(addr_offset), "must be");
233
234 return Address(base, addr_offset);
235 } else {
236 Unimplemented();
237 return Address();
238 }
239 }
240
241
242 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
243 Address base = as_Address(addr);
244 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
245 }
246
247
248 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
249 return as_Address(addr);
250 }
251
252
253 void LIR_Assembler::osr_entry() {
254 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
255 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
256 ValueStack* entry_state = osr_entry->state();
257 int number_of_locks = entry_state->locks_size();
258
259 // we jump here if osr happens with the interpreter
260 // state set up to continue at the beginning of the
261 // loop that triggered osr - in particular, we have
262 // the following registers setup:
263 //
264 // rcx: osr buffer
265 //
266
267 // build frame
268 ciMethod* m = compilation()->method();
269 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
270
271 // OSR buffer is
272 //
273 // locals[nlocals-1..0]
274 // monitors[0..number_of_locks]
275 //
276 // locals is a direct copy of the interpreter frame so in the osr buffer
277 // so first slot in the local array is the last local from the interpreter
278 // and last slot is local[0] (receiver) from the interpreter
279 //
280 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
281 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
282 // in the interpreter frame (the method lock if a sync method)
283
284 // Initialize monitors in the compiled activation.
285 // rcx: pointer to osr buffer
286 //
287 // All other registers are dead at this point and the locals will be
288 // copied into place by code emitted in the IR.
289
290 Register OSR_buf = osrBufferPointer()->as_pointer_register();
291 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
292 int monitor_offset = BytesPerWord * method()->max_locals() +
293 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
294 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
295 // the OSR buffer using 2 word entries: first the lock and then
296 // the oop.
297 for (int i = 0; i < number_of_locks; i++) {
298 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
299 #ifdef ASSERT
300 // verify the interpreter's monitor has a non-null object
301 {
302 Label L;
303 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), NULL_WORD);
304 __ jcc(Assembler::notZero, L);
305 __ stop("locked object is null");
306 __ bind(L);
307 }
308 #endif
309 __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
310 __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
311 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
312 __ movptr(frame_map()->address_for_monitor_object(i), rbx);
313 }
314 }
315 }
316
317
318 // inline cache check; done before the frame is built.
319 int LIR_Assembler::check_icache() {
320 return __ ic_check(CodeEntryAlignment);
321 }
322
323 void LIR_Assembler::clinit_barrier(ciMethod* method) {
324 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
325 assert(!method->holder()->is_not_initialized(), "initialization should have been started");
326
327 Label L_skip_barrier;
328 Register klass = rscratch1;
329
330 __ mov_metadata(klass, method->holder()->constant_encoding());
331 __ clinit_barrier(klass, &L_skip_barrier /*L_fast_path*/);
332
333 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
334
335 __ bind(L_skip_barrier);
336 }
337
338 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
339 jobject o = nullptr;
340 PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
341 __ movoop(reg, o);
342 patching_epilog(patch, lir_patch_normal, reg, info);
343 }
344
345 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
346 Metadata* o = nullptr;
347 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
348 __ mov_metadata(reg, o);
349 patching_epilog(patch, lir_patch_normal, reg, info);
350 }
351
352 // This specifies the rsp decrement needed to build the frame
353 int LIR_Assembler::initial_frame_size_in_bytes() const {
354 // if rounding, must let FrameMap know!
355
356 // The frame_map records size in slots (32bit word)
357
358 // subtract two words to account for return address and link
359 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size;
360 }
361
362
363 int LIR_Assembler::emit_exception_handler() {
364 // generate code for exception handler
365 address handler_base = __ start_a_stub(exception_handler_size());
366 if (handler_base == nullptr) {
367 // not enough space left for the handler
368 bailout("exception handler overflow");
369 return -1;
370 }
371
372 int offset = code_offset();
373
374 // the exception oop and pc are in rax, and rdx
375 // no other registers need to be preserved, so invalidate them
376 __ invalidate_registers(false, true, true, false, true, true);
377
378 // check that there is really an exception
379 __ verify_not_null_oop(rax);
380
381 // search an exception handler (rax: exception oop, rdx: throwing pc)
382 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::handle_exception_from_callee_id)));
383 __ should_not_reach_here();
384 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
385 __ end_a_stub();
386
387 return offset;
388 }
389
390
391 // Emit the code to remove the frame from the stack in the exception
392 // unwind path.
393 int LIR_Assembler::emit_unwind_handler() {
394 #ifndef PRODUCT
395 if (CommentedAssembly) {
396 _masm->block_comment("Unwind handler");
397 }
398 #endif
399
400 int offset = code_offset();
401
402 // Fetch the exception from TLS and clear out exception related thread state
403 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
404 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), NULL_WORD);
405 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), NULL_WORD);
406
407 __ bind(_unwind_handler_entry);
408 __ verify_not_null_oop(rax);
409 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
410 __ mov(rbx, rax); // Preserve the exception (rbx is always callee-saved)
411 }
412
413 // Perform needed unlocking
414 MonitorExitStub* stub = nullptr;
415 if (method()->is_synchronized()) {
416 monitor_address(0, FrameMap::rax_opr);
417 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
418 if (LockingMode == LM_MONITOR) {
419 __ jmp(*stub->entry());
420 } else {
421 __ unlock_object(rdi, rsi, rax, *stub->entry());
422 }
423 __ bind(*stub->continuation());
424 }
425
426 if (compilation()->env()->dtrace_method_probes()) {
427 __ mov(rdi, r15_thread);
428 __ mov_metadata(rsi, method()->constant_encoding());
429 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
430 }
431
432 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
433 __ mov(rax, rbx); // Restore the exception
434 }
435
436 // remove the activation and dispatch to the unwind handler
437 __ remove_frame(initial_frame_size_in_bytes());
438 __ jump(RuntimeAddress(Runtime1::entry_for(C1StubId::unwind_exception_id)));
439
440 // Emit the slow path assembly
441 if (stub != nullptr) {
442 stub->emit_code(this);
443 }
444
445 return offset;
446 }
447
448
449 int LIR_Assembler::emit_deopt_handler() {
450 // generate code for exception handler
451 address handler_base = __ start_a_stub(deopt_handler_size());
452 if (handler_base == nullptr) {
453 // not enough space left for the handler
454 bailout("deopt handler overflow");
455 return -1;
456 }
457
458 int offset = code_offset();
459 InternalAddress here(__ pc());
460
461 __ pushptr(here.addr(), rscratch1);
462 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
463 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
464 __ end_a_stub();
465
466 return offset;
467 }
468
469 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
470 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
471 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
472 assert(result->fpu() == 0, "result must already be on TOS");
473 }
474
475 // Pop the stack before the safepoint code
476 __ remove_frame(initial_frame_size_in_bytes());
477
478 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
479 __ reserved_stack_check();
480 }
481
482 // Note: we do not need to round double result; float result has the right precision
483 // the poll sets the condition code, but no data registers
484
485 code_stub->set_safepoint_offset(__ offset());
486 __ relocate(relocInfo::poll_return_type);
487 __ safepoint_poll(*code_stub->entry(), true /* at_return */, true /* in_nmethod */);
488 __ ret(0);
489 }
490
491
492 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
493 guarantee(info != nullptr, "Shouldn't be null");
494 int offset = __ offset();
495 const Register poll_addr = rscratch1;
496 __ movptr(poll_addr, Address(r15_thread, JavaThread::polling_page_offset()));
497 add_debug_info_for_branch(info);
498 __ relocate(relocInfo::poll_type);
499 address pre_pc = __ pc();
500 __ testl(rax, Address(poll_addr, 0));
501 address post_pc = __ pc();
502 guarantee(pointer_delta(post_pc, pre_pc, 1) == 3, "must be exact length");
503 return offset;
504 }
505
506
507 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
508 if (from_reg != to_reg) __ mov(to_reg, from_reg);
509 }
510
511 void LIR_Assembler::swap_reg(Register a, Register b) {
512 __ xchgptr(a, b);
513 }
514
515
516 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
517 assert(src->is_constant(), "should not call otherwise");
518 assert(dest->is_register(), "should not call otherwise");
519 LIR_Const* c = src->as_constant_ptr();
520
521 switch (c->type()) {
522 case T_INT: {
523 assert(patch_code == lir_patch_none, "no patching handled here");
524 __ movl(dest->as_register(), c->as_jint());
525 break;
526 }
527
528 case T_ADDRESS: {
529 assert(patch_code == lir_patch_none, "no patching handled here");
530 __ movptr(dest->as_register(), c->as_jint());
531 break;
532 }
533
534 case T_LONG: {
535 assert(patch_code == lir_patch_none, "no patching handled here");
536 if (AOTCodeCache::is_on_for_write()) {
537 // AOTCodeCache needs relocation info for card table base
538 address b = c->as_pointer();
539 if (is_card_table_address(b)) {
540 __ lea(dest->as_register_lo(), ExternalAddress(b));
541 break;
542 }
543 #if INCLUDE_CDS
544 if (AOTRuntimeConstants::contains(b)) {
545 __ load_aotrc_address(dest->as_register_lo(), b);
546 break;
547 }
548 #endif
549 }
550 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
551 break;
552 }
553
554 case T_OBJECT: {
555 if (patch_code != lir_patch_none) {
556 jobject2reg_with_patching(dest->as_register(), info);
557 } else {
558 __ movoop(dest->as_register(), c->as_jobject());
559 }
560 break;
561 }
562
563 case T_METADATA: {
564 if (patch_code != lir_patch_none) {
565 klass2reg_with_patching(dest->as_register(), info);
566 } else {
567 __ mov_metadata(dest->as_register(), c->as_metadata());
568 }
569 break;
570 }
571
572 case T_FLOAT: {
573 if (dest->is_single_xmm()) {
574 if (UseAVX <= 2 && c->is_zero_float()) {
575 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
576 } else {
577 __ movflt(dest->as_xmm_float_reg(),
578 InternalAddress(float_constant(c->as_jfloat())));
579 }
580 } else {
581 ShouldNotReachHere();
582 }
583 break;
584 }
585
586 case T_DOUBLE: {
587 if (dest->is_double_xmm()) {
588 if (UseAVX <= 2 && c->is_zero_double()) {
589 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
590 } else {
591 __ movdbl(dest->as_xmm_double_reg(),
592 InternalAddress(double_constant(c->as_jdouble())));
593 }
594 } else {
595 ShouldNotReachHere();
596 }
597 break;
598 }
599
600 default:
601 ShouldNotReachHere();
602 }
603 }
604
605 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
606 assert(src->is_constant(), "should not call otherwise");
607 assert(dest->is_stack(), "should not call otherwise");
608 LIR_Const* c = src->as_constant_ptr();
609
610 switch (c->type()) {
611 case T_INT: // fall through
612 case T_FLOAT:
613 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
614 break;
615
616 case T_ADDRESS:
617 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
618 break;
619
620 case T_OBJECT:
621 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject(), rscratch1);
622 break;
623
624 case T_LONG: // fall through
625 case T_DOUBLE:
626 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
627 lo_word_offset_in_bytes),
628 (intptr_t)c->as_jlong_bits(),
629 rscratch1);
630 break;
631
632 default:
633 ShouldNotReachHere();
634 }
635 }
636
637 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
638 assert(src->is_constant(), "should not call otherwise");
639 assert(dest->is_address(), "should not call otherwise");
640 LIR_Const* c = src->as_constant_ptr();
641 LIR_Address* addr = dest->as_address_ptr();
642
643 int null_check_here = code_offset();
644 switch (type) {
645 case T_INT: // fall through
646 case T_FLOAT:
647 __ movl(as_Address(addr), c->as_jint_bits());
648 break;
649
650 case T_ADDRESS:
651 __ movptr(as_Address(addr), c->as_jint_bits());
652 break;
653
654 case T_OBJECT: // fall through
655 case T_ARRAY:
656 if (c->as_jobject() == nullptr) {
657 if (UseCompressedOops && !wide) {
658 __ movl(as_Address(addr), NULL_WORD);
659 } else {
660 __ xorptr(rscratch1, rscratch1);
661 null_check_here = code_offset();
662 __ movptr(as_Address(addr), rscratch1);
663 }
664 } else {
665 if (is_literal_address(addr)) {
666 ShouldNotReachHere();
667 __ movoop(as_Address(addr, noreg), c->as_jobject(), rscratch1);
668 } else {
669 __ movoop(rscratch1, c->as_jobject());
670 if (UseCompressedOops && !wide) {
671 __ encode_heap_oop(rscratch1);
672 null_check_here = code_offset();
673 __ movl(as_Address_lo(addr), rscratch1);
674 } else {
675 null_check_here = code_offset();
676 __ movptr(as_Address_lo(addr), rscratch1);
677 }
678 }
679 }
680 break;
681
682 case T_LONG: // fall through
683 case T_DOUBLE:
684 if (is_literal_address(addr)) {
685 ShouldNotReachHere();
686 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
687 } else {
688 __ movptr(r10, (intptr_t)c->as_jlong_bits());
689 null_check_here = code_offset();
690 __ movptr(as_Address_lo(addr), r10);
691 }
692 break;
693
694 case T_BOOLEAN: // fall through
695 case T_BYTE:
696 __ movb(as_Address(addr), c->as_jint() & 0xFF);
697 break;
698
699 case T_CHAR: // fall through
700 case T_SHORT:
701 __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
702 break;
703
704 default:
705 ShouldNotReachHere();
706 };
707
708 if (info != nullptr) {
709 add_debug_info_for_null_check(null_check_here, info);
710 }
711 }
712
713
714 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
715 assert(src->is_register(), "should not call otherwise");
716 assert(dest->is_register(), "should not call otherwise");
717
718 // move between cpu-registers
719 if (dest->is_single_cpu()) {
720 if (src->type() == T_LONG) {
721 // Can do LONG -> OBJECT
722 move_regs(src->as_register_lo(), dest->as_register());
723 return;
724 }
725 assert(src->is_single_cpu(), "must match");
726 if (src->type() == T_OBJECT) {
727 __ verify_oop(src->as_register());
728 }
729 move_regs(src->as_register(), dest->as_register());
730
731 } else if (dest->is_double_cpu()) {
732 if (is_reference_type(src->type())) {
733 // Surprising to me but we can see move of a long to t_object
734 __ verify_oop(src->as_register());
735 move_regs(src->as_register(), dest->as_register_lo());
736 return;
737 }
738 assert(src->is_double_cpu(), "must match");
739 Register f_lo = src->as_register_lo();
740 Register f_hi = src->as_register_hi();
741 Register t_lo = dest->as_register_lo();
742 Register t_hi = dest->as_register_hi();
743 assert(f_hi == f_lo, "must be same");
744 assert(t_hi == t_lo, "must be same");
745 move_regs(f_lo, t_lo);
746
747 // move between xmm-registers
748 } else if (dest->is_single_xmm()) {
749 assert(src->is_single_xmm(), "must match");
750 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
751 } else if (dest->is_double_xmm()) {
752 assert(src->is_double_xmm(), "must match");
753 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
754
755 } else {
756 ShouldNotReachHere();
757 }
758 }
759
760 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
761 assert(src->is_register(), "should not call otherwise");
762 assert(dest->is_stack(), "should not call otherwise");
763
764 if (src->is_single_cpu()) {
765 Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
766 if (is_reference_type(type)) {
767 __ verify_oop(src->as_register());
768 __ movptr (dst, src->as_register());
769 } else if (type == T_METADATA || type == T_ADDRESS) {
770 __ movptr (dst, src->as_register());
771 } else {
772 __ movl (dst, src->as_register());
773 }
774
775 } else if (src->is_double_cpu()) {
776 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
777 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
778 __ movptr (dstLO, src->as_register_lo());
779
780 } else if (src->is_single_xmm()) {
781 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
782 __ movflt(dst_addr, src->as_xmm_float_reg());
783
784 } else if (src->is_double_xmm()) {
785 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
786 __ movdbl(dst_addr, src->as_xmm_double_reg());
787
788 } else {
789 ShouldNotReachHere();
790 }
791 }
792
793
794 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
795 LIR_Address* to_addr = dest->as_address_ptr();
796 PatchingStub* patch = nullptr;
797 Register compressed_src = rscratch1;
798
799 if (is_reference_type(type)) {
800 __ verify_oop(src->as_register());
801 if (UseCompressedOops && !wide) {
802 __ movptr(compressed_src, src->as_register());
803 __ encode_heap_oop(compressed_src);
804 if (patch_code != lir_patch_none) {
805 info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
806 }
807 }
808 }
809
810 if (patch_code != lir_patch_none) {
811 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
812 Address toa = as_Address(to_addr);
813 assert(toa.disp() != 0, "must have");
814 }
815
816 int null_check_here = code_offset();
817 switch (type) {
818 case T_FLOAT: {
819 assert(src->is_single_xmm(), "not a float");
820 __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
821 break;
822 }
823
824 case T_DOUBLE: {
825 assert(src->is_double_xmm(), "not a double");
826 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
827 break;
828 }
829
830 case T_ARRAY: // fall through
831 case T_OBJECT: // fall through
832 if (UseCompressedOops && !wide) {
833 __ movl(as_Address(to_addr), compressed_src);
834 } else {
835 __ movptr(as_Address(to_addr), src->as_register());
836 }
837 break;
838 case T_ADDRESS:
839 __ movptr(as_Address(to_addr), src->as_register());
840 break;
841 case T_INT:
842 __ movl(as_Address(to_addr), src->as_register());
843 break;
844
845 case T_LONG: {
846 Register from_lo = src->as_register_lo();
847 Register from_hi = src->as_register_hi();
848 __ movptr(as_Address_lo(to_addr), from_lo);
849 break;
850 }
851
852 case T_BYTE: // fall through
853 case T_BOOLEAN: {
854 Register src_reg = src->as_register();
855 Address dst_addr = as_Address(to_addr);
856 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
857 __ movb(dst_addr, src_reg);
858 break;
859 }
860
861 case T_CHAR: // fall through
862 case T_SHORT:
863 __ movw(as_Address(to_addr), src->as_register());
864 break;
865
866 default:
867 ShouldNotReachHere();
868 }
869 if (info != nullptr) {
870 add_debug_info_for_null_check(null_check_here, info);
871 }
872
873 if (patch_code != lir_patch_none) {
874 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
875 }
876 }
877
878
879 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
880 assert(src->is_stack(), "should not call otherwise");
881 assert(dest->is_register(), "should not call otherwise");
882
883 if (dest->is_single_cpu()) {
884 if (is_reference_type(type)) {
885 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
886 __ verify_oop(dest->as_register());
887 } else if (type == T_METADATA || type == T_ADDRESS) {
888 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
889 } else {
890 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
891 }
892
893 } else if (dest->is_double_cpu()) {
894 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
895 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
896 __ movptr(dest->as_register_lo(), src_addr_LO);
897
898 } else if (dest->is_single_xmm()) {
899 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
900 __ movflt(dest->as_xmm_float_reg(), src_addr);
901
902 } else if (dest->is_double_xmm()) {
903 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
904 __ movdbl(dest->as_xmm_double_reg(), src_addr);
905
906 } else {
907 ShouldNotReachHere();
908 }
909 }
910
911
912 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
913 if (src->is_single_stack()) {
914 if (is_reference_type(type)) {
915 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
916 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
917 } else {
918 //no pushl on 64bits
919 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
920 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
921 }
922
923 } else if (src->is_double_stack()) {
924 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
925 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
926
927 } else {
928 ShouldNotReachHere();
929 }
930 }
931
932
933 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
934 assert(src->is_address(), "should not call otherwise");
935 assert(dest->is_register(), "should not call otherwise");
936
937 LIR_Address* addr = src->as_address_ptr();
938 Address from_addr = as_Address(addr);
939
940 if (addr->base()->type() == T_OBJECT) {
941 __ verify_oop(addr->base()->as_pointer_register());
942 }
943
944 switch (type) {
945 case T_BOOLEAN: // fall through
946 case T_BYTE: // fall through
947 case T_CHAR: // fall through
948 case T_SHORT:
949 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
950 // on pre P6 processors we may get partial register stalls
951 // so blow away the value of to_rinfo before loading a
952 // partial word into it. Do it here so that it precedes
953 // the potential patch point below.
954 __ xorptr(dest->as_register(), dest->as_register());
955 }
956 break;
957 default:
958 break;
959 }
960
961 PatchingStub* patch = nullptr;
962 if (patch_code != lir_patch_none) {
963 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
964 assert(from_addr.disp() != 0, "must have");
965 }
966 if (info != nullptr) {
967 add_debug_info_for_null_check_here(info);
968 }
969
970 switch (type) {
971 case T_FLOAT: {
972 if (dest->is_single_xmm()) {
973 __ movflt(dest->as_xmm_float_reg(), from_addr);
974 } else {
975 ShouldNotReachHere();
976 }
977 break;
978 }
979
980 case T_DOUBLE: {
981 if (dest->is_double_xmm()) {
982 __ movdbl(dest->as_xmm_double_reg(), from_addr);
983 } else {
984 ShouldNotReachHere();
985 }
986 break;
987 }
988
989 case T_OBJECT: // fall through
990 case T_ARRAY: // fall through
991 if (UseCompressedOops && !wide) {
992 __ movl(dest->as_register(), from_addr);
993 } else {
994 __ movptr(dest->as_register(), from_addr);
995 }
996 break;
997
998 case T_ADDRESS:
999 __ movptr(dest->as_register(), from_addr);
1000 break;
1001 case T_INT:
1002 __ movl(dest->as_register(), from_addr);
1003 break;
1004
1005 case T_LONG: {
1006 Register to_lo = dest->as_register_lo();
1007 Register to_hi = dest->as_register_hi();
1008 __ movptr(to_lo, as_Address_lo(addr));
1009 break;
1010 }
1011
1012 case T_BOOLEAN: // fall through
1013 case T_BYTE: {
1014 Register dest_reg = dest->as_register();
1015 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1016 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1017 __ movsbl(dest_reg, from_addr);
1018 } else {
1019 __ movb(dest_reg, from_addr);
1020 __ shll(dest_reg, 24);
1021 __ sarl(dest_reg, 24);
1022 }
1023 break;
1024 }
1025
1026 case T_CHAR: {
1027 Register dest_reg = dest->as_register();
1028 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1029 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1030 __ movzwl(dest_reg, from_addr);
1031 } else {
1032 __ movw(dest_reg, from_addr);
1033 }
1034 break;
1035 }
1036
1037 case T_SHORT: {
1038 Register dest_reg = dest->as_register();
1039 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1040 __ movswl(dest_reg, from_addr);
1041 } else {
1042 __ movw(dest_reg, from_addr);
1043 __ shll(dest_reg, 16);
1044 __ sarl(dest_reg, 16);
1045 }
1046 break;
1047 }
1048
1049 default:
1050 ShouldNotReachHere();
1051 }
1052
1053 if (patch != nullptr) {
1054 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1055 }
1056
1057 if (is_reference_type(type)) {
1058 if (UseCompressedOops && !wide) {
1059 __ decode_heap_oop(dest->as_register());
1060 }
1061
1062 __ verify_oop(dest->as_register());
1063 }
1064 }
1065
1066
1067 NEEDS_CLEANUP; // This could be static?
1068 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1069 int elem_size = type2aelembytes(type);
1070 switch (elem_size) {
1071 case 1: return Address::times_1;
1072 case 2: return Address::times_2;
1073 case 4: return Address::times_4;
1074 case 8: return Address::times_8;
1075 }
1076 ShouldNotReachHere();
1077 return Address::no_scale;
1078 }
1079
1080
1081 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1082 switch (op->code()) {
1083 case lir_idiv:
1084 case lir_irem:
1085 arithmetic_idiv(op->code(),
1086 op->in_opr1(),
1087 op->in_opr2(),
1088 op->in_opr3(),
1089 op->result_opr(),
1090 op->info());
1091 break;
1092 case lir_fmad:
1093 __ fmad(op->result_opr()->as_xmm_double_reg(),
1094 op->in_opr1()->as_xmm_double_reg(),
1095 op->in_opr2()->as_xmm_double_reg(),
1096 op->in_opr3()->as_xmm_double_reg());
1097 break;
1098 case lir_fmaf:
1099 __ fmaf(op->result_opr()->as_xmm_float_reg(),
1100 op->in_opr1()->as_xmm_float_reg(),
1101 op->in_opr2()->as_xmm_float_reg(),
1102 op->in_opr3()->as_xmm_float_reg());
1103 break;
1104 default: ShouldNotReachHere(); break;
1105 }
1106 }
1107
1108 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1109 #ifdef ASSERT
1110 assert(op->block() == nullptr || op->block()->label() == op->label(), "wrong label");
1111 if (op->block() != nullptr) _branch_target_blocks.append(op->block());
1112 if (op->ublock() != nullptr) _branch_target_blocks.append(op->ublock());
1113 #endif
1114
1115 if (op->cond() == lir_cond_always) {
1116 if (op->info() != nullptr) add_debug_info_for_branch(op->info());
1117 __ jmp (*(op->label()));
1118 } else {
1119 Assembler::Condition acond = Assembler::zero;
1120 if (op->code() == lir_cond_float_branch) {
1121 assert(op->ublock() != nullptr, "must have unordered successor");
1122 __ jcc(Assembler::parity, *(op->ublock()->label()));
1123 switch(op->cond()) {
1124 case lir_cond_equal: acond = Assembler::equal; break;
1125 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1126 case lir_cond_less: acond = Assembler::below; break;
1127 case lir_cond_lessEqual: acond = Assembler::belowEqual; break;
1128 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1129 case lir_cond_greater: acond = Assembler::above; break;
1130 default: ShouldNotReachHere();
1131 }
1132 } else {
1133 switch (op->cond()) {
1134 case lir_cond_equal: acond = Assembler::equal; break;
1135 case lir_cond_notEqual: acond = Assembler::notEqual; break;
1136 case lir_cond_less: acond = Assembler::less; break;
1137 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
1138 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1139 case lir_cond_greater: acond = Assembler::greater; break;
1140 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
1141 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
1142 default: ShouldNotReachHere();
1143 }
1144 }
1145 __ jcc(acond,*(op->label()));
1146 }
1147 }
1148
1149 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1150 LIR_Opr src = op->in_opr();
1151 LIR_Opr dest = op->result_opr();
1152
1153 switch (op->bytecode()) {
1154 case Bytecodes::_i2l:
1155 __ movl2ptr(dest->as_register_lo(), src->as_register());
1156 break;
1157
1158 case Bytecodes::_l2i:
1159 __ movl(dest->as_register(), src->as_register_lo());
1160 break;
1161
1162 case Bytecodes::_i2b:
1163 move_regs(src->as_register(), dest->as_register());
1164 __ sign_extend_byte(dest->as_register());
1165 break;
1166
1167 case Bytecodes::_i2c:
1168 move_regs(src->as_register(), dest->as_register());
1169 __ andl(dest->as_register(), 0xFFFF);
1170 break;
1171
1172 case Bytecodes::_i2s:
1173 move_regs(src->as_register(), dest->as_register());
1174 __ sign_extend_short(dest->as_register());
1175 break;
1176
1177 case Bytecodes::_f2d:
1178 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1179 break;
1180
1181 case Bytecodes::_d2f:
1182 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1183 break;
1184
1185 case Bytecodes::_i2f:
1186 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1187 break;
1188
1189 case Bytecodes::_i2d:
1190 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1191 break;
1192
1193 case Bytecodes::_l2f:
1194 __ cvtsi2ssq(dest->as_xmm_float_reg(), src->as_register_lo());
1195 break;
1196
1197 case Bytecodes::_l2d:
1198 __ cvtsi2sdq(dest->as_xmm_double_reg(), src->as_register_lo());
1199 break;
1200
1201 case Bytecodes::_f2i:
1202 __ convert_f2i(dest->as_register(), src->as_xmm_float_reg());
1203 break;
1204
1205 case Bytecodes::_d2i:
1206 __ convert_d2i(dest->as_register(), src->as_xmm_double_reg());
1207 break;
1208
1209 case Bytecodes::_f2l:
1210 __ convert_f2l(dest->as_register_lo(), src->as_xmm_float_reg());
1211 break;
1212
1213 case Bytecodes::_d2l:
1214 __ convert_d2l(dest->as_register_lo(), src->as_xmm_double_reg());
1215 break;
1216
1217 default: ShouldNotReachHere();
1218 }
1219 }
1220
1221 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1222 if (op->init_check()) {
1223 add_debug_info_for_null_check_here(op->stub()->info());
1224 // init_state needs acquire, but x86 is TSO, and so we are already good.
1225 __ cmpb(Address(op->klass()->as_register(),
1226 InstanceKlass::init_state_offset()),
1227 InstanceKlass::fully_initialized);
1228 __ jcc(Assembler::notEqual, *op->stub()->entry());
1229 }
1230 __ allocate_object(op->obj()->as_register(),
1231 op->tmp1()->as_register(),
1232 op->tmp2()->as_register(),
1233 op->header_size(),
1234 op->object_size(),
1235 op->klass()->as_register(),
1236 *op->stub()->entry());
1237 __ bind(*op->stub()->continuation());
1238 }
1239
1240 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1241 Register len = op->len()->as_register();
1242 __ movslq(len, len);
1243
1244 if (UseSlowPath ||
1245 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1246 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1247 __ jmp(*op->stub()->entry());
1248 } else {
1249 Register tmp1 = op->tmp1()->as_register();
1250 Register tmp2 = op->tmp2()->as_register();
1251 Register tmp3 = op->tmp3()->as_register();
1252 if (len == tmp1) {
1253 tmp1 = tmp3;
1254 } else if (len == tmp2) {
1255 tmp2 = tmp3;
1256 } else if (len == tmp3) {
1257 // everything is ok
1258 } else {
1259 __ mov(tmp3, len);
1260 }
1261 __ allocate_array(op->obj()->as_register(),
1262 len,
1263 tmp1,
1264 tmp2,
1265 arrayOopDesc::base_offset_in_bytes(op->type()),
1266 array_element_size(op->type()),
1267 op->klass()->as_register(),
1268 *op->stub()->entry(),
1269 op->zero_array());
1270 }
1271 __ bind(*op->stub()->continuation());
1272 }
1273
1274 void LIR_Assembler::type_profile_helper(Register mdo,
1275 ciMethodData *md, ciProfileData *data,
1276 Register recv, Label* update_done) {
1277 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1278 Label next_test;
1279 // See if the receiver is receiver[n].
1280 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1281 __ jccb(Assembler::notEqual, next_test);
1282 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1283 __ addptr(data_addr, DataLayout::counter_increment);
1284 __ jmp(*update_done);
1285 __ bind(next_test);
1286 }
1287
1288 // Didn't find receiver; find next empty slot and fill it in
1289 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1290 Label next_test;
1291 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1292 __ cmpptr(recv_addr, NULL_WORD);
1293 __ jccb(Assembler::notEqual, next_test);
1294 __ movptr(recv_addr, recv);
1295 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1296 __ jmp(*update_done);
1297 __ bind(next_test);
1298 }
1299 }
1300
1301 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1302 // we always need a stub for the failure case.
1303 CodeStub* stub = op->stub();
1304 Register obj = op->object()->as_register();
1305 Register k_RInfo = op->tmp1()->as_register();
1306 Register klass_RInfo = op->tmp2()->as_register();
1307 Register dst = op->result_opr()->as_register();
1308 ciKlass* k = op->klass();
1309 Register Rtmp1 = noreg;
1310 Register tmp_load_klass = rscratch1;
1311
1312 // check if it needs to be profiled
1313 ciMethodData* md = nullptr;
1314 ciProfileData* data = nullptr;
1315
1316 if (op->should_profile()) {
1317 ciMethod* method = op->profiled_method();
1318 assert(method != nullptr, "Should have method");
1319 int bci = op->profiled_bci();
1320 md = method->method_data_or_null();
1321 assert(md != nullptr, "Sanity");
1322 data = md->bci_to_data(bci);
1323 assert(data != nullptr, "need data for type check");
1324 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1325 }
1326 Label* success_target = success;
1327 Label* failure_target = failure;
1328
1329 if (obj == k_RInfo) {
1330 k_RInfo = dst;
1331 } else if (obj == klass_RInfo) {
1332 klass_RInfo = dst;
1333 }
1334 if (k->is_loaded() && !UseCompressedClassPointers) {
1335 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1336 } else {
1337 Rtmp1 = op->tmp3()->as_register();
1338 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1339 }
1340
1341 assert_different_registers(obj, k_RInfo, klass_RInfo);
1342
1343 __ testptr(obj, obj);
1344 if (op->should_profile()) {
1345 Label not_null;
1346 Register mdo = klass_RInfo;
1347 __ mov_metadata(mdo, md->constant_encoding());
1348 __ jccb(Assembler::notEqual, not_null);
1349 // Object is null; update MDO and exit
1350 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1351 int header_bits = BitData::null_seen_byte_constant();
1352 __ orb(data_addr, header_bits);
1353 __ jmp(*obj_is_null);
1354 __ bind(not_null);
1355
1356 Label update_done;
1357 Register recv = k_RInfo;
1358 __ load_klass(recv, obj, tmp_load_klass);
1359 type_profile_helper(mdo, md, data, recv, &update_done);
1360
1361 Address nonprofiled_receiver_count_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1362 __ addptr(nonprofiled_receiver_count_addr, DataLayout::counter_increment);
1363
1364 __ bind(update_done);
1365 } else {
1366 __ jcc(Assembler::equal, *obj_is_null);
1367 }
1368
1369 if (!k->is_loaded()) {
1370 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1371 } else {
1372 __ mov_metadata(k_RInfo, k->constant_encoding());
1373 }
1374 __ verify_oop(obj);
1375
1376 if (op->fast_check()) {
1377 // get object class
1378 // not a safepoint as obj null check happens earlier
1379 if (UseCompressedClassPointers) {
1380 __ load_klass(Rtmp1, obj, tmp_load_klass);
1381 __ cmpptr(k_RInfo, Rtmp1);
1382 } else {
1383 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1384 }
1385 __ jcc(Assembler::notEqual, *failure_target);
1386 // successful cast, fall through to profile or jump
1387 } else {
1388 // get object class
1389 // not a safepoint as obj null check happens earlier
1390 __ load_klass(klass_RInfo, obj, tmp_load_klass);
1391 if (k->is_loaded()) {
1392 // See if we get an immediate positive hit
1393 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1394 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1395 __ jcc(Assembler::notEqual, *failure_target);
1396 // successful cast, fall through to profile or jump
1397 } else {
1398 // See if we get an immediate positive hit
1399 __ jcc(Assembler::equal, *success_target);
1400 // check for self
1401 __ cmpptr(klass_RInfo, k_RInfo);
1402 __ jcc(Assembler::equal, *success_target);
1403
1404 __ push(klass_RInfo);
1405 __ push(k_RInfo);
1406 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1407 __ pop(klass_RInfo);
1408 __ pop(klass_RInfo);
1409 // result is a boolean
1410 __ testl(klass_RInfo, klass_RInfo);
1411 __ jcc(Assembler::equal, *failure_target);
1412 // successful cast, fall through to profile or jump
1413 }
1414 } else {
1415 // perform the fast part of the checking logic
1416 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1417 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1418 __ push(klass_RInfo);
1419 __ push(k_RInfo);
1420 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1421 __ pop(klass_RInfo);
1422 __ pop(k_RInfo);
1423 // result is a boolean
1424 __ testl(k_RInfo, k_RInfo);
1425 __ jcc(Assembler::equal, *failure_target);
1426 // successful cast, fall through to profile or jump
1427 }
1428 }
1429 __ jmp(*success);
1430 }
1431
1432
1433 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1434 Register tmp_load_klass = rscratch1;
1435 LIR_Code code = op->code();
1436 if (code == lir_store_check) {
1437 Register value = op->object()->as_register();
1438 Register array = op->array()->as_register();
1439 Register k_RInfo = op->tmp1()->as_register();
1440 Register klass_RInfo = op->tmp2()->as_register();
1441 Register Rtmp1 = op->tmp3()->as_register();
1442
1443 CodeStub* stub = op->stub();
1444
1445 // check if it needs to be profiled
1446 ciMethodData* md = nullptr;
1447 ciProfileData* data = nullptr;
1448
1449 if (op->should_profile()) {
1450 ciMethod* method = op->profiled_method();
1451 assert(method != nullptr, "Should have method");
1452 int bci = op->profiled_bci();
1453 md = method->method_data_or_null();
1454 assert(md != nullptr, "Sanity");
1455 data = md->bci_to_data(bci);
1456 assert(data != nullptr, "need data for type check");
1457 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1458 }
1459 Label done;
1460 Label* success_target = &done;
1461 Label* failure_target = stub->entry();
1462
1463 __ testptr(value, value);
1464 if (op->should_profile()) {
1465 Label not_null;
1466 Register mdo = klass_RInfo;
1467 __ mov_metadata(mdo, md->constant_encoding());
1468 __ jccb(Assembler::notEqual, not_null);
1469 // Object is null; update MDO and exit
1470 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1471 int header_bits = BitData::null_seen_byte_constant();
1472 __ orb(data_addr, header_bits);
1473 __ jmp(done);
1474 __ bind(not_null);
1475
1476 Label update_done;
1477 Register recv = k_RInfo;
1478 __ load_klass(recv, value, tmp_load_klass);
1479 type_profile_helper(mdo, md, data, recv, &update_done);
1480
1481 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1482 __ addptr(counter_addr, DataLayout::counter_increment);
1483 __ bind(update_done);
1484 } else {
1485 __ jcc(Assembler::equal, done);
1486 }
1487
1488 add_debug_info_for_null_check_here(op->info_for_exception());
1489 __ load_klass(k_RInfo, array, tmp_load_klass);
1490 __ load_klass(klass_RInfo, value, tmp_load_klass);
1491
1492 // get instance klass (it's already uncompressed)
1493 __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1494 // perform the fast part of the checking logic
1495 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, nullptr);
1496 // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1497 __ push(klass_RInfo);
1498 __ push(k_RInfo);
1499 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
1500 __ pop(klass_RInfo);
1501 __ pop(k_RInfo);
1502 // result is a boolean
1503 __ testl(k_RInfo, k_RInfo);
1504 __ jcc(Assembler::equal, *failure_target);
1505 // fall through to the success case
1506
1507 __ bind(done);
1508 } else
1509 if (code == lir_checkcast) {
1510 Register obj = op->object()->as_register();
1511 Register dst = op->result_opr()->as_register();
1512 Label success;
1513 emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1514 __ bind(success);
1515 if (dst != obj) {
1516 __ mov(dst, obj);
1517 }
1518 } else
1519 if (code == lir_instanceof) {
1520 Register obj = op->object()->as_register();
1521 Register dst = op->result_opr()->as_register();
1522 Label success, failure, done;
1523 emit_typecheck_helper(op, &success, &failure, &failure);
1524 __ bind(failure);
1525 __ xorptr(dst, dst);
1526 __ jmpb(done);
1527 __ bind(success);
1528 __ movptr(dst, 1);
1529 __ bind(done);
1530 } else {
1531 ShouldNotReachHere();
1532 }
1533
1534 }
1535
1536
1537 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1538 if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
1539 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1540 Register newval = op->new_value()->as_register();
1541 Register cmpval = op->cmp_value()->as_register();
1542 assert(cmpval == rax, "wrong register");
1543 assert(newval != noreg, "new val must be register");
1544 assert(cmpval != newval, "cmp and new values must be in different registers");
1545 assert(cmpval != addr, "cmp and addr must be in different registers");
1546 assert(newval != addr, "new value and addr must be in different registers");
1547
1548 if (op->code() == lir_cas_obj) {
1549 if (UseCompressedOops) {
1550 __ encode_heap_oop(cmpval);
1551 __ mov(rscratch1, newval);
1552 __ encode_heap_oop(rscratch1);
1553 __ lock();
1554 // cmpval (rax) is implicitly used by this instruction
1555 __ cmpxchgl(rscratch1, Address(addr, 0));
1556 } else {
1557 __ lock();
1558 __ cmpxchgptr(newval, Address(addr, 0));
1559 }
1560 } else {
1561 assert(op->code() == lir_cas_int, "lir_cas_int expected");
1562 __ lock();
1563 __ cmpxchgl(newval, Address(addr, 0));
1564 }
1565 } else if (op->code() == lir_cas_long) {
1566 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1567 Register newval = op->new_value()->as_register_lo();
1568 Register cmpval = op->cmp_value()->as_register_lo();
1569 assert(cmpval == rax, "wrong register");
1570 assert(newval != noreg, "new val must be register");
1571 assert(cmpval != newval, "cmp and new values must be in different registers");
1572 assert(cmpval != addr, "cmp and addr must be in different registers");
1573 assert(newval != addr, "new value and addr must be in different registers");
1574 __ lock();
1575 __ cmpxchgq(newval, Address(addr, 0));
1576 } else {
1577 Unimplemented();
1578 }
1579 }
1580
1581 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
1582 LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
1583 assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on x86");
1584
1585 Assembler::Condition acond, ncond;
1586 switch (condition) {
1587 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
1588 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break;
1589 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break;
1590 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break;
1591 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break;
1592 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break;
1593 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break;
1594 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break;
1595 default: acond = Assembler::equal; ncond = Assembler::notEqual;
1596 ShouldNotReachHere();
1597 }
1598
1599 if (opr1->is_cpu_register()) {
1600 reg2reg(opr1, result);
1601 } else if (opr1->is_stack()) {
1602 stack2reg(opr1, result, result->type());
1603 } else if (opr1->is_constant()) {
1604 const2reg(opr1, result, lir_patch_none, nullptr);
1605 } else {
1606 ShouldNotReachHere();
1607 }
1608
1609 if (VM_Version::supports_cmov() && !opr2->is_constant()) {
1610 // optimized version that does not require a branch
1611 if (opr2->is_single_cpu()) {
1612 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
1613 __ cmov(ncond, result->as_register(), opr2->as_register());
1614 } else if (opr2->is_double_cpu()) {
1615 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1616 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1617 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
1618 } else if (opr2->is_single_stack()) {
1619 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
1620 } else if (opr2->is_double_stack()) {
1621 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
1622 } else {
1623 ShouldNotReachHere();
1624 }
1625
1626 } else {
1627 Label skip;
1628 __ jccb(acond, skip);
1629 if (opr2->is_cpu_register()) {
1630 reg2reg(opr2, result);
1631 } else if (opr2->is_stack()) {
1632 stack2reg(opr2, result, result->type());
1633 } else if (opr2->is_constant()) {
1634 const2reg(opr2, result, lir_patch_none, nullptr);
1635 } else {
1636 ShouldNotReachHere();
1637 }
1638 __ bind(skip);
1639 }
1640 }
1641
1642
1643 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info) {
1644 assert(info == nullptr, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1645
1646 if (left->is_single_cpu()) {
1647 assert(left == dest, "left and dest must be equal");
1648 Register lreg = left->as_register();
1649
1650 if (right->is_single_cpu()) {
1651 // cpu register - cpu register
1652 Register rreg = right->as_register();
1653 switch (code) {
1654 case lir_add: __ addl (lreg, rreg); break;
1655 case lir_sub: __ subl (lreg, rreg); break;
1656 case lir_mul: __ imull(lreg, rreg); break;
1657 default: ShouldNotReachHere();
1658 }
1659
1660 } else if (right->is_stack()) {
1661 // cpu register - stack
1662 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
1663 switch (code) {
1664 case lir_add: __ addl(lreg, raddr); break;
1665 case lir_sub: __ subl(lreg, raddr); break;
1666 default: ShouldNotReachHere();
1667 }
1668
1669 } else if (right->is_constant()) {
1670 // cpu register - constant
1671 jint c = right->as_constant_ptr()->as_jint();
1672 switch (code) {
1673 case lir_add: {
1674 __ incrementl(lreg, c);
1675 break;
1676 }
1677 case lir_sub: {
1678 __ decrementl(lreg, c);
1679 break;
1680 }
1681 default: ShouldNotReachHere();
1682 }
1683
1684 } else {
1685 ShouldNotReachHere();
1686 }
1687
1688 } else if (left->is_double_cpu()) {
1689 assert(left == dest, "left and dest must be equal");
1690 Register lreg_lo = left->as_register_lo();
1691 Register lreg_hi = left->as_register_hi();
1692
1693 if (right->is_double_cpu()) {
1694 // cpu register - cpu register
1695 Register rreg_lo = right->as_register_lo();
1696 Register rreg_hi = right->as_register_hi();
1697 assert_different_registers(lreg_lo, rreg_lo);
1698 switch (code) {
1699 case lir_add:
1700 __ addptr(lreg_lo, rreg_lo);
1701 break;
1702 case lir_sub:
1703 __ subptr(lreg_lo, rreg_lo);
1704 break;
1705 case lir_mul:
1706 __ imulq(lreg_lo, rreg_lo);
1707 break;
1708 default:
1709 ShouldNotReachHere();
1710 }
1711
1712 } else if (right->is_constant()) {
1713 // cpu register - constant
1714 jlong c = right->as_constant_ptr()->as_jlong_bits();
1715 __ movptr(r10, (intptr_t) c);
1716 switch (code) {
1717 case lir_add:
1718 __ addptr(lreg_lo, r10);
1719 break;
1720 case lir_sub:
1721 __ subptr(lreg_lo, r10);
1722 break;
1723 default:
1724 ShouldNotReachHere();
1725 }
1726
1727 } else {
1728 ShouldNotReachHere();
1729 }
1730
1731 } else if (left->is_single_xmm()) {
1732 assert(left == dest, "left and dest must be equal");
1733 XMMRegister lreg = left->as_xmm_float_reg();
1734
1735 if (right->is_single_xmm()) {
1736 XMMRegister rreg = right->as_xmm_float_reg();
1737 switch (code) {
1738 case lir_add: __ addss(lreg, rreg); break;
1739 case lir_sub: __ subss(lreg, rreg); break;
1740 case lir_mul: __ mulss(lreg, rreg); break;
1741 case lir_div: __ divss(lreg, rreg); break;
1742 default: ShouldNotReachHere();
1743 }
1744 } else {
1745 Address raddr;
1746 if (right->is_single_stack()) {
1747 raddr = frame_map()->address_for_slot(right->single_stack_ix());
1748 } else if (right->is_constant()) {
1749 // hack for now
1750 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
1751 } else {
1752 ShouldNotReachHere();
1753 }
1754 switch (code) {
1755 case lir_add: __ addss(lreg, raddr); break;
1756 case lir_sub: __ subss(lreg, raddr); break;
1757 case lir_mul: __ mulss(lreg, raddr); break;
1758 case lir_div: __ divss(lreg, raddr); break;
1759 default: ShouldNotReachHere();
1760 }
1761 }
1762
1763 } else if (left->is_double_xmm()) {
1764 assert(left == dest, "left and dest must be equal");
1765
1766 XMMRegister lreg = left->as_xmm_double_reg();
1767 if (right->is_double_xmm()) {
1768 XMMRegister rreg = right->as_xmm_double_reg();
1769 switch (code) {
1770 case lir_add: __ addsd(lreg, rreg); break;
1771 case lir_sub: __ subsd(lreg, rreg); break;
1772 case lir_mul: __ mulsd(lreg, rreg); break;
1773 case lir_div: __ divsd(lreg, rreg); break;
1774 default: ShouldNotReachHere();
1775 }
1776 } else {
1777 Address raddr;
1778 if (right->is_double_stack()) {
1779 raddr = frame_map()->address_for_slot(right->double_stack_ix());
1780 } else if (right->is_constant()) {
1781 // hack for now
1782 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
1783 } else {
1784 ShouldNotReachHere();
1785 }
1786 switch (code) {
1787 case lir_add: __ addsd(lreg, raddr); break;
1788 case lir_sub: __ subsd(lreg, raddr); break;
1789 case lir_mul: __ mulsd(lreg, raddr); break;
1790 case lir_div: __ divsd(lreg, raddr); break;
1791 default: ShouldNotReachHere();
1792 }
1793 }
1794
1795 } else if (left->is_single_stack() || left->is_address()) {
1796 assert(left == dest, "left and dest must be equal");
1797
1798 Address laddr;
1799 if (left->is_single_stack()) {
1800 laddr = frame_map()->address_for_slot(left->single_stack_ix());
1801 } else if (left->is_address()) {
1802 laddr = as_Address(left->as_address_ptr());
1803 } else {
1804 ShouldNotReachHere();
1805 }
1806
1807 if (right->is_single_cpu()) {
1808 Register rreg = right->as_register();
1809 switch (code) {
1810 case lir_add: __ addl(laddr, rreg); break;
1811 case lir_sub: __ subl(laddr, rreg); break;
1812 default: ShouldNotReachHere();
1813 }
1814 } else if (right->is_constant()) {
1815 jint c = right->as_constant_ptr()->as_jint();
1816 switch (code) {
1817 case lir_add: {
1818 __ incrementl(laddr, c);
1819 break;
1820 }
1821 case lir_sub: {
1822 __ decrementl(laddr, c);
1823 break;
1824 }
1825 default: ShouldNotReachHere();
1826 }
1827 } else {
1828 ShouldNotReachHere();
1829 }
1830
1831 } else {
1832 ShouldNotReachHere();
1833 }
1834 }
1835
1836
1837 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
1838 if (value->is_double_xmm()) {
1839 switch(code) {
1840 case lir_abs :
1841 {
1842 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
1843 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
1844 }
1845 assert(!tmp->is_valid(), "do not need temporary");
1846 __ andpd(dest->as_xmm_double_reg(),
1847 ExternalAddress(LIR_Assembler::double_signmask_pool),
1848 rscratch1);
1849 }
1850 break;
1851
1852 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
1853 // all other intrinsics are not available in the SSE instruction set, so FPU is used
1854 default : ShouldNotReachHere();
1855 }
1856
1857 } else if (code == lir_f2hf) {
1858 __ flt_to_flt16(dest->as_register(), value->as_xmm_float_reg(), tmp->as_xmm_float_reg());
1859 } else if (code == lir_hf2f) {
1860 __ flt16_to_flt(dest->as_xmm_float_reg(), value->as_register());
1861 } else {
1862 Unimplemented();
1863 }
1864 }
1865
1866 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1867 // assert(left->destroys_register(), "check");
1868 if (left->is_single_cpu()) {
1869 Register reg = left->as_register();
1870 if (right->is_constant()) {
1871 int val = right->as_constant_ptr()->as_jint();
1872 switch (code) {
1873 case lir_logic_and: __ andl (reg, val); break;
1874 case lir_logic_or: __ orl (reg, val); break;
1875 case lir_logic_xor: __ xorl (reg, val); break;
1876 default: ShouldNotReachHere();
1877 }
1878 } else if (right->is_stack()) {
1879 // added support for stack operands
1880 Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
1881 switch (code) {
1882 case lir_logic_and: __ andl (reg, raddr); break;
1883 case lir_logic_or: __ orl (reg, raddr); break;
1884 case lir_logic_xor: __ xorl (reg, raddr); break;
1885 default: ShouldNotReachHere();
1886 }
1887 } else {
1888 Register rright = right->as_register();
1889 switch (code) {
1890 case lir_logic_and: __ andptr (reg, rright); break;
1891 case lir_logic_or : __ orptr (reg, rright); break;
1892 case lir_logic_xor: __ xorptr (reg, rright); break;
1893 default: ShouldNotReachHere();
1894 }
1895 }
1896 move_regs(reg, dst->as_register());
1897 } else {
1898 Register l_lo = left->as_register_lo();
1899 Register l_hi = left->as_register_hi();
1900 if (right->is_constant()) {
1901 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
1902 switch (code) {
1903 case lir_logic_and:
1904 __ andq(l_lo, rscratch1);
1905 break;
1906 case lir_logic_or:
1907 __ orq(l_lo, rscratch1);
1908 break;
1909 case lir_logic_xor:
1910 __ xorq(l_lo, rscratch1);
1911 break;
1912 default: ShouldNotReachHere();
1913 }
1914 } else {
1915 Register r_lo;
1916 if (is_reference_type(right->type())) {
1917 r_lo = right->as_register();
1918 } else {
1919 r_lo = right->as_register_lo();
1920 }
1921 switch (code) {
1922 case lir_logic_and:
1923 __ andptr(l_lo, r_lo);
1924 break;
1925 case lir_logic_or:
1926 __ orptr(l_lo, r_lo);
1927 break;
1928 case lir_logic_xor:
1929 __ xorptr(l_lo, r_lo);
1930 break;
1931 default: ShouldNotReachHere();
1932 }
1933 }
1934
1935 Register dst_lo = dst->as_register_lo();
1936 Register dst_hi = dst->as_register_hi();
1937
1938 move_regs(l_lo, dst_lo);
1939 }
1940 }
1941
1942
1943 // we assume that rax, and rdx can be overwritten
1944 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
1945
1946 assert(left->is_single_cpu(), "left must be register");
1947 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant");
1948 assert(result->is_single_cpu(), "result must be register");
1949
1950 // assert(left->destroys_register(), "check");
1951 // assert(right->destroys_register(), "check");
1952
1953 Register lreg = left->as_register();
1954 Register dreg = result->as_register();
1955
1956 if (right->is_constant()) {
1957 jint divisor = right->as_constant_ptr()->as_jint();
1958 assert(divisor > 0 && is_power_of_2(divisor), "must be");
1959 if (code == lir_idiv) {
1960 assert(lreg == rax, "must be rax,");
1961 assert(temp->as_register() == rdx, "tmp register must be rdx");
1962 __ cdql(); // sign extend into rdx:rax
1963 if (divisor == 2) {
1964 __ subl(lreg, rdx);
1965 } else {
1966 __ andl(rdx, divisor - 1);
1967 __ addl(lreg, rdx);
1968 }
1969 __ sarl(lreg, log2i_exact(divisor));
1970 move_regs(lreg, dreg);
1971 } else if (code == lir_irem) {
1972 Label done;
1973 __ mov(dreg, lreg);
1974 __ andl(dreg, 0x80000000 | (divisor - 1));
1975 __ jcc(Assembler::positive, done);
1976 __ decrement(dreg);
1977 __ orl(dreg, ~(divisor - 1));
1978 __ increment(dreg);
1979 __ bind(done);
1980 } else {
1981 ShouldNotReachHere();
1982 }
1983 } else {
1984 Register rreg = right->as_register();
1985 assert(lreg == rax, "left register must be rax,");
1986 assert(rreg != rdx, "right register must not be rdx");
1987 assert(temp->as_register() == rdx, "tmp register must be rdx");
1988
1989 move_regs(lreg, rax);
1990
1991 int idivl_offset = __ corrected_idivl(rreg);
1992 if (ImplicitDiv0Checks) {
1993 add_debug_info_for_div0(idivl_offset, info);
1994 }
1995 if (code == lir_irem) {
1996 move_regs(rdx, dreg); // result is in rdx
1997 } else {
1998 move_regs(rax, dreg);
1999 }
2000 }
2001 }
2002
2003
2004 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2005 if (opr1->is_single_cpu()) {
2006 Register reg1 = opr1->as_register();
2007 if (opr2->is_single_cpu()) {
2008 // cpu register - cpu register
2009 if (is_reference_type(opr1->type())) {
2010 __ cmpoop(reg1, opr2->as_register());
2011 } else {
2012 assert(!is_reference_type(opr2->type()), "cmp int, oop?");
2013 __ cmpl(reg1, opr2->as_register());
2014 }
2015 } else if (opr2->is_stack()) {
2016 // cpu register - stack
2017 if (is_reference_type(opr1->type())) {
2018 __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2019 } else {
2020 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2021 }
2022 } else if (opr2->is_constant()) {
2023 // cpu register - constant
2024 LIR_Const* c = opr2->as_constant_ptr();
2025 if (c->type() == T_INT) {
2026 jint i = c->as_jint();
2027 if (i == 0) {
2028 __ testl(reg1, reg1);
2029 } else {
2030 __ cmpl(reg1, i);
2031 }
2032 } else if (c->type() == T_METADATA) {
2033 // All we need for now is a comparison with null for equality.
2034 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
2035 Metadata* m = c->as_metadata();
2036 if (m == nullptr) {
2037 __ testptr(reg1, reg1);
2038 } else {
2039 ShouldNotReachHere();
2040 }
2041 } else if (is_reference_type(c->type())) {
2042 // In 64bit oops are single register
2043 jobject o = c->as_jobject();
2044 if (o == nullptr) {
2045 __ testptr(reg1, reg1);
2046 } else {
2047 __ cmpoop(reg1, o, rscratch1);
2048 }
2049 } else {
2050 fatal("unexpected type: %s", basictype_to_str(c->type()));
2051 }
2052 // cpu register - address
2053 } else if (opr2->is_address()) {
2054 if (op->info() != nullptr) {
2055 add_debug_info_for_null_check_here(op->info());
2056 }
2057 __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2058 } else {
2059 ShouldNotReachHere();
2060 }
2061
2062 } else if(opr1->is_double_cpu()) {
2063 Register xlo = opr1->as_register_lo();
2064 Register xhi = opr1->as_register_hi();
2065 if (opr2->is_double_cpu()) {
2066 __ cmpptr(xlo, opr2->as_register_lo());
2067 } else if (opr2->is_constant()) {
2068 // cpu register - constant 0
2069 assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2070 __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2071 } else {
2072 ShouldNotReachHere();
2073 }
2074
2075 } else if (opr1->is_single_xmm()) {
2076 XMMRegister reg1 = opr1->as_xmm_float_reg();
2077 if (opr2->is_single_xmm()) {
2078 // xmm register - xmm register
2079 __ ucomiss(reg1, opr2->as_xmm_float_reg());
2080 } else if (opr2->is_stack()) {
2081 // xmm register - stack
2082 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2083 } else if (opr2->is_constant()) {
2084 // xmm register - constant
2085 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2086 } else if (opr2->is_address()) {
2087 // xmm register - address
2088 if (op->info() != nullptr) {
2089 add_debug_info_for_null_check_here(op->info());
2090 }
2091 __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2092 } else {
2093 ShouldNotReachHere();
2094 }
2095
2096 } else if (opr1->is_double_xmm()) {
2097 XMMRegister reg1 = opr1->as_xmm_double_reg();
2098 if (opr2->is_double_xmm()) {
2099 // xmm register - xmm register
2100 __ ucomisd(reg1, opr2->as_xmm_double_reg());
2101 } else if (opr2->is_stack()) {
2102 // xmm register - stack
2103 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2104 } else if (opr2->is_constant()) {
2105 // xmm register - constant
2106 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2107 } else if (opr2->is_address()) {
2108 // xmm register - address
2109 if (op->info() != nullptr) {
2110 add_debug_info_for_null_check_here(op->info());
2111 }
2112 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2113 } else {
2114 ShouldNotReachHere();
2115 }
2116
2117 } else if (opr1->is_address() && opr2->is_constant()) {
2118 LIR_Const* c = opr2->as_constant_ptr();
2119 if (is_reference_type(c->type())) {
2120 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2121 __ movoop(rscratch1, c->as_jobject());
2122 }
2123 if (op->info() != nullptr) {
2124 add_debug_info_for_null_check_here(op->info());
2125 }
2126 // special case: address - constant
2127 LIR_Address* addr = opr1->as_address_ptr();
2128 if (c->type() == T_INT) {
2129 __ cmpl(as_Address(addr), c->as_jint());
2130 } else if (is_reference_type(c->type())) {
2131 // %%% Make this explode if addr isn't reachable until we figure out a
2132 // better strategy by giving noreg as the temp for as_Address
2133 __ cmpoop(rscratch1, as_Address(addr, noreg));
2134 } else {
2135 ShouldNotReachHere();
2136 }
2137
2138 } else {
2139 ShouldNotReachHere();
2140 }
2141 }
2142
2143 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2144 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2145 if (left->is_single_xmm()) {
2146 assert(right->is_single_xmm(), "must match");
2147 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2148 } else if (left->is_double_xmm()) {
2149 assert(right->is_double_xmm(), "must match");
2150 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2151
2152 } else {
2153 ShouldNotReachHere();
2154 }
2155 } else {
2156 assert(code == lir_cmp_l2i, "check");
2157 Label done;
2158 Register dest = dst->as_register();
2159 __ cmpptr(left->as_register_lo(), right->as_register_lo());
2160 __ movl(dest, -1);
2161 __ jccb(Assembler::less, done);
2162 __ setb(Assembler::notZero, dest);
2163 __ movzbl(dest, dest);
2164 __ bind(done);
2165 }
2166 }
2167
2168
2169 void LIR_Assembler::align_call(LIR_Code code) {
2170 // make sure that the displacement word of the call ends up word aligned
2171 int offset = __ offset();
2172 switch (code) {
2173 case lir_static_call:
2174 case lir_optvirtual_call:
2175 case lir_dynamic_call:
2176 offset += NativeCall::displacement_offset;
2177 break;
2178 case lir_icvirtual_call:
2179 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size_rex;
2180 break;
2181 default: ShouldNotReachHere();
2182 }
2183 __ align(BytesPerWord, offset);
2184 }
2185
2186
2187 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2188 assert((__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2189 "must be aligned");
2190 __ call(AddressLiteral(op->addr(), rtype));
2191 add_call_info(code_offset(), op->info());
2192 __ post_call_nop();
2193 }
2194
2195
2196 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2197 __ ic_call(op->addr());
2198 add_call_info(code_offset(), op->info());
2199 assert((__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2200 "must be aligned");
2201 __ post_call_nop();
2202 }
2203
2204
2205 void LIR_Assembler::emit_static_call_stub() {
2206 address call_pc = __ pc();
2207 address stub = __ start_a_stub(call_stub_size());
2208 if (stub == nullptr) {
2209 bailout("static call stub overflow");
2210 return;
2211 }
2212
2213 int start = __ offset();
2214
2215 // make sure that the displacement word of the call ends up word aligned
2216 __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size_rex + NativeCall::displacement_offset);
2217 __ relocate(static_stub_Relocation::spec(call_pc));
2218 __ mov_metadata(rbx, (Metadata*)nullptr);
2219 // must be set to -1 at code generation time
2220 assert(((__ offset() + 1) % BytesPerWord) == 0, "must be aligned");
2221 // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2222 __ jump(RuntimeAddress(__ pc()));
2223
2224 assert(__ offset() - start <= call_stub_size(), "stub too big");
2225 __ end_a_stub();
2226 }
2227
2228
2229 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2230 assert(exceptionOop->as_register() == rax, "must match");
2231 assert(exceptionPC->as_register() == rdx, "must match");
2232
2233 // exception object is not added to oop map by LinearScan
2234 // (LinearScan assumes that no oops are in fixed registers)
2235 info->add_register_oop(exceptionOop);
2236 C1StubId unwind_id;
2237
2238 // get current pc information
2239 // pc is only needed if the method has an exception handler, the unwind code does not need it.
2240 int pc_for_athrow_offset = __ offset();
2241 InternalAddress pc_for_athrow(__ pc());
2242 __ lea(exceptionPC->as_register(), pc_for_athrow);
2243 add_call_info(pc_for_athrow_offset, info); // for exception handler
2244
2245 __ verify_not_null_oop(rax);
2246 // search an exception handler (rax: exception oop, rdx: throwing pc)
2247 if (compilation()->has_fpu_code()) {
2248 unwind_id = C1StubId::handle_exception_id;
2249 } else {
2250 unwind_id = C1StubId::handle_exception_nofpu_id;
2251 }
2252 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2253
2254 // enough room for two byte trap
2255 __ nop();
2256 }
2257
2258
2259 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2260 assert(exceptionOop->as_register() == rax, "must match");
2261
2262 __ jmp(_unwind_handler_entry);
2263 }
2264
2265
2266 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2267
2268 // optimized version for linear scan:
2269 // * count must be already in ECX (guaranteed by LinearScan)
2270 // * left and dest must be equal
2271 // * tmp must be unused
2272 assert(count->as_register() == SHIFT_count, "count must be in ECX");
2273 assert(left == dest, "left and dest must be equal");
2274 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2275
2276 if (left->is_single_cpu()) {
2277 Register value = left->as_register();
2278 assert(value != SHIFT_count, "left cannot be ECX");
2279
2280 switch (code) {
2281 case lir_shl: __ shll(value); break;
2282 case lir_shr: __ sarl(value); break;
2283 case lir_ushr: __ shrl(value); break;
2284 default: ShouldNotReachHere();
2285 }
2286 } else if (left->is_double_cpu()) {
2287 Register lo = left->as_register_lo();
2288 Register hi = left->as_register_hi();
2289 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2290 switch (code) {
2291 case lir_shl: __ shlptr(lo); break;
2292 case lir_shr: __ sarptr(lo); break;
2293 case lir_ushr: __ shrptr(lo); break;
2294 default: ShouldNotReachHere();
2295 }
2296 } else {
2297 ShouldNotReachHere();
2298 }
2299 }
2300
2301
2302 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2303 if (dest->is_single_cpu()) {
2304 // first move left into dest so that left is not destroyed by the shift
2305 Register value = dest->as_register();
2306 count = count & 0x1F; // Java spec
2307
2308 move_regs(left->as_register(), value);
2309 switch (code) {
2310 case lir_shl: __ shll(value, count); break;
2311 case lir_shr: __ sarl(value, count); break;
2312 case lir_ushr: __ shrl(value, count); break;
2313 default: ShouldNotReachHere();
2314 }
2315 } else if (dest->is_double_cpu()) {
2316 // first move left into dest so that left is not destroyed by the shift
2317 Register value = dest->as_register_lo();
2318 count = count & 0x1F; // Java spec
2319
2320 move_regs(left->as_register_lo(), value);
2321 switch (code) {
2322 case lir_shl: __ shlptr(value, count); break;
2323 case lir_shr: __ sarptr(value, count); break;
2324 case lir_ushr: __ shrptr(value, count); break;
2325 default: ShouldNotReachHere();
2326 }
2327 } else {
2328 ShouldNotReachHere();
2329 }
2330 }
2331
2332
2333 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2334 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2335 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2336 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2337 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
2338 }
2339
2340
2341 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2342 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2343 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2344 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2345 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
2346 }
2347
2348
2349 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2350 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2351 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2352 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2353 __ movoop(Address(rsp, offset_from_rsp_in_bytes), o, rscratch1);
2354 }
2355
2356
2357 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_rsp_in_words) {
2358 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2359 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2360 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2361 __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m, rscratch1);
2362 }
2363
2364
2365 // This code replaces a call to arraycopy; no exception may
2366 // be thrown in this code, they must be thrown in the System.arraycopy
2367 // activation frame; we could save some checks if this would not be the case
2368 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2369 ciArrayKlass* default_type = op->expected_type();
2370 Register src = op->src()->as_register();
2371 Register dst = op->dst()->as_register();
2372 Register src_pos = op->src_pos()->as_register();
2373 Register dst_pos = op->dst_pos()->as_register();
2374 Register length = op->length()->as_register();
2375 Register tmp = op->tmp()->as_register();
2376 Register tmp_load_klass = rscratch1;
2377 Register tmp2 = UseCompactObjectHeaders ? rscratch2 : noreg;
2378
2379 CodeStub* stub = op->stub();
2380 int flags = op->flags();
2381 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
2382 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2383
2384 // if we don't know anything, just go through the generic arraycopy
2385 if (default_type == nullptr) {
2386 // save outgoing arguments on stack in case call to System.arraycopy is needed
2387 // HACK ALERT. This code used to push the parameters in a hardwired fashion
2388 // for interpreter calling conventions. Now we have to do it in new style conventions.
2389 // For the moment until C1 gets the new register allocator I just force all the
2390 // args to the right place (except the register args) and then on the back side
2391 // reload the register args properly if we go slow path. Yuck
2392
2393 // These are proper for the calling convention
2394 store_parameter(length, 2);
2395 store_parameter(dst_pos, 1);
2396 store_parameter(dst, 0);
2397
2398 // these are just temporary placements until we need to reload
2399 store_parameter(src_pos, 3);
2400 store_parameter(src, 4);
2401
2402 address copyfunc_addr = StubRoutines::generic_arraycopy();
2403 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
2404
2405 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
2406 // The arguments are in java calling convention so we can trivially shift them to C
2407 // convention
2408 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2409 __ mov(c_rarg0, j_rarg0);
2410 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2411 __ mov(c_rarg1, j_rarg1);
2412 assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2413 __ mov(c_rarg2, j_rarg2);
2414 assert_different_registers(c_rarg3, j_rarg4);
2415 __ mov(c_rarg3, j_rarg3);
2416 #ifdef _WIN64
2417 // Allocate abi space for args but be sure to keep stack aligned
2418 __ subptr(rsp, 6*wordSize);
2419 store_parameter(j_rarg4, 4);
2420 #ifndef PRODUCT
2421 if (PrintC1Statistics) {
2422 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
2423 }
2424 #endif
2425 __ call(RuntimeAddress(copyfunc_addr));
2426 __ addptr(rsp, 6*wordSize);
2427 #else
2428 __ mov(c_rarg4, j_rarg4);
2429 #ifndef PRODUCT
2430 if (PrintC1Statistics) {
2431 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt), rscratch1);
2432 }
2433 #endif
2434 __ call(RuntimeAddress(copyfunc_addr));
2435 #endif // _WIN64
2436
2437 __ testl(rax, rax);
2438 __ jcc(Assembler::equal, *stub->continuation());
2439
2440 __ mov(tmp, rax);
2441 __ xorl(tmp, -1);
2442
2443 // Reload values from the stack so they are where the stub
2444 // expects them.
2445 __ movptr (dst, Address(rsp, 0*BytesPerWord));
2446 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
2447 __ movptr (length, Address(rsp, 2*BytesPerWord));
2448 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
2449 __ movptr (src, Address(rsp, 4*BytesPerWord));
2450
2451 __ subl(length, tmp);
2452 __ addl(src_pos, tmp);
2453 __ addl(dst_pos, tmp);
2454 __ jmp(*stub->entry());
2455
2456 __ bind(*stub->continuation());
2457 return;
2458 }
2459
2460 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2461
2462 int elem_size = type2aelembytes(basic_type);
2463 Address::ScaleFactor scale;
2464
2465 switch (elem_size) {
2466 case 1 :
2467 scale = Address::times_1;
2468 break;
2469 case 2 :
2470 scale = Address::times_2;
2471 break;
2472 case 4 :
2473 scale = Address::times_4;
2474 break;
2475 case 8 :
2476 scale = Address::times_8;
2477 break;
2478 default:
2479 scale = Address::no_scale;
2480 ShouldNotReachHere();
2481 }
2482
2483 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2484 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2485
2486 // length and pos's are all sign extended at this point on 64bit
2487
2488 // test for null
2489 if (flags & LIR_OpArrayCopy::src_null_check) {
2490 __ testptr(src, src);
2491 __ jcc(Assembler::zero, *stub->entry());
2492 }
2493 if (flags & LIR_OpArrayCopy::dst_null_check) {
2494 __ testptr(dst, dst);
2495 __ jcc(Assembler::zero, *stub->entry());
2496 }
2497
2498 // If the compiler was not able to prove that exact type of the source or the destination
2499 // of the arraycopy is an array type, check at runtime if the source or the destination is
2500 // an instance type.
2501 if (flags & LIR_OpArrayCopy::type_check) {
2502 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2503 __ load_klass(tmp, dst, tmp_load_klass);
2504 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
2505 __ jcc(Assembler::greaterEqual, *stub->entry());
2506 }
2507
2508 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2509 __ load_klass(tmp, src, tmp_load_klass);
2510 __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
2511 __ jcc(Assembler::greaterEqual, *stub->entry());
2512 }
2513 }
2514
2515 // check if negative
2516 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2517 __ testl(src_pos, src_pos);
2518 __ jcc(Assembler::less, *stub->entry());
2519 }
2520 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2521 __ testl(dst_pos, dst_pos);
2522 __ jcc(Assembler::less, *stub->entry());
2523 }
2524
2525 if (flags & LIR_OpArrayCopy::src_range_check) {
2526 __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
2527 __ cmpl(tmp, src_length_addr);
2528 __ jcc(Assembler::above, *stub->entry());
2529 }
2530 if (flags & LIR_OpArrayCopy::dst_range_check) {
2531 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
2532 __ cmpl(tmp, dst_length_addr);
2533 __ jcc(Assembler::above, *stub->entry());
2534 }
2535
2536 if (flags & LIR_OpArrayCopy::length_positive_check) {
2537 __ testl(length, length);
2538 __ jcc(Assembler::less, *stub->entry());
2539 }
2540
2541 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
2542 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
2543
2544 if (flags & LIR_OpArrayCopy::type_check) {
2545 // We don't know the array types are compatible
2546 if (basic_type != T_OBJECT) {
2547 // Simple test for basic type arrays
2548 __ cmp_klasses_from_objects(src, dst, tmp, tmp2);
2549 __ jcc(Assembler::notEqual, *stub->entry());
2550 } else {
2551 // For object arrays, if src is a sub class of dst then we can
2552 // safely do the copy.
2553 Label cont, slow;
2554
2555 __ push(src);
2556 __ push(dst);
2557
2558 __ load_klass(src, src, tmp_load_klass);
2559 __ load_klass(dst, dst, tmp_load_klass);
2560
2561 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, nullptr);
2562
2563 __ push(src);
2564 __ push(dst);
2565 __ call(RuntimeAddress(Runtime1::entry_for(C1StubId::slow_subtype_check_id)));
2566 __ pop(dst);
2567 __ pop(src);
2568
2569 __ testl(src, src);
2570 __ jcc(Assembler::notEqual, cont);
2571
2572 __ bind(slow);
2573 __ pop(dst);
2574 __ pop(src);
2575
2576 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2577 if (copyfunc_addr != nullptr) { // use stub if available
2578 // src is not a sub class of dst so we have to do a
2579 // per-element check.
2580
2581 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2582 if ((flags & mask) != mask) {
2583 // Check that at least both of them object arrays.
2584 assert(flags & mask, "one of the two should be known to be an object array");
2585
2586 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2587 __ load_klass(tmp, src, tmp_load_klass);
2588 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2589 __ load_klass(tmp, dst, tmp_load_klass);
2590 }
2591 int lh_offset = in_bytes(Klass::layout_helper_offset());
2592 Address klass_lh_addr(tmp, lh_offset);
2593 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2594 __ cmpl(klass_lh_addr, objArray_lh);
2595 __ jcc(Assembler::notEqual, *stub->entry());
2596 }
2597
2598 // Spill because stubs can use any register they like and it's
2599 // easier to restore just those that we care about.
2600 store_parameter(dst, 0);
2601 store_parameter(dst_pos, 1);
2602 store_parameter(length, 2);
2603 store_parameter(src_pos, 3);
2604 store_parameter(src, 4);
2605
2606 __ movl2ptr(length, length); //higher 32bits must be null
2607
2608 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
2609 assert_different_registers(c_rarg0, dst, dst_pos, length);
2610 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
2611 assert_different_registers(c_rarg1, dst, length);
2612
2613 __ mov(c_rarg2, length);
2614 assert_different_registers(c_rarg2, dst);
2615
2616 #ifdef _WIN64
2617 // Allocate abi space for args but be sure to keep stack aligned
2618 __ subptr(rsp, 6*wordSize);
2619 __ load_klass(c_rarg3, dst, tmp_load_klass);
2620 __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
2621 store_parameter(c_rarg3, 4);
2622 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
2623 __ call(RuntimeAddress(copyfunc_addr));
2624 __ addptr(rsp, 6*wordSize);
2625 #else
2626 __ load_klass(c_rarg4, dst, tmp_load_klass);
2627 __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2628 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2629 __ call(RuntimeAddress(copyfunc_addr));
2630 #endif
2631
2632 #ifndef PRODUCT
2633 if (PrintC1Statistics) {
2634 Label failed;
2635 __ testl(rax, rax);
2636 __ jcc(Assembler::notZero, failed);
2637 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt), rscratch1);
2638 __ bind(failed);
2639 }
2640 #endif
2641
2642 __ testl(rax, rax);
2643 __ jcc(Assembler::zero, *stub->continuation());
2644
2645 #ifndef PRODUCT
2646 if (PrintC1Statistics) {
2647 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt), rscratch1);
2648 }
2649 #endif
2650
2651 __ mov(tmp, rax);
2652
2653 __ xorl(tmp, -1);
2654
2655 // Restore previously spilled arguments
2656 __ movptr (dst, Address(rsp, 0*BytesPerWord));
2657 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord));
2658 __ movptr (length, Address(rsp, 2*BytesPerWord));
2659 __ movptr (src_pos, Address(rsp, 3*BytesPerWord));
2660 __ movptr (src, Address(rsp, 4*BytesPerWord));
2661
2662
2663 __ subl(length, tmp);
2664 __ addl(src_pos, tmp);
2665 __ addl(dst_pos, tmp);
2666 }
2667
2668 __ jmp(*stub->entry());
2669
2670 __ bind(cont);
2671 __ pop(dst);
2672 __ pop(src);
2673 }
2674 }
2675
2676 #ifdef ASSERT
2677 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2678 // Sanity check the known type with the incoming class. For the
2679 // primitive case the types must match exactly with src.klass and
2680 // dst.klass each exactly matching the default type. For the
2681 // object array case, if no type check is needed then either the
2682 // dst type is exactly the expected type and the src type is a
2683 // subtype which we can't check or src is the same array as dst
2684 // but not necessarily exactly of type default_type.
2685 Label known_ok, halt;
2686 __ mov_metadata(tmp, default_type->constant_encoding());
2687 if (UseCompressedClassPointers) {
2688 __ encode_klass_not_null(tmp, rscratch1);
2689 }
2690
2691 if (basic_type != T_OBJECT) {
2692 __ cmp_klass(tmp, dst, tmp2);
2693 __ jcc(Assembler::notEqual, halt);
2694 __ cmp_klass(tmp, src, tmp2);
2695 __ jcc(Assembler::equal, known_ok);
2696 } else {
2697 __ cmp_klass(tmp, dst, tmp2);
2698 __ jcc(Assembler::equal, known_ok);
2699 __ cmpptr(src, dst);
2700 __ jcc(Assembler::equal, known_ok);
2701 }
2702 __ bind(halt);
2703 __ stop("incorrect type information in arraycopy");
2704 __ bind(known_ok);
2705 }
2706 #endif
2707
2708 #ifndef PRODUCT
2709 if (PrintC1Statistics) {
2710 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)), rscratch1);
2711 }
2712 #endif
2713
2714 assert_different_registers(c_rarg0, dst, dst_pos, length);
2715 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
2716 assert_different_registers(c_rarg1, length);
2717 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
2718 __ mov(c_rarg2, length);
2719
2720 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2721 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2722 const char *name;
2723 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2724 __ call_VM_leaf(entry, 0);
2725
2726 if (stub != nullptr) {
2727 __ bind(*stub->continuation());
2728 }
2729 }
2730
2731 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2732 assert(op->crc()->is_single_cpu(), "crc must be register");
2733 assert(op->val()->is_single_cpu(), "byte value must be register");
2734 assert(op->result_opr()->is_single_cpu(), "result must be register");
2735 Register crc = op->crc()->as_register();
2736 Register val = op->val()->as_register();
2737 Register res = op->result_opr()->as_register();
2738
2739 assert_different_registers(val, crc, res);
2740
2741 __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
2742 __ notl(crc); // ~crc
2743 __ update_byte_crc32(crc, val, res);
2744 __ notl(crc); // ~crc
2745 __ mov(res, crc);
2746 }
2747
2748 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2749 Register obj = op->obj_opr()->as_register(); // may not be an oop
2750 Register hdr = op->hdr_opr()->as_register();
2751 Register lock = op->lock_opr()->as_register();
2752 if (LockingMode == LM_MONITOR) {
2753 if (op->info() != nullptr) {
2754 add_debug_info_for_null_check_here(op->info());
2755 __ null_check(obj);
2756 }
2757 __ jmp(*op->stub()->entry());
2758 } else if (op->code() == lir_lock) {
2759 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2760 Register tmp = LockingMode == LM_LIGHTWEIGHT ? op->scratch_opr()->as_register() : noreg;
2761 // add debug info for NullPointerException only if one is possible
2762 int null_check_offset = __ lock_object(hdr, obj, lock, tmp, *op->stub()->entry());
2763 if (op->info() != nullptr) {
2764 add_debug_info_for_null_check(null_check_offset, op->info());
2765 }
2766 // done
2767 } else if (op->code() == lir_unlock) {
2768 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2769 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2770 } else {
2771 Unimplemented();
2772 }
2773 __ bind(*op->stub()->continuation());
2774 }
2775
2776 void LIR_Assembler::emit_load_klass(LIR_OpLoadKlass* op) {
2777 Register obj = op->obj()->as_pointer_register();
2778 Register result = op->result_opr()->as_pointer_register();
2779
2780 CodeEmitInfo* info = op->info();
2781 if (info != nullptr) {
2782 add_debug_info_for_null_check_here(info);
2783 }
2784
2785 __ load_klass(result, obj, rscratch1);
2786 }
2787
2788 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2789 ciMethod* method = op->profiled_method();
2790 int bci = op->profiled_bci();
2791 ciMethod* callee = op->profiled_callee();
2792 Register tmp_load_klass = rscratch1;
2793
2794 // Update counter for all call types
2795 ciMethodData* md = method->method_data_or_null();
2796 assert(md != nullptr, "Sanity");
2797 ciProfileData* data = md->bci_to_data(bci);
2798 assert(data != nullptr && data->is_CounterData(), "need CounterData for calls");
2799 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2800 Register mdo = op->mdo()->as_register();
2801 __ mov_metadata(mdo, md->constant_encoding());
2802 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2803 // Perform additional virtual call profiling for invokevirtual and
2804 // invokeinterface bytecodes
2805 if (op->should_profile_receiver_type()) {
2806 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2807 Register recv = op->recv()->as_register();
2808 assert_different_registers(mdo, recv);
2809 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2810 ciKlass* known_klass = op->known_holder();
2811 if (C1OptimizeVirtualCallProfiling && known_klass != nullptr) {
2812 // We know the type that will be seen at this call site; we can
2813 // statically update the MethodData* rather than needing to do
2814 // dynamic tests on the receiver type
2815
2816 // NOTE: we should probably put a lock around this search to
2817 // avoid collisions by concurrent compilations
2818 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2819 uint i;
2820 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2821 ciKlass* receiver = vc_data->receiver(i);
2822 if (known_klass->equals(receiver)) {
2823 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2824 __ addptr(data_addr, DataLayout::counter_increment);
2825 return;
2826 }
2827 }
2828
2829 // Receiver type not found in profile data; select an empty slot
2830
2831 // Note that this is less efficient than it should be because it
2832 // always does a write to the receiver part of the
2833 // VirtualCallData rather than just the first time
2834 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2835 ciKlass* receiver = vc_data->receiver(i);
2836 if (receiver == nullptr) {
2837 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
2838 __ mov_metadata(recv_addr, known_klass->constant_encoding(), rscratch1);
2839 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2840 __ addptr(data_addr, DataLayout::counter_increment);
2841 return;
2842 }
2843 }
2844 } else {
2845 __ load_klass(recv, recv, tmp_load_klass);
2846 Label update_done;
2847 type_profile_helper(mdo, md, data, recv, &update_done);
2848 // Receiver did not match any saved receiver and there is no empty row for it.
2849 // Increment total counter to indicate polymorphic case.
2850 __ addptr(counter_addr, DataLayout::counter_increment);
2851
2852 __ bind(update_done);
2853 }
2854 } else {
2855 // Static call
2856 __ addptr(counter_addr, DataLayout::counter_increment);
2857 }
2858 }
2859
2860 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2861 Register obj = op->obj()->as_register();
2862 Register tmp = op->tmp()->as_pointer_register();
2863 Register tmp_load_klass = rscratch1;
2864 Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2865 ciKlass* exact_klass = op->exact_klass();
2866 intptr_t current_klass = op->current_klass();
2867 bool not_null = op->not_null();
2868 bool no_conflict = op->no_conflict();
2869
2870 Label update, next, none;
2871
2872 bool do_null = !not_null;
2873 bool exact_klass_set = exact_klass != nullptr && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2874 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2875
2876 assert(do_null || do_update, "why are we here?");
2877 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2878
2879 __ verify_oop(obj);
2880
2881 #ifdef ASSERT
2882 if (obj == tmp) {
2883 assert_different_registers(obj, rscratch1, mdo_addr.base(), mdo_addr.index());
2884 } else {
2885 assert_different_registers(obj, tmp, rscratch1, mdo_addr.base(), mdo_addr.index());
2886 }
2887 #endif
2888 if (do_null) {
2889 __ testptr(obj, obj);
2890 __ jccb(Assembler::notZero, update);
2891 if (!TypeEntries::was_null_seen(current_klass)) {
2892 __ testptr(mdo_addr, TypeEntries::null_seen);
2893 #ifndef ASSERT
2894 __ jccb(Assembler::notZero, next); // already set
2895 #else
2896 __ jcc(Assembler::notZero, next); // already set
2897 #endif
2898 // atomic update to prevent overwriting Klass* with 0
2899 __ lock();
2900 __ orptr(mdo_addr, TypeEntries::null_seen);
2901 }
2902 if (do_update) {
2903 #ifndef ASSERT
2904 __ jmpb(next);
2905 }
2906 #else
2907 __ jmp(next);
2908 }
2909 } else {
2910 __ testptr(obj, obj);
2911 __ jcc(Assembler::notZero, update);
2912 __ stop("unexpected null obj");
2913 #endif
2914 }
2915
2916 __ bind(update);
2917
2918 if (do_update) {
2919 #ifdef ASSERT
2920 if (exact_klass != nullptr) {
2921 Label ok;
2922 __ load_klass(tmp, obj, tmp_load_klass);
2923 __ push(tmp);
2924 __ mov_metadata(tmp, exact_klass->constant_encoding());
2925 __ cmpptr(tmp, Address(rsp, 0));
2926 __ jcc(Assembler::equal, ok);
2927 __ stop("exact klass and actual klass differ");
2928 __ bind(ok);
2929 __ pop(tmp);
2930 }
2931 #endif
2932 if (!no_conflict) {
2933 if (exact_klass == nullptr || TypeEntries::is_type_none(current_klass)) {
2934 if (exact_klass != nullptr) {
2935 __ mov_metadata(tmp, exact_klass->constant_encoding());
2936 } else {
2937 __ load_klass(tmp, obj, tmp_load_klass);
2938 }
2939 __ mov(rscratch1, tmp); // save original value before XOR
2940 __ xorptr(tmp, mdo_addr);
2941 __ testptr(tmp, TypeEntries::type_klass_mask);
2942 // klass seen before, nothing to do. The unknown bit may have been
2943 // set already but no need to check.
2944 __ jccb(Assembler::zero, next);
2945
2946 __ testptr(tmp, TypeEntries::type_unknown);
2947 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
2948
2949 if (TypeEntries::is_type_none(current_klass)) {
2950 __ testptr(mdo_addr, TypeEntries::type_mask);
2951 __ jccb(Assembler::zero, none);
2952 // There is a chance that the checks above (re-reading profiling
2953 // data from memory) fail if another thread has just set the
2954 // profiling to this obj's klass
2955 __ mov(tmp, rscratch1); // get back original value before XOR
2956 __ xorptr(tmp, mdo_addr);
2957 __ testptr(tmp, TypeEntries::type_klass_mask);
2958 __ jccb(Assembler::zero, next);
2959 }
2960 } else {
2961 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2962 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2963
2964 __ testptr(mdo_addr, TypeEntries::type_unknown);
2965 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
2966 }
2967
2968 // different than before. Cannot keep accurate profile.
2969 __ orptr(mdo_addr, TypeEntries::type_unknown);
2970
2971 if (TypeEntries::is_type_none(current_klass)) {
2972 __ jmpb(next);
2973
2974 __ bind(none);
2975 // first time here. Set profile type.
2976 __ movptr(mdo_addr, tmp);
2977 #ifdef ASSERT
2978 __ andptr(tmp, TypeEntries::type_klass_mask);
2979 __ verify_klass_ptr(tmp);
2980 #endif
2981 }
2982 } else {
2983 // There's a single possible klass at this profile point
2984 assert(exact_klass != nullptr, "should be");
2985 if (TypeEntries::is_type_none(current_klass)) {
2986 __ mov_metadata(tmp, exact_klass->constant_encoding());
2987 __ xorptr(tmp, mdo_addr);
2988 __ testptr(tmp, TypeEntries::type_klass_mask);
2989 #ifdef ASSERT
2990 __ jcc(Assembler::zero, next);
2991
2992 {
2993 Label ok;
2994 __ push(tmp);
2995 __ testptr(mdo_addr, TypeEntries::type_mask);
2996 __ jcc(Assembler::zero, ok);
2997 // may have been set by another thread
2998 __ mov_metadata(tmp, exact_klass->constant_encoding());
2999 __ xorptr(tmp, mdo_addr);
3000 __ testptr(tmp, TypeEntries::type_mask);
3001 __ jcc(Assembler::zero, ok);
3002
3003 __ stop("unexpected profiling mismatch");
3004 __ bind(ok);
3005 __ pop(tmp);
3006 }
3007 #else
3008 __ jccb(Assembler::zero, next);
3009 #endif
3010 // first time here. Set profile type.
3011 __ movptr(mdo_addr, tmp);
3012 #ifdef ASSERT
3013 __ andptr(tmp, TypeEntries::type_klass_mask);
3014 __ verify_klass_ptr(tmp);
3015 #endif
3016 } else {
3017 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3018 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3019
3020 __ testptr(mdo_addr, TypeEntries::type_unknown);
3021 __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3022
3023 __ orptr(mdo_addr, TypeEntries::type_unknown);
3024 }
3025 }
3026 }
3027 __ bind(next);
3028 }
3029
3030 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3031 Unimplemented();
3032 }
3033
3034
3035 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3036 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3037 }
3038
3039
3040 void LIR_Assembler::align_backward_branch_target() {
3041 __ align(BytesPerWord);
3042 }
3043
3044
3045 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
3046 if (left->is_single_cpu()) {
3047 __ negl(left->as_register());
3048 move_regs(left->as_register(), dest->as_register());
3049
3050 } else if (left->is_double_cpu()) {
3051 Register lo = left->as_register_lo();
3052 Register dst = dest->as_register_lo();
3053 __ movptr(dst, lo);
3054 __ negptr(dst);
3055
3056 } else if (dest->is_single_xmm()) {
3057 assert(!tmp->is_valid(), "do not need temporary");
3058 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3059 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3060 }
3061 __ xorps(dest->as_xmm_float_reg(),
3062 ExternalAddress((address)float_signflip_pool),
3063 rscratch1);
3064 } else if (dest->is_double_xmm()) {
3065 assert(!tmp->is_valid(), "do not need temporary");
3066 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3067 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3068 }
3069 __ xorpd(dest->as_xmm_double_reg(),
3070 ExternalAddress((address)double_signflip_pool),
3071 rscratch1);
3072 } else {
3073 ShouldNotReachHere();
3074 }
3075 }
3076
3077
3078 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3079 assert(src->is_address(), "must be an address");
3080 assert(dest->is_register(), "must be a register");
3081
3082 PatchingStub* patch = nullptr;
3083 if (patch_code != lir_patch_none) {
3084 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
3085 }
3086
3087 Register reg = dest->as_pointer_register();
3088 LIR_Address* addr = src->as_address_ptr();
3089 __ lea(reg, as_Address(addr));
3090
3091 if (patch != nullptr) {
3092 patching_epilog(patch, patch_code, addr->base()->as_register(), info);
3093 }
3094 }
3095
3096
3097
3098 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3099 assert(!tmp->is_valid(), "don't need temporary");
3100 __ call(RuntimeAddress(dest));
3101 if (info != nullptr) {
3102 add_call_info_here(info);
3103 }
3104 __ post_call_nop();
3105 }
3106
3107
3108 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3109 assert(type == T_LONG, "only for volatile long fields");
3110
3111 if (info != nullptr) {
3112 add_debug_info_for_null_check_here(info);
3113 }
3114
3115 if (src->is_double_xmm()) {
3116 if (dest->is_double_cpu()) {
3117 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3118 } else if (dest->is_double_stack()) {
3119 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3120 } else if (dest->is_address()) {
3121 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3122 } else {
3123 ShouldNotReachHere();
3124 }
3125
3126 } else if (dest->is_double_xmm()) {
3127 if (src->is_double_stack()) {
3128 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3129 } else if (src->is_address()) {
3130 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3131 } else {
3132 ShouldNotReachHere();
3133 }
3134
3135 } else {
3136 ShouldNotReachHere();
3137 }
3138 }
3139
3140 #ifdef ASSERT
3141 // emit run-time assertion
3142 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3143 assert(op->code() == lir_assert, "must be");
3144
3145 if (op->in_opr1()->is_valid()) {
3146 assert(op->in_opr2()->is_valid(), "both operands must be valid");
3147 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3148 } else {
3149 assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3150 assert(op->condition() == lir_cond_always, "no other conditions allowed");
3151 }
3152
3153 Label ok;
3154 if (op->condition() != lir_cond_always) {
3155 Assembler::Condition acond = Assembler::zero;
3156 switch (op->condition()) {
3157 case lir_cond_equal: acond = Assembler::equal; break;
3158 case lir_cond_notEqual: acond = Assembler::notEqual; break;
3159 case lir_cond_less: acond = Assembler::less; break;
3160 case lir_cond_lessEqual: acond = Assembler::lessEqual; break;
3161 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3162 case lir_cond_greater: acond = Assembler::greater; break;
3163 case lir_cond_belowEqual: acond = Assembler::belowEqual; break;
3164 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break;
3165 default: ShouldNotReachHere();
3166 }
3167 __ jcc(acond, ok);
3168 }
3169 if (op->halt()) {
3170 const char* str = __ code_string(op->msg());
3171 __ stop(str);
3172 } else {
3173 breakpoint();
3174 }
3175 __ bind(ok);
3176 }
3177 #endif
3178
3179 void LIR_Assembler::membar() {
3180 // QQQ sparc TSO uses this,
3181 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3182 }
3183
3184 void LIR_Assembler::membar_acquire() {
3185 // No x86 machines currently require load fences
3186 }
3187
3188 void LIR_Assembler::membar_release() {
3189 // No x86 machines currently require store fences
3190 }
3191
3192 void LIR_Assembler::membar_loadload() {
3193 // no-op
3194 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3195 }
3196
3197 void LIR_Assembler::membar_storestore() {
3198 // no-op
3199 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3200 }
3201
3202 void LIR_Assembler::membar_loadstore() {
3203 // no-op
3204 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3205 }
3206
3207 void LIR_Assembler::membar_storeload() {
3208 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3209 }
3210
3211 void LIR_Assembler::on_spin_wait() {
3212 __ pause ();
3213 }
3214
3215 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3216 assert(result_reg->is_register(), "check");
3217 __ mov(result_reg->as_register(), r15_thread);
3218 }
3219
3220
3221 void LIR_Assembler::peephole(LIR_List*) {
3222 // do nothing for now
3223 }
3224
3225 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
3226 assert(data == dest, "xchg/xadd uses only 2 operands");
3227
3228 if (data->type() == T_INT) {
3229 if (code == lir_xadd) {
3230 __ lock();
3231 __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
3232 } else {
3233 __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
3234 }
3235 } else if (data->is_oop()) {
3236 assert (code == lir_xchg, "xadd for oops");
3237 Register obj = data->as_register();
3238 if (UseCompressedOops) {
3239 __ encode_heap_oop(obj);
3240 __ xchgl(obj, as_Address(src->as_address_ptr()));
3241 __ decode_heap_oop(obj);
3242 } else {
3243 __ xchgptr(obj, as_Address(src->as_address_ptr()));
3244 }
3245 } else if (data->type() == T_LONG) {
3246 assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
3247 if (code == lir_xadd) {
3248 __ lock();
3249 __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
3250 } else {
3251 __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
3252 }
3253 } else {
3254 ShouldNotReachHere();
3255 }
3256 }
3257
3258 #undef __