1 //
2 // Copyright (c) 2003, 2024, Oracle and/or its affiliates. All rights reserved.
3 // Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 // Copyright (c) 2020, 2024, Huawei Technologies Co., Ltd. All rights reserved.
5 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
6 //
7 // This code is free software; you can redistribute it and/or modify it
8 // under the terms of the GNU General Public License version 2 only, as
9 // published by the Free Software Foundation.
10 //
11 // This code is distributed in the hope that it will be useful, but WITHOUT
12 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 // version 2 for more details (a copy is included in the LICENSE file that
15 // accompanied this code).
16 //
17 // You should have received a copy of the GNU General Public License version
18 // 2 along with this work; if not, write to the Free Software Foundation,
19 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 //
21 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 // or visit www.oracle.com if you need additional information or have any
23 // questions.
24 //
25 //
26
27 // RISCV Architecture Description File
28
29 //----------REGISTER DEFINITION BLOCK------------------------------------------
30 // This information is used by the matcher and the register allocator to
31 // describe individual registers and classes of registers within the target
32 // architecture.
33
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name ( register save type, C convention save type,
38 // ideal register type, encoding );
39 // Register Save Types:
40 //
41 // NS = No-Save: The register allocator assumes that these registers
42 // can be used without saving upon entry to the method, &
43 // that they do not need to be saved at call sites.
44 //
45 // SOC = Save-On-Call: The register allocator assumes that these registers
46 // can be used without saving upon entry to the method,
47 // but that they must be saved at call sites.
48 //
49 // SOE = Save-On-Entry: The register allocator assumes that these registers
50 // must be saved before using them upon entry to the
51 // method, but they do not need to be saved at call
52 // sites.
53 //
54 // AS = Always-Save: The register allocator assumes that these registers
55 // must be saved before using them upon entry to the
56 // method, & that they must be saved at call sites.
57 //
58 // Ideal Register Type is used to determine how to save & restore a
59 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
60 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
61 //
62 // The encoding number is the actual bit-pattern placed into the opcodes.
63
64 // We must define the 64 bit int registers in two 32 bit halves, the
65 // real lower register and a virtual upper half register. upper halves
66 // are used by the register allocator but are not actually supplied as
67 // operands to memory ops.
68 //
69 // follow the C1 compiler in making registers
70 //
71 // x7, x9-x17, x27-x31 volatile (caller save)
72 // x0-x4, x8, x23 system (no save, no allocate)
73 // x5-x6 non-allocatable (so we can use them as temporary regs)
74
75 //
76 // as regards Java usage. we don't use any callee save registers
77 // because this makes it difficult to de-optimise a frame (see comment
78 // in x86 implementation of Deoptimization::unwind_callee_save_values)
79 //
80
81 // General Registers
82
83 reg_def R0 ( NS, NS, Op_RegI, 0, x0->as_VMReg() ); // zr
84 reg_def R0_H ( NS, NS, Op_RegI, 0, x0->as_VMReg()->next() );
85 reg_def R1 ( NS, SOC, Op_RegI, 1, x1->as_VMReg() ); // ra
86 reg_def R1_H ( NS, SOC, Op_RegI, 1, x1->as_VMReg()->next() );
87 reg_def R2 ( NS, NS, Op_RegI, 2, x2->as_VMReg() ); // sp
88 reg_def R2_H ( NS, NS, Op_RegI, 2, x2->as_VMReg()->next() );
89 reg_def R3 ( NS, NS, Op_RegI, 3, x3->as_VMReg() ); // gp
90 reg_def R3_H ( NS, NS, Op_RegI, 3, x3->as_VMReg()->next() );
91 reg_def R4 ( NS, NS, Op_RegI, 4, x4->as_VMReg() ); // tp
92 reg_def R4_H ( NS, NS, Op_RegI, 4, x4->as_VMReg()->next() );
93 reg_def R7 ( SOC, SOC, Op_RegI, 7, x7->as_VMReg() );
94 reg_def R7_H ( SOC, SOC, Op_RegI, 7, x7->as_VMReg()->next() );
95 reg_def R8 ( NS, SOE, Op_RegI, 8, x8->as_VMReg() ); // fp
96 reg_def R8_H ( NS, SOE, Op_RegI, 8, x8->as_VMReg()->next() );
97 reg_def R9 ( SOC, SOE, Op_RegI, 9, x9->as_VMReg() );
98 reg_def R9_H ( SOC, SOE, Op_RegI, 9, x9->as_VMReg()->next() );
99 reg_def R10 ( SOC, SOC, Op_RegI, 10, x10->as_VMReg() );
100 reg_def R10_H ( SOC, SOC, Op_RegI, 10, x10->as_VMReg()->next());
101 reg_def R11 ( SOC, SOC, Op_RegI, 11, x11->as_VMReg() );
102 reg_def R11_H ( SOC, SOC, Op_RegI, 11, x11->as_VMReg()->next());
103 reg_def R12 ( SOC, SOC, Op_RegI, 12, x12->as_VMReg() );
104 reg_def R12_H ( SOC, SOC, Op_RegI, 12, x12->as_VMReg()->next());
105 reg_def R13 ( SOC, SOC, Op_RegI, 13, x13->as_VMReg() );
106 reg_def R13_H ( SOC, SOC, Op_RegI, 13, x13->as_VMReg()->next());
107 reg_def R14 ( SOC, SOC, Op_RegI, 14, x14->as_VMReg() );
108 reg_def R14_H ( SOC, SOC, Op_RegI, 14, x14->as_VMReg()->next());
109 reg_def R15 ( SOC, SOC, Op_RegI, 15, x15->as_VMReg() );
110 reg_def R15_H ( SOC, SOC, Op_RegI, 15, x15->as_VMReg()->next());
111 reg_def R16 ( SOC, SOC, Op_RegI, 16, x16->as_VMReg() );
112 reg_def R16_H ( SOC, SOC, Op_RegI, 16, x16->as_VMReg()->next());
113 reg_def R17 ( SOC, SOC, Op_RegI, 17, x17->as_VMReg() );
114 reg_def R17_H ( SOC, SOC, Op_RegI, 17, x17->as_VMReg()->next());
115 reg_def R18 ( SOC, SOE, Op_RegI, 18, x18->as_VMReg() );
116 reg_def R18_H ( SOC, SOE, Op_RegI, 18, x18->as_VMReg()->next());
117 reg_def R19 ( SOC, SOE, Op_RegI, 19, x19->as_VMReg() );
118 reg_def R19_H ( SOC, SOE, Op_RegI, 19, x19->as_VMReg()->next());
119 reg_def R20 ( SOC, SOE, Op_RegI, 20, x20->as_VMReg() ); // caller esp
120 reg_def R20_H ( SOC, SOE, Op_RegI, 20, x20->as_VMReg()->next());
121 reg_def R21 ( SOC, SOE, Op_RegI, 21, x21->as_VMReg() );
122 reg_def R21_H ( SOC, SOE, Op_RegI, 21, x21->as_VMReg()->next());
123 reg_def R22 ( SOC, SOE, Op_RegI, 22, x22->as_VMReg() );
124 reg_def R22_H ( SOC, SOE, Op_RegI, 22, x22->as_VMReg()->next());
125 reg_def R23 ( NS, SOE, Op_RegI, 23, x23->as_VMReg() ); // java thread
126 reg_def R23_H ( NS, SOE, Op_RegI, 23, x23->as_VMReg()->next());
127 reg_def R24 ( SOC, SOE, Op_RegI, 24, x24->as_VMReg() );
128 reg_def R24_H ( SOC, SOE, Op_RegI, 24, x24->as_VMReg()->next());
129 reg_def R25 ( SOC, SOE, Op_RegI, 25, x25->as_VMReg() );
130 reg_def R25_H ( SOC, SOE, Op_RegI, 25, x25->as_VMReg()->next());
131 reg_def R26 ( SOC, SOE, Op_RegI, 26, x26->as_VMReg() );
132 reg_def R26_H ( SOC, SOE, Op_RegI, 26, x26->as_VMReg()->next());
133 reg_def R27 ( SOC, SOE, Op_RegI, 27, x27->as_VMReg() ); // heapbase
134 reg_def R27_H ( SOC, SOE, Op_RegI, 27, x27->as_VMReg()->next());
135 reg_def R28 ( SOC, SOC, Op_RegI, 28, x28->as_VMReg() );
136 reg_def R28_H ( SOC, SOC, Op_RegI, 28, x28->as_VMReg()->next());
137 reg_def R29 ( SOC, SOC, Op_RegI, 29, x29->as_VMReg() );
138 reg_def R29_H ( SOC, SOC, Op_RegI, 29, x29->as_VMReg()->next());
139 reg_def R30 ( SOC, SOC, Op_RegI, 30, x30->as_VMReg() );
140 reg_def R30_H ( SOC, SOC, Op_RegI, 30, x30->as_VMReg()->next());
141 reg_def R31 ( SOC, SOC, Op_RegI, 31, x31->as_VMReg() );
142 reg_def R31_H ( SOC, SOC, Op_RegI, 31, x31->as_VMReg()->next());
143
144 // ----------------------------
145 // Float/Double Registers
146 // ----------------------------
147
148 // Double Registers
149
150 // The rules of ADL require that double registers be defined in pairs.
151 // Each pair must be two 32-bit values, but not necessarily a pair of
152 // single float registers. In each pair, ADLC-assigned register numbers
153 // must be adjacent, with the lower number even. Finally, when the
154 // CPU stores such a register pair to memory, the word associated with
155 // the lower ADLC-assigned number must be stored to the lower address.
156
157 // RISCV has 32 floating-point registers. Each can store a single
158 // or double precision floating-point value.
159
160 // for Java use float registers f0-f31 are always save on call whereas
161 // the platform ABI treats f8-f9 and f18-f27 as callee save). Other
162 // float registers are SOC as per the platform spec
163
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, f0->as_VMReg() );
165 reg_def F0_H ( SOC, SOC, Op_RegF, 0, f0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, f1->as_VMReg() );
167 reg_def F1_H ( SOC, SOC, Op_RegF, 1, f1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, f2->as_VMReg() );
169 reg_def F2_H ( SOC, SOC, Op_RegF, 2, f2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, f3->as_VMReg() );
171 reg_def F3_H ( SOC, SOC, Op_RegF, 3, f3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, f4->as_VMReg() );
173 reg_def F4_H ( SOC, SOC, Op_RegF, 4, f4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, f5->as_VMReg() );
175 reg_def F5_H ( SOC, SOC, Op_RegF, 5, f5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, f6->as_VMReg() );
177 reg_def F6_H ( SOC, SOC, Op_RegF, 6, f6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, f7->as_VMReg() );
179 reg_def F7_H ( SOC, SOC, Op_RegF, 7, f7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOE, Op_RegF, 8, f8->as_VMReg() );
181 reg_def F8_H ( SOC, SOE, Op_RegF, 8, f8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOE, Op_RegF, 9, f9->as_VMReg() );
183 reg_def F9_H ( SOC, SOE, Op_RegF, 9, f9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, f10->as_VMReg() );
185 reg_def F10_H ( SOC, SOC, Op_RegF, 10, f10->as_VMReg()->next() );
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, f11->as_VMReg() );
187 reg_def F11_H ( SOC, SOC, Op_RegF, 11, f11->as_VMReg()->next() );
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, f12->as_VMReg() );
189 reg_def F12_H ( SOC, SOC, Op_RegF, 12, f12->as_VMReg()->next() );
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, f13->as_VMReg() );
191 reg_def F13_H ( SOC, SOC, Op_RegF, 13, f13->as_VMReg()->next() );
192 reg_def F14 ( SOC, SOC, Op_RegF, 14, f14->as_VMReg() );
193 reg_def F14_H ( SOC, SOC, Op_RegF, 14, f14->as_VMReg()->next() );
194 reg_def F15 ( SOC, SOC, Op_RegF, 15, f15->as_VMReg() );
195 reg_def F15_H ( SOC, SOC, Op_RegF, 15, f15->as_VMReg()->next() );
196 reg_def F16 ( SOC, SOC, Op_RegF, 16, f16->as_VMReg() );
197 reg_def F16_H ( SOC, SOC, Op_RegF, 16, f16->as_VMReg()->next() );
198 reg_def F17 ( SOC, SOC, Op_RegF, 17, f17->as_VMReg() );
199 reg_def F17_H ( SOC, SOC, Op_RegF, 17, f17->as_VMReg()->next() );
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, f18->as_VMReg() );
201 reg_def F18_H ( SOC, SOE, Op_RegF, 18, f18->as_VMReg()->next() );
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, f19->as_VMReg() );
203 reg_def F19_H ( SOC, SOE, Op_RegF, 19, f19->as_VMReg()->next() );
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, f20->as_VMReg() );
205 reg_def F20_H ( SOC, SOE, Op_RegF, 20, f20->as_VMReg()->next() );
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, f21->as_VMReg() );
207 reg_def F21_H ( SOC, SOE, Op_RegF, 21, f21->as_VMReg()->next() );
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, f22->as_VMReg() );
209 reg_def F22_H ( SOC, SOE, Op_RegF, 22, f22->as_VMReg()->next() );
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, f23->as_VMReg() );
211 reg_def F23_H ( SOC, SOE, Op_RegF, 23, f23->as_VMReg()->next() );
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, f24->as_VMReg() );
213 reg_def F24_H ( SOC, SOE, Op_RegF, 24, f24->as_VMReg()->next() );
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, f25->as_VMReg() );
215 reg_def F25_H ( SOC, SOE, Op_RegF, 25, f25->as_VMReg()->next() );
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, f26->as_VMReg() );
217 reg_def F26_H ( SOC, SOE, Op_RegF, 26, f26->as_VMReg()->next() );
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, f27->as_VMReg() );
219 reg_def F27_H ( SOC, SOE, Op_RegF, 27, f27->as_VMReg()->next() );
220 reg_def F28 ( SOC, SOC, Op_RegF, 28, f28->as_VMReg() );
221 reg_def F28_H ( SOC, SOC, Op_RegF, 28, f28->as_VMReg()->next() );
222 reg_def F29 ( SOC, SOC, Op_RegF, 29, f29->as_VMReg() );
223 reg_def F29_H ( SOC, SOC, Op_RegF, 29, f29->as_VMReg()->next() );
224 reg_def F30 ( SOC, SOC, Op_RegF, 30, f30->as_VMReg() );
225 reg_def F30_H ( SOC, SOC, Op_RegF, 30, f30->as_VMReg()->next() );
226 reg_def F31 ( SOC, SOC, Op_RegF, 31, f31->as_VMReg() );
227 reg_def F31_H ( SOC, SOC, Op_RegF, 31, f31->as_VMReg()->next() );
228
229 // ----------------------------
230 // Vector Registers
231 // ----------------------------
232
233 // For RVV vector registers, we simply extend vector register size to 4
234 // 'logical' slots. This is nominally 128 bits but it actually covers
235 // all possible 'physical' RVV vector register lengths from 128 ~ 1024
236 // bits. The 'physical' RVV vector register length is detected during
237 // startup, so the register allocator is able to identify the correct
238 // number of bytes needed for an RVV spill/unspill.
239
240 reg_def V0 ( SOC, SOC, Op_VecA, 0, v0->as_VMReg() );
241 reg_def V0_H ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next() );
242 reg_def V0_J ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next(2) );
243 reg_def V0_K ( SOC, SOC, Op_VecA, 0, v0->as_VMReg()->next(3) );
244
245 reg_def V1 ( SOC, SOC, Op_VecA, 1, v1->as_VMReg() );
246 reg_def V1_H ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next() );
247 reg_def V1_J ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next(2) );
248 reg_def V1_K ( SOC, SOC, Op_VecA, 1, v1->as_VMReg()->next(3) );
249
250 reg_def V2 ( SOC, SOC, Op_VecA, 2, v2->as_VMReg() );
251 reg_def V2_H ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next() );
252 reg_def V2_J ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next(2) );
253 reg_def V2_K ( SOC, SOC, Op_VecA, 2, v2->as_VMReg()->next(3) );
254
255 reg_def V3 ( SOC, SOC, Op_VecA, 3, v3->as_VMReg() );
256 reg_def V3_H ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next() );
257 reg_def V3_J ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next(2) );
258 reg_def V3_K ( SOC, SOC, Op_VecA, 3, v3->as_VMReg()->next(3) );
259
260 reg_def V4 ( SOC, SOC, Op_VecA, 4, v4->as_VMReg() );
261 reg_def V4_H ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next() );
262 reg_def V4_J ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next(2) );
263 reg_def V4_K ( SOC, SOC, Op_VecA, 4, v4->as_VMReg()->next(3) );
264
265 reg_def V5 ( SOC, SOC, Op_VecA, 5, v5->as_VMReg() );
266 reg_def V5_H ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next() );
267 reg_def V5_J ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next(2) );
268 reg_def V5_K ( SOC, SOC, Op_VecA, 5, v5->as_VMReg()->next(3) );
269
270 reg_def V6 ( SOC, SOC, Op_VecA, 6, v6->as_VMReg() );
271 reg_def V6_H ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next() );
272 reg_def V6_J ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next(2) );
273 reg_def V6_K ( SOC, SOC, Op_VecA, 6, v6->as_VMReg()->next(3) );
274
275 reg_def V7 ( SOC, SOC, Op_VecA, 7, v7->as_VMReg() );
276 reg_def V7_H ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next() );
277 reg_def V7_J ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next(2) );
278 reg_def V7_K ( SOC, SOC, Op_VecA, 7, v7->as_VMReg()->next(3) );
279
280 reg_def V8 ( SOC, SOC, Op_VecA, 8, v8->as_VMReg() );
281 reg_def V8_H ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next() );
282 reg_def V8_J ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next(2) );
283 reg_def V8_K ( SOC, SOC, Op_VecA, 8, v8->as_VMReg()->next(3) );
284
285 reg_def V9 ( SOC, SOC, Op_VecA, 9, v9->as_VMReg() );
286 reg_def V9_H ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next() );
287 reg_def V9_J ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next(2) );
288 reg_def V9_K ( SOC, SOC, Op_VecA, 9, v9->as_VMReg()->next(3) );
289
290 reg_def V10 ( SOC, SOC, Op_VecA, 10, v10->as_VMReg() );
291 reg_def V10_H ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next() );
292 reg_def V10_J ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(2) );
293 reg_def V10_K ( SOC, SOC, Op_VecA, 10, v10->as_VMReg()->next(3) );
294
295 reg_def V11 ( SOC, SOC, Op_VecA, 11, v11->as_VMReg() );
296 reg_def V11_H ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next() );
297 reg_def V11_J ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(2) );
298 reg_def V11_K ( SOC, SOC, Op_VecA, 11, v11->as_VMReg()->next(3) );
299
300 reg_def V12 ( SOC, SOC, Op_VecA, 12, v12->as_VMReg() );
301 reg_def V12_H ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next() );
302 reg_def V12_J ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(2) );
303 reg_def V12_K ( SOC, SOC, Op_VecA, 12, v12->as_VMReg()->next(3) );
304
305 reg_def V13 ( SOC, SOC, Op_VecA, 13, v13->as_VMReg() );
306 reg_def V13_H ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next() );
307 reg_def V13_J ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(2) );
308 reg_def V13_K ( SOC, SOC, Op_VecA, 13, v13->as_VMReg()->next(3) );
309
310 reg_def V14 ( SOC, SOC, Op_VecA, 14, v14->as_VMReg() );
311 reg_def V14_H ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next() );
312 reg_def V14_J ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(2) );
313 reg_def V14_K ( SOC, SOC, Op_VecA, 14, v14->as_VMReg()->next(3) );
314
315 reg_def V15 ( SOC, SOC, Op_VecA, 15, v15->as_VMReg() );
316 reg_def V15_H ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next() );
317 reg_def V15_J ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(2) );
318 reg_def V15_K ( SOC, SOC, Op_VecA, 15, v15->as_VMReg()->next(3) );
319
320 reg_def V16 ( SOC, SOC, Op_VecA, 16, v16->as_VMReg() );
321 reg_def V16_H ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next() );
322 reg_def V16_J ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(2) );
323 reg_def V16_K ( SOC, SOC, Op_VecA, 16, v16->as_VMReg()->next(3) );
324
325 reg_def V17 ( SOC, SOC, Op_VecA, 17, v17->as_VMReg() );
326 reg_def V17_H ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next() );
327 reg_def V17_J ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(2) );
328 reg_def V17_K ( SOC, SOC, Op_VecA, 17, v17->as_VMReg()->next(3) );
329
330 reg_def V18 ( SOC, SOC, Op_VecA, 18, v18->as_VMReg() );
331 reg_def V18_H ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next() );
332 reg_def V18_J ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(2) );
333 reg_def V18_K ( SOC, SOC, Op_VecA, 18, v18->as_VMReg()->next(3) );
334
335 reg_def V19 ( SOC, SOC, Op_VecA, 19, v19->as_VMReg() );
336 reg_def V19_H ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next() );
337 reg_def V19_J ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(2) );
338 reg_def V19_K ( SOC, SOC, Op_VecA, 19, v19->as_VMReg()->next(3) );
339
340 reg_def V20 ( SOC, SOC, Op_VecA, 20, v20->as_VMReg() );
341 reg_def V20_H ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next() );
342 reg_def V20_J ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(2) );
343 reg_def V20_K ( SOC, SOC, Op_VecA, 20, v20->as_VMReg()->next(3) );
344
345 reg_def V21 ( SOC, SOC, Op_VecA, 21, v21->as_VMReg() );
346 reg_def V21_H ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next() );
347 reg_def V21_J ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(2) );
348 reg_def V21_K ( SOC, SOC, Op_VecA, 21, v21->as_VMReg()->next(3) );
349
350 reg_def V22 ( SOC, SOC, Op_VecA, 22, v22->as_VMReg() );
351 reg_def V22_H ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next() );
352 reg_def V22_J ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(2) );
353 reg_def V22_K ( SOC, SOC, Op_VecA, 22, v22->as_VMReg()->next(3) );
354
355 reg_def V23 ( SOC, SOC, Op_VecA, 23, v23->as_VMReg() );
356 reg_def V23_H ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next() );
357 reg_def V23_J ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(2) );
358 reg_def V23_K ( SOC, SOC, Op_VecA, 23, v23->as_VMReg()->next(3) );
359
360 reg_def V24 ( SOC, SOC, Op_VecA, 24, v24->as_VMReg() );
361 reg_def V24_H ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next() );
362 reg_def V24_J ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(2) );
363 reg_def V24_K ( SOC, SOC, Op_VecA, 24, v24->as_VMReg()->next(3) );
364
365 reg_def V25 ( SOC, SOC, Op_VecA, 25, v25->as_VMReg() );
366 reg_def V25_H ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next() );
367 reg_def V25_J ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(2) );
368 reg_def V25_K ( SOC, SOC, Op_VecA, 25, v25->as_VMReg()->next(3) );
369
370 reg_def V26 ( SOC, SOC, Op_VecA, 26, v26->as_VMReg() );
371 reg_def V26_H ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next() );
372 reg_def V26_J ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(2) );
373 reg_def V26_K ( SOC, SOC, Op_VecA, 26, v26->as_VMReg()->next(3) );
374
375 reg_def V27 ( SOC, SOC, Op_VecA, 27, v27->as_VMReg() );
376 reg_def V27_H ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next() );
377 reg_def V27_J ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(2) );
378 reg_def V27_K ( SOC, SOC, Op_VecA, 27, v27->as_VMReg()->next(3) );
379
380 reg_def V28 ( SOC, SOC, Op_VecA, 28, v28->as_VMReg() );
381 reg_def V28_H ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next() );
382 reg_def V28_J ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(2) );
383 reg_def V28_K ( SOC, SOC, Op_VecA, 28, v28->as_VMReg()->next(3) );
384
385 reg_def V29 ( SOC, SOC, Op_VecA, 29, v29->as_VMReg() );
386 reg_def V29_H ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next() );
387 reg_def V29_J ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(2) );
388 reg_def V29_K ( SOC, SOC, Op_VecA, 29, v29->as_VMReg()->next(3) );
389
390 reg_def V30 ( SOC, SOC, Op_VecA, 30, v30->as_VMReg() );
391 reg_def V30_H ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next() );
392 reg_def V30_J ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(2) );
393 reg_def V30_K ( SOC, SOC, Op_VecA, 30, v30->as_VMReg()->next(3) );
394
395 reg_def V31 ( SOC, SOC, Op_VecA, 31, v31->as_VMReg() );
396 reg_def V31_H ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next() );
397 reg_def V31_J ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(2) );
398 reg_def V31_K ( SOC, SOC, Op_VecA, 31, v31->as_VMReg()->next(3) );
399
400 // ----------------------------
401 // Special Registers
402 // ----------------------------
403
404 // On riscv, the physical flag register is missing, so we use t1 instead,
405 // to bridge the RegFlag semantics in share/opto
406
407 reg_def RFLAGS (SOC, SOC, Op_RegFlags, 6, x6->as_VMReg() );
408
409 // Specify priority of register selection within phases of register
410 // allocation. Highest priority is first. A useful heuristic is to
411 // give registers a low priority when they are required by machine
412 // instructions, like EAX and EDX on I486, and choose no-save registers
413 // before save-on-call, & save-on-call before save-on-entry. Registers
414 // which participate in fixed calling sequences should come last.
415 // Registers which are used as pairs must fall on an even boundary.
416
417 alloc_class chunk0(
418 // volatiles
419 R7, R7_H,
420 R28, R28_H,
421 R29, R29_H,
422 R30, R30_H,
423 R31, R31_H,
424
425 // arg registers
426 R10, R10_H,
427 R11, R11_H,
428 R12, R12_H,
429 R13, R13_H,
430 R14, R14_H,
431 R15, R15_H,
432 R16, R16_H,
433 R17, R17_H,
434
435 // non-volatiles
436 R9, R9_H,
437 R18, R18_H,
438 R19, R19_H,
439 R20, R20_H,
440 R21, R21_H,
441 R22, R22_H,
442 R24, R24_H,
443 R25, R25_H,
444 R26, R26_H,
445
446 // non-allocatable registers
447 R23, R23_H, // java thread
448 R27, R27_H, // heapbase
449 R4, R4_H, // thread
450 R8, R8_H, // fp
451 R0, R0_H, // zero
452 R1, R1_H, // ra
453 R2, R2_H, // sp
454 R3, R3_H, // gp
455 );
456
457 alloc_class chunk1(
458
459 // no save
460 F0, F0_H,
461 F1, F1_H,
462 F2, F2_H,
463 F3, F3_H,
464 F4, F4_H,
465 F5, F5_H,
466 F6, F6_H,
467 F7, F7_H,
468 F28, F28_H,
469 F29, F29_H,
470 F30, F30_H,
471 F31, F31_H,
472
473 // arg registers
474 F10, F10_H,
475 F11, F11_H,
476 F12, F12_H,
477 F13, F13_H,
478 F14, F14_H,
479 F15, F15_H,
480 F16, F16_H,
481 F17, F17_H,
482
483 // non-volatiles
484 F8, F8_H,
485 F9, F9_H,
486 F18, F18_H,
487 F19, F19_H,
488 F20, F20_H,
489 F21, F21_H,
490 F22, F22_H,
491 F23, F23_H,
492 F24, F24_H,
493 F25, F25_H,
494 F26, F26_H,
495 F27, F27_H,
496 );
497
498 alloc_class chunk2(
499 V0, V0_H, V0_J, V0_K,
500 V1, V1_H, V1_J, V1_K,
501 V2, V2_H, V2_J, V2_K,
502 V3, V3_H, V3_J, V3_K,
503 V4, V4_H, V4_J, V4_K,
504 V5, V5_H, V5_J, V5_K,
505 V6, V6_H, V6_J, V6_K,
506 V7, V7_H, V7_J, V7_K,
507 V8, V8_H, V8_J, V8_K,
508 V9, V9_H, V9_J, V9_K,
509 V10, V10_H, V10_J, V10_K,
510 V11, V11_H, V11_J, V11_K,
511 V12, V12_H, V12_J, V12_K,
512 V13, V13_H, V13_J, V13_K,
513 V14, V14_H, V14_J, V14_K,
514 V15, V15_H, V15_J, V15_K,
515 V16, V16_H, V16_J, V16_K,
516 V17, V17_H, V17_J, V17_K,
517 V18, V18_H, V18_J, V18_K,
518 V19, V19_H, V19_J, V19_K,
519 V20, V20_H, V20_J, V20_K,
520 V21, V21_H, V21_J, V21_K,
521 V22, V22_H, V22_J, V22_K,
522 V23, V23_H, V23_J, V23_K,
523 V24, V24_H, V24_J, V24_K,
524 V25, V25_H, V25_J, V25_K,
525 V26, V26_H, V26_J, V26_K,
526 V27, V27_H, V27_J, V27_K,
527 V28, V28_H, V28_J, V28_K,
528 V29, V29_H, V29_J, V29_K,
529 V30, V30_H, V30_J, V30_K,
530 V31, V31_H, V31_J, V31_K,
531 );
532
533 alloc_class chunk3(RFLAGS);
534
535 //----------Architecture Description Register Classes--------------------------
536 // Several register classes are automatically defined based upon information in
537 // this architecture description.
538 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
539 // 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
540 //
541
542 // Class for all 32 bit general purpose registers
543 reg_class all_reg32(
544 R0,
545 R1,
546 R2,
547 R3,
548 R4,
549 R7,
550 R8,
551 R9,
552 R10,
553 R11,
554 R12,
555 R13,
556 R14,
557 R15,
558 R16,
559 R17,
560 R18,
561 R19,
562 R20,
563 R21,
564 R22,
565 R23,
566 R24,
567 R25,
568 R26,
569 R27,
570 R28,
571 R29,
572 R30,
573 R31
574 );
575
576 // Class for any 32 bit integer registers (excluding zr)
577 reg_class any_reg32 %{
578 return _ANY_REG32_mask;
579 %}
580
581 // Singleton class for R10 int register
582 reg_class int_r10_reg(R10);
583
584 // Singleton class for R12 int register
585 reg_class int_r12_reg(R12);
586
587 // Singleton class for R13 int register
588 reg_class int_r13_reg(R13);
589
590 // Singleton class for R14 int register
591 reg_class int_r14_reg(R14);
592
593 // Class for all long integer registers
594 reg_class all_reg(
595 R0, R0_H,
596 R1, R1_H,
597 R2, R2_H,
598 R3, R3_H,
599 R4, R4_H,
600 R7, R7_H,
601 R8, R8_H,
602 R9, R9_H,
603 R10, R10_H,
604 R11, R11_H,
605 R12, R12_H,
606 R13, R13_H,
607 R14, R14_H,
608 R15, R15_H,
609 R16, R16_H,
610 R17, R17_H,
611 R18, R18_H,
612 R19, R19_H,
613 R20, R20_H,
614 R21, R21_H,
615 R22, R22_H,
616 R23, R23_H,
617 R24, R24_H,
618 R25, R25_H,
619 R26, R26_H,
620 R27, R27_H,
621 R28, R28_H,
622 R29, R29_H,
623 R30, R30_H,
624 R31, R31_H
625 );
626
627 // Class for all long integer registers (excluding zr)
628 reg_class any_reg %{
629 return _ANY_REG_mask;
630 %}
631
632 // Class for non-allocatable 32 bit registers
633 reg_class non_allocatable_reg32(
634 R0, // zr
635 R1, // ra
636 R2, // sp
637 R3, // gp
638 R4, // tp
639 R23 // java thread
640 );
641
642 // Class for non-allocatable 64 bit registers
643 reg_class non_allocatable_reg(
644 R0, R0_H, // zr
645 R1, R1_H, // ra
646 R2, R2_H, // sp
647 R3, R3_H, // gp
648 R4, R4_H, // tp
649 R23, R23_H // java thread
650 );
651
652 // Class for all non-special integer registers
653 reg_class no_special_reg32 %{
654 return _NO_SPECIAL_REG32_mask;
655 %}
656
657 // Class for all non-special long integer registers
658 reg_class no_special_reg %{
659 return _NO_SPECIAL_REG_mask;
660 %}
661
662 reg_class ptr_reg %{
663 return _PTR_REG_mask;
664 %}
665
666 // Class for all non_special pointer registers
667 reg_class no_special_ptr_reg %{
668 return _NO_SPECIAL_PTR_REG_mask;
669 %}
670
671 // Class for all non_special pointer registers (excluding fp)
672 reg_class no_special_no_fp_ptr_reg %{
673 return _NO_SPECIAL_NO_FP_PTR_REG_mask;
674 %}
675
676 // Class for 64 bit register r10
677 reg_class r10_reg(
678 R10, R10_H
679 );
680
681 // Class for 64 bit register r11
682 reg_class r11_reg(
683 R11, R11_H
684 );
685
686 // Class for 64 bit register r12
687 reg_class r12_reg(
688 R12, R12_H
689 );
690
691 // Class for 64 bit register r13
692 reg_class r13_reg(
693 R13, R13_H
694 );
695
696 // Class for 64 bit register r14
697 reg_class r14_reg(
698 R14, R14_H
699 );
700
701 // Class for 64 bit register r15
702 reg_class r15_reg(
703 R15, R15_H
704 );
705
706 // Class for 64 bit register r16
707 reg_class r16_reg(
708 R16, R16_H
709 );
710
711 // Class for method register
712 reg_class method_reg(
713 R31, R31_H
714 );
715
716 // Class for java thread register
717 reg_class java_thread_reg(
718 R23, R23_H
719 );
720
721 reg_class r28_reg(
722 R28, R28_H
723 );
724
725 reg_class r29_reg(
726 R29, R29_H
727 );
728
729 reg_class r30_reg(
730 R30, R30_H
731 );
732
733 reg_class r31_reg(
734 R31, R31_H
735 );
736
737 // Class for zero registesr
738 reg_class zr_reg(
739 R0, R0_H
740 );
741
742 // Class for thread register
743 reg_class thread_reg(
744 R4, R4_H
745 );
746
747 // Class for frame pointer register
748 reg_class fp_reg(
749 R8, R8_H
750 );
751
752 // Class for link register
753 reg_class ra_reg(
754 R1, R1_H
755 );
756
757 // Class for long sp register
758 reg_class sp_reg(
759 R2, R2_H
760 );
761
762 // Class for all float registers
763 reg_class float_reg(
764 F0,
765 F1,
766 F2,
767 F3,
768 F4,
769 F5,
770 F6,
771 F7,
772 F8,
773 F9,
774 F10,
775 F11,
776 F12,
777 F13,
778 F14,
779 F15,
780 F16,
781 F17,
782 F18,
783 F19,
784 F20,
785 F21,
786 F22,
787 F23,
788 F24,
789 F25,
790 F26,
791 F27,
792 F28,
793 F29,
794 F30,
795 F31
796 );
797
798 // Double precision float registers have virtual `high halves' that
799 // are needed by the allocator.
800 // Class for all double registers
801 reg_class double_reg(
802 F0, F0_H,
803 F1, F1_H,
804 F2, F2_H,
805 F3, F3_H,
806 F4, F4_H,
807 F5, F5_H,
808 F6, F6_H,
809 F7, F7_H,
810 F8, F8_H,
811 F9, F9_H,
812 F10, F10_H,
813 F11, F11_H,
814 F12, F12_H,
815 F13, F13_H,
816 F14, F14_H,
817 F15, F15_H,
818 F16, F16_H,
819 F17, F17_H,
820 F18, F18_H,
821 F19, F19_H,
822 F20, F20_H,
823 F21, F21_H,
824 F22, F22_H,
825 F23, F23_H,
826 F24, F24_H,
827 F25, F25_H,
828 F26, F26_H,
829 F27, F27_H,
830 F28, F28_H,
831 F29, F29_H,
832 F30, F30_H,
833 F31, F31_H
834 );
835
836 // Class for RVV vector registers
837 // Note: v0, v30 and v31 are used as mask registers.
838 reg_class vectora_reg(
839 V1, V1_H, V1_J, V1_K,
840 V2, V2_H, V2_J, V2_K,
841 V3, V3_H, V3_J, V3_K,
842 V4, V4_H, V4_J, V4_K,
843 V5, V5_H, V5_J, V5_K,
844 V6, V6_H, V6_J, V6_K,
845 V7, V7_H, V7_J, V7_K,
846 V8, V8_H, V8_J, V8_K,
847 V9, V9_H, V9_J, V9_K,
848 V10, V10_H, V10_J, V10_K,
849 V11, V11_H, V11_J, V11_K,
850 V12, V12_H, V12_J, V12_K,
851 V13, V13_H, V13_J, V13_K,
852 V14, V14_H, V14_J, V14_K,
853 V15, V15_H, V15_J, V15_K,
854 V16, V16_H, V16_J, V16_K,
855 V17, V17_H, V17_J, V17_K,
856 V18, V18_H, V18_J, V18_K,
857 V19, V19_H, V19_J, V19_K,
858 V20, V20_H, V20_J, V20_K,
859 V21, V21_H, V21_J, V21_K,
860 V22, V22_H, V22_J, V22_K,
861 V23, V23_H, V23_J, V23_K,
862 V24, V24_H, V24_J, V24_K,
863 V25, V25_H, V25_J, V25_K,
864 V26, V26_H, V26_J, V26_K,
865 V27, V27_H, V27_J, V27_K,
866 V28, V28_H, V28_J, V28_K,
867 V29, V29_H, V29_J, V29_K
868 );
869
870 // Class for 64 bit register f0
871 reg_class f0_reg(
872 F0, F0_H
873 );
874
875 // Class for 64 bit register f1
876 reg_class f1_reg(
877 F1, F1_H
878 );
879
880 // Class for 64 bit register f2
881 reg_class f2_reg(
882 F2, F2_H
883 );
884
885 // Class for 64 bit register f3
886 reg_class f3_reg(
887 F3, F3_H
888 );
889
890 // class for vector register v1
891 reg_class v1_reg(
892 V1, V1_H, V1_J, V1_K
893 );
894
895 // class for vector register v2
896 reg_class v2_reg(
897 V2, V2_H, V2_J, V2_K
898 );
899
900 // class for vector register v3
901 reg_class v3_reg(
902 V3, V3_H, V3_J, V3_K
903 );
904
905 // class for vector register v4
906 reg_class v4_reg(
907 V4, V4_H, V4_J, V4_K
908 );
909
910 // class for vector register v5
911 reg_class v5_reg(
912 V5, V5_H, V5_J, V5_K
913 );
914
915 // class for vector register v6
916 reg_class v6_reg(
917 V6, V6_H, V6_J, V6_K
918 );
919
920 // class for vector register v7
921 reg_class v7_reg(
922 V7, V7_H, V7_J, V7_K
923 );
924
925 // class for vector register v8
926 reg_class v8_reg(
927 V8, V8_H, V8_J, V8_K
928 );
929
930 // class for vector register v9
931 reg_class v9_reg(
932 V9, V9_H, V9_J, V9_K
933 );
934
935 // class for vector register v10
936 reg_class v10_reg(
937 V10, V10_H, V10_J, V10_K
938 );
939
940 // class for vector register v11
941 reg_class v11_reg(
942 V11, V11_H, V11_J, V11_K
943 );
944
945 // class for condition codes
946 reg_class reg_flags(RFLAGS);
947
948 // Class for RVV v0 mask register
949 // https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#53-vector-masking
950 // The mask value used to control execution of a masked vector
951 // instruction is always supplied by vector register v0.
952 reg_class vmask_reg_v0 (
953 V0
954 );
955
956 // Class for RVV mask registers
957 // We need two more vmask registers to do the vector mask logical ops,
958 // so define v30, v31 as mask register too.
959 reg_class vmask_reg (
960 V0,
961 V30,
962 V31
963 );
964 %}
965
966 //----------DEFINITION BLOCK---------------------------------------------------
967 // Define name --> value mappings to inform the ADLC of an integer valued name
968 // Current support includes integer values in the range [0, 0x7FFFFFFF]
969 // Format:
970 // int_def <name> ( <int_value>, <expression>);
971 // Generated Code in ad_<arch>.hpp
972 // #define <name> (<expression>)
973 // // value == <int_value>
974 // Generated code in ad_<arch>.cpp adlc_verification()
975 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
976 //
977
978 // we follow the ppc-aix port in using a simple cost model which ranks
979 // register operations as cheap, memory ops as more expensive and
980 // branches as most expensive. the first two have a low as well as a
981 // normal cost. huge cost appears to be a way of saying don't do
982 // something
983
984 definitions %{
985 // The default cost (of a register move instruction).
986 int_def DEFAULT_COST ( 100, 100);
987 int_def ALU_COST ( 100, 1 * DEFAULT_COST); // unknown, const, arith, shift, slt,
988 // multi, auipc, nop, logical, move
989 int_def LOAD_COST ( 300, 3 * DEFAULT_COST); // load, fpload
990 int_def STORE_COST ( 100, 1 * DEFAULT_COST); // store, fpstore
991 int_def XFER_COST ( 300, 3 * DEFAULT_COST); // mfc, mtc, fcvt, fmove, fcmp
992 int_def FMVX_COST ( 100, 1 * DEFAULT_COST); // shuffles with no conversion
993 int_def BRANCH_COST ( 200, 2 * DEFAULT_COST); // branch, jmp, call
994 int_def IMUL_COST ( 1000, 10 * DEFAULT_COST); // imul
995 int_def IDIVSI_COST ( 3400, 34 * DEFAULT_COST); // idivsi
996 int_def IDIVDI_COST ( 6600, 66 * DEFAULT_COST); // idivdi
997 int_def FMUL_SINGLE_COST ( 500, 5 * DEFAULT_COST); // fmul, fmadd
998 int_def FMUL_DOUBLE_COST ( 700, 7 * DEFAULT_COST); // fmul, fmadd
999 int_def FDIV_COST ( 2000, 20 * DEFAULT_COST); // fdiv
1000 int_def FSQRT_COST ( 2500, 25 * DEFAULT_COST); // fsqrt
1001 int_def VOLATILE_REF_COST ( 1000, 10 * DEFAULT_COST);
1002 int_def CACHE_MISS_COST ( 2000, 20 * DEFAULT_COST); // typicall cache miss penalty
1003 %}
1004
1005
1006
1007 //----------SOURCE BLOCK-------------------------------------------------------
1008 // This is a block of C++ code which provides values, functions, and
1009 // definitions necessary in the rest of the architecture description
1010
1011 source_hpp %{
1012
1013 #include "asm/macroAssembler.hpp"
1014 #include "gc/shared/barrierSetAssembler.hpp"
1015 #include "gc/shared/cardTable.hpp"
1016 #include "gc/shared/cardTableBarrierSet.hpp"
1017 #include "gc/shared/collectedHeap.hpp"
1018 #include "opto/addnode.hpp"
1019 #include "opto/convertnode.hpp"
1020 #include "runtime/objectMonitor.hpp"
1021
1022 extern RegMask _ANY_REG32_mask;
1023 extern RegMask _ANY_REG_mask;
1024 extern RegMask _PTR_REG_mask;
1025 extern RegMask _NO_SPECIAL_REG32_mask;
1026 extern RegMask _NO_SPECIAL_REG_mask;
1027 extern RegMask _NO_SPECIAL_PTR_REG_mask;
1028 extern RegMask _NO_SPECIAL_NO_FP_PTR_REG_mask;
1029
1030 class CallStubImpl {
1031
1032 //--------------------------------------------------------------
1033 //---< Used for optimization in Compile::shorten_branches >---
1034 //--------------------------------------------------------------
1035
1036 public:
1037 // Size of call trampoline stub.
1038 static uint size_call_trampoline() {
1039 return 0; // no call trampolines on this platform
1040 }
1041
1042 // number of relocations needed by a call trampoline stub
1043 static uint reloc_call_trampoline() {
1044 return 0; // no call trampolines on this platform
1045 }
1046 };
1047
1048 class HandlerImpl {
1049
1050 public:
1051
1052 static int emit_exception_handler(C2_MacroAssembler *masm);
1053 static int emit_deopt_handler(C2_MacroAssembler* masm);
1054
1055 static uint size_exception_handler() {
1056 return MacroAssembler::far_branch_size();
1057 }
1058
1059 static uint size_deopt_handler() {
1060 // count auipc + far branch
1061 return NativeInstruction::instruction_size + MacroAssembler::far_branch_size();
1062 }
1063 };
1064
1065 class Node::PD {
1066 public:
1067 enum NodeFlags {
1068 _last_flag = Node::_last_flag
1069 };
1070 };
1071
1072 bool is_CAS(int opcode, bool maybe_volatile);
1073
1074 // predicate controlling translation of CompareAndSwapX
1075 bool needs_acquiring_load_reserved(const Node *load);
1076
1077 // predicate controlling addressing modes
1078 bool size_fits_all_mem_uses(AddPNode* addp, int shift);
1079 %}
1080
1081 source %{
1082
1083 // Derived RegMask with conditionally allocatable registers
1084
1085 RegMask _ANY_REG32_mask;
1086 RegMask _ANY_REG_mask;
1087 RegMask _PTR_REG_mask;
1088 RegMask _NO_SPECIAL_REG32_mask;
1089 RegMask _NO_SPECIAL_REG_mask;
1090 RegMask _NO_SPECIAL_PTR_REG_mask;
1091 RegMask _NO_SPECIAL_NO_FP_PTR_REG_mask;
1092
1093 void reg_mask_init() {
1094
1095 _ANY_REG32_mask = _ALL_REG32_mask;
1096 _ANY_REG32_mask.Remove(OptoReg::as_OptoReg(x0->as_VMReg()));
1097
1098 _ANY_REG_mask = _ALL_REG_mask;
1099 _ANY_REG_mask.SUBTRACT(_ZR_REG_mask);
1100
1101 _PTR_REG_mask = _ALL_REG_mask;
1102 _PTR_REG_mask.SUBTRACT(_ZR_REG_mask);
1103
1104 _NO_SPECIAL_REG32_mask = _ALL_REG32_mask;
1105 _NO_SPECIAL_REG32_mask.SUBTRACT(_NON_ALLOCATABLE_REG32_mask);
1106
1107 _NO_SPECIAL_REG_mask = _ALL_REG_mask;
1108 _NO_SPECIAL_REG_mask.SUBTRACT(_NON_ALLOCATABLE_REG_mask);
1109
1110 _NO_SPECIAL_PTR_REG_mask = _ALL_REG_mask;
1111 _NO_SPECIAL_PTR_REG_mask.SUBTRACT(_NON_ALLOCATABLE_REG_mask);
1112
1113 // x27 is not allocatable when compressed oops is on
1114 if (UseCompressedOops) {
1115 _NO_SPECIAL_REG32_mask.Remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1116 _NO_SPECIAL_REG_mask.Remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1117 _NO_SPECIAL_PTR_REG_mask.Remove(OptoReg::as_OptoReg(x27->as_VMReg()));
1118 }
1119
1120 // x8 is not allocatable when PreserveFramePointer is on
1121 if (PreserveFramePointer) {
1122 _NO_SPECIAL_REG32_mask.Remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1123 _NO_SPECIAL_REG_mask.Remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1124 _NO_SPECIAL_PTR_REG_mask.Remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1125 }
1126
1127 _NO_SPECIAL_NO_FP_PTR_REG_mask = _NO_SPECIAL_PTR_REG_mask;
1128 _NO_SPECIAL_NO_FP_PTR_REG_mask.Remove(OptoReg::as_OptoReg(x8->as_VMReg()));
1129 }
1130
1131 void PhaseOutput::pd_perform_mach_node_analysis() {
1132 }
1133
1134 int MachNode::pd_alignment_required() const {
1135 return 1;
1136 }
1137
1138 int MachNode::compute_padding(int current_offset) const {
1139 return 0;
1140 }
1141
1142 // is_CAS(int opcode, bool maybe_volatile)
1143 //
1144 // return true if opcode is one of the possible CompareAndSwapX
1145 // values otherwise false.
1146 bool is_CAS(int opcode, bool maybe_volatile)
1147 {
1148 switch (opcode) {
1149 // We handle these
1150 case Op_CompareAndSwapI:
1151 case Op_CompareAndSwapL:
1152 case Op_CompareAndSwapP:
1153 case Op_CompareAndSwapN:
1154 case Op_ShenandoahCompareAndSwapP:
1155 case Op_ShenandoahCompareAndSwapN:
1156 case Op_CompareAndSwapB:
1157 case Op_CompareAndSwapS:
1158 case Op_GetAndSetI:
1159 case Op_GetAndSetL:
1160 case Op_GetAndSetP:
1161 case Op_GetAndSetN:
1162 case Op_GetAndAddI:
1163 case Op_GetAndAddL:
1164 return true;
1165 case Op_CompareAndExchangeI:
1166 case Op_CompareAndExchangeN:
1167 case Op_CompareAndExchangeB:
1168 case Op_CompareAndExchangeS:
1169 case Op_CompareAndExchangeL:
1170 case Op_CompareAndExchangeP:
1171 case Op_WeakCompareAndSwapB:
1172 case Op_WeakCompareAndSwapS:
1173 case Op_WeakCompareAndSwapI:
1174 case Op_WeakCompareAndSwapL:
1175 case Op_WeakCompareAndSwapP:
1176 case Op_WeakCompareAndSwapN:
1177 case Op_ShenandoahWeakCompareAndSwapP:
1178 case Op_ShenandoahWeakCompareAndSwapN:
1179 case Op_ShenandoahCompareAndExchangeP:
1180 case Op_ShenandoahCompareAndExchangeN:
1181 return maybe_volatile;
1182 default:
1183 return false;
1184 }
1185 }
1186
1187 // predicate controlling translation of CAS
1188 //
1189 // returns true if CAS needs to use an acquiring load otherwise false
1190 bool needs_acquiring_load_reserved(const Node *n)
1191 {
1192 assert(n != nullptr && is_CAS(n->Opcode(), true), "expecting a compare and swap");
1193
1194 LoadStoreNode* ldst = n->as_LoadStore();
1195 if (n != nullptr && is_CAS(n->Opcode(), false)) {
1196 assert(ldst != nullptr && ldst->trailing_membar() != nullptr, "expected trailing membar");
1197 } else {
1198 return ldst != nullptr && ldst->trailing_membar() != nullptr;
1199 }
1200 // so we can just return true here
1201 return true;
1202 }
1203 #define __ masm->
1204
1205 // advance declarations for helper functions to convert register
1206 // indices to register objects
1207
1208 // the ad file has to provide implementations of certain methods
1209 // expected by the generic code
1210 //
1211 // REQUIRED FUNCTIONALITY
1212
1213 //=============================================================================
1214
1215 // !!!!! Special hack to get all types of calls to specify the byte offset
1216 // from the start of the call to the point where the return address
1217 // will point.
1218
1219 int MachCallStaticJavaNode::ret_addr_offset()
1220 {
1221 return 3 * NativeInstruction::instruction_size; // auipc + ld + jalr
1222 }
1223
1224 int MachCallDynamicJavaNode::ret_addr_offset()
1225 {
1226 return NativeMovConstReg::movptr2_instruction_size + (3 * NativeInstruction::instruction_size); // movptr2, auipc + ld + jal
1227 }
1228
1229 int MachCallRuntimeNode::ret_addr_offset() {
1230 // For address inside the code cache the call will be:
1231 // auipc + jalr
1232 // For real runtime callouts it will be 8 instructions
1233 // see riscv_enc_java_to_runtime
1234 // la(t0, retaddr) -> auipc + addi
1235 // sd(t0, Address(xthread, JavaThread::last_Java_pc_offset())) -> sd
1236 // movptr(t1, addr, offset, t0) -> lui + lui + slli + add
1237 // jalr(t1, offset) -> jalr
1238 if (CodeCache::contains(_entry_point)) {
1239 return 2 * NativeInstruction::instruction_size;
1240 } else {
1241 return 8 * NativeInstruction::instruction_size;
1242 }
1243 }
1244
1245 //
1246 // Compute padding required for nodes which need alignment
1247 //
1248
1249 // With RVC a call instruction may get 2-byte aligned.
1250 // The address of the call instruction needs to be 4-byte aligned to
1251 // ensure that it does not span a cache line so that it can be patched.
1252 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
1253 {
1254 // to make sure the address of jal 4-byte aligned.
1255 return align_up(current_offset, alignment_required()) - current_offset;
1256 }
1257
1258 // With RVC a call instruction may get 2-byte aligned.
1259 // The address of the call instruction needs to be 4-byte aligned to
1260 // ensure that it does not span a cache line so that it can be patched.
1261 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
1262 {
1263 // skip the movptr2 in MacroAssembler::ic_call():
1264 // lui, lui, slli, add, addi
1265 // Though movptr2() has already 4-byte aligned with or without RVC,
1266 // We need to prevent from further changes by explicitly calculating the size.
1267 current_offset += NativeMovConstReg::movptr2_instruction_size;
1268 // to make sure the address of jal 4-byte aligned.
1269 return align_up(current_offset, alignment_required()) - current_offset;
1270 }
1271
1272 //=============================================================================
1273
1274 #ifndef PRODUCT
1275 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1276 assert_cond(st != nullptr);
1277 st->print("BREAKPOINT");
1278 }
1279 #endif
1280
1281 void MachBreakpointNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1282 __ ebreak();
1283 }
1284
1285 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1286 return MachNode::size(ra_);
1287 }
1288
1289 //=============================================================================
1290
1291 #ifndef PRODUCT
1292 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const {
1293 st->print("nop \t# %d bytes pad for loops and calls", _count);
1294 }
1295 #endif
1296
1297 void MachNopNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc*) const {
1298 Assembler::CompressibleRegion cr(masm); // nops shall be 2-byte under RVC for alignment purposes.
1299 for (int i = 0; i < _count; i++) {
1300 __ nop();
1301 }
1302 }
1303
1304 uint MachNopNode::size(PhaseRegAlloc*) const {
1305 return _count * (UseRVC ? NativeInstruction::compressed_instruction_size : NativeInstruction::instruction_size);
1306 }
1307
1308 //=============================================================================
1309 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
1310
1311 int ConstantTable::calculate_table_base_offset() const {
1312 return 0; // absolute addressing, no offset
1313 }
1314
1315 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1316 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1317 ShouldNotReachHere();
1318 }
1319
1320 void MachConstantBaseNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const {
1321 // Empty encoding
1322 }
1323
1324 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1325 return 0;
1326 }
1327
1328 #ifndef PRODUCT
1329 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1330 assert_cond(st != nullptr);
1331 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1332 }
1333 #endif
1334
1335 #ifndef PRODUCT
1336 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1337 assert_cond(st != nullptr && ra_ != nullptr);
1338 Compile* C = ra_->C;
1339
1340 int framesize = C->output()->frame_slots() << LogBytesPerInt;
1341
1342 if (C->output()->need_stack_bang(framesize)) {
1343 st->print("# stack bang size=%d\n\t", framesize);
1344 }
1345
1346 st->print("sd fp, [sp, #%d]\n\t", - 2 * wordSize);
1347 st->print("sd ra, [sp, #%d]\n\t", - wordSize);
1348 if (PreserveFramePointer) { st->print("sub fp, sp, #%d\n\t", 2 * wordSize); }
1349 st->print("sub sp, sp, #%d\n\t", framesize);
1350
1351 if (C->stub_function() == nullptr) {
1352 st->print("ld t0, [guard]\n\t");
1353 st->print("membar LoadLoad\n\t");
1354 st->print("ld t1, [xthread, #thread_disarmed_guard_value_offset]\n\t");
1355 st->print("beq t0, t1, skip\n\t");
1356 st->print("jalr #nmethod_entry_barrier_stub\n\t");
1357 st->print("j skip\n\t");
1358 st->print("guard: int\n\t");
1359 st->print("skip:\n\t");
1360 }
1361 }
1362 #endif
1363
1364 void MachPrologNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1365 assert_cond(ra_ != nullptr);
1366 Compile* C = ra_->C;
1367
1368 // n.b. frame size includes space for return pc and fp
1369 const int framesize = C->output()->frame_size_in_bytes();
1370
1371 // insert a nop at the start of the prolog so we can patch in a
1372 // branch if we need to invalidate the method later
1373 {
1374 Assembler::IncompressibleRegion ir(masm); // keep the nop as 4 bytes for patching.
1375 MacroAssembler::assert_alignment(__ pc());
1376 __ nop(); // 4 bytes
1377 }
1378
1379 assert_cond(C != nullptr);
1380
1381 if (C->clinit_barrier_on_entry()) {
1382 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
1383
1384 Label L_skip_barrier;
1385
1386 __ mov_metadata(t1, C->method()->holder()->constant_encoding());
1387 __ clinit_barrier(t1, t0, &L_skip_barrier);
1388 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
1389 __ bind(L_skip_barrier);
1390 }
1391
1392 int bangsize = C->output()->bang_size_in_bytes();
1393 if (C->output()->need_stack_bang(bangsize)) {
1394 __ generate_stack_overflow_check(bangsize);
1395 }
1396
1397 __ build_frame(framesize);
1398
1399 if (C->stub_function() == nullptr) {
1400 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
1401 // Dummy labels for just measuring the code size
1402 Label dummy_slow_path;
1403 Label dummy_continuation;
1404 Label dummy_guard;
1405 Label* slow_path = &dummy_slow_path;
1406 Label* continuation = &dummy_continuation;
1407 Label* guard = &dummy_guard;
1408 if (!Compile::current()->output()->in_scratch_emit_size()) {
1409 // Use real labels from actual stub when not emitting code for purpose of measuring its size
1410 C2EntryBarrierStub* stub = new (Compile::current()->comp_arena()) C2EntryBarrierStub();
1411 Compile::current()->output()->add_stub(stub);
1412 slow_path = &stub->entry();
1413 continuation = &stub->continuation();
1414 guard = &stub->guard();
1415 }
1416 // In the C2 code, we move the non-hot part of nmethod entry barriers out-of-line to a stub.
1417 bs->nmethod_entry_barrier(masm, slow_path, continuation, guard);
1418 }
1419
1420 if (VerifyStackAtCalls) {
1421 Unimplemented();
1422 }
1423
1424 C->output()->set_frame_complete(__ offset());
1425
1426 if (C->has_mach_constant_base_node()) {
1427 // NOTE: We set the table base offset here because users might be
1428 // emitted before MachConstantBaseNode.
1429 ConstantTable& constant_table = C->output()->constant_table();
1430 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1431 }
1432 }
1433
1434 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
1435 {
1436 assert_cond(ra_ != nullptr);
1437 return MachNode::size(ra_); // too many variables; just compute it
1438 // the hard way
1439 }
1440
1441 int MachPrologNode::reloc() const
1442 {
1443 return 0;
1444 }
1445
1446 //=============================================================================
1447
1448 #ifndef PRODUCT
1449 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1450 assert_cond(st != nullptr && ra_ != nullptr);
1451 Compile* C = ra_->C;
1452 assert_cond(C != nullptr);
1453 int framesize = C->output()->frame_size_in_bytes();
1454
1455 st->print("# pop frame %d\n\t", framesize);
1456
1457 if (framesize == 0) {
1458 st->print("ld ra, [sp,#%d]\n\t", (2 * wordSize));
1459 st->print("ld fp, [sp,#%d]\n\t", (3 * wordSize));
1460 st->print("add sp, sp, #%d\n\t", (2 * wordSize));
1461 } else {
1462 st->print("add sp, sp, #%d\n\t", framesize);
1463 st->print("ld ra, [sp,#%d]\n\t", - 2 * wordSize);
1464 st->print("ld fp, [sp,#%d]\n\t", - wordSize);
1465 }
1466
1467 if (do_polling() && C->is_method_compilation()) {
1468 st->print("# test polling word\n\t");
1469 st->print("ld t0, [xthread,#%d]\n\t", in_bytes(JavaThread::polling_word_offset()));
1470 st->print("bgtu sp, t0, #slow_path");
1471 }
1472 }
1473 #endif
1474
1475 void MachEpilogNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1476 assert_cond(ra_ != nullptr);
1477 Compile* C = ra_->C;
1478 assert_cond(C != nullptr);
1479 int framesize = C->output()->frame_size_in_bytes();
1480
1481 __ remove_frame(framesize);
1482
1483 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1484 __ reserved_stack_check();
1485 }
1486
1487 if (do_polling() && C->is_method_compilation()) {
1488 Label dummy_label;
1489 Label* code_stub = &dummy_label;
1490 if (!C->output()->in_scratch_emit_size()) {
1491 C2SafepointPollStub* stub = new (C->comp_arena()) C2SafepointPollStub(__ offset());
1492 C->output()->add_stub(stub);
1493 code_stub = &stub->entry();
1494 }
1495 __ relocate(relocInfo::poll_return_type);
1496 __ safepoint_poll(*code_stub, true /* at_return */, false /* acquire */, true /* in_nmethod */);
1497 }
1498 }
1499
1500 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1501 assert_cond(ra_ != nullptr);
1502 // Variable size. Determine dynamically.
1503 return MachNode::size(ra_);
1504 }
1505
1506 int MachEpilogNode::reloc() const {
1507 // Return number of relocatable values contained in this instruction.
1508 return 1; // 1 for polling page.
1509 }
1510 const Pipeline * MachEpilogNode::pipeline() const {
1511 return MachNode::pipeline_class();
1512 }
1513
1514 //=============================================================================
1515
1516 // Figure out which register class each belongs in: rc_int, rc_float or
1517 // rc_stack.
1518 enum RC { rc_bad, rc_int, rc_float, rc_vector, rc_stack };
1519
1520 static enum RC rc_class(OptoReg::Name reg) {
1521
1522 if (reg == OptoReg::Bad) {
1523 return rc_bad;
1524 }
1525
1526 // we have 30 int registers * 2 halves
1527 // (t0 and t1 are omitted)
1528 int slots_of_int_registers = Register::max_slots_per_register * (Register::number_of_registers - 2);
1529 if (reg < slots_of_int_registers) {
1530 return rc_int;
1531 }
1532
1533 // we have 32 float register * 2 halves
1534 int slots_of_float_registers = FloatRegister::max_slots_per_register * FloatRegister::number_of_registers;
1535 if (reg < slots_of_int_registers + slots_of_float_registers) {
1536 return rc_float;
1537 }
1538
1539 // we have 32 vector register * 4 halves
1540 int slots_of_vector_registers = VectorRegister::max_slots_per_register * VectorRegister::number_of_registers;
1541 if (reg < slots_of_int_registers + slots_of_float_registers + slots_of_vector_registers) {
1542 return rc_vector;
1543 }
1544
1545 // Between vector regs & stack is the flags regs.
1546 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1547
1548 return rc_stack;
1549 }
1550
1551 uint MachSpillCopyNode::implementation(C2_MacroAssembler *masm, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1552 assert_cond(ra_ != nullptr);
1553 Compile* C = ra_->C;
1554
1555 // Get registers to move.
1556 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1557 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1558 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1559 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1560
1561 enum RC src_hi_rc = rc_class(src_hi);
1562 enum RC src_lo_rc = rc_class(src_lo);
1563 enum RC dst_hi_rc = rc_class(dst_hi);
1564 enum RC dst_lo_rc = rc_class(dst_lo);
1565
1566 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1567
1568 if (src_hi != OptoReg::Bad && !bottom_type()->isa_vectmask()) {
1569 assert((src_lo & 1) == 0 && src_lo + 1 == src_hi &&
1570 (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi,
1571 "expected aligned-adjacent pairs");
1572 }
1573
1574 if (src_lo == dst_lo && src_hi == dst_hi) {
1575 return 0; // Self copy, no move.
1576 }
1577
1578 bool is64 = (src_lo & 1) == 0 && src_lo + 1 == src_hi &&
1579 (dst_lo & 1) == 0 && dst_lo + 1 == dst_hi;
1580 int src_offset = ra_->reg2offset(src_lo);
1581 int dst_offset = ra_->reg2offset(dst_lo);
1582
1583 if (bottom_type()->isa_vect() != nullptr) {
1584 uint ireg = ideal_reg();
1585 if (ireg == Op_VecA && masm) {
1586 int vector_reg_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
1587 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1588 // stack to stack
1589 __ spill_copy_vector_stack_to_stack(src_offset, dst_offset,
1590 vector_reg_size_in_bytes);
1591 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
1592 // vpr to stack
1593 __ spill(as_VectorRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo));
1594 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
1595 // stack to vpr
1596 __ unspill(as_VectorRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo));
1597 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
1598 // vpr to vpr
1599 __ vmv1r_v(as_VectorRegister(Matcher::_regEncode[dst_lo]), as_VectorRegister(Matcher::_regEncode[src_lo]));
1600 } else {
1601 ShouldNotReachHere();
1602 }
1603 } else if (bottom_type()->isa_vectmask() && masm) {
1604 int vmask_size_in_bytes = Matcher::scalable_predicate_reg_slots() * 32 / 8;
1605 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1606 // stack to stack
1607 __ spill_copy_vmask_stack_to_stack(src_offset, dst_offset,
1608 vmask_size_in_bytes);
1609 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_stack) {
1610 // vmask to stack
1611 __ spill_vmask(as_VectorRegister(Matcher::_regEncode[src_lo]), ra_->reg2offset(dst_lo));
1612 } else if (src_lo_rc == rc_stack && dst_lo_rc == rc_vector) {
1613 // stack to vmask
1614 __ unspill_vmask(as_VectorRegister(Matcher::_regEncode[dst_lo]), ra_->reg2offset(src_lo));
1615 } else if (src_lo_rc == rc_vector && dst_lo_rc == rc_vector) {
1616 // vmask to vmask
1617 __ vmv1r_v(as_VectorRegister(Matcher::_regEncode[dst_lo]), as_VectorRegister(Matcher::_regEncode[src_lo]));
1618 } else {
1619 ShouldNotReachHere();
1620 }
1621 }
1622 } else if (masm != nullptr) {
1623 switch (src_lo_rc) {
1624 case rc_int:
1625 if (dst_lo_rc == rc_int) { // gpr --> gpr copy
1626 if (!is64 && this->ideal_reg() != Op_RegI) { // zero extended for narrow oop or klass
1627 __ zext(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]), 32);
1628 } else {
1629 __ mv(as_Register(Matcher::_regEncode[dst_lo]), as_Register(Matcher::_regEncode[src_lo]));
1630 }
1631 } else if (dst_lo_rc == rc_float) { // gpr --> fpr copy
1632 if (is64) {
1633 __ fmv_d_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1634 as_Register(Matcher::_regEncode[src_lo]));
1635 } else {
1636 __ fmv_w_x(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1637 as_Register(Matcher::_regEncode[src_lo]));
1638 }
1639 } else { // gpr --> stack spill
1640 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1641 __ spill(as_Register(Matcher::_regEncode[src_lo]), is64, dst_offset);
1642 }
1643 break;
1644 case rc_float:
1645 if (dst_lo_rc == rc_int) { // fpr --> gpr copy
1646 if (is64) {
1647 __ fmv_x_d(as_Register(Matcher::_regEncode[dst_lo]),
1648 as_FloatRegister(Matcher::_regEncode[src_lo]));
1649 } else {
1650 __ fmv_x_w(as_Register(Matcher::_regEncode[dst_lo]),
1651 as_FloatRegister(Matcher::_regEncode[src_lo]));
1652 }
1653 } else if (dst_lo_rc == rc_float) { // fpr --> fpr copy
1654 if (is64) {
1655 __ fmv_d(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1656 as_FloatRegister(Matcher::_regEncode[src_lo]));
1657 } else {
1658 __ fmv_s(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1659 as_FloatRegister(Matcher::_regEncode[src_lo]));
1660 }
1661 } else { // fpr --> stack spill
1662 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1663 __ spill(as_FloatRegister(Matcher::_regEncode[src_lo]),
1664 is64, dst_offset);
1665 }
1666 break;
1667 case rc_stack:
1668 if (dst_lo_rc == rc_int) { // stack --> gpr load
1669 if (this->ideal_reg() == Op_RegI) {
1670 __ unspill(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
1671 } else { // // zero extended for narrow oop or klass
1672 __ unspillu(as_Register(Matcher::_regEncode[dst_lo]), is64, src_offset);
1673 }
1674 } else if (dst_lo_rc == rc_float) { // stack --> fpr load
1675 __ unspill(as_FloatRegister(Matcher::_regEncode[dst_lo]),
1676 is64, src_offset);
1677 } else { // stack --> stack copy
1678 assert(dst_lo_rc == rc_stack, "spill to bad register class");
1679 if (this->ideal_reg() == Op_RegI) {
1680 __ unspill(t0, is64, src_offset);
1681 } else { // zero extended for narrow oop or klass
1682 __ unspillu(t0, is64, src_offset);
1683 }
1684 __ spill(t0, is64, dst_offset);
1685 }
1686 break;
1687 default:
1688 ShouldNotReachHere();
1689 }
1690 }
1691
1692 if (st != nullptr) {
1693 st->print("spill ");
1694 if (src_lo_rc == rc_stack) {
1695 st->print("[sp, #%d] -> ", src_offset);
1696 } else {
1697 st->print("%s -> ", Matcher::regName[src_lo]);
1698 }
1699 if (dst_lo_rc == rc_stack) {
1700 st->print("[sp, #%d]", dst_offset);
1701 } else {
1702 st->print("%s", Matcher::regName[dst_lo]);
1703 }
1704 if (bottom_type()->isa_vect() && !bottom_type()->isa_vectmask()) {
1705 int vsize = 0;
1706 if (ideal_reg() == Op_VecA) {
1707 vsize = Matcher::scalable_vector_reg_size(T_BYTE) * 8;
1708 } else {
1709 ShouldNotReachHere();
1710 }
1711 st->print("\t# vector spill size = %d", vsize);
1712 } else if (ideal_reg() == Op_RegVectMask) {
1713 assert(Matcher::supports_scalable_vector(), "bad register type for spill");
1714 int vsize = Matcher::scalable_predicate_reg_slots() * 32;
1715 st->print("\t# vmask spill size = %d", vsize);
1716 } else {
1717 st->print("\t# spill size = %d", is64 ? 64 : 32);
1718 }
1719 }
1720
1721 return 0;
1722 }
1723
1724 #ifndef PRODUCT
1725 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1726 if (ra_ == nullptr) {
1727 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1728 } else {
1729 implementation(nullptr, ra_, false, st);
1730 }
1731 }
1732 #endif
1733
1734 void MachSpillCopyNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1735 implementation(masm, ra_, false, nullptr);
1736 }
1737
1738 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1739 return MachNode::size(ra_);
1740 }
1741
1742 //=============================================================================
1743
1744 #ifndef PRODUCT
1745 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1746 assert_cond(ra_ != nullptr && st != nullptr);
1747 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1748 int reg = ra_->get_reg_first(this);
1749 st->print("add %s, sp, #%d\t# box lock",
1750 Matcher::regName[reg], offset);
1751 }
1752 #endif
1753
1754 void BoxLockNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1755 Assembler::IncompressibleRegion ir(masm); // Fixed length: see BoxLockNode::size()
1756
1757 assert_cond(ra_ != nullptr);
1758 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1759 int reg = ra_->get_encode(this);
1760
1761 if (Assembler::is_simm12(offset)) {
1762 __ addi(as_Register(reg), sp, offset);
1763 } else {
1764 __ li32(t0, offset);
1765 __ add(as_Register(reg), sp, t0);
1766 }
1767 }
1768
1769 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1770 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1771 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1772
1773 if (Assembler::is_simm12(offset)) {
1774 return NativeInstruction::instruction_size;
1775 } else {
1776 return 3 * NativeInstruction::instruction_size; // lui + addiw + add;
1777 }
1778 }
1779
1780 //=============================================================================
1781
1782 #ifndef PRODUCT
1783 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1784 {
1785 assert_cond(st != nullptr);
1786 st->print_cr("# MachUEPNode");
1787 if (UseCompressedClassPointers) {
1788 st->print_cr("\tlwu t1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1789 st->print_cr("\tlwu t2, [t0 + CompiledICData::speculated_klass_offset()]\t# compressed klass");
1790 } else {
1791 st->print_cr("\tld t1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1792 st->print_cr("\tld t2, [t0 + CompiledICData::speculated_klass_offset()]\t# compressed klass");
1793 }
1794 st->print_cr("\tbeq t1, t2, ic_hit");
1795 st->print_cr("\tj, SharedRuntime::_ic_miss_stub\t # Inline cache check");
1796 st->print_cr("\tic_hit:");
1797 }
1798 #endif
1799
1800 void MachUEPNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const
1801 {
1802 // This is the unverified entry point.
1803 __ ic_check(CodeEntryAlignment);
1804
1805 // Verified entry point must be properly 4 bytes aligned for patching by NativeJump::patch_verified_entry().
1806 // ic_check() aligns to CodeEntryAlignment >= InteriorEntryAlignment(min 16) > NativeInstruction::instruction_size(4).
1807 assert(((__ offset()) % CodeEntryAlignment) == 0, "Misaligned verified entry point");
1808 }
1809
1810 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1811 {
1812 assert_cond(ra_ != nullptr);
1813 return MachNode::size(ra_);
1814 }
1815
1816 // REQUIRED EMIT CODE
1817
1818 //=============================================================================
1819
1820 // Emit exception handler code.
1821 int HandlerImpl::emit_exception_handler(C2_MacroAssembler* masm)
1822 {
1823 // auipc t1, #exception_blob_entry_point
1824 // jr (offset)t1
1825 // Note that the code buffer's insts_mark is always relative to insts.
1826 // That's why we must use the macroassembler to generate a handler.
1827 address base = __ start_a_stub(size_exception_handler());
1828 if (base == nullptr) {
1829 ciEnv::current()->record_failure("CodeCache is full");
1830 return 0; // CodeBuffer::expand failed
1831 }
1832 int offset = __ offset();
1833 __ far_jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1834 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1835 __ end_a_stub();
1836 return offset;
1837 }
1838
1839 // Emit deopt handler code.
1840 int HandlerImpl::emit_deopt_handler(C2_MacroAssembler* masm)
1841 {
1842 address base = __ start_a_stub(size_deopt_handler());
1843 if (base == nullptr) {
1844 ciEnv::current()->record_failure("CodeCache is full");
1845 return 0; // CodeBuffer::expand failed
1846 }
1847 int offset = __ offset();
1848
1849 __ auipc(ra, 0);
1850 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1851
1852 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1853 __ end_a_stub();
1854 return offset;
1855
1856 }
1857 // REQUIRED MATCHER CODE
1858
1859 //=============================================================================
1860
1861 bool Matcher::match_rule_supported(int opcode) {
1862 if (!has_match_rule(opcode)) {
1863 return false;
1864 }
1865
1866 switch (opcode) {
1867 case Op_OnSpinWait:
1868 return VM_Version::supports_on_spin_wait();
1869 case Op_CacheWB: // fall through
1870 case Op_CacheWBPreSync: // fall through
1871 case Op_CacheWBPostSync:
1872 if (!VM_Version::supports_data_cache_line_flush()) {
1873 return false;
1874 }
1875 break;
1876
1877 case Op_StrCompressedCopy: // fall through
1878 case Op_StrInflatedCopy: // fall through
1879 case Op_CountPositives: // fall through
1880 case Op_EncodeISOArray:
1881 return UseRVV;
1882
1883 // Current test shows that, it brings performance gain when MaxVectorSize >= 32, but brings
1884 // regression when MaxVectorSize == 16. So only enable the intrinsic when MaxVectorSize >= 32.
1885 case Op_RoundVF:
1886 return UseRVV && MaxVectorSize >= 32;
1887
1888 // For double, current test shows that even with MaxVectorSize == 32, there is still some regression.
1889 // Although there is no hardware to verify it for now, from the trend of performance data on hardwares
1890 // (with vlenb == 16 and 32 respectively), it's promising to bring better performance rather than
1891 // regression for double when MaxVectorSize == 64+. So only enable the intrinsic when MaxVectorSize >= 64.
1892 case Op_RoundVD:
1893 return UseRVV && MaxVectorSize >= 64;
1894
1895 case Op_PopCountI:
1896 case Op_PopCountL:
1897 return UsePopCountInstruction;
1898
1899 case Op_ReverseI:
1900 case Op_ReverseL:
1901 return UseZbkb;
1902
1903 case Op_ReverseBytesI:
1904 case Op_ReverseBytesL:
1905 case Op_ReverseBytesS:
1906 case Op_ReverseBytesUS:
1907 case Op_RotateRight:
1908 case Op_RotateLeft:
1909 case Op_CountLeadingZerosI:
1910 case Op_CountLeadingZerosL:
1911 case Op_CountTrailingZerosI:
1912 case Op_CountTrailingZerosL:
1913 return UseZbb;
1914
1915 case Op_FmaF:
1916 case Op_FmaD:
1917 case Op_FmaVF:
1918 case Op_FmaVD:
1919 return UseFMA;
1920
1921 case Op_ConvHF2F:
1922 case Op_ConvF2HF:
1923 return VM_Version::supports_float16_float_conversion();
1924 case Op_ReinterpretS2HF:
1925 case Op_ReinterpretHF2S:
1926 return UseZfh || UseZfhmin;
1927 case Op_AddHF:
1928 case Op_DivHF:
1929 case Op_FmaHF:
1930 case Op_MaxHF:
1931 case Op_MinHF:
1932 case Op_MulHF:
1933 case Op_SubHF:
1934 case Op_SqrtHF:
1935 return UseZfh;
1936 }
1937
1938 return true; // Per default match rules are supported.
1939 }
1940
1941 const RegMask* Matcher::predicate_reg_mask(void) {
1942 return &_VMASK_REG_mask;
1943 }
1944
1945 // Vector calling convention not yet implemented.
1946 bool Matcher::supports_vector_calling_convention(void) {
1947 return EnableVectorSupport && UseVectorStubs;
1948 }
1949
1950 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
1951 assert(EnableVectorSupport && UseVectorStubs, "sanity");
1952 assert(ideal_reg == Op_VecA, "sanity");
1953 // check more info at https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc
1954 int lo = V8_num;
1955 int hi = V8_K_num;
1956 return OptoRegPair(hi, lo);
1957 }
1958
1959 // Is this branch offset short enough that a short branch can be used?
1960 //
1961 // NOTE: If the platform does not provide any short branch variants, then
1962 // this method should return false for offset 0.
1963 // |---label(L1)-----|
1964 // |-----------------|
1965 // |-----------------|----------eq: float-------------------
1966 // |-----------------| // far_cmpD_branch | cmpD_branch
1967 // |------- ---------| feq; | feq;
1968 // |-far_cmpD_branch-| beqz done; | bnez L;
1969 // |-----------------| j L; |
1970 // |-----------------| bind(done); |
1971 // |-----------------|--------------------------------------
1972 // |-----------------| // so shortBrSize = br_size - 4;
1973 // |-----------------| // so offs = offset - shortBrSize + 4;
1974 // |---label(L2)-----|
1975 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1976 // The passed offset is relative to address of the branch.
1977 int shortBrSize = br_size - 4;
1978 int offs = offset - shortBrSize + 4;
1979 return (-4096 <= offs && offs < 4096);
1980 }
1981
1982 // Vector width in bytes.
1983 int Matcher::vector_width_in_bytes(BasicType bt) {
1984 if (UseRVV) {
1985 // The MaxVectorSize should have been set by detecting RVV max vector register size when check UseRVV.
1986 // MaxVectorSize == VM_Version::_initial_vector_length
1987 int size = MaxVectorSize;
1988 // Minimum 2 values in vector
1989 if (size < 2 * type2aelembytes(bt)) size = 0;
1990 // But never < 4
1991 if (size < 4) size = 0;
1992 return size;
1993 }
1994 return 0;
1995 }
1996
1997 // Limits on vector size (number of elements) loaded into vector.
1998 int Matcher::max_vector_size(const BasicType bt) {
1999 return vector_width_in_bytes(bt) / type2aelembytes(bt);
2000 }
2001
2002 int Matcher::min_vector_size(const BasicType bt) {
2003 int max_size = max_vector_size(bt);
2004 // Limit the min vector size to 8 bytes.
2005 int size = 8 / type2aelembytes(bt);
2006 if (bt == T_BYTE) {
2007 // To support vector api shuffle/rearrange.
2008 size = 4;
2009 } else if (bt == T_BOOLEAN) {
2010 // To support vector api load/store mask.
2011 size = 2;
2012 }
2013 if (size < 2) size = 2;
2014 return MIN2(size, max_size);
2015 }
2016
2017 int Matcher::max_vector_size_auto_vectorization(const BasicType bt) {
2018 return Matcher::max_vector_size(bt);
2019 }
2020
2021 // Vector ideal reg.
2022 uint Matcher::vector_ideal_reg(int len) {
2023 assert(MaxVectorSize >= len, "");
2024 if (UseRVV) {
2025 return Op_VecA;
2026 }
2027
2028 ShouldNotReachHere();
2029 return 0;
2030 }
2031
2032 int Matcher::scalable_vector_reg_size(const BasicType bt) {
2033 return Matcher::max_vector_size(bt);
2034 }
2035
2036 MachOper* Matcher::pd_specialize_generic_vector_operand(MachOper* original_opnd, uint ideal_reg, bool is_temp) {
2037 ShouldNotReachHere(); // generic vector operands not supported
2038 return nullptr;
2039 }
2040
2041 bool Matcher::is_reg2reg_move(MachNode* m) {
2042 ShouldNotReachHere(); // generic vector operands not supported
2043 return false;
2044 }
2045
2046 bool Matcher::is_generic_vector(MachOper* opnd) {
2047 ShouldNotReachHere(); // generic vector operands not supported
2048 return false;
2049 }
2050
2051 // Return whether or not this register is ever used as an argument.
2052 // This function is used on startup to build the trampoline stubs in
2053 // generateOptoStub. Registers not mentioned will be killed by the VM
2054 // call in the trampoline, and arguments in those registers not be
2055 // available to the callee.
2056 bool Matcher::can_be_java_arg(int reg)
2057 {
2058 return
2059 reg == R10_num || reg == R10_H_num ||
2060 reg == R11_num || reg == R11_H_num ||
2061 reg == R12_num || reg == R12_H_num ||
2062 reg == R13_num || reg == R13_H_num ||
2063 reg == R14_num || reg == R14_H_num ||
2064 reg == R15_num || reg == R15_H_num ||
2065 reg == R16_num || reg == R16_H_num ||
2066 reg == R17_num || reg == R17_H_num ||
2067 reg == F10_num || reg == F10_H_num ||
2068 reg == F11_num || reg == F11_H_num ||
2069 reg == F12_num || reg == F12_H_num ||
2070 reg == F13_num || reg == F13_H_num ||
2071 reg == F14_num || reg == F14_H_num ||
2072 reg == F15_num || reg == F15_H_num ||
2073 reg == F16_num || reg == F16_H_num ||
2074 reg == F17_num || reg == F17_H_num;
2075 }
2076
2077 bool Matcher::is_spillable_arg(int reg)
2078 {
2079 return can_be_java_arg(reg);
2080 }
2081
2082 uint Matcher::int_pressure_limit()
2083 {
2084 // A derived pointer is live at CallNode and then is flagged by RA
2085 // as a spilled LRG. Spilling heuristics(Spill-USE) explicitly skip
2086 // derived pointers and lastly fail to spill after reaching maximum
2087 // number of iterations. Lowering the default pressure threshold to
2088 // (_NO_SPECIAL_REG32_mask.Size() minus 1) forces CallNode to become
2089 // a high register pressure area of the code so that split_DEF can
2090 // generate DefinitionSpillCopy for the derived pointer.
2091 uint default_int_pressure_threshold = _NO_SPECIAL_REG32_mask.Size() - 1;
2092 if (!PreserveFramePointer) {
2093 // When PreserveFramePointer is off, frame pointer is allocatable,
2094 // but different from other SOC registers, it is excluded from
2095 // fatproj's mask because its save type is No-Save. Decrease 1 to
2096 // ensure high pressure at fatproj when PreserveFramePointer is off.
2097 // See check_pressure_at_fatproj().
2098 default_int_pressure_threshold--;
2099 }
2100 return (INTPRESSURE == -1) ? default_int_pressure_threshold : INTPRESSURE;
2101 }
2102
2103 uint Matcher::float_pressure_limit()
2104 {
2105 // _FLOAT_REG_mask is generated by adlc from the float_reg register class.
2106 return (FLOATPRESSURE == -1) ? _FLOAT_REG_mask.Size() : FLOATPRESSURE;
2107 }
2108
2109 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2110 return false;
2111 }
2112
2113 RegMask Matcher::divI_proj_mask() {
2114 ShouldNotReachHere();
2115 return RegMask();
2116 }
2117
2118 // Register for MODI projection of divmodI.
2119 RegMask Matcher::modI_proj_mask() {
2120 ShouldNotReachHere();
2121 return RegMask();
2122 }
2123
2124 // Register for DIVL projection of divmodL.
2125 RegMask Matcher::divL_proj_mask() {
2126 ShouldNotReachHere();
2127 return RegMask();
2128 }
2129
2130 // Register for MODL projection of divmodL.
2131 RegMask Matcher::modL_proj_mask() {
2132 ShouldNotReachHere();
2133 return RegMask();
2134 }
2135
2136 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2137 return FP_REG_mask();
2138 }
2139
2140 bool size_fits_all_mem_uses(AddPNode* addp, int shift) {
2141 assert_cond(addp != nullptr);
2142 for (DUIterator_Fast imax, i = addp->fast_outs(imax); i < imax; i++) {
2143 Node* u = addp->fast_out(i);
2144 if (u != nullptr && u->is_Mem()) {
2145 int opsize = u->as_Mem()->memory_size();
2146 assert(opsize > 0, "unexpected memory operand size");
2147 if (u->as_Mem()->memory_size() != (1 << shift)) {
2148 return false;
2149 }
2150 }
2151 }
2152 return true;
2153 }
2154
2155 // Binary src (Replicate scalar/immediate)
2156 static bool is_vector_scalar_bitwise_pattern(Node* n, Node* m) {
2157 if (n == nullptr || m == nullptr) {
2158 return false;
2159 }
2160
2161 if (m->Opcode() != Op_Replicate) {
2162 return false;
2163 }
2164
2165 switch (n->Opcode()) {
2166 case Op_AndV:
2167 case Op_OrV:
2168 case Op_XorV:
2169 case Op_AddVB:
2170 case Op_AddVS:
2171 case Op_AddVI:
2172 case Op_AddVL:
2173 case Op_SubVB:
2174 case Op_SubVS:
2175 case Op_SubVI:
2176 case Op_SubVL:
2177 case Op_MulVB:
2178 case Op_MulVS:
2179 case Op_MulVI:
2180 case Op_MulVL: {
2181 return true;
2182 }
2183 default:
2184 return false;
2185 }
2186 }
2187
2188 // (XorV src (Replicate m1))
2189 // (XorVMask src (MaskAll m1))
2190 static bool is_vector_bitwise_not_pattern(Node* n, Node* m) {
2191 if (n != nullptr && m != nullptr) {
2192 return (n->Opcode() == Op_XorV || n->Opcode() == Op_XorVMask) &&
2193 VectorNode::is_all_ones_vector(m);
2194 }
2195 return false;
2196 }
2197
2198 // Should the Matcher clone input 'm' of node 'n'?
2199 bool Matcher::pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
2200 assert_cond(m != nullptr);
2201 if (is_vshift_con_pattern(n, m) || // ShiftV src (ShiftCntV con)
2202 is_vector_bitwise_not_pattern(n, m) ||
2203 is_vector_scalar_bitwise_pattern(n, m) ||
2204 is_encode_and_store_pattern(n, m)) {
2205 mstack.push(m, Visit);
2206 return true;
2207 }
2208 return false;
2209 }
2210
2211 // Should the Matcher clone shifts on addressing modes, expecting them
2212 // to be subsumed into complex addressing expressions or compute them
2213 // into registers?
2214 bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2215 return clone_base_plus_offset_address(m, mstack, address_visited);
2216 }
2217
2218 %}
2219
2220
2221
2222 //----------ENCODING BLOCK-----------------------------------------------------
2223 // This block specifies the encoding classes used by the compiler to
2224 // output byte streams. Encoding classes are parameterized macros
2225 // used by Machine Instruction Nodes in order to generate the bit
2226 // encoding of the instruction. Operands specify their base encoding
2227 // interface with the interface keyword. There are currently
2228 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
2229 // COND_INTER. REG_INTER causes an operand to generate a function
2230 // which returns its register number when queried. CONST_INTER causes
2231 // an operand to generate a function which returns the value of the
2232 // constant when queried. MEMORY_INTER causes an operand to generate
2233 // four functions which return the Base Register, the Index Register,
2234 // the Scale Value, and the Offset Value of the operand when queried.
2235 // COND_INTER causes an operand to generate six functions which return
2236 // the encoding code (ie - encoding bits for the instruction)
2237 // associated with each basic boolean condition for a conditional
2238 // instruction.
2239 //
2240 // Instructions specify two basic values for encoding. Again, a
2241 // function is available to check if the constant displacement is an
2242 // oop. They use the ins_encode keyword to specify their encoding
2243 // classes (which must be a sequence of enc_class names, and their
2244 // parameters, specified in the encoding block), and they use the
2245 // opcode keyword to specify, in order, their primary, secondary, and
2246 // tertiary opcode. Only the opcode sections which a particular
2247 // instruction needs for encoding need to be specified.
2248 encode %{
2249 // BEGIN Non-volatile memory access
2250
2251 enc_class riscv_enc_mov_imm(iRegIorL dst, immIorL src) %{
2252 int64_t con = (int64_t)$src$$constant;
2253 Register dst_reg = as_Register($dst$$reg);
2254 __ mv(dst_reg, con);
2255 %}
2256
2257 enc_class riscv_enc_mov_p(iRegP dst, immP src) %{
2258 Register dst_reg = as_Register($dst$$reg);
2259 address con = (address)$src$$constant;
2260 if (con == nullptr || con == (address)1) {
2261 ShouldNotReachHere();
2262 } else {
2263 relocInfo::relocType rtype = $src->constant_reloc();
2264 if (rtype == relocInfo::oop_type) {
2265 __ movoop(dst_reg, (jobject)con);
2266 } else if (rtype == relocInfo::metadata_type) {
2267 __ mov_metadata(dst_reg, (Metadata*)con);
2268 } else {
2269 assert(rtype == relocInfo::none, "unexpected reloc type");
2270 __ mv(dst_reg, $src$$constant);
2271 }
2272 }
2273 %}
2274
2275 enc_class riscv_enc_mov_p1(iRegP dst) %{
2276 Register dst_reg = as_Register($dst$$reg);
2277 __ mv(dst_reg, 1);
2278 %}
2279
2280 enc_class riscv_enc_mov_byte_map_base(iRegP dst) %{
2281 __ load_byte_map_base($dst$$Register);
2282 %}
2283
2284 enc_class riscv_enc_mov_n(iRegN dst, immN src) %{
2285 Register dst_reg = as_Register($dst$$reg);
2286 address con = (address)$src$$constant;
2287 if (con == nullptr) {
2288 ShouldNotReachHere();
2289 } else {
2290 relocInfo::relocType rtype = $src->constant_reloc();
2291 assert(rtype == relocInfo::oop_type, "unexpected reloc type");
2292 __ set_narrow_oop(dst_reg, (jobject)con);
2293 }
2294 %}
2295
2296 enc_class riscv_enc_mov_zero(iRegNorP dst) %{
2297 Register dst_reg = as_Register($dst$$reg);
2298 __ mv(dst_reg, zr);
2299 %}
2300
2301 enc_class riscv_enc_mov_nk(iRegN dst, immNKlass src) %{
2302 Register dst_reg = as_Register($dst$$reg);
2303 address con = (address)$src$$constant;
2304 if (con == nullptr) {
2305 ShouldNotReachHere();
2306 } else {
2307 relocInfo::relocType rtype = $src->constant_reloc();
2308 assert(rtype == relocInfo::metadata_type, "unexpected reloc type");
2309 __ set_narrow_klass(dst_reg, (Klass *)con);
2310 }
2311 %}
2312
2313 enc_class riscv_enc_cmpxchgw(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
2314 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
2315 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
2316 /*result as bool*/ true);
2317 %}
2318
2319 enc_class riscv_enc_cmpxchgn(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
2320 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
2321 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
2322 /*result as bool*/ true);
2323 %}
2324
2325 enc_class riscv_enc_cmpxchg(iRegINoSp res, memory mem, iRegL oldval, iRegL newval) %{
2326 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
2327 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
2328 /*result as bool*/ true);
2329 %}
2330
2331 enc_class riscv_enc_cmpxchgw_acq(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
2332 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
2333 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
2334 /*result as bool*/ true);
2335 %}
2336
2337 enc_class riscv_enc_cmpxchgn_acq(iRegINoSp res, memory mem, iRegI oldval, iRegI newval) %{
2338 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
2339 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
2340 /*result as bool*/ true);
2341 %}
2342
2343 enc_class riscv_enc_cmpxchg_acq(iRegINoSp res, memory mem, iRegL oldval, iRegL newval) %{
2344 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
2345 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
2346 /*result as bool*/ true);
2347 %}
2348
2349 // compare and branch instruction encodings
2350
2351 enc_class riscv_enc_j(label lbl) %{
2352 Label* L = $lbl$$label;
2353 __ j(*L);
2354 %}
2355
2356 enc_class riscv_enc_far_cmpULtGe_imm0_branch(cmpOpULtGe cmp, iRegIorL op1, label lbl) %{
2357 Label* L = $lbl$$label;
2358 switch ($cmp$$cmpcode) {
2359 case(BoolTest::ge):
2360 __ j(*L);
2361 break;
2362 case(BoolTest::lt):
2363 break;
2364 default:
2365 Unimplemented();
2366 }
2367 %}
2368
2369 // call instruction encodings
2370
2371 enc_class riscv_enc_partial_subtype_check(iRegP sub, iRegP super, iRegP temp, iRegP result) %{
2372 Register sub_reg = as_Register($sub$$reg);
2373 Register super_reg = as_Register($super$$reg);
2374 Register temp_reg = as_Register($temp$$reg);
2375 Register result_reg = as_Register($result$$reg);
2376 Register cr_reg = t1;
2377
2378 Label miss;
2379 Label done;
2380 __ check_klass_subtype_slow_path(sub_reg, super_reg, temp_reg, result_reg,
2381 nullptr, &miss, /*set_cond_codes*/ true);
2382 if ($primary) {
2383 __ mv(result_reg, zr);
2384 } else {
2385 __ mv(cr_reg, zr);
2386 __ j(done);
2387 }
2388
2389 __ bind(miss);
2390 if (!$primary) {
2391 __ mv(cr_reg, 1);
2392 }
2393
2394 __ bind(done);
2395 %}
2396
2397 enc_class riscv_enc_java_static_call(method meth) %{
2398 Assembler::IncompressibleRegion ir(masm); // Fixed length: see ret_addr_offset
2399
2400 address addr = (address)$meth$$method;
2401 address call = nullptr;
2402 assert_cond(addr != nullptr);
2403 if (!_method) {
2404 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
2405 call = __ reloc_call(Address(addr, relocInfo::runtime_call_type));
2406 if (call == nullptr) {
2407 ciEnv::current()->record_failure("CodeCache is full");
2408 return;
2409 }
2410 } else if (_method->intrinsic_id() == vmIntrinsicID::_ensureMaterializedForStackWalk) {
2411 // The NOP here is purely to ensure that eliding a call to
2412 // JVM_EnsureMaterializedForStackWalk doesn't change the code size.
2413 __ nop();
2414 __ nop();
2415 __ nop();
2416 __ block_comment("call JVM_EnsureMaterializedForStackWalk (elided)");
2417 } else {
2418 int method_index = resolved_method_index(masm);
2419 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2420 : static_call_Relocation::spec(method_index);
2421 call = __ reloc_call(Address(addr, rspec));
2422 if (call == nullptr) {
2423 ciEnv::current()->record_failure("CodeCache is full");
2424 return;
2425 }
2426
2427 if (CodeBuffer::supports_shared_stubs() && _method->can_be_statically_bound()) {
2428 // Calls of the same statically bound method can share
2429 // a stub to the interpreter.
2430 __ code()->shared_stub_to_interp_for(_method, call - (__ begin()));
2431 } else {
2432 // Emit stub for static call
2433 address stub = CompiledDirectCall::emit_to_interp_stub(masm, call);
2434 if (stub == nullptr) {
2435 ciEnv::current()->record_failure("CodeCache is full");
2436 return;
2437 }
2438 }
2439 }
2440
2441 __ post_call_nop();
2442 %}
2443
2444 enc_class riscv_enc_java_dynamic_call(method meth) %{
2445 Assembler::IncompressibleRegion ir(masm); // Fixed length: see ret_addr_offset
2446 int method_index = resolved_method_index(masm);
2447 address call = __ ic_call((address)$meth$$method, method_index);
2448 if (call == nullptr) {
2449 ciEnv::current()->record_failure("CodeCache is full");
2450 return;
2451 }
2452
2453 __ post_call_nop();
2454 %}
2455
2456 enc_class riscv_enc_call_epilog() %{
2457 if (VerifyStackAtCalls) {
2458 // Check that stack depth is unchanged: find majik cookie on stack
2459 __ call_Unimplemented();
2460 }
2461 %}
2462
2463 enc_class riscv_enc_java_to_runtime(method meth) %{
2464 Assembler::IncompressibleRegion ir(masm); // Fixed length: see ret_addr_offset
2465
2466 // Some calls to generated routines (arraycopy code) are scheduled by C2
2467 // as runtime calls. if so we can call them using a far call (they will be
2468 // in the code cache, thus in a reachable segment) otherwise we have to use
2469 // a movptr+jalr pair which loads the absolute address into a register.
2470 address entry = (address)$meth$$method;
2471 if (CodeCache::contains(entry)) {
2472 __ far_call(Address(entry, relocInfo::runtime_call_type));
2473 __ post_call_nop();
2474 } else {
2475 Label retaddr;
2476 // Make the anchor frame walkable
2477 __ la(t0, retaddr);
2478 __ sd(t0, Address(xthread, JavaThread::last_Java_pc_offset()));
2479 int32_t offset = 0;
2480 // No relocation needed
2481 __ movptr(t1, entry, offset, t0); // lui + lui + slli + add
2482 __ jalr(t1, offset);
2483 __ bind(retaddr);
2484 __ post_call_nop();
2485 }
2486 %}
2487
2488 enc_class riscv_enc_tail_call(iRegP jump_target) %{
2489 Register target_reg = as_Register($jump_target$$reg);
2490 __ jr(target_reg);
2491 %}
2492
2493 enc_class riscv_enc_tail_jmp(iRegP jump_target) %{
2494 Register target_reg = as_Register($jump_target$$reg);
2495 // exception oop should be in x10
2496 // ret addr has been popped into ra
2497 // callee expects it in x13
2498 __ mv(x13, ra);
2499 __ jr(target_reg);
2500 %}
2501
2502 enc_class riscv_enc_rethrow() %{
2503 __ far_jump(RuntimeAddress(OptoRuntime::rethrow_stub()));
2504 %}
2505
2506 enc_class riscv_enc_ret() %{
2507 __ ret();
2508 %}
2509
2510 %}
2511
2512 //----------FRAME--------------------------------------------------------------
2513 // Definition of frame structure and management information.
2514 //
2515 // S T A C K L A Y O U T Allocators stack-slot number
2516 // | (to get allocators register number
2517 // G Owned by | | v add OptoReg::stack0())
2518 // r CALLER | |
2519 // o | +--------+ pad to even-align allocators stack-slot
2520 // w V | pad0 | numbers; owned by CALLER
2521 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2522 // h ^ | in | 5
2523 // | | args | 4 Holes in incoming args owned by SELF
2524 // | | | | 3
2525 // | | +--------+
2526 // V | | old out| Empty on Intel, window on Sparc
2527 // | old |preserve| Must be even aligned.
2528 // | SP-+--------+----> Matcher::_old_SP, even aligned
2529 // | | in | 3 area for Intel ret address
2530 // Owned by |preserve| Empty on Sparc.
2531 // SELF +--------+
2532 // | | pad2 | 2 pad to align old SP
2533 // | +--------+ 1
2534 // | | locks | 0
2535 // | +--------+----> OptoReg::stack0(), even aligned
2536 // | | pad1 | 11 pad to align new SP
2537 // | +--------+
2538 // | | | 10
2539 // | | spills | 9 spills
2540 // V | | 8 (pad0 slot for callee)
2541 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2542 // ^ | out | 7
2543 // | | args | 6 Holes in outgoing args owned by CALLEE
2544 // Owned by +--------+
2545 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2546 // | new |preserve| Must be even-aligned.
2547 // | SP-+--------+----> Matcher::_new_SP, even aligned
2548 // | | |
2549 //
2550 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2551 // known from SELF's arguments and the Java calling convention.
2552 // Region 6-7 is determined per call site.
2553 // Note 2: If the calling convention leaves holes in the incoming argument
2554 // area, those holes are owned by SELF. Holes in the outgoing area
2555 // are owned by the CALLEE. Holes should not be necessary in the
2556 // incoming area, as the Java calling convention is completely under
2557 // the control of the AD file. Doubles can be sorted and packed to
2558 // avoid holes. Holes in the outgoing arguments may be necessary for
2559 // varargs C calling conventions.
2560 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2561 // even aligned with pad0 as needed.
2562 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2563 // (the latter is true on Intel but is it false on RISCV?)
2564 // region 6-11 is even aligned; it may be padded out more so that
2565 // the region from SP to FP meets the minimum stack alignment.
2566 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2567 // alignment. Region 11, pad1, may be dynamically extended so that
2568 // SP meets the minimum alignment.
2569
2570 frame %{
2571 // These three registers define part of the calling convention
2572 // between compiled code and the interpreter.
2573
2574 // Inline Cache Register or methodOop for I2C.
2575 inline_cache_reg(R31);
2576
2577 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
2578 cisc_spilling_operand_name(indOffset);
2579
2580 // Number of stack slots consumed by locking an object
2581 // generate Compile::sync_stack_slots
2582 // VMRegImpl::slots_per_word = wordSize / stack_slot_size = 8 / 4 = 2
2583 sync_stack_slots(1 * VMRegImpl::slots_per_word);
2584
2585 // Compiled code's Frame Pointer
2586 frame_pointer(R2);
2587
2588 // Interpreter stores its frame pointer in a register which is
2589 // stored to the stack by I2CAdaptors.
2590 // I2CAdaptors convert from interpreted java to compiled java.
2591 interpreter_frame_pointer(R8);
2592
2593 // Stack alignment requirement
2594 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2595
2596 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2597 // for calls to C. Supports the var-args backing area for register parms.
2598 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes / BytesPerInt);
2599
2600 // The after-PROLOG location of the return address. Location of
2601 // return address specifies a type (REG or STACK) and a number
2602 // representing the register number (i.e. - use a register name) or
2603 // stack slot.
2604 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2605 // Otherwise, it is above the locks and verification slot and alignment word
2606 // TODO this may well be correct but need to check why that - 2 is there
2607 // ppc port uses 0 but we definitely need to allow for fixed_slots
2608 // which folds in the space used for monitors
2609 return_addr(STACK - 2 +
2610 align_up((Compile::current()->in_preserve_stack_slots() +
2611 Compile::current()->fixed_slots()),
2612 stack_alignment_in_slots()));
2613
2614 // Location of compiled Java return values. Same as C for now.
2615 return_value
2616 %{
2617 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2618 "only return normal values");
2619
2620 static const int lo[Op_RegL + 1] = { // enum name
2621 0, // Op_Node
2622 0, // Op_Set
2623 R10_num, // Op_RegN
2624 R10_num, // Op_RegI
2625 R10_num, // Op_RegP
2626 F10_num, // Op_RegF
2627 F10_num, // Op_RegD
2628 R10_num // Op_RegL
2629 };
2630
2631 static const int hi[Op_RegL + 1] = { // enum name
2632 0, // Op_Node
2633 0, // Op_Set
2634 OptoReg::Bad, // Op_RegN
2635 OptoReg::Bad, // Op_RegI
2636 R10_H_num, // Op_RegP
2637 OptoReg::Bad, // Op_RegF
2638 F10_H_num, // Op_RegD
2639 R10_H_num // Op_RegL
2640 };
2641
2642 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2643 %}
2644 %}
2645
2646 //----------ATTRIBUTES---------------------------------------------------------
2647 //----------Operand Attributes-------------------------------------------------
2648 op_attrib op_cost(1); // Required cost attribute
2649
2650 //----------Instruction Attributes---------------------------------------------
2651 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
2652 ins_attrib ins_size(32); // Required size attribute (in bits)
2653 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2654 // a non-matching short branch variant
2655 // of some long branch?
2656 ins_attrib ins_alignment(4); // Required alignment attribute (must
2657 // be a power of 2) specifies the
2658 // alignment that some part of the
2659 // instruction (not necessarily the
2660 // start) requires. If > 1, a
2661 // compute_padding() function must be
2662 // provided for the instruction
2663
2664 //----------OPERANDS-----------------------------------------------------------
2665 // Operand definitions must precede instruction definitions for correct parsing
2666 // in the ADLC because operands constitute user defined types which are used in
2667 // instruction definitions.
2668
2669 //----------Simple Operands----------------------------------------------------
2670
2671 // Integer operands 32 bit
2672 // 32 bit immediate
2673 operand immI()
2674 %{
2675 match(ConI);
2676
2677 op_cost(0);
2678 format %{ %}
2679 interface(CONST_INTER);
2680 %}
2681
2682 // 32 bit zero
2683 operand immI0()
2684 %{
2685 predicate(n->get_int() == 0);
2686 match(ConI);
2687
2688 op_cost(0);
2689 format %{ %}
2690 interface(CONST_INTER);
2691 %}
2692
2693 // 32 bit unit increment
2694 operand immI_1()
2695 %{
2696 predicate(n->get_int() == 1);
2697 match(ConI);
2698
2699 op_cost(0);
2700 format %{ %}
2701 interface(CONST_INTER);
2702 %}
2703
2704 // 32 bit unit decrement
2705 operand immI_M1()
2706 %{
2707 predicate(n->get_int() == -1);
2708 match(ConI);
2709
2710 op_cost(0);
2711 format %{ %}
2712 interface(CONST_INTER);
2713 %}
2714
2715 // Unsigned Integer Immediate: 6-bit int, greater than 32
2716 operand uimmI6_ge32() %{
2717 predicate(((unsigned int)(n->get_int()) < 64) && (n->get_int() >= 32));
2718 match(ConI);
2719 op_cost(0);
2720 format %{ %}
2721 interface(CONST_INTER);
2722 %}
2723
2724 operand immI_le_4()
2725 %{
2726 predicate(n->get_int() <= 4);
2727 match(ConI);
2728
2729 op_cost(0);
2730 format %{ %}
2731 interface(CONST_INTER);
2732 %}
2733
2734 operand immI_16()
2735 %{
2736 predicate(n->get_int() == 16);
2737 match(ConI);
2738 op_cost(0);
2739 format %{ %}
2740 interface(CONST_INTER);
2741 %}
2742
2743 operand immI_24()
2744 %{
2745 predicate(n->get_int() == 24);
2746 match(ConI);
2747 op_cost(0);
2748 format %{ %}
2749 interface(CONST_INTER);
2750 %}
2751
2752 operand immI_31()
2753 %{
2754 predicate(n->get_int() == 31);
2755 match(ConI);
2756
2757 op_cost(0);
2758 format %{ %}
2759 interface(CONST_INTER);
2760 %}
2761
2762 operand immI_63()
2763 %{
2764 predicate(n->get_int() == 63);
2765 match(ConI);
2766
2767 op_cost(0);
2768 format %{ %}
2769 interface(CONST_INTER);
2770 %}
2771
2772 // 32 bit integer valid for add immediate
2773 operand immIAdd()
2774 %{
2775 predicate(Assembler::is_simm12((int64_t)n->get_int()));
2776 match(ConI);
2777 op_cost(0);
2778 format %{ %}
2779 interface(CONST_INTER);
2780 %}
2781
2782 // 32 bit integer valid for sub immediate
2783 operand immISub()
2784 %{
2785 predicate(Assembler::is_simm12(-(int64_t)n->get_int()));
2786 match(ConI);
2787 op_cost(0);
2788 format %{ %}
2789 interface(CONST_INTER);
2790 %}
2791
2792 // 5 bit signed value.
2793 operand immI5()
2794 %{
2795 predicate(n->get_int() <= 15 && n->get_int() >= -16);
2796 match(ConI);
2797
2798 op_cost(0);
2799 format %{ %}
2800 interface(CONST_INTER);
2801 %}
2802
2803 // 5 bit signed value (simm5)
2804 operand immL5()
2805 %{
2806 predicate(n->get_long() <= 15 && n->get_long() >= -16);
2807 match(ConL);
2808
2809 op_cost(0);
2810 format %{ %}
2811 interface(CONST_INTER);
2812 %}
2813
2814 // Integer operands 64 bit
2815 // 64 bit immediate
2816 operand immL()
2817 %{
2818 match(ConL);
2819
2820 op_cost(0);
2821 format %{ %}
2822 interface(CONST_INTER);
2823 %}
2824
2825 // 64 bit zero
2826 operand immL0()
2827 %{
2828 predicate(n->get_long() == 0);
2829 match(ConL);
2830
2831 op_cost(0);
2832 format %{ %}
2833 interface(CONST_INTER);
2834 %}
2835
2836 // Pointer operands
2837 // Pointer Immediate
2838 operand immP()
2839 %{
2840 match(ConP);
2841
2842 op_cost(0);
2843 format %{ %}
2844 interface(CONST_INTER);
2845 %}
2846
2847 // Null Pointer Immediate
2848 operand immP0()
2849 %{
2850 predicate(n->get_ptr() == 0);
2851 match(ConP);
2852
2853 op_cost(0);
2854 format %{ %}
2855 interface(CONST_INTER);
2856 %}
2857
2858 // Pointer Immediate One
2859 // this is used in object initialization (initial object header)
2860 operand immP_1()
2861 %{
2862 predicate(n->get_ptr() == 1);
2863 match(ConP);
2864
2865 op_cost(0);
2866 format %{ %}
2867 interface(CONST_INTER);
2868 %}
2869
2870 // Card Table Byte Map Base
2871 operand immByteMapBase()
2872 %{
2873 // Get base of card map
2874 predicate(BarrierSet::barrier_set()->is_a(BarrierSet::CardTableBarrierSet) &&
2875 SHENANDOAHGC_ONLY(!BarrierSet::barrier_set()->is_a(BarrierSet::ShenandoahBarrierSet) &&)
2876 (CardTable::CardValue*)n->get_ptr() ==
2877 ((CardTableBarrierSet*)(BarrierSet::barrier_set()))->card_table()->byte_map_base());
2878 match(ConP);
2879
2880 op_cost(0);
2881 format %{ %}
2882 interface(CONST_INTER);
2883 %}
2884
2885 // Int Immediate: low 16-bit mask
2886 operand immI_16bits()
2887 %{
2888 predicate(n->get_int() == 0xFFFF);
2889 match(ConI);
2890 op_cost(0);
2891 format %{ %}
2892 interface(CONST_INTER);
2893 %}
2894
2895 operand immIpowerOf2() %{
2896 predicate(is_power_of_2((juint)(n->get_int())));
2897 match(ConI);
2898 op_cost(0);
2899 format %{ %}
2900 interface(CONST_INTER);
2901 %}
2902
2903 // Long Immediate: low 32-bit mask
2904 operand immL_32bits()
2905 %{
2906 predicate(n->get_long() == 0xFFFFFFFFL);
2907 match(ConL);
2908 op_cost(0);
2909 format %{ %}
2910 interface(CONST_INTER);
2911 %}
2912
2913 // 64 bit unit decrement
2914 operand immL_M1()
2915 %{
2916 predicate(n->get_long() == -1);
2917 match(ConL);
2918
2919 op_cost(0);
2920 format %{ %}
2921 interface(CONST_INTER);
2922 %}
2923
2924
2925 // 64 bit integer valid for add immediate
2926 operand immLAdd()
2927 %{
2928 predicate(Assembler::is_simm12(n->get_long()));
2929 match(ConL);
2930 op_cost(0);
2931 format %{ %}
2932 interface(CONST_INTER);
2933 %}
2934
2935 // 64 bit integer valid for sub immediate
2936 operand immLSub()
2937 %{
2938 predicate(Assembler::is_simm12(-(n->get_long())));
2939 match(ConL);
2940 op_cost(0);
2941 format %{ %}
2942 interface(CONST_INTER);
2943 %}
2944
2945 // Narrow pointer operands
2946 // Narrow Pointer Immediate
2947 operand immN()
2948 %{
2949 match(ConN);
2950
2951 op_cost(0);
2952 format %{ %}
2953 interface(CONST_INTER);
2954 %}
2955
2956 // Narrow Null Pointer Immediate
2957 operand immN0()
2958 %{
2959 predicate(n->get_narrowcon() == 0);
2960 match(ConN);
2961
2962 op_cost(0);
2963 format %{ %}
2964 interface(CONST_INTER);
2965 %}
2966
2967 operand immNKlass()
2968 %{
2969 match(ConNKlass);
2970
2971 op_cost(0);
2972 format %{ %}
2973 interface(CONST_INTER);
2974 %}
2975
2976 // Float and Double operands
2977 // Double Immediate
2978 operand immD()
2979 %{
2980 match(ConD);
2981 op_cost(0);
2982 format %{ %}
2983 interface(CONST_INTER);
2984 %}
2985
2986 // Double Immediate: +0.0d
2987 operand immD0()
2988 %{
2989 predicate(jlong_cast(n->getd()) == 0);
2990 match(ConD);
2991
2992 op_cost(0);
2993 format %{ %}
2994 interface(CONST_INTER);
2995 %}
2996
2997 // Float Immediate
2998 operand immF()
2999 %{
3000 match(ConF);
3001 op_cost(0);
3002 format %{ %}
3003 interface(CONST_INTER);
3004 %}
3005
3006 // Float Immediate: +0.0f.
3007 operand immF0()
3008 %{
3009 predicate(jint_cast(n->getf()) == 0);
3010 match(ConF);
3011
3012 op_cost(0);
3013 format %{ %}
3014 interface(CONST_INTER);
3015 %}
3016
3017 // Half Float Immediate
3018 operand immH()
3019 %{
3020 match(ConH);
3021
3022 op_cost(0);
3023 format %{ %}
3024 interface(CONST_INTER);
3025 %}
3026
3027 // Half Float Immediate: +0.0f.
3028 operand immH0()
3029 %{
3030 predicate(jint_cast(n->geth()) == 0);
3031 match(ConH);
3032
3033 op_cost(0);
3034 format %{ %}
3035 interface(CONST_INTER);
3036 %}
3037
3038 operand immIOffset()
3039 %{
3040 predicate(Assembler::is_simm12(n->get_int()));
3041 match(ConI);
3042 op_cost(0);
3043 format %{ %}
3044 interface(CONST_INTER);
3045 %}
3046
3047 operand immLOffset()
3048 %{
3049 predicate(Assembler::is_simm12(n->get_long()));
3050 match(ConL);
3051 op_cost(0);
3052 format %{ %}
3053 interface(CONST_INTER);
3054 %}
3055
3056 // Scale values
3057 operand immIScale()
3058 %{
3059 predicate(1 <= n->get_int() && (n->get_int() <= 3));
3060 match(ConI);
3061
3062 op_cost(0);
3063 format %{ %}
3064 interface(CONST_INTER);
3065 %}
3066
3067 // Integer 32 bit Register Operands
3068 operand iRegI()
3069 %{
3070 constraint(ALLOC_IN_RC(any_reg32));
3071 match(RegI);
3072 match(iRegINoSp);
3073 op_cost(0);
3074 format %{ %}
3075 interface(REG_INTER);
3076 %}
3077
3078 // Integer 32 bit Register not Special
3079 operand iRegINoSp()
3080 %{
3081 constraint(ALLOC_IN_RC(no_special_reg32));
3082 match(RegI);
3083 op_cost(0);
3084 format %{ %}
3085 interface(REG_INTER);
3086 %}
3087
3088 // Register R10 only
3089 operand iRegI_R10()
3090 %{
3091 constraint(ALLOC_IN_RC(int_r10_reg));
3092 match(RegI);
3093 match(iRegINoSp);
3094 op_cost(0);
3095 format %{ %}
3096 interface(REG_INTER);
3097 %}
3098
3099 // Register R12 only
3100 operand iRegI_R12()
3101 %{
3102 constraint(ALLOC_IN_RC(int_r12_reg));
3103 match(RegI);
3104 match(iRegINoSp);
3105 op_cost(0);
3106 format %{ %}
3107 interface(REG_INTER);
3108 %}
3109
3110 // Register R13 only
3111 operand iRegI_R13()
3112 %{
3113 constraint(ALLOC_IN_RC(int_r13_reg));
3114 match(RegI);
3115 match(iRegINoSp);
3116 op_cost(0);
3117 format %{ %}
3118 interface(REG_INTER);
3119 %}
3120
3121 // Register R14 only
3122 operand iRegI_R14()
3123 %{
3124 constraint(ALLOC_IN_RC(int_r14_reg));
3125 match(RegI);
3126 match(iRegINoSp);
3127 op_cost(0);
3128 format %{ %}
3129 interface(REG_INTER);
3130 %}
3131
3132 // Integer 64 bit Register Operands
3133 operand iRegL()
3134 %{
3135 constraint(ALLOC_IN_RC(any_reg));
3136 match(RegL);
3137 match(iRegLNoSp);
3138 op_cost(0);
3139 format %{ %}
3140 interface(REG_INTER);
3141 %}
3142
3143 // Integer 64 bit Register not Special
3144 operand iRegLNoSp()
3145 %{
3146 constraint(ALLOC_IN_RC(no_special_reg));
3147 match(RegL);
3148 match(iRegL_R10);
3149 format %{ %}
3150 interface(REG_INTER);
3151 %}
3152
3153 // Long 64 bit Register R29 only
3154 operand iRegL_R29()
3155 %{
3156 constraint(ALLOC_IN_RC(r29_reg));
3157 match(RegL);
3158 match(iRegLNoSp);
3159 op_cost(0);
3160 format %{ %}
3161 interface(REG_INTER);
3162 %}
3163
3164 // Long 64 bit Register R30 only
3165 operand iRegL_R30()
3166 %{
3167 constraint(ALLOC_IN_RC(r30_reg));
3168 match(RegL);
3169 match(iRegLNoSp);
3170 op_cost(0);
3171 format %{ %}
3172 interface(REG_INTER);
3173 %}
3174
3175 // Pointer Register Operands
3176 // Pointer Register
3177 operand iRegP()
3178 %{
3179 constraint(ALLOC_IN_RC(ptr_reg));
3180 match(RegP);
3181 match(iRegPNoSp);
3182 match(iRegP_R10);
3183 match(iRegP_R15);
3184 match(javaThread_RegP);
3185 op_cost(0);
3186 format %{ %}
3187 interface(REG_INTER);
3188 %}
3189
3190 // Pointer 64 bit Register not Special
3191 operand iRegPNoSp()
3192 %{
3193 constraint(ALLOC_IN_RC(no_special_ptr_reg));
3194 match(RegP);
3195 op_cost(0);
3196 format %{ %}
3197 interface(REG_INTER);
3198 %}
3199
3200 // This operand is not allowed to use fp even if
3201 // fp is not used to hold the frame pointer.
3202 operand iRegPNoSpNoFp()
3203 %{
3204 constraint(ALLOC_IN_RC(no_special_no_fp_ptr_reg));
3205 match(RegP);
3206 match(iRegPNoSp);
3207 op_cost(0);
3208 format %{ %}
3209 interface(REG_INTER);
3210 %}
3211
3212 operand iRegP_R10()
3213 %{
3214 constraint(ALLOC_IN_RC(r10_reg));
3215 match(RegP);
3216 // match(iRegP);
3217 match(iRegPNoSp);
3218 op_cost(0);
3219 format %{ %}
3220 interface(REG_INTER);
3221 %}
3222
3223 // Pointer 64 bit Register R11 only
3224 operand iRegP_R11()
3225 %{
3226 constraint(ALLOC_IN_RC(r11_reg));
3227 match(RegP);
3228 match(iRegPNoSp);
3229 op_cost(0);
3230 format %{ %}
3231 interface(REG_INTER);
3232 %}
3233
3234 operand iRegP_R12()
3235 %{
3236 constraint(ALLOC_IN_RC(r12_reg));
3237 match(RegP);
3238 // match(iRegP);
3239 match(iRegPNoSp);
3240 op_cost(0);
3241 format %{ %}
3242 interface(REG_INTER);
3243 %}
3244
3245 // Pointer 64 bit Register R13 only
3246 operand iRegP_R13()
3247 %{
3248 constraint(ALLOC_IN_RC(r13_reg));
3249 match(RegP);
3250 match(iRegPNoSp);
3251 op_cost(0);
3252 format %{ %}
3253 interface(REG_INTER);
3254 %}
3255
3256 operand iRegP_R14()
3257 %{
3258 constraint(ALLOC_IN_RC(r14_reg));
3259 match(RegP);
3260 // match(iRegP);
3261 match(iRegPNoSp);
3262 op_cost(0);
3263 format %{ %}
3264 interface(REG_INTER);
3265 %}
3266
3267 operand iRegP_R15()
3268 %{
3269 constraint(ALLOC_IN_RC(r15_reg));
3270 match(RegP);
3271 // match(iRegP);
3272 match(iRegPNoSp);
3273 op_cost(0);
3274 format %{ %}
3275 interface(REG_INTER);
3276 %}
3277
3278 operand iRegP_R16()
3279 %{
3280 constraint(ALLOC_IN_RC(r16_reg));
3281 match(RegP);
3282 match(iRegPNoSp);
3283 op_cost(0);
3284 format %{ %}
3285 interface(REG_INTER);
3286 %}
3287
3288 // Pointer 64 bit Register R28 only
3289 operand iRegP_R28()
3290 %{
3291 constraint(ALLOC_IN_RC(r28_reg));
3292 match(RegP);
3293 match(iRegPNoSp);
3294 op_cost(0);
3295 format %{ %}
3296 interface(REG_INTER);
3297 %}
3298
3299 // Pointer 64 bit Register R30 only
3300 operand iRegP_R30()
3301 %{
3302 constraint(ALLOC_IN_RC(r30_reg));
3303 match(RegP);
3304 match(iRegPNoSp);
3305 op_cost(0);
3306 format %{ %}
3307 interface(REG_INTER);
3308 %}
3309
3310 // Pointer 64 bit Register R31 only
3311 operand iRegP_R31()
3312 %{
3313 constraint(ALLOC_IN_RC(r31_reg));
3314 match(RegP);
3315 match(iRegPNoSp);
3316 op_cost(0);
3317 format %{ %}
3318 interface(REG_INTER);
3319 %}
3320
3321 // Pointer Register Operands
3322 // Narrow Pointer Register
3323 operand iRegN()
3324 %{
3325 constraint(ALLOC_IN_RC(any_reg32));
3326 match(RegN);
3327 match(iRegNNoSp);
3328 op_cost(0);
3329 format %{ %}
3330 interface(REG_INTER);
3331 %}
3332
3333 // Integer 64 bit Register not Special
3334 operand iRegNNoSp()
3335 %{
3336 constraint(ALLOC_IN_RC(no_special_reg32));
3337 match(RegN);
3338 op_cost(0);
3339 format %{ %}
3340 interface(REG_INTER);
3341 %}
3342
3343 // Long 64 bit Register R10 only
3344 operand iRegL_R10()
3345 %{
3346 constraint(ALLOC_IN_RC(r10_reg));
3347 match(RegL);
3348 match(iRegLNoSp);
3349 op_cost(0);
3350 format %{ %}
3351 interface(REG_INTER);
3352 %}
3353
3354 // Float Register
3355 // Float register operands
3356 operand fRegF()
3357 %{
3358 constraint(ALLOC_IN_RC(float_reg));
3359 match(RegF);
3360
3361 op_cost(0);
3362 format %{ %}
3363 interface(REG_INTER);
3364 %}
3365
3366 // Double Register
3367 // Double register operands
3368 operand fRegD()
3369 %{
3370 constraint(ALLOC_IN_RC(double_reg));
3371 match(RegD);
3372
3373 op_cost(0);
3374 format %{ %}
3375 interface(REG_INTER);
3376 %}
3377
3378 // Generic vector class. This will be used for
3379 // all vector operands.
3380 operand vReg()
3381 %{
3382 constraint(ALLOC_IN_RC(vectora_reg));
3383 match(VecA);
3384 op_cost(0);
3385 format %{ %}
3386 interface(REG_INTER);
3387 %}
3388
3389 operand vReg_V1()
3390 %{
3391 constraint(ALLOC_IN_RC(v1_reg));
3392 match(VecA);
3393 match(vReg);
3394 op_cost(0);
3395 format %{ %}
3396 interface(REG_INTER);
3397 %}
3398
3399 operand vReg_V2()
3400 %{
3401 constraint(ALLOC_IN_RC(v2_reg));
3402 match(VecA);
3403 match(vReg);
3404 op_cost(0);
3405 format %{ %}
3406 interface(REG_INTER);
3407 %}
3408
3409 operand vReg_V3()
3410 %{
3411 constraint(ALLOC_IN_RC(v3_reg));
3412 match(VecA);
3413 match(vReg);
3414 op_cost(0);
3415 format %{ %}
3416 interface(REG_INTER);
3417 %}
3418
3419 operand vReg_V4()
3420 %{
3421 constraint(ALLOC_IN_RC(v4_reg));
3422 match(VecA);
3423 match(vReg);
3424 op_cost(0);
3425 format %{ %}
3426 interface(REG_INTER);
3427 %}
3428
3429 operand vReg_V5()
3430 %{
3431 constraint(ALLOC_IN_RC(v5_reg));
3432 match(VecA);
3433 match(vReg);
3434 op_cost(0);
3435 format %{ %}
3436 interface(REG_INTER);
3437 %}
3438
3439 operand vReg_V6()
3440 %{
3441 constraint(ALLOC_IN_RC(v6_reg));
3442 match(VecA);
3443 match(vReg);
3444 op_cost(0);
3445 format %{ %}
3446 interface(REG_INTER);
3447 %}
3448
3449 operand vReg_V7()
3450 %{
3451 constraint(ALLOC_IN_RC(v7_reg));
3452 match(VecA);
3453 match(vReg);
3454 op_cost(0);
3455 format %{ %}
3456 interface(REG_INTER);
3457 %}
3458
3459 operand vReg_V8()
3460 %{
3461 constraint(ALLOC_IN_RC(v8_reg));
3462 match(VecA);
3463 match(vReg);
3464 op_cost(0);
3465 format %{ %}
3466 interface(REG_INTER);
3467 %}
3468
3469 operand vReg_V9()
3470 %{
3471 constraint(ALLOC_IN_RC(v9_reg));
3472 match(VecA);
3473 match(vReg);
3474 op_cost(0);
3475 format %{ %}
3476 interface(REG_INTER);
3477 %}
3478
3479 operand vReg_V10()
3480 %{
3481 constraint(ALLOC_IN_RC(v10_reg));
3482 match(VecA);
3483 match(vReg);
3484 op_cost(0);
3485 format %{ %}
3486 interface(REG_INTER);
3487 %}
3488
3489 operand vReg_V11()
3490 %{
3491 constraint(ALLOC_IN_RC(v11_reg));
3492 match(VecA);
3493 match(vReg);
3494 op_cost(0);
3495 format %{ %}
3496 interface(REG_INTER);
3497 %}
3498
3499 operand vRegMask()
3500 %{
3501 constraint(ALLOC_IN_RC(vmask_reg));
3502 match(RegVectMask);
3503 match(vRegMask_V0);
3504 op_cost(0);
3505 format %{ %}
3506 interface(REG_INTER);
3507 %}
3508
3509 // The mask value used to control execution of a masked
3510 // vector instruction is always supplied by vector register v0.
3511 operand vRegMask_V0()
3512 %{
3513 constraint(ALLOC_IN_RC(vmask_reg_v0));
3514 match(RegVectMask);
3515 match(vRegMask);
3516 op_cost(0);
3517 format %{ %}
3518 interface(REG_INTER);
3519 %}
3520
3521 // Java Thread Register
3522 operand javaThread_RegP(iRegP reg)
3523 %{
3524 constraint(ALLOC_IN_RC(java_thread_reg)); // java_thread_reg
3525 match(reg);
3526 op_cost(0);
3527 format %{ %}
3528 interface(REG_INTER);
3529 %}
3530
3531 //----------Memory Operands----------------------------------------------------
3532 // RISCV has only base_plus_offset and literal address mode, so no need to use
3533 // index and scale. Here set index as 0xffffffff and scale as 0x0.
3534 operand indirect(iRegP reg)
3535 %{
3536 constraint(ALLOC_IN_RC(ptr_reg));
3537 match(reg);
3538 op_cost(0);
3539 format %{ "[$reg]" %}
3540 interface(MEMORY_INTER) %{
3541 base($reg);
3542 index(0xffffffff);
3543 scale(0x0);
3544 disp(0x0);
3545 %}
3546 %}
3547
3548 operand indOffI(iRegP reg, immIOffset off)
3549 %{
3550 constraint(ALLOC_IN_RC(ptr_reg));
3551 match(AddP reg off);
3552 op_cost(0);
3553 format %{ "[$reg, $off]" %}
3554 interface(MEMORY_INTER) %{
3555 base($reg);
3556 index(0xffffffff);
3557 scale(0x0);
3558 disp($off);
3559 %}
3560 %}
3561
3562 operand indOffL(iRegP reg, immLOffset off)
3563 %{
3564 constraint(ALLOC_IN_RC(ptr_reg));
3565 match(AddP reg off);
3566 op_cost(0);
3567 format %{ "[$reg, $off]" %}
3568 interface(MEMORY_INTER) %{
3569 base($reg);
3570 index(0xffffffff);
3571 scale(0x0);
3572 disp($off);
3573 %}
3574 %}
3575
3576 operand indirectN(iRegN reg)
3577 %{
3578 predicate(CompressedOops::shift() == 0);
3579 constraint(ALLOC_IN_RC(ptr_reg));
3580 match(DecodeN reg);
3581 op_cost(0);
3582 format %{ "[$reg]\t# narrow" %}
3583 interface(MEMORY_INTER) %{
3584 base($reg);
3585 index(0xffffffff);
3586 scale(0x0);
3587 disp(0x0);
3588 %}
3589 %}
3590
3591 operand indOffIN(iRegN reg, immIOffset off)
3592 %{
3593 predicate(CompressedOops::shift() == 0);
3594 constraint(ALLOC_IN_RC(ptr_reg));
3595 match(AddP (DecodeN reg) off);
3596 op_cost(0);
3597 format %{ "[$reg, $off]\t# narrow" %}
3598 interface(MEMORY_INTER) %{
3599 base($reg);
3600 index(0xffffffff);
3601 scale(0x0);
3602 disp($off);
3603 %}
3604 %}
3605
3606 operand indOffLN(iRegN reg, immLOffset off)
3607 %{
3608 predicate(CompressedOops::shift() == 0);
3609 constraint(ALLOC_IN_RC(ptr_reg));
3610 match(AddP (DecodeN reg) off);
3611 op_cost(0);
3612 format %{ "[$reg, $off]\t# narrow" %}
3613 interface(MEMORY_INTER) %{
3614 base($reg);
3615 index(0xffffffff);
3616 scale(0x0);
3617 disp($off);
3618 %}
3619 %}
3620
3621 //----------Special Memory Operands--------------------------------------------
3622 // Stack Slot Operand - This operand is used for loading and storing temporary
3623 // values on the stack where a match requires a value to
3624 // flow through memory.
3625 operand stackSlotI(sRegI reg)
3626 %{
3627 constraint(ALLOC_IN_RC(stack_slots));
3628 // No match rule because this operand is only generated in matching
3629 // match(RegI);
3630 format %{ "[$reg]" %}
3631 interface(MEMORY_INTER) %{
3632 base(0x02); // RSP
3633 index(0xffffffff); // No Index
3634 scale(0x0); // No Scale
3635 disp($reg); // Stack Offset
3636 %}
3637 %}
3638
3639 operand stackSlotF(sRegF reg)
3640 %{
3641 constraint(ALLOC_IN_RC(stack_slots));
3642 // No match rule because this operand is only generated in matching
3643 // match(RegF);
3644 format %{ "[$reg]" %}
3645 interface(MEMORY_INTER) %{
3646 base(0x02); // RSP
3647 index(0xffffffff); // No Index
3648 scale(0x0); // No Scale
3649 disp($reg); // Stack Offset
3650 %}
3651 %}
3652
3653 operand stackSlotD(sRegD reg)
3654 %{
3655 constraint(ALLOC_IN_RC(stack_slots));
3656 // No match rule because this operand is only generated in matching
3657 // match(RegD);
3658 format %{ "[$reg]" %}
3659 interface(MEMORY_INTER) %{
3660 base(0x02); // RSP
3661 index(0xffffffff); // No Index
3662 scale(0x0); // No Scale
3663 disp($reg); // Stack Offset
3664 %}
3665 %}
3666
3667 operand stackSlotL(sRegL reg)
3668 %{
3669 constraint(ALLOC_IN_RC(stack_slots));
3670 // No match rule because this operand is only generated in matching
3671 // match(RegL);
3672 format %{ "[$reg]" %}
3673 interface(MEMORY_INTER) %{
3674 base(0x02); // RSP
3675 index(0xffffffff); // No Index
3676 scale(0x0); // No Scale
3677 disp($reg); // Stack Offset
3678 %}
3679 %}
3680
3681 // Special operand allowing long args to int ops to be truncated for free
3682
3683 operand iRegL2I(iRegL reg) %{
3684
3685 op_cost(0);
3686
3687 match(ConvL2I reg);
3688
3689 format %{ "l2i($reg)" %}
3690
3691 interface(REG_INTER)
3692 %}
3693
3694
3695 // Comparison Operands
3696 // NOTE: Label is a predefined operand which should not be redefined in
3697 // the AD file. It is generically handled within the ADLC.
3698
3699 //----------Conditional Branch Operands----------------------------------------
3700 // Comparison Op - This is the operation of the comparison, and is limited to
3701 // the following set of codes:
3702 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3703 //
3704 // Other attributes of the comparison, such as unsignedness, are specified
3705 // by the comparison instruction that sets a condition code flags register.
3706 // That result is represented by a flags operand whose subtype is appropriate
3707 // to the unsignedness (etc.) of the comparison.
3708 //
3709 // Later, the instruction which matches both the Comparison Op (a Bool) and
3710 // the flags (produced by the Cmp) specifies the coding of the comparison op
3711 // by matching a specific subtype of Bool operand below, such as cmpOpU.
3712
3713
3714 // used for signed integral comparisons and fp comparisons
3715 operand cmpOp()
3716 %{
3717 match(Bool);
3718
3719 format %{ "" %}
3720
3721 // the values in interface derives from struct BoolTest::mask
3722 interface(COND_INTER) %{
3723 equal(0x0, "eq");
3724 greater(0x1, "gt");
3725 overflow(0x2, "overflow");
3726 less(0x3, "lt");
3727 not_equal(0x4, "ne");
3728 less_equal(0x5, "le");
3729 no_overflow(0x6, "no_overflow");
3730 greater_equal(0x7, "ge");
3731 %}
3732 %}
3733
3734 // used for unsigned integral comparisons
3735 operand cmpOpU()
3736 %{
3737 match(Bool);
3738
3739 format %{ "" %}
3740 // the values in interface derives from struct BoolTest::mask
3741 interface(COND_INTER) %{
3742 equal(0x0, "eq");
3743 greater(0x1, "gtu");
3744 overflow(0x2, "overflow");
3745 less(0x3, "ltu");
3746 not_equal(0x4, "ne");
3747 less_equal(0x5, "leu");
3748 no_overflow(0x6, "no_overflow");
3749 greater_equal(0x7, "geu");
3750 %}
3751 %}
3752
3753 // used for certain integral comparisons which can be
3754 // converted to bxx instructions
3755 operand cmpOpEqNe()
3756 %{
3757 match(Bool);
3758 op_cost(0);
3759 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
3760 n->as_Bool()->_test._test == BoolTest::eq);
3761
3762 format %{ "" %}
3763 interface(COND_INTER) %{
3764 equal(0x0, "eq");
3765 greater(0x1, "gt");
3766 overflow(0x2, "overflow");
3767 less(0x3, "lt");
3768 not_equal(0x4, "ne");
3769 less_equal(0x5, "le");
3770 no_overflow(0x6, "no_overflow");
3771 greater_equal(0x7, "ge");
3772 %}
3773 %}
3774
3775 operand cmpOpULtGe()
3776 %{
3777 match(Bool);
3778 op_cost(0);
3779 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
3780 n->as_Bool()->_test._test == BoolTest::ge);
3781
3782 format %{ "" %}
3783 interface(COND_INTER) %{
3784 equal(0x0, "eq");
3785 greater(0x1, "gtu");
3786 overflow(0x2, "overflow");
3787 less(0x3, "ltu");
3788 not_equal(0x4, "ne");
3789 less_equal(0x5, "leu");
3790 no_overflow(0x6, "no_overflow");
3791 greater_equal(0x7, "geu");
3792 %}
3793 %}
3794
3795 operand cmpOpUEqNeLeGt()
3796 %{
3797 match(Bool);
3798 op_cost(0);
3799 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
3800 n->as_Bool()->_test._test == BoolTest::eq ||
3801 n->as_Bool()->_test._test == BoolTest::le ||
3802 n->as_Bool()->_test._test == BoolTest::gt);
3803
3804 format %{ "" %}
3805 interface(COND_INTER) %{
3806 equal(0x0, "eq");
3807 greater(0x1, "gtu");
3808 overflow(0x2, "overflow");
3809 less(0x3, "ltu");
3810 not_equal(0x4, "ne");
3811 less_equal(0x5, "leu");
3812 no_overflow(0x6, "no_overflow");
3813 greater_equal(0x7, "geu");
3814 %}
3815 %}
3816
3817
3818 // Flags register, used as output of compare logic
3819 operand rFlagsReg()
3820 %{
3821 constraint(ALLOC_IN_RC(reg_flags));
3822 match(RegFlags);
3823
3824 op_cost(0);
3825 format %{ "RFLAGS" %}
3826 interface(REG_INTER);
3827 %}
3828
3829 // Special Registers
3830
3831 // Method Register
3832 operand inline_cache_RegP(iRegP reg)
3833 %{
3834 constraint(ALLOC_IN_RC(method_reg)); // inline_cache_reg
3835 match(reg);
3836 match(iRegPNoSp);
3837 op_cost(0);
3838 format %{ %}
3839 interface(REG_INTER);
3840 %}
3841
3842 //----------OPERAND CLASSES----------------------------------------------------
3843 // Operand Classes are groups of operands that are used as to simplify
3844 // instruction definitions by not requiring the AD writer to specify
3845 // separate instructions for every form of operand when the
3846 // instruction accepts multiple operand types with the same basic
3847 // encoding and format. The classic case of this is memory operands.
3848
3849 // memory is used to define read/write location for load/store
3850 // instruction defs. we can turn a memory op into an Address
3851
3852 opclass memory(indirect, indOffI, indOffL, indirectN, indOffIN, indOffLN);
3853
3854 // iRegIorL2I is used for src inputs in rules for 32 bit int (I)
3855 // operations. it allows the src to be either an iRegI or a (ConvL2I
3856 // iRegL). in the latter case the l2i normally planted for a ConvL2I
3857 // can be elided because the 32-bit instruction will just employ the
3858 // lower 32 bits anyway.
3859 //
3860 // n.b. this does not elide all L2I conversions. if the truncated
3861 // value is consumed by more than one operation then the ConvL2I
3862 // cannot be bundled into the consuming nodes so an l2i gets planted
3863 // (actually an addiw $dst, $src, 0) and the downstream instructions
3864 // consume the result of the L2I as an iRegI input. That's a shame since
3865 // the addiw is actually redundant but its not too costly.
3866
3867 opclass iRegIorL2I(iRegI, iRegL2I);
3868 opclass iRegIorL(iRegI, iRegL);
3869 opclass iRegNorP(iRegN, iRegP);
3870 opclass iRegILNP(iRegI, iRegL, iRegN, iRegP);
3871 opclass iRegILNPNoSp(iRegINoSp, iRegLNoSp, iRegNNoSp, iRegPNoSp);
3872 opclass immIorL(immI, immL);
3873
3874 //----------PIPELINE-----------------------------------------------------------
3875 // Rules which define the behavior of the target architectures pipeline.
3876
3877 // For specific pipelines, e.g. generic RISC-V, define the stages of that pipeline
3878 //pipe_desc(ID, EX, MEM, WR);
3879 #define ID S0
3880 #define EX S1
3881 #define MEM S2
3882 #define WR S3
3883
3884 // Integer ALU reg operation
3885 pipeline %{
3886
3887 attributes %{
3888 // RISC-V instructions are of fixed length
3889 fixed_size_instructions; // Fixed size instructions TODO does
3890 max_instructions_per_bundle = 2; // Generic RISC-V 1, Sifive Series 7 2
3891 // RISC-V instructions come in 32-bit word units
3892 instruction_unit_size = 4; // An instruction is 4 bytes long
3893 instruction_fetch_unit_size = 64; // The processor fetches one line
3894 instruction_fetch_units = 1; // of 64 bytes
3895
3896 // List of nop instructions
3897 nops( MachNop );
3898 %}
3899
3900 // We don't use an actual pipeline model so don't care about resources
3901 // or description. we do use pipeline classes to introduce fixed
3902 // latencies
3903
3904 //----------RESOURCES----------------------------------------------------------
3905 // Resources are the functional units available to the machine
3906
3907 // Generic RISC-V pipeline
3908 // 1 decoder
3909 // 1 instruction decoded per cycle
3910 // 1 load/store ops per cycle, 1 branch, 1 FPU
3911 // 1 mul, 1 div
3912
3913 resources ( DECODE,
3914 ALU,
3915 MUL,
3916 DIV,
3917 BRANCH,
3918 LDST,
3919 FPU);
3920
3921 //----------PIPELINE DESCRIPTION-----------------------------------------------
3922 // Pipeline Description specifies the stages in the machine's pipeline
3923
3924 // Define the pipeline as a generic 6 stage pipeline
3925 pipe_desc(S0, S1, S2, S3, S4, S5);
3926
3927 //----------PIPELINE CLASSES---------------------------------------------------
3928 // Pipeline Classes describe the stages in which input and output are
3929 // referenced by the hardware pipeline.
3930
3931 pipe_class fp_dop_reg_reg_s(fRegF dst, fRegF src1, fRegF src2)
3932 %{
3933 single_instruction;
3934 src1 : S1(read);
3935 src2 : S2(read);
3936 dst : S5(write);
3937 DECODE : ID;
3938 FPU : S5;
3939 %}
3940
3941 pipe_class fp_dop_reg_reg_d(fRegD dst, fRegD src1, fRegD src2)
3942 %{
3943 src1 : S1(read);
3944 src2 : S2(read);
3945 dst : S5(write);
3946 DECODE : ID;
3947 FPU : S5;
3948 %}
3949
3950 pipe_class fp_uop_s(fRegF dst, fRegF src)
3951 %{
3952 single_instruction;
3953 src : S1(read);
3954 dst : S5(write);
3955 DECODE : ID;
3956 FPU : S5;
3957 %}
3958
3959 pipe_class fp_uop_d(fRegD dst, fRegD src)
3960 %{
3961 single_instruction;
3962 src : S1(read);
3963 dst : S5(write);
3964 DECODE : ID;
3965 FPU : S5;
3966 %}
3967
3968 pipe_class fp_d2f(fRegF dst, fRegD src)
3969 %{
3970 single_instruction;
3971 src : S1(read);
3972 dst : S5(write);
3973 DECODE : ID;
3974 FPU : S5;
3975 %}
3976
3977 pipe_class fp_f2d(fRegD dst, fRegF src)
3978 %{
3979 single_instruction;
3980 src : S1(read);
3981 dst : S5(write);
3982 DECODE : ID;
3983 FPU : S5;
3984 %}
3985
3986 pipe_class fp_f2i(iRegINoSp dst, fRegF src)
3987 %{
3988 single_instruction;
3989 src : S1(read);
3990 dst : S5(write);
3991 DECODE : ID;
3992 FPU : S5;
3993 %}
3994
3995 pipe_class fp_f2l(iRegLNoSp dst, fRegF src)
3996 %{
3997 single_instruction;
3998 src : S1(read);
3999 dst : S5(write);
4000 DECODE : ID;
4001 FPU : S5;
4002 %}
4003
4004 pipe_class fp_i2f(fRegF dst, iRegIorL2I src)
4005 %{
4006 single_instruction;
4007 src : S1(read);
4008 dst : S5(write);
4009 DECODE : ID;
4010 FPU : S5;
4011 %}
4012
4013 pipe_class fp_l2f(fRegF dst, iRegL src)
4014 %{
4015 single_instruction;
4016 src : S1(read);
4017 dst : S5(write);
4018 DECODE : ID;
4019 FPU : S5;
4020 %}
4021
4022 pipe_class fp_d2i(iRegINoSp dst, fRegD src)
4023 %{
4024 single_instruction;
4025 src : S1(read);
4026 dst : S5(write);
4027 DECODE : ID;
4028 FPU : S5;
4029 %}
4030
4031 pipe_class fp_d2l(iRegLNoSp dst, fRegD src)
4032 %{
4033 single_instruction;
4034 src : S1(read);
4035 dst : S5(write);
4036 DECODE : ID;
4037 FPU : S5;
4038 %}
4039
4040 pipe_class fp_i2d(fRegD dst, iRegIorL2I src)
4041 %{
4042 single_instruction;
4043 src : S1(read);
4044 dst : S5(write);
4045 DECODE : ID;
4046 FPU : S5;
4047 %}
4048
4049 pipe_class fp_l2d(fRegD dst, iRegIorL2I src)
4050 %{
4051 single_instruction;
4052 src : S1(read);
4053 dst : S5(write);
4054 DECODE : ID;
4055 FPU : S5;
4056 %}
4057
4058 pipe_class fp_div_s(fRegF dst, fRegF src1, fRegF src2)
4059 %{
4060 single_instruction;
4061 src1 : S1(read);
4062 src2 : S2(read);
4063 dst : S5(write);
4064 DECODE : ID;
4065 FPU : S5;
4066 %}
4067
4068 pipe_class fp_div_d(fRegD dst, fRegD src1, fRegD src2)
4069 %{
4070 single_instruction;
4071 src1 : S1(read);
4072 src2 : S2(read);
4073 dst : S5(write);
4074 DECODE : ID;
4075 FPU : S5;
4076 %}
4077
4078 pipe_class fp_sqrt_s(fRegF dst, fRegF src)
4079 %{
4080 single_instruction;
4081 src : S1(read);
4082 dst : S5(write);
4083 DECODE : ID;
4084 FPU : S5;
4085 %}
4086
4087 pipe_class fp_sqrt_d(fRegD dst, fRegD src)
4088 %{
4089 single_instruction;
4090 src : S1(read);
4091 dst : S5(write);
4092 DECODE : ID;
4093 FPU : S5;
4094 %}
4095
4096 pipe_class fp_load_constant_s(fRegF dst)
4097 %{
4098 single_instruction;
4099 dst : S5(write);
4100 DECODE : ID;
4101 FPU : S5;
4102 %}
4103
4104 pipe_class fp_load_constant_d(fRegD dst)
4105 %{
4106 single_instruction;
4107 dst : S5(write);
4108 DECODE : ID;
4109 FPU : S5;
4110 %}
4111
4112 pipe_class fp_load_mem_s(fRegF dst, memory mem)
4113 %{
4114 single_instruction;
4115 mem : S1(read);
4116 dst : S5(write);
4117 DECODE : ID;
4118 LDST : MEM;
4119 %}
4120
4121 pipe_class fp_load_mem_d(fRegD dst, memory mem)
4122 %{
4123 single_instruction;
4124 mem : S1(read);
4125 dst : S5(write);
4126 DECODE : ID;
4127 LDST : MEM;
4128 %}
4129
4130 pipe_class fp_store_reg_s(fRegF src, memory mem)
4131 %{
4132 single_instruction;
4133 src : S1(read);
4134 mem : S5(write);
4135 DECODE : ID;
4136 LDST : MEM;
4137 %}
4138
4139 pipe_class fp_store_reg_d(fRegD src, memory mem)
4140 %{
4141 single_instruction;
4142 src : S1(read);
4143 mem : S5(write);
4144 DECODE : ID;
4145 LDST : MEM;
4146 %}
4147
4148 //------- Integer ALU operations --------------------------
4149
4150 // Integer ALU reg-reg operation
4151 // Operands needs in ID, result generated in EX
4152 // E.g. ADD Rd, Rs1, Rs2
4153 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4154 %{
4155 single_instruction;
4156 dst : EX(write);
4157 src1 : ID(read);
4158 src2 : ID(read);
4159 DECODE : ID;
4160 ALU : EX;
4161 %}
4162
4163 // Integer ALU reg operation with constant shift
4164 // E.g. SLLI Rd, Rs1, #shift
4165 pipe_class ialu_reg_shift(iRegI dst, iRegI src1)
4166 %{
4167 single_instruction;
4168 dst : EX(write);
4169 src1 : ID(read);
4170 DECODE : ID;
4171 ALU : EX;
4172 %}
4173
4174 // Integer ALU reg-reg operation with variable shift
4175 // both operands must be available in ID
4176 // E.g. SLL Rd, Rs1, Rs2
4177 pipe_class ialu_reg_reg_vshift(iRegI dst, iRegI src1, iRegI src2)
4178 %{
4179 single_instruction;
4180 dst : EX(write);
4181 src1 : ID(read);
4182 src2 : ID(read);
4183 DECODE : ID;
4184 ALU : EX;
4185 %}
4186
4187 // Integer ALU reg operation
4188 // E.g. NEG Rd, Rs2
4189 pipe_class ialu_reg(iRegI dst, iRegI src)
4190 %{
4191 single_instruction;
4192 dst : EX(write);
4193 src : ID(read);
4194 DECODE : ID;
4195 ALU : EX;
4196 %}
4197
4198 // Integer ALU reg immediate operation
4199 // E.g. ADDI Rd, Rs1, #imm
4200 pipe_class ialu_reg_imm(iRegI dst, iRegI src1)
4201 %{
4202 single_instruction;
4203 dst : EX(write);
4204 src1 : ID(read);
4205 DECODE : ID;
4206 ALU : EX;
4207 %}
4208
4209 // Integer ALU immediate operation (no source operands)
4210 // E.g. LI Rd, #imm
4211 pipe_class ialu_imm(iRegI dst)
4212 %{
4213 single_instruction;
4214 dst : EX(write);
4215 DECODE : ID;
4216 ALU : EX;
4217 %}
4218
4219 //------- Multiply pipeline operations --------------------
4220
4221 // Multiply reg-reg
4222 // E.g. MULW Rd, Rs1, Rs2
4223 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4224 %{
4225 single_instruction;
4226 dst : WR(write);
4227 src1 : ID(read);
4228 src2 : ID(read);
4229 DECODE : ID;
4230 MUL : WR;
4231 %}
4232
4233 // E.g. MUL RD, Rs1, Rs2
4234 pipe_class lmul_reg_reg(iRegL dst, iRegL src1, iRegL src2)
4235 %{
4236 single_instruction;
4237 fixed_latency(3); // Maximum latency for 64 bit mul
4238 dst : WR(write);
4239 src1 : ID(read);
4240 src2 : ID(read);
4241 DECODE : ID;
4242 MUL : WR;
4243 %}
4244
4245 //------- Divide pipeline operations --------------------
4246
4247 // E.g. DIVW Rd, Rs1, Rs2
4248 pipe_class idiv_reg_reg(iRegI dst, iRegI src1, iRegI src2)
4249 %{
4250 single_instruction;
4251 fixed_latency(8); // Maximum latency for 32 bit divide
4252 dst : WR(write);
4253 src1 : ID(read);
4254 src2 : ID(read);
4255 DECODE : ID;
4256 DIV : WR;
4257 %}
4258
4259 // E.g. DIV RD, Rs1, Rs2
4260 pipe_class ldiv_reg_reg(iRegL dst, iRegL src1, iRegL src2)
4261 %{
4262 single_instruction;
4263 fixed_latency(16); // Maximum latency for 64 bit divide
4264 dst : WR(write);
4265 src1 : ID(read);
4266 src2 : ID(read);
4267 DECODE : ID;
4268 DIV : WR;
4269 %}
4270
4271 //------- Load pipeline operations ------------------------
4272
4273 // Load - prefetch
4274 // Eg. PREFETCH_W mem
4275 pipe_class iload_prefetch(memory mem)
4276 %{
4277 single_instruction;
4278 mem : ID(read);
4279 DECODE : ID;
4280 LDST : MEM;
4281 %}
4282
4283 // Load - reg, mem
4284 // E.g. LA Rd, mem
4285 pipe_class iload_reg_mem(iRegI dst, memory mem)
4286 %{
4287 single_instruction;
4288 dst : WR(write);
4289 mem : ID(read);
4290 DECODE : ID;
4291 LDST : MEM;
4292 %}
4293
4294 // Load - reg, reg
4295 // E.g. LD Rd, Rs
4296 pipe_class iload_reg_reg(iRegI dst, iRegI src)
4297 %{
4298 single_instruction;
4299 dst : WR(write);
4300 src : ID(read);
4301 DECODE : ID;
4302 LDST : MEM;
4303 %}
4304
4305 //------- Store pipeline operations -----------------------
4306
4307 // Store - zr, mem
4308 // E.g. SD zr, mem
4309 pipe_class istore_mem(memory mem)
4310 %{
4311 single_instruction;
4312 mem : ID(read);
4313 DECODE : ID;
4314 LDST : MEM;
4315 %}
4316
4317 // Store - reg, mem
4318 // E.g. SD Rs, mem
4319 pipe_class istore_reg_mem(iRegI src, memory mem)
4320 %{
4321 single_instruction;
4322 mem : ID(read);
4323 src : EX(read);
4324 DECODE : ID;
4325 LDST : MEM;
4326 %}
4327
4328 // Store - reg, reg
4329 // E.g. SD Rs2, Rs1
4330 pipe_class istore_reg_reg(iRegI dst, iRegI src)
4331 %{
4332 single_instruction;
4333 dst : ID(read);
4334 src : EX(read);
4335 DECODE : ID;
4336 LDST : MEM;
4337 %}
4338
4339 //------- Control transfer pipeline operations ------------
4340
4341 // Branch
4342 pipe_class pipe_branch()
4343 %{
4344 single_instruction;
4345 DECODE : ID;
4346 BRANCH : EX;
4347 %}
4348
4349 // Branch
4350 pipe_class pipe_branch_reg(iRegI src)
4351 %{
4352 single_instruction;
4353 src : ID(read);
4354 DECODE : ID;
4355 BRANCH : EX;
4356 %}
4357
4358 // Compare & Branch
4359 // E.g. BEQ Rs1, Rs2, L
4360 pipe_class pipe_cmp_branch(iRegI src1, iRegI src2)
4361 %{
4362 single_instruction;
4363 src1 : ID(read);
4364 src2 : ID(read);
4365 DECODE : ID;
4366 BRANCH : EX;
4367 %}
4368
4369 // E.g. BEQZ Rs, L
4370 pipe_class pipe_cmpz_branch(iRegI src)
4371 %{
4372 single_instruction;
4373 src : ID(read);
4374 DECODE : ID;
4375 BRANCH : EX;
4376 %}
4377
4378 //------- Synchronisation operations ----------------------
4379 // Any operation requiring serialization
4380 // E.g. FENCE/Atomic Ops/Load Acquire/Store Release
4381 pipe_class pipe_serial()
4382 %{
4383 single_instruction;
4384 force_serialization;
4385 fixed_latency(16);
4386 DECODE : ID;
4387 LDST : MEM;
4388 %}
4389
4390 pipe_class pipe_slow()
4391 %{
4392 instruction_count(10);
4393 multiple_bundles;
4394 force_serialization;
4395 fixed_latency(16);
4396 DECODE : ID;
4397 LDST : MEM;
4398 %}
4399
4400 // Empty pipeline class
4401 pipe_class pipe_class_empty()
4402 %{
4403 single_instruction;
4404 fixed_latency(0);
4405 %}
4406
4407 // Default pipeline class.
4408 pipe_class pipe_class_default()
4409 %{
4410 single_instruction;
4411 fixed_latency(2);
4412 %}
4413
4414 // Pipeline class for compares.
4415 pipe_class pipe_class_compare()
4416 %{
4417 single_instruction;
4418 fixed_latency(16);
4419 %}
4420
4421 // Pipeline class for memory operations.
4422 pipe_class pipe_class_memory()
4423 %{
4424 single_instruction;
4425 fixed_latency(16);
4426 %}
4427
4428 // Pipeline class for call.
4429 pipe_class pipe_class_call()
4430 %{
4431 single_instruction;
4432 fixed_latency(100);
4433 %}
4434
4435 // Define the class for the Nop node.
4436 define %{
4437 MachNop = pipe_class_empty;
4438 %}
4439 %}
4440 //----------INSTRUCTIONS-------------------------------------------------------
4441 //
4442 // match -- States which machine-independent subtree may be replaced
4443 // by this instruction.
4444 // ins_cost -- The estimated cost of this instruction is used by instruction
4445 // selection to identify a minimum cost tree of machine
4446 // instructions that matches a tree of machine-independent
4447 // instructions.
4448 // format -- A string providing the disassembly for this instruction.
4449 // The value of an instruction's operand may be inserted
4450 // by referring to it with a '$' prefix.
4451 // opcode -- Three instruction opcodes may be provided. These are referred
4452 // to within an encode class as $primary, $secondary, and $tertiary
4453 // rrspectively. The primary opcode is commonly used to
4454 // indicate the type of machine instruction, while secondary
4455 // and tertiary are often used for prefix options or addressing
4456 // modes.
4457 // ins_encode -- A list of encode classes with parameters. The encode class
4458 // name must have been defined in an 'enc_class' specification
4459 // in the encode section of the architecture description.
4460
4461 // ============================================================================
4462 // Memory (Load/Store) Instructions
4463
4464 // Load Instructions
4465
4466 // Load Byte (8 bit signed)
4467 instruct loadB(iRegINoSp dst, memory mem)
4468 %{
4469 match(Set dst (LoadB mem));
4470
4471 ins_cost(LOAD_COST);
4472 format %{ "lb $dst, $mem\t# byte, #@loadB" %}
4473
4474 ins_encode %{
4475 __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4476 %}
4477
4478 ins_pipe(iload_reg_mem);
4479 %}
4480
4481 // Load Byte (8 bit signed) into long
4482 instruct loadB2L(iRegLNoSp dst, memory mem)
4483 %{
4484 match(Set dst (ConvI2L (LoadB mem)));
4485
4486 ins_cost(LOAD_COST);
4487 format %{ "lb $dst, $mem\t# byte, #@loadB2L" %}
4488
4489 ins_encode %{
4490 __ lb(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4491 %}
4492
4493 ins_pipe(iload_reg_mem);
4494 %}
4495
4496 // Load Byte (8 bit unsigned)
4497 instruct loadUB(iRegINoSp dst, memory mem)
4498 %{
4499 match(Set dst (LoadUB mem));
4500
4501 ins_cost(LOAD_COST);
4502 format %{ "lbu $dst, $mem\t# byte, #@loadUB" %}
4503
4504 ins_encode %{
4505 __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4506 %}
4507
4508 ins_pipe(iload_reg_mem);
4509 %}
4510
4511 // Load Byte (8 bit unsigned) into long
4512 instruct loadUB2L(iRegLNoSp dst, memory mem)
4513 %{
4514 match(Set dst (ConvI2L (LoadUB mem)));
4515
4516 ins_cost(LOAD_COST);
4517 format %{ "lbu $dst, $mem\t# byte, #@loadUB2L" %}
4518
4519 ins_encode %{
4520 __ lbu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4521 %}
4522
4523 ins_pipe(iload_reg_mem);
4524 %}
4525
4526 // Load Short (16 bit signed)
4527 instruct loadS(iRegINoSp dst, memory mem)
4528 %{
4529 match(Set dst (LoadS mem));
4530
4531 ins_cost(LOAD_COST);
4532 format %{ "lh $dst, $mem\t# short, #@loadS" %}
4533
4534 ins_encode %{
4535 __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4536 %}
4537
4538 ins_pipe(iload_reg_mem);
4539 %}
4540
4541 // Load Short (16 bit signed) into long
4542 instruct loadS2L(iRegLNoSp dst, memory mem)
4543 %{
4544 match(Set dst (ConvI2L (LoadS mem)));
4545
4546 ins_cost(LOAD_COST);
4547 format %{ "lh $dst, $mem\t# short, #@loadS2L" %}
4548
4549 ins_encode %{
4550 __ lh(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4551 %}
4552
4553 ins_pipe(iload_reg_mem);
4554 %}
4555
4556 // Load Char (16 bit unsigned)
4557 instruct loadUS(iRegINoSp dst, memory mem)
4558 %{
4559 match(Set dst (LoadUS mem));
4560
4561 ins_cost(LOAD_COST);
4562 format %{ "lhu $dst, $mem\t# short, #@loadUS" %}
4563
4564 ins_encode %{
4565 __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4566 %}
4567
4568 ins_pipe(iload_reg_mem);
4569 %}
4570
4571 // Load Short/Char (16 bit unsigned) into long
4572 instruct loadUS2L(iRegLNoSp dst, memory mem)
4573 %{
4574 match(Set dst (ConvI2L (LoadUS mem)));
4575
4576 ins_cost(LOAD_COST);
4577 format %{ "lhu $dst, $mem\t# short, #@loadUS2L" %}
4578
4579 ins_encode %{
4580 __ lhu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4581 %}
4582
4583 ins_pipe(iload_reg_mem);
4584 %}
4585
4586 // Load Integer (32 bit signed)
4587 instruct loadI(iRegINoSp dst, memory mem)
4588 %{
4589 match(Set dst (LoadI mem));
4590
4591 ins_cost(LOAD_COST);
4592 format %{ "lw $dst, $mem\t# int, #@loadI" %}
4593
4594 ins_encode %{
4595 __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4596 %}
4597
4598 ins_pipe(iload_reg_mem);
4599 %}
4600
4601 // Load Integer (32 bit signed) into long
4602 instruct loadI2L(iRegLNoSp dst, memory mem)
4603 %{
4604 match(Set dst (ConvI2L (LoadI mem)));
4605
4606 ins_cost(LOAD_COST);
4607 format %{ "lw $dst, $mem\t# int, #@loadI2L" %}
4608
4609 ins_encode %{
4610 __ lw(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4611 %}
4612
4613 ins_pipe(iload_reg_mem);
4614 %}
4615
4616 // Load Integer (32 bit unsigned) into long
4617 instruct loadUI2L(iRegLNoSp dst, memory mem, immL_32bits mask)
4618 %{
4619 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
4620
4621 ins_cost(LOAD_COST);
4622 format %{ "lwu $dst, $mem\t# int, #@loadUI2L" %}
4623
4624 ins_encode %{
4625 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4626 %}
4627
4628 ins_pipe(iload_reg_mem);
4629 %}
4630
4631 // Load Long (64 bit signed)
4632 instruct loadL(iRegLNoSp dst, memory mem)
4633 %{
4634 match(Set dst (LoadL mem));
4635
4636 ins_cost(LOAD_COST);
4637 format %{ "ld $dst, $mem\t# int, #@loadL" %}
4638
4639 ins_encode %{
4640 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4641 %}
4642
4643 ins_pipe(iload_reg_mem);
4644 %}
4645
4646 // Load Range
4647 instruct loadRange(iRegINoSp dst, memory mem)
4648 %{
4649 match(Set dst (LoadRange mem));
4650
4651 ins_cost(LOAD_COST);
4652 format %{ "lwu $dst, $mem\t# range, #@loadRange" %}
4653
4654 ins_encode %{
4655 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4656 %}
4657
4658 ins_pipe(iload_reg_mem);
4659 %}
4660
4661 // Load Pointer
4662 instruct loadP(iRegPNoSp dst, memory mem)
4663 %{
4664 match(Set dst (LoadP mem));
4665 predicate(n->as_Load()->barrier_data() == 0);
4666
4667 ins_cost(LOAD_COST);
4668 format %{ "ld $dst, $mem\t# ptr, #@loadP" %}
4669
4670 ins_encode %{
4671 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4672 %}
4673
4674 ins_pipe(iload_reg_mem);
4675 %}
4676
4677 // Load Compressed Pointer
4678 instruct loadN(iRegNNoSp dst, memory mem)
4679 %{
4680 predicate(n->as_Load()->barrier_data() == 0);
4681 match(Set dst (LoadN mem));
4682
4683 ins_cost(LOAD_COST);
4684 format %{ "lwu $dst, $mem\t# compressed ptr, #@loadN" %}
4685
4686 ins_encode %{
4687 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4688 %}
4689
4690 ins_pipe(iload_reg_mem);
4691 %}
4692
4693 // Load Klass Pointer
4694 instruct loadKlass(iRegPNoSp dst, memory mem)
4695 %{
4696 match(Set dst (LoadKlass mem));
4697
4698 ins_cost(LOAD_COST);
4699 format %{ "ld $dst, $mem\t# class, #@loadKlass" %}
4700
4701 ins_encode %{
4702 __ ld(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4703 %}
4704
4705 ins_pipe(iload_reg_mem);
4706 %}
4707
4708 // Load Narrow Klass Pointer
4709 instruct loadNKlass(iRegNNoSp dst, memory mem)
4710 %{
4711 predicate(!UseCompactObjectHeaders);
4712 match(Set dst (LoadNKlass mem));
4713
4714 ins_cost(LOAD_COST);
4715 format %{ "lwu $dst, $mem\t# compressed class ptr, #@loadNKlass" %}
4716
4717 ins_encode %{
4718 __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4719 %}
4720
4721 ins_pipe(iload_reg_mem);
4722 %}
4723
4724 instruct loadNKlassCompactHeaders(iRegNNoSp dst, memory mem)
4725 %{
4726 predicate(UseCompactObjectHeaders);
4727 match(Set dst (LoadNKlass mem));
4728
4729 ins_cost(LOAD_COST);
4730 format %{
4731 "lwu $dst, $mem\t# compressed klass ptr, shifted\n\t"
4732 "srli $dst, $dst, markWord::klass_shift_at_offset"
4733 %}
4734
4735 ins_encode %{
4736 Unimplemented();
4737 // __ lwu(as_Register($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4738 // __ srli(as_Register($dst$$reg), as_Register($dst$$reg), (unsigned) markWord::klass_shift_at_offset);
4739 %}
4740
4741 ins_pipe(iload_reg_mem);
4742 %}
4743
4744 // Load Float
4745 instruct loadF(fRegF dst, memory mem)
4746 %{
4747 match(Set dst (LoadF mem));
4748
4749 ins_cost(LOAD_COST);
4750 format %{ "flw $dst, $mem\t# float, #@loadF" %}
4751
4752 ins_encode %{
4753 __ flw(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4754 %}
4755
4756 ins_pipe(fp_load_mem_s);
4757 %}
4758
4759 // Load Double
4760 instruct loadD(fRegD dst, memory mem)
4761 %{
4762 match(Set dst (LoadD mem));
4763
4764 ins_cost(LOAD_COST);
4765 format %{ "fld $dst, $mem\t# double, #@loadD" %}
4766
4767 ins_encode %{
4768 __ fld(as_FloatRegister($dst$$reg), Address(as_Register($mem$$base), $mem$$disp));
4769 %}
4770
4771 ins_pipe(fp_load_mem_d);
4772 %}
4773
4774 // Load Int Constant
4775 instruct loadConI(iRegINoSp dst, immI src)
4776 %{
4777 match(Set dst src);
4778
4779 ins_cost(ALU_COST);
4780 format %{ "mv $dst, $src\t# int, #@loadConI" %}
4781
4782 ins_encode(riscv_enc_mov_imm(dst, src));
4783
4784 ins_pipe(ialu_imm);
4785 %}
4786
4787 // Load Long Constant
4788 instruct loadConL(iRegLNoSp dst, immL src)
4789 %{
4790 match(Set dst src);
4791
4792 ins_cost(ALU_COST);
4793 format %{ "mv $dst, $src\t# long, #@loadConL" %}
4794
4795 ins_encode(riscv_enc_mov_imm(dst, src));
4796
4797 ins_pipe(ialu_imm);
4798 %}
4799
4800 // Load Pointer Constant
4801 instruct loadConP(iRegPNoSp dst, immP con)
4802 %{
4803 match(Set dst con);
4804
4805 ins_cost(ALU_COST);
4806 format %{ "mv $dst, $con\t# ptr, #@loadConP" %}
4807
4808 ins_encode(riscv_enc_mov_p(dst, con));
4809
4810 ins_pipe(ialu_imm);
4811 %}
4812
4813 // Load Null Pointer Constant
4814 instruct loadConP0(iRegPNoSp dst, immP0 con)
4815 %{
4816 match(Set dst con);
4817
4818 ins_cost(ALU_COST);
4819 format %{ "mv $dst, $con\t# null pointer, #@loadConP0" %}
4820
4821 ins_encode(riscv_enc_mov_zero(dst));
4822
4823 ins_pipe(ialu_imm);
4824 %}
4825
4826 // Load Pointer Constant One
4827 instruct loadConP1(iRegPNoSp dst, immP_1 con)
4828 %{
4829 match(Set dst con);
4830
4831 ins_cost(ALU_COST);
4832 format %{ "mv $dst, $con\t# load ptr constant one, #@loadConP1" %}
4833
4834 ins_encode(riscv_enc_mov_p1(dst));
4835
4836 ins_pipe(ialu_imm);
4837 %}
4838
4839 // Load Byte Map Base Constant
4840 instruct loadByteMapBase(iRegPNoSp dst, immByteMapBase con)
4841 %{
4842 match(Set dst con);
4843 ins_cost(ALU_COST);
4844 format %{ "mv $dst, $con\t# Byte Map Base, #@loadByteMapBase" %}
4845
4846 ins_encode(riscv_enc_mov_byte_map_base(dst));
4847
4848 ins_pipe(ialu_imm);
4849 %}
4850
4851 // Load Narrow Pointer Constant
4852 instruct loadConN(iRegNNoSp dst, immN con)
4853 %{
4854 match(Set dst con);
4855
4856 ins_cost(ALU_COST * 4);
4857 format %{ "mv $dst, $con\t# compressed ptr, #@loadConN" %}
4858
4859 ins_encode(riscv_enc_mov_n(dst, con));
4860
4861 ins_pipe(ialu_imm);
4862 %}
4863
4864 // Load Narrow Null Pointer Constant
4865 instruct loadConN0(iRegNNoSp dst, immN0 con)
4866 %{
4867 match(Set dst con);
4868
4869 ins_cost(ALU_COST);
4870 format %{ "mv $dst, $con\t# compressed null pointer, #@loadConN0" %}
4871
4872 ins_encode(riscv_enc_mov_zero(dst));
4873
4874 ins_pipe(ialu_imm);
4875 %}
4876
4877 // Load Narrow Klass Constant
4878 instruct loadConNKlass(iRegNNoSp dst, immNKlass con)
4879 %{
4880 match(Set dst con);
4881
4882 ins_cost(ALU_COST * 6);
4883 format %{ "mv $dst, $con\t# compressed klass ptr, #@loadConNKlass" %}
4884
4885 ins_encode(riscv_enc_mov_nk(dst, con));
4886
4887 ins_pipe(ialu_imm);
4888 %}
4889
4890 // Load Half Float Constant
4891 instruct loadConH(fRegF dst, immH con) %{
4892 match(Set dst con);
4893
4894 ins_cost(LOAD_COST);
4895 format %{
4896 "flh $dst, [$constantaddress]\t# load from constant table: float=$con, #@loadConH"
4897 %}
4898
4899 ins_encode %{
4900 assert(UseZfh || UseZfhmin, "must");
4901 if (MacroAssembler::can_hf_imm_load($con$$constant)) {
4902 __ fli_h(as_FloatRegister($dst$$reg), $con$$constant);
4903 } else {
4904 __ flh(as_FloatRegister($dst$$reg), $constantaddress($con));
4905 }
4906 %}
4907
4908 ins_pipe(fp_load_constant_s);
4909 %}
4910
4911 instruct loadConH0(fRegF dst, immH0 con) %{
4912 match(Set dst con);
4913
4914 ins_cost(XFER_COST);
4915
4916 format %{ "fmv.h.x $dst, zr\t# float, #@loadConH0" %}
4917
4918 ins_encode %{
4919 assert(UseZfh || UseZfhmin, "must");
4920 __ fmv_h_x(as_FloatRegister($dst$$reg), zr);
4921 %}
4922
4923 ins_pipe(fp_load_constant_s);
4924 %}
4925
4926 // Load Float Constant
4927 instruct loadConF(fRegF dst, immF con) %{
4928 match(Set dst con);
4929
4930 ins_cost(LOAD_COST);
4931 format %{
4932 "flw $dst, [$constantaddress]\t# load from constant table: float=$con, #@loadConF"
4933 %}
4934
4935 ins_encode %{
4936 if (MacroAssembler::can_fp_imm_load($con$$constant)) {
4937 __ fli_s(as_FloatRegister($dst$$reg), $con$$constant);
4938 } else {
4939 __ flw(as_FloatRegister($dst$$reg), $constantaddress($con));
4940 }
4941 %}
4942
4943 ins_pipe(fp_load_constant_s);
4944 %}
4945
4946 instruct loadConF0(fRegF dst, immF0 con) %{
4947 match(Set dst con);
4948
4949 ins_cost(XFER_COST);
4950
4951 format %{ "fmv.w.x $dst, zr\t# float, #@loadConF0" %}
4952
4953 ins_encode %{
4954 __ fmv_w_x(as_FloatRegister($dst$$reg), zr);
4955 %}
4956
4957 ins_pipe(fp_load_constant_s);
4958 %}
4959
4960 // Load Double Constant
4961 instruct loadConD(fRegD dst, immD con) %{
4962 match(Set dst con);
4963
4964 ins_cost(LOAD_COST);
4965 format %{
4966 "fld $dst, [$constantaddress]\t# load from constant table: double=$con, #@loadConD"
4967 %}
4968
4969 ins_encode %{
4970 if (MacroAssembler::can_dp_imm_load($con$$constant)) {
4971 __ fli_d(as_FloatRegister($dst$$reg), $con$$constant);
4972 } else {
4973 __ fld(as_FloatRegister($dst$$reg), $constantaddress($con));
4974 }
4975 %}
4976
4977 ins_pipe(fp_load_constant_d);
4978 %}
4979
4980 instruct loadConD0(fRegD dst, immD0 con) %{
4981 match(Set dst con);
4982
4983 ins_cost(XFER_COST);
4984
4985 format %{ "fmv.d.x $dst, zr\t# double, #@loadConD0" %}
4986
4987 ins_encode %{
4988 __ fmv_d_x(as_FloatRegister($dst$$reg), zr);
4989 %}
4990
4991 ins_pipe(fp_load_constant_d);
4992 %}
4993
4994 // Store Byte
4995 instruct storeB(iRegIorL2I src, memory mem)
4996 %{
4997 match(Set mem (StoreB mem src));
4998
4999 ins_cost(STORE_COST);
5000 format %{ "sb $src, $mem\t# byte, #@storeB" %}
5001
5002 ins_encode %{
5003 __ sb(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5004 %}
5005
5006 ins_pipe(istore_reg_mem);
5007 %}
5008
5009 instruct storeimmB0(immI0 zero, memory mem)
5010 %{
5011 match(Set mem (StoreB mem zero));
5012
5013 ins_cost(STORE_COST);
5014 format %{ "sb zr, $mem\t# byte, #@storeimmB0" %}
5015
5016 ins_encode %{
5017 __ sb(zr, Address(as_Register($mem$$base), $mem$$disp));
5018 %}
5019
5020 ins_pipe(istore_mem);
5021 %}
5022
5023 // Store Char/Short
5024 instruct storeC(iRegIorL2I src, memory mem)
5025 %{
5026 match(Set mem (StoreC mem src));
5027
5028 ins_cost(STORE_COST);
5029 format %{ "sh $src, $mem\t# short, #@storeC" %}
5030
5031 ins_encode %{
5032 __ sh(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5033 %}
5034
5035 ins_pipe(istore_reg_mem);
5036 %}
5037
5038 instruct storeimmC0(immI0 zero, memory mem)
5039 %{
5040 match(Set mem (StoreC mem zero));
5041
5042 ins_cost(STORE_COST);
5043 format %{ "sh zr, $mem\t# short, #@storeimmC0" %}
5044
5045 ins_encode %{
5046 __ sh(zr, Address(as_Register($mem$$base), $mem$$disp));
5047 %}
5048
5049 ins_pipe(istore_mem);
5050 %}
5051
5052 // Store Integer
5053 instruct storeI(iRegIorL2I src, memory mem)
5054 %{
5055 match(Set mem(StoreI mem src));
5056
5057 ins_cost(STORE_COST);
5058 format %{ "sw $src, $mem\t# int, #@storeI" %}
5059
5060 ins_encode %{
5061 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5062 %}
5063
5064 ins_pipe(istore_reg_mem);
5065 %}
5066
5067 instruct storeimmI0(immI0 zero, memory mem)
5068 %{
5069 match(Set mem(StoreI mem zero));
5070
5071 ins_cost(STORE_COST);
5072 format %{ "sw zr, $mem\t# int, #@storeimmI0" %}
5073
5074 ins_encode %{
5075 __ sw(zr, Address(as_Register($mem$$base), $mem$$disp));
5076 %}
5077
5078 ins_pipe(istore_mem);
5079 %}
5080
5081 // Store Long (64 bit signed)
5082 instruct storeL(iRegL src, memory mem)
5083 %{
5084 match(Set mem (StoreL mem src));
5085
5086 ins_cost(STORE_COST);
5087 format %{ "sd $src, $mem\t# long, #@storeL" %}
5088
5089 ins_encode %{
5090 __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5091 %}
5092
5093 ins_pipe(istore_reg_mem);
5094 %}
5095
5096 // Store Long (64 bit signed)
5097 instruct storeimmL0(immL0 zero, memory mem)
5098 %{
5099 match(Set mem (StoreL mem zero));
5100
5101 ins_cost(STORE_COST);
5102 format %{ "sd zr, $mem\t# long, #@storeimmL0" %}
5103
5104 ins_encode %{
5105 __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
5106 %}
5107
5108 ins_pipe(istore_mem);
5109 %}
5110
5111 // Store Pointer
5112 instruct storeP(iRegP src, memory mem)
5113 %{
5114 match(Set mem (StoreP mem src));
5115 predicate(n->as_Store()->barrier_data() == 0);
5116
5117 ins_cost(STORE_COST);
5118 format %{ "sd $src, $mem\t# ptr, #@storeP" %}
5119
5120 ins_encode %{
5121 __ sd(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5122 %}
5123
5124 ins_pipe(istore_reg_mem);
5125 %}
5126
5127 // Store Pointer
5128 instruct storeimmP0(immP0 zero, memory mem)
5129 %{
5130 match(Set mem (StoreP mem zero));
5131 predicate(n->as_Store()->barrier_data() == 0);
5132
5133 ins_cost(STORE_COST);
5134 format %{ "sd zr, $mem\t# ptr, #@storeimmP0" %}
5135
5136 ins_encode %{
5137 __ sd(zr, Address(as_Register($mem$$base), $mem$$disp));
5138 %}
5139
5140 ins_pipe(istore_mem);
5141 %}
5142
5143 // Store Compressed Pointer
5144 instruct storeN(iRegN src, memory mem)
5145 %{
5146 predicate(n->as_Store()->barrier_data() == 0);
5147 match(Set mem (StoreN mem src));
5148
5149 ins_cost(STORE_COST);
5150 format %{ "sw $src, $mem\t# compressed ptr, #@storeN" %}
5151
5152 ins_encode %{
5153 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5154 %}
5155
5156 ins_pipe(istore_reg_mem);
5157 %}
5158
5159 instruct storeImmN0(immN0 zero, memory mem)
5160 %{
5161 predicate(n->as_Store()->barrier_data() == 0);
5162 match(Set mem (StoreN mem zero));
5163
5164 ins_cost(STORE_COST);
5165 format %{ "sw zr, $mem\t# compressed ptr, #@storeImmN0" %}
5166
5167 ins_encode %{
5168 __ sw(zr, Address(as_Register($mem$$base), $mem$$disp));
5169 %}
5170
5171 ins_pipe(istore_reg_mem);
5172 %}
5173
5174 // Store Float
5175 instruct storeF(fRegF src, memory mem)
5176 %{
5177 match(Set mem (StoreF mem src));
5178
5179 ins_cost(STORE_COST);
5180 format %{ "fsw $src, $mem\t# float, #@storeF" %}
5181
5182 ins_encode %{
5183 __ fsw(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5184 %}
5185
5186 ins_pipe(fp_store_reg_s);
5187 %}
5188
5189 // Store Double
5190 instruct storeD(fRegD src, memory mem)
5191 %{
5192 match(Set mem (StoreD mem src));
5193
5194 ins_cost(STORE_COST);
5195 format %{ "fsd $src, $mem\t# double, #@storeD" %}
5196
5197 ins_encode %{
5198 __ fsd(as_FloatRegister($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5199 %}
5200
5201 ins_pipe(fp_store_reg_d);
5202 %}
5203
5204 // Store Compressed Klass Pointer
5205 instruct storeNKlass(iRegN src, memory mem)
5206 %{
5207 match(Set mem (StoreNKlass mem src));
5208
5209 ins_cost(STORE_COST);
5210 format %{ "sw $src, $mem\t# compressed klass ptr, #@storeNKlass" %}
5211
5212 ins_encode %{
5213 __ sw(as_Register($src$$reg), Address(as_Register($mem$$base), $mem$$disp));
5214 %}
5215
5216 ins_pipe(istore_reg_mem);
5217 %}
5218
5219 // ============================================================================
5220 // Prefetch instructions
5221 // Must be safe to execute with invalid address (cannot fault).
5222
5223 instruct prefetchalloc( memory mem ) %{
5224 predicate(UseZicbop);
5225 match(PrefetchAllocation mem);
5226
5227 ins_cost(ALU_COST * 1);
5228 format %{ "prefetch_w $mem\t# Prefetch for write" %}
5229
5230 ins_encode %{
5231 if (Assembler::is_simm12($mem$$disp)) {
5232 if (($mem$$disp & 0x1f) == 0) {
5233 __ prefetch_w(as_Register($mem$$base), $mem$$disp);
5234 } else {
5235 __ addi(t0, as_Register($mem$$base), $mem$$disp);
5236 __ prefetch_w(t0, 0);
5237 }
5238 } else {
5239 __ mv(t0, $mem$$disp);
5240 __ add(t0, as_Register($mem$$base), t0);
5241 __ prefetch_w(t0, 0);
5242 }
5243 %}
5244
5245 ins_pipe(iload_prefetch);
5246 %}
5247
5248 // ============================================================================
5249 // Atomic operation instructions
5250 //
5251
5252 // standard CompareAndSwapX when we are using barriers
5253 // these have higher priority than the rules selected by a predicate
5254 instruct compareAndSwapB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5255 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5256 %{
5257 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5258
5259 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 10 + BRANCH_COST * 4);
5260
5261 effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
5262
5263 format %{
5264 "cmpxchg $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5265 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapB"
5266 %}
5267
5268 ins_encode %{
5269 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5270 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5271 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5272 %}
5273
5274 ins_pipe(pipe_slow);
5275 %}
5276
5277 instruct compareAndSwapS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5278 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5279 %{
5280 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5281
5282 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 11 + BRANCH_COST * 4);
5283
5284 effect(TEMP_DEF res, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
5285
5286 format %{
5287 "cmpxchg $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5288 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapS"
5289 %}
5290
5291 ins_encode %{
5292 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5293 Assembler::relaxed /* acquire */, Assembler::rl /* release */, $res$$Register,
5294 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5295 %}
5296
5297 ins_pipe(pipe_slow);
5298 %}
5299
5300 instruct compareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5301 %{
5302 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
5303
5304 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5305
5306 format %{
5307 "cmpxchg $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
5308 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapI"
5309 %}
5310
5311 ins_encode(riscv_enc_cmpxchgw(res, mem, oldval, newval));
5312
5313 ins_pipe(pipe_slow);
5314 %}
5315
5316 instruct compareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5317 %{
5318 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
5319
5320 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5321
5322 format %{
5323 "cmpxchg $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
5324 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapL"
5325 %}
5326
5327 ins_encode(riscv_enc_cmpxchg(res, mem, oldval, newval));
5328
5329 ins_pipe(pipe_slow);
5330 %}
5331
5332 instruct compareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5333 %{
5334 predicate(n->as_LoadStore()->barrier_data() == 0);
5335
5336 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
5337
5338 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5339
5340 format %{
5341 "cmpxchg $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
5342 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapP"
5343 %}
5344
5345 ins_encode(riscv_enc_cmpxchg(res, mem, oldval, newval));
5346
5347 ins_pipe(pipe_slow);
5348 %}
5349
5350 instruct compareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5351 %{
5352 predicate(n->as_LoadStore()->barrier_data() == 0);
5353 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
5354
5355 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 8 + BRANCH_COST * 4);
5356
5357 format %{
5358 "cmpxchg $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
5359 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapN"
5360 %}
5361
5362 ins_encode(riscv_enc_cmpxchgn(res, mem, oldval, newval));
5363
5364 ins_pipe(pipe_slow);
5365 %}
5366
5367 // alternative CompareAndSwapX when we are eliding barriers
5368 instruct compareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5369 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5370 %{
5371 predicate(needs_acquiring_load_reserved(n));
5372
5373 match(Set res (CompareAndSwapB mem (Binary oldval newval)));
5374
5375 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 10 + BRANCH_COST * 4);
5376
5377 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5378
5379 format %{
5380 "cmpxchg_acq $mem, $oldval, $newval\t# (byte) if $mem == $oldval then $mem <-- $newval\n\t"
5381 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapBAcq"
5382 %}
5383
5384 ins_encode %{
5385 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5386 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5387 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5388 %}
5389
5390 ins_pipe(pipe_slow);
5391 %}
5392
5393 instruct compareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5394 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5395 %{
5396 predicate(needs_acquiring_load_reserved(n));
5397
5398 match(Set res (CompareAndSwapS mem (Binary oldval newval)));
5399
5400 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 11 + BRANCH_COST * 4);
5401
5402 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5403
5404 format %{
5405 "cmpxchg_acq $mem, $oldval, $newval\t# (short) if $mem == $oldval then $mem <-- $newval\n\t"
5406 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapSAcq"
5407 %}
5408
5409 ins_encode %{
5410 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5411 Assembler::aq /* acquire */, Assembler::rl /* release */, $res$$Register,
5412 true /* result as bool */, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5413 %}
5414
5415 ins_pipe(pipe_slow);
5416 %}
5417
5418 instruct compareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5419 %{
5420 predicate(needs_acquiring_load_reserved(n));
5421
5422 match(Set res (CompareAndSwapI mem (Binary oldval newval)));
5423
5424 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5425
5426 format %{
5427 "cmpxchg_acq $mem, $oldval, $newval\t# (int) if $mem == $oldval then $mem <-- $newval\n\t"
5428 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapIAcq"
5429 %}
5430
5431 ins_encode(riscv_enc_cmpxchgw_acq(res, mem, oldval, newval));
5432
5433 ins_pipe(pipe_slow);
5434 %}
5435
5436 instruct compareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5437 %{
5438 predicate(needs_acquiring_load_reserved(n));
5439
5440 match(Set res (CompareAndSwapL mem (Binary oldval newval)));
5441
5442 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5443
5444 format %{
5445 "cmpxchg_acq $mem, $oldval, $newval\t# (long) if $mem == $oldval then $mem <-- $newval\n\t"
5446 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapLAcq"
5447 %}
5448
5449 ins_encode(riscv_enc_cmpxchg_acq(res, mem, oldval, newval));
5450
5451 ins_pipe(pipe_slow);
5452 %}
5453
5454 instruct compareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5455 %{
5456 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5457
5458 match(Set res (CompareAndSwapP mem (Binary oldval newval)));
5459
5460 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 6 + BRANCH_COST * 4);
5461
5462 format %{
5463 "cmpxchg_acq $mem, $oldval, $newval\t# (ptr) if $mem == $oldval then $mem <-- $newval\n\t"
5464 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapPAcq"
5465 %}
5466
5467 ins_encode(riscv_enc_cmpxchg_acq(res, mem, oldval, newval));
5468
5469 ins_pipe(pipe_slow);
5470 %}
5471
5472 instruct compareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5473 %{
5474 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
5475
5476 match(Set res (CompareAndSwapN mem (Binary oldval newval)));
5477
5478 ins_cost(LOAD_COST + STORE_COST + ALU_COST * 8 + BRANCH_COST * 4);
5479
5480 format %{
5481 "cmpxchg_acq $mem, $oldval, $newval\t# (narrow oop) if $mem == $oldval then $mem <-- $newval\n\t"
5482 "mv $res, $res == $oldval\t# $res <-- ($res == $oldval ? 1 : 0), #@compareAndSwapNAcq"
5483 %}
5484
5485 ins_encode(riscv_enc_cmpxchgn_acq(res, mem, oldval, newval));
5486
5487 ins_pipe(pipe_slow);
5488 %}
5489
5490 // Sundry CAS operations. Note that release is always true,
5491 // regardless of the memory ordering of the CAS. This is because we
5492 // need the volatile case to be sequentially consistent but there is
5493 // no trailing StoreLoad barrier emitted by C2. Unfortunately we
5494 // can't check the type of memory ordering here, so we always emit a
5495 // sc_d(w) with rl bit set.
5496 instruct compareAndExchangeB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5497 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5498 %{
5499 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5500
5501 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 5);
5502
5503 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5504
5505 format %{
5506 "cmpxchg $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeB"
5507 %}
5508
5509 ins_encode %{
5510 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5511 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5512 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5513 %}
5514
5515 ins_pipe(pipe_slow);
5516 %}
5517
5518 instruct compareAndExchangeS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5519 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5520 %{
5521 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5522
5523 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 6);
5524
5525 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5526
5527 format %{
5528 "cmpxchg $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeS"
5529 %}
5530
5531 ins_encode %{
5532 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5533 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5534 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5535 %}
5536
5537 ins_pipe(pipe_slow);
5538 %}
5539
5540 instruct compareAndExchangeI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5541 %{
5542 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
5543
5544 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5545
5546 effect(TEMP_DEF res);
5547
5548 format %{
5549 "cmpxchg $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeI"
5550 %}
5551
5552 ins_encode %{
5553 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5554 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5555 %}
5556
5557 ins_pipe(pipe_slow);
5558 %}
5559
5560 instruct compareAndExchangeL(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
5561 %{
5562 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
5563
5564 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5565
5566 effect(TEMP_DEF res);
5567
5568 format %{
5569 "cmpxchg $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeL"
5570 %}
5571
5572 ins_encode %{
5573 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5574 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5575 %}
5576
5577 ins_pipe(pipe_slow);
5578 %}
5579
5580 instruct compareAndExchangeN(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
5581 %{
5582 predicate(n->as_LoadStore()->barrier_data() == 0);
5583 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
5584
5585 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 3);
5586
5587 effect(TEMP_DEF res);
5588
5589 format %{
5590 "cmpxchg $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeN"
5591 %}
5592
5593 ins_encode %{
5594 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5595 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5596 %}
5597
5598 ins_pipe(pipe_slow);
5599 %}
5600
5601 instruct compareAndExchangeP(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
5602 %{
5603 predicate(n->as_LoadStore()->barrier_data() == 0);
5604 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
5605
5606 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5607
5608 effect(TEMP_DEF res);
5609
5610 format %{
5611 "cmpxchg $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeP"
5612 %}
5613
5614 ins_encode %{
5615 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5616 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5617 %}
5618
5619 ins_pipe(pipe_slow);
5620 %}
5621
5622 instruct compareAndExchangeBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5623 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5624 %{
5625 predicate(needs_acquiring_load_reserved(n));
5626
5627 match(Set res (CompareAndExchangeB mem (Binary oldval newval)));
5628
5629 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 5);
5630
5631 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5632
5633 format %{
5634 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeBAcq"
5635 %}
5636
5637 ins_encode %{
5638 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5639 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5640 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5641 %}
5642
5643 ins_pipe(pipe_slow);
5644 %}
5645
5646 instruct compareAndExchangeSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5647 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5648 %{
5649 predicate(needs_acquiring_load_reserved(n));
5650
5651 match(Set res (CompareAndExchangeS mem (Binary oldval newval)));
5652
5653 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST * 6);
5654
5655 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5656
5657 format %{
5658 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeSAcq"
5659 %}
5660
5661 ins_encode %{
5662 __ cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5663 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5664 /*result_as_bool*/ false, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5665 %}
5666
5667 ins_pipe(pipe_slow);
5668 %}
5669
5670 instruct compareAndExchangeIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5671 %{
5672 predicate(needs_acquiring_load_reserved(n));
5673
5674 match(Set res (CompareAndExchangeI mem (Binary oldval newval)));
5675
5676 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5677
5678 effect(TEMP_DEF res);
5679
5680 format %{
5681 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeIAcq"
5682 %}
5683
5684 ins_encode %{
5685 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5686 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5687 %}
5688
5689 ins_pipe(pipe_slow);
5690 %}
5691
5692 instruct compareAndExchangeLAcq(iRegLNoSp res, indirect mem, iRegL oldval, iRegL newval)
5693 %{
5694 predicate(needs_acquiring_load_reserved(n));
5695
5696 match(Set res (CompareAndExchangeL mem (Binary oldval newval)));
5697
5698 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5699
5700 effect(TEMP_DEF res);
5701
5702 format %{
5703 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeLAcq"
5704 %}
5705
5706 ins_encode %{
5707 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5708 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5709 %}
5710
5711 ins_pipe(pipe_slow);
5712 %}
5713
5714 instruct compareAndExchangeNAcq(iRegNNoSp res, indirect mem, iRegN oldval, iRegN newval)
5715 %{
5716 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
5717
5718 match(Set res (CompareAndExchangeN mem (Binary oldval newval)));
5719
5720 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5721
5722 effect(TEMP_DEF res);
5723
5724 format %{
5725 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangeNAcq"
5726 %}
5727
5728 ins_encode %{
5729 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5730 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5731 %}
5732
5733 ins_pipe(pipe_slow);
5734 %}
5735
5736 instruct compareAndExchangePAcq(iRegPNoSp res, indirect mem, iRegP oldval, iRegP newval)
5737 %{
5738 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5739
5740 match(Set res (CompareAndExchangeP mem (Binary oldval newval)));
5741
5742 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 3 + ALU_COST);
5743
5744 effect(TEMP_DEF res);
5745
5746 format %{
5747 "cmpxchg_acq $res = $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval, #@compareAndExchangePAcq"
5748 %}
5749
5750 ins_encode %{
5751 __ cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5752 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5753 %}
5754
5755 ins_pipe(pipe_slow);
5756 %}
5757
5758 instruct weakCompareAndSwapB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5759 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5760 %{
5761 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
5762
5763 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 6);
5764
5765 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5766
5767 format %{
5768 "weak_cmpxchg $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5769 "# $res == 1 when success, #@weakCompareAndSwapB"
5770 %}
5771
5772 ins_encode %{
5773 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5774 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5775 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5776 %}
5777
5778 ins_pipe(pipe_slow);
5779 %}
5780
5781 instruct weakCompareAndSwapS(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5782 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5783 %{
5784 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
5785
5786 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 7);
5787
5788 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5789
5790 format %{
5791 "weak_cmpxchg $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5792 "# $res == 1 when success, #@weakCompareAndSwapS"
5793 %}
5794
5795 ins_encode %{
5796 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5797 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register,
5798 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5799 %}
5800
5801 ins_pipe(pipe_slow);
5802 %}
5803
5804 instruct weakCompareAndSwapI(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5805 %{
5806 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
5807
5808 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5809
5810 format %{
5811 "weak_cmpxchg $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5812 "# $res == 1 when success, #@weakCompareAndSwapI"
5813 %}
5814
5815 ins_encode %{
5816 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5817 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5818 %}
5819
5820 ins_pipe(pipe_slow);
5821 %}
5822
5823 instruct weakCompareAndSwapL(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5824 %{
5825 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
5826
5827 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5828
5829 format %{
5830 "weak_cmpxchg $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5831 "# $res == 1 when success, #@weakCompareAndSwapL"
5832 %}
5833
5834 ins_encode %{
5835 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5836 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5837 %}
5838
5839 ins_pipe(pipe_slow);
5840 %}
5841
5842 instruct weakCompareAndSwapN(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5843 %{
5844 predicate(n->as_LoadStore()->barrier_data() == 0);
5845 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
5846
5847 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 4);
5848
5849 format %{
5850 "weak_cmpxchg $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5851 "# $res == 1 when success, #@weakCompareAndSwapN"
5852 %}
5853
5854 ins_encode %{
5855 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5856 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5857 %}
5858
5859 ins_pipe(pipe_slow);
5860 %}
5861
5862 instruct weakCompareAndSwapP(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5863 %{
5864 predicate(n->as_LoadStore()->barrier_data() == 0);
5865 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
5866
5867 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5868
5869 format %{
5870 "weak_cmpxchg $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5871 "# $res == 1 when success, #@weakCompareAndSwapP"
5872 %}
5873
5874 ins_encode %{
5875 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5876 /*acquire*/ Assembler::relaxed, /*release*/ Assembler::rl, $res$$Register);
5877 %}
5878
5879 ins_pipe(pipe_slow);
5880 %}
5881
5882 instruct weakCompareAndSwapBAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5883 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5884 %{
5885 predicate(needs_acquiring_load_reserved(n));
5886
5887 match(Set res (WeakCompareAndSwapB mem (Binary oldval newval)));
5888
5889 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 6);
5890
5891 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5892
5893 format %{
5894 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (byte, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5895 "# $res == 1 when success, #@weakCompareAndSwapBAcq"
5896 %}
5897
5898 ins_encode %{
5899 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int8,
5900 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5901 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5902 %}
5903
5904 ins_pipe(pipe_slow);
5905 %}
5906
5907 instruct weakCompareAndSwapSAcq(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval,
5908 iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3, rFlagsReg cr)
5909 %{
5910 predicate(needs_acquiring_load_reserved(n));
5911
5912 match(Set res (WeakCompareAndSwapS mem (Binary oldval newval)));
5913
5914 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 7);
5915
5916 effect(TEMP_DEF res, KILL cr, USE_KILL oldval, USE_KILL newval, TEMP tmp1, TEMP tmp2, TEMP tmp3);
5917
5918 format %{
5919 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (short, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5920 "# $res == 1 when success, #@weakCompareAndSwapSAcq"
5921 %}
5922
5923 ins_encode %{
5924 __ weak_cmpxchg_narrow_value(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int16,
5925 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register,
5926 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
5927 %}
5928
5929 ins_pipe(pipe_slow);
5930 %}
5931
5932 instruct weakCompareAndSwapIAcq(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
5933 %{
5934 predicate(needs_acquiring_load_reserved(n));
5935
5936 match(Set res (WeakCompareAndSwapI mem (Binary oldval newval)));
5937
5938 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5939
5940 format %{
5941 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (int, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5942 "# $res == 1 when success, #@weakCompareAndSwapIAcq"
5943 %}
5944
5945 ins_encode %{
5946 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int32,
5947 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5948 %}
5949
5950 ins_pipe(pipe_slow);
5951 %}
5952
5953 instruct weakCompareAndSwapLAcq(iRegINoSp res, indirect mem, iRegL oldval, iRegL newval)
5954 %{
5955 predicate(needs_acquiring_load_reserved(n));
5956
5957 match(Set res (WeakCompareAndSwapL mem (Binary oldval newval)));
5958
5959 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
5960
5961 format %{
5962 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (long, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5963 "# $res == 1 when success, #@weakCompareAndSwapLAcq"
5964 %}
5965
5966 ins_encode %{
5967 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
5968 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5969 %}
5970
5971 ins_pipe(pipe_slow);
5972 %}
5973
5974 instruct weakCompareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN oldval, iRegN newval)
5975 %{
5976 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
5977
5978 match(Set res (WeakCompareAndSwapN mem (Binary oldval newval)));
5979
5980 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 4);
5981
5982 format %{
5983 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (narrow oop, weak) if $mem == $oldval then $mem <-- $newval\n\t"
5984 "# $res == 1 when success, #@weakCompareAndSwapNAcq"
5985 %}
5986
5987 ins_encode %{
5988 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::uint32,
5989 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
5990 %}
5991
5992 ins_pipe(pipe_slow);
5993 %}
5994
5995 instruct weakCompareAndSwapPAcq(iRegINoSp res, indirect mem, iRegP oldval, iRegP newval)
5996 %{
5997 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
5998
5999 match(Set res (WeakCompareAndSwapP mem (Binary oldval newval)));
6000
6001 ins_cost(LOAD_COST + STORE_COST + BRANCH_COST * 2 + ALU_COST * 2);
6002
6003 format %{
6004 "weak_cmpxchg_acq $mem, $oldval, $newval\t# (ptr, weak) if $mem == $oldval then $mem <-- $newval\n\t"
6005 "\t# $res == 1 when success, #@weakCompareAndSwapPAcq"
6006 %}
6007
6008 ins_encode %{
6009 __ weak_cmpxchg(as_Register($mem$$base), $oldval$$Register, $newval$$Register, Assembler::int64,
6010 /*acquire*/ Assembler::aq, /*release*/ Assembler::rl, $res$$Register);
6011 %}
6012
6013 ins_pipe(pipe_slow);
6014 %}
6015
6016 instruct get_and_setI(indirect mem, iRegI newv, iRegINoSp prev)
6017 %{
6018 match(Set prev (GetAndSetI mem newv));
6019
6020 ins_cost(ALU_COST);
6021
6022 format %{ "atomic_xchgw $prev, $newv, [$mem]\t#@get_and_setI" %}
6023
6024 ins_encode %{
6025 __ atomic_xchgw($prev$$Register, $newv$$Register, as_Register($mem$$base));
6026 %}
6027
6028 ins_pipe(pipe_serial);
6029 %}
6030
6031 instruct get_and_setL(indirect mem, iRegL newv, iRegLNoSp prev)
6032 %{
6033 match(Set prev (GetAndSetL mem newv));
6034
6035 ins_cost(ALU_COST);
6036
6037 format %{ "atomic_xchg $prev, $newv, [$mem]\t#@get_and_setL" %}
6038
6039 ins_encode %{
6040 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
6041 %}
6042
6043 ins_pipe(pipe_serial);
6044 %}
6045
6046 instruct get_and_setN(indirect mem, iRegN newv, iRegINoSp prev)
6047 %{
6048 predicate(n->as_LoadStore()->barrier_data() == 0);
6049
6050 match(Set prev (GetAndSetN mem newv));
6051
6052 ins_cost(ALU_COST);
6053
6054 format %{ "atomic_xchgwu $prev, $newv, [$mem]\t#@get_and_setN" %}
6055
6056 ins_encode %{
6057 __ atomic_xchgwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
6058 %}
6059
6060 ins_pipe(pipe_serial);
6061 %}
6062
6063 instruct get_and_setP(indirect mem, iRegP newv, iRegPNoSp prev)
6064 %{
6065 predicate(n->as_LoadStore()->barrier_data() == 0);
6066 match(Set prev (GetAndSetP mem newv));
6067
6068 ins_cost(ALU_COST);
6069
6070 format %{ "atomic_xchg $prev, $newv, [$mem]\t#@get_and_setP" %}
6071
6072 ins_encode %{
6073 __ atomic_xchg($prev$$Register, $newv$$Register, as_Register($mem$$base));
6074 %}
6075
6076 ins_pipe(pipe_serial);
6077 %}
6078
6079 instruct get_and_setIAcq(indirect mem, iRegI newv, iRegINoSp prev)
6080 %{
6081 predicate(needs_acquiring_load_reserved(n));
6082
6083 match(Set prev (GetAndSetI mem newv));
6084
6085 ins_cost(ALU_COST);
6086
6087 format %{ "atomic_xchgw_acq $prev, $newv, [$mem]\t#@get_and_setIAcq" %}
6088
6089 ins_encode %{
6090 __ atomic_xchgalw($prev$$Register, $newv$$Register, as_Register($mem$$base));
6091 %}
6092
6093 ins_pipe(pipe_serial);
6094 %}
6095
6096 instruct get_and_setLAcq(indirect mem, iRegL newv, iRegLNoSp prev)
6097 %{
6098 predicate(needs_acquiring_load_reserved(n));
6099
6100 match(Set prev (GetAndSetL mem newv));
6101
6102 ins_cost(ALU_COST);
6103
6104 format %{ "atomic_xchg_acq $prev, $newv, [$mem]\t#@get_and_setLAcq" %}
6105
6106 ins_encode %{
6107 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
6108 %}
6109
6110 ins_pipe(pipe_serial);
6111 %}
6112
6113 instruct get_and_setNAcq(indirect mem, iRegN newv, iRegINoSp prev)
6114 %{
6115 predicate(needs_acquiring_load_reserved(n) && n->as_LoadStore()->barrier_data() == 0);
6116
6117 match(Set prev (GetAndSetN mem newv));
6118
6119 ins_cost(ALU_COST);
6120
6121 format %{ "atomic_xchgwu_acq $prev, $newv, [$mem]\t#@get_and_setNAcq" %}
6122
6123 ins_encode %{
6124 __ atomic_xchgalwu($prev$$Register, $newv$$Register, as_Register($mem$$base));
6125 %}
6126
6127 ins_pipe(pipe_serial);
6128 %}
6129
6130 instruct get_and_setPAcq(indirect mem, iRegP newv, iRegPNoSp prev)
6131 %{
6132 predicate(needs_acquiring_load_reserved(n) && (n->as_LoadStore()->barrier_data() == 0));
6133
6134 match(Set prev (GetAndSetP mem newv));
6135
6136 ins_cost(ALU_COST);
6137
6138 format %{ "atomic_xchg_acq $prev, $newv, [$mem]\t#@get_and_setPAcq" %}
6139
6140 ins_encode %{
6141 __ atomic_xchgal($prev$$Register, $newv$$Register, as_Register($mem$$base));
6142 %}
6143
6144 ins_pipe(pipe_serial);
6145 %}
6146
6147 instruct get_and_addL(indirect mem, iRegLNoSp newval, iRegL incr)
6148 %{
6149 match(Set newval (GetAndAddL mem incr));
6150
6151 ins_cost(ALU_COST);
6152
6153 format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addL" %}
6154
6155 ins_encode %{
6156 __ atomic_add($newval$$Register, $incr$$Register, as_Register($mem$$base));
6157 %}
6158
6159 ins_pipe(pipe_serial);
6160 %}
6161
6162 instruct get_and_addL_no_res(indirect mem, Universe dummy, iRegL incr)
6163 %{
6164 predicate(n->as_LoadStore()->result_not_used());
6165
6166 match(Set dummy (GetAndAddL mem incr));
6167
6168 ins_cost(ALU_COST);
6169
6170 format %{ "get_and_addL [$mem], $incr\t#@get_and_addL_no_res" %}
6171
6172 ins_encode %{
6173 __ atomic_add(noreg, $incr$$Register, as_Register($mem$$base));
6174 %}
6175
6176 ins_pipe(pipe_serial);
6177 %}
6178
6179 instruct get_and_addLi(indirect mem, iRegLNoSp newval, immLAdd incr)
6180 %{
6181 match(Set newval (GetAndAddL mem incr));
6182
6183 ins_cost(ALU_COST);
6184
6185 format %{ "get_and_addL $newval, [$mem], $incr\t#@get_and_addLi" %}
6186
6187 ins_encode %{
6188 __ atomic_add($newval$$Register, $incr$$constant, as_Register($mem$$base));
6189 %}
6190
6191 ins_pipe(pipe_serial);
6192 %}
6193
6194 instruct get_and_addLi_no_res(indirect mem, Universe dummy, immLAdd incr)
6195 %{
6196 predicate(n->as_LoadStore()->result_not_used());
6197
6198 match(Set dummy (GetAndAddL mem incr));
6199
6200 ins_cost(ALU_COST);
6201
6202 format %{ "get_and_addL [$mem], $incr\t#@get_and_addLi_no_res" %}
6203
6204 ins_encode %{
6205 __ atomic_add(noreg, $incr$$constant, as_Register($mem$$base));
6206 %}
6207
6208 ins_pipe(pipe_serial);
6209 %}
6210
6211 instruct get_and_addI(indirect mem, iRegINoSp newval, iRegIorL2I incr)
6212 %{
6213 match(Set newval (GetAndAddI mem incr));
6214
6215 ins_cost(ALU_COST);
6216
6217 format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addI" %}
6218
6219 ins_encode %{
6220 __ atomic_addw($newval$$Register, $incr$$Register, as_Register($mem$$base));
6221 %}
6222
6223 ins_pipe(pipe_serial);
6224 %}
6225
6226 instruct get_and_addI_no_res(indirect mem, Universe dummy, iRegIorL2I incr)
6227 %{
6228 predicate(n->as_LoadStore()->result_not_used());
6229
6230 match(Set dummy (GetAndAddI mem incr));
6231
6232 ins_cost(ALU_COST);
6233
6234 format %{ "get_and_addI [$mem], $incr\t#@get_and_addI_no_res" %}
6235
6236 ins_encode %{
6237 __ atomic_addw(noreg, $incr$$Register, as_Register($mem$$base));
6238 %}
6239
6240 ins_pipe(pipe_serial);
6241 %}
6242
6243 instruct get_and_addIi(indirect mem, iRegINoSp newval, immIAdd incr)
6244 %{
6245 match(Set newval (GetAndAddI mem incr));
6246
6247 ins_cost(ALU_COST);
6248
6249 format %{ "get_and_addI $newval, [$mem], $incr\t#@get_and_addIi" %}
6250
6251 ins_encode %{
6252 __ atomic_addw($newval$$Register, $incr$$constant, as_Register($mem$$base));
6253 %}
6254
6255 ins_pipe(pipe_serial);
6256 %}
6257
6258 instruct get_and_addIi_no_res(indirect mem, Universe dummy, immIAdd incr)
6259 %{
6260 predicate(n->as_LoadStore()->result_not_used());
6261
6262 match(Set dummy (GetAndAddI mem incr));
6263
6264 ins_cost(ALU_COST);
6265
6266 format %{ "get_and_addI [$mem], $incr\t#@get_and_addIi_no_res" %}
6267
6268 ins_encode %{
6269 __ atomic_addw(noreg, $incr$$constant, as_Register($mem$$base));
6270 %}
6271
6272 ins_pipe(pipe_serial);
6273 %}
6274
6275 instruct get_and_addLAcq(indirect mem, iRegLNoSp newval, iRegL incr)
6276 %{
6277 predicate(needs_acquiring_load_reserved(n));
6278
6279 match(Set newval (GetAndAddL mem incr));
6280
6281 ins_cost(ALU_COST);
6282
6283 format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLAcq" %}
6284
6285 ins_encode %{
6286 __ atomic_addal($newval$$Register, $incr$$Register, as_Register($mem$$base));
6287 %}
6288
6289 ins_pipe(pipe_serial);
6290 %}
6291
6292 instruct get_and_addL_no_resAcq(indirect mem, Universe dummy, iRegL incr) %{
6293 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6294
6295 match(Set dummy (GetAndAddL mem incr));
6296
6297 ins_cost(ALU_COST);
6298
6299 format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addL_no_resAcq" %}
6300
6301 ins_encode %{
6302 __ atomic_addal(noreg, $incr$$Register, as_Register($mem$$base));
6303 %}
6304
6305 ins_pipe(pipe_serial);
6306 %}
6307
6308 instruct get_and_addLiAcq(indirect mem, iRegLNoSp newval, immLAdd incr)
6309 %{
6310 predicate(needs_acquiring_load_reserved(n));
6311
6312 match(Set newval (GetAndAddL mem incr));
6313
6314 ins_cost(ALU_COST);
6315
6316 format %{ "get_and_addL_acq $newval, [$mem], $incr\t#@get_and_addLiAcq" %}
6317
6318 ins_encode %{
6319 __ atomic_addal($newval$$Register, $incr$$constant, as_Register($mem$$base));
6320 %}
6321
6322 ins_pipe(pipe_serial);
6323 %}
6324
6325 instruct get_and_addLi_no_resAcq(indirect mem, Universe dummy, immLAdd incr)
6326 %{
6327 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6328
6329 match(Set dummy (GetAndAddL mem incr));
6330
6331 ins_cost(ALU_COST);
6332
6333 format %{ "get_and_addL_acq [$mem], $incr\t#@get_and_addLi_no_resAcq" %}
6334
6335 ins_encode %{
6336 __ atomic_addal(noreg, $incr$$constant, as_Register($mem$$base));
6337 %}
6338
6339 ins_pipe(pipe_serial);
6340 %}
6341
6342 instruct get_and_addIAcq(indirect mem, iRegINoSp newval, iRegIorL2I incr)
6343 %{
6344 predicate(needs_acquiring_load_reserved(n));
6345
6346 match(Set newval (GetAndAddI mem incr));
6347
6348 ins_cost(ALU_COST);
6349
6350 format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIAcq" %}
6351
6352 ins_encode %{
6353 __ atomic_addalw($newval$$Register, $incr$$Register, as_Register($mem$$base));
6354 %}
6355
6356 ins_pipe(pipe_serial);
6357 %}
6358
6359 instruct get_and_addI_no_resAcq(indirect mem, Universe dummy, iRegIorL2I incr)
6360 %{
6361 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6362
6363 match(Set dummy (GetAndAddI mem incr));
6364
6365 ins_cost(ALU_COST);
6366
6367 format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addI_no_resAcq" %}
6368
6369 ins_encode %{
6370 __ atomic_addalw(noreg, $incr$$Register, as_Register($mem$$base));
6371 %}
6372
6373 ins_pipe(pipe_serial);
6374 %}
6375
6376 instruct get_and_addIiAcq(indirect mem, iRegINoSp newval, immIAdd incr)
6377 %{
6378 predicate(needs_acquiring_load_reserved(n));
6379
6380 match(Set newval (GetAndAddI mem incr));
6381
6382 ins_cost(ALU_COST);
6383
6384 format %{ "get_and_addI_acq $newval, [$mem], $incr\t#@get_and_addIiAcq" %}
6385
6386 ins_encode %{
6387 __ atomic_addalw($newval$$Register, $incr$$constant, as_Register($mem$$base));
6388 %}
6389
6390 ins_pipe(pipe_serial);
6391 %}
6392
6393 instruct get_and_addIi_no_resAcq(indirect mem, Universe dummy, immIAdd incr)
6394 %{
6395 predicate(n->as_LoadStore()->result_not_used() && needs_acquiring_load_reserved(n));
6396
6397 match(Set dummy (GetAndAddI mem incr));
6398
6399 ins_cost(ALU_COST);
6400
6401 format %{ "get_and_addI_acq [$mem], $incr\t#@get_and_addIi_no_resAcq" %}
6402
6403 ins_encode %{
6404 __ atomic_addalw(noreg, $incr$$constant, as_Register($mem$$base));
6405 %}
6406
6407 ins_pipe(pipe_serial);
6408 %}
6409
6410 // ============================================================================
6411 // Arithmetic Instructions
6412 //
6413
6414 // Integer Addition
6415
6416 // TODO
6417 // these currently employ operations which do not set CR and hence are
6418 // not flagged as killing CR but we would like to isolate the cases
6419 // where we want to set flags from those where we don't. need to work
6420 // out how to do that.
6421 instruct addI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6422 match(Set dst (AddI src1 src2));
6423
6424 ins_cost(ALU_COST);
6425 format %{ "addw $dst, $src1, $src2\t#@addI_reg_reg" %}
6426
6427 ins_encode %{
6428 __ addw(as_Register($dst$$reg),
6429 as_Register($src1$$reg),
6430 as_Register($src2$$reg));
6431 %}
6432
6433 ins_pipe(ialu_reg_reg);
6434 %}
6435
6436 instruct addI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAdd src2) %{
6437 match(Set dst (AddI src1 src2));
6438
6439 ins_cost(ALU_COST);
6440 format %{ "addiw $dst, $src1, $src2\t#@addI_reg_imm" %}
6441
6442 ins_encode %{
6443 int32_t con = (int32_t)$src2$$constant;
6444 __ addiw(as_Register($dst$$reg),
6445 as_Register($src1$$reg),
6446 $src2$$constant);
6447 %}
6448
6449 ins_pipe(ialu_reg_imm);
6450 %}
6451
6452 instruct addI_reg_imm_l2i(iRegINoSp dst, iRegL src1, immIAdd src2) %{
6453 match(Set dst (AddI (ConvL2I src1) src2));
6454
6455 ins_cost(ALU_COST);
6456 format %{ "addiw $dst, $src1, $src2\t#@addI_reg_imm_l2i" %}
6457
6458 ins_encode %{
6459 __ addiw(as_Register($dst$$reg),
6460 as_Register($src1$$reg),
6461 $src2$$constant);
6462 %}
6463
6464 ins_pipe(ialu_reg_imm);
6465 %}
6466
6467 // Pointer Addition
6468 instruct addP_reg_reg(iRegPNoSp dst, iRegP src1, iRegL src2) %{
6469 match(Set dst (AddP src1 src2));
6470
6471 ins_cost(ALU_COST);
6472 format %{ "add $dst, $src1, $src2\t# ptr, #@addP_reg_reg" %}
6473
6474 ins_encode %{
6475 __ add(as_Register($dst$$reg),
6476 as_Register($src1$$reg),
6477 as_Register($src2$$reg));
6478 %}
6479
6480 ins_pipe(ialu_reg_reg);
6481 %}
6482
6483 // If we shift more than 32 bits, we need not convert I2L.
6484 instruct lShiftL_regI_immGE32(iRegLNoSp dst, iRegI src, uimmI6_ge32 scale) %{
6485 match(Set dst (LShiftL (ConvI2L src) scale));
6486 ins_cost(ALU_COST);
6487 format %{ "slli $dst, $src, $scale & 63\t#@lShiftL_regI_immGE32" %}
6488
6489 ins_encode %{
6490 __ slli(as_Register($dst$$reg), as_Register($src$$reg), $scale$$constant & 63);
6491 %}
6492
6493 ins_pipe(ialu_reg_shift);
6494 %}
6495
6496 // Pointer Immediate Addition
6497 // n.b. this needs to be more expensive than using an indirect memory
6498 // operand
6499 instruct addP_reg_imm(iRegPNoSp dst, iRegP src1, immLAdd src2) %{
6500 match(Set dst (AddP src1 src2));
6501 ins_cost(ALU_COST);
6502 format %{ "addi $dst, $src1, $src2\t# ptr, #@addP_reg_imm" %}
6503
6504 ins_encode %{
6505 // src2 is imm, so actually call the addi
6506 __ addi(as_Register($dst$$reg),
6507 as_Register($src1$$reg),
6508 $src2$$constant);
6509 %}
6510
6511 ins_pipe(ialu_reg_imm);
6512 %}
6513
6514 // Long Addition
6515 instruct addL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6516 match(Set dst (AddL src1 src2));
6517 ins_cost(ALU_COST);
6518 format %{ "add $dst, $src1, $src2\t#@addL_reg_reg" %}
6519
6520 ins_encode %{
6521 __ add(as_Register($dst$$reg),
6522 as_Register($src1$$reg),
6523 as_Register($src2$$reg));
6524 %}
6525
6526 ins_pipe(ialu_reg_reg);
6527 %}
6528
6529 // No constant pool entries requiredLong Immediate Addition.
6530 instruct addL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
6531 match(Set dst (AddL src1 src2));
6532 ins_cost(ALU_COST);
6533 format %{ "addi $dst, $src1, $src2\t#@addL_reg_imm" %}
6534
6535 ins_encode %{
6536 // src2 is imm, so actually call the addi
6537 __ addi(as_Register($dst$$reg),
6538 as_Register($src1$$reg),
6539 $src2$$constant);
6540 %}
6541
6542 ins_pipe(ialu_reg_imm);
6543 %}
6544
6545 // Integer Subtraction
6546 instruct subI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6547 match(Set dst (SubI src1 src2));
6548
6549 ins_cost(ALU_COST);
6550 format %{ "subw $dst, $src1, $src2\t#@subI_reg_reg" %}
6551
6552 ins_encode %{
6553 __ subw(as_Register($dst$$reg),
6554 as_Register($src1$$reg),
6555 as_Register($src2$$reg));
6556 %}
6557
6558 ins_pipe(ialu_reg_reg);
6559 %}
6560
6561 // Immediate Subtraction
6562 instruct subI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immISub src2) %{
6563 match(Set dst (SubI src1 src2));
6564
6565 ins_cost(ALU_COST);
6566 format %{ "addiw $dst, $src1, -$src2\t#@subI_reg_imm" %}
6567
6568 ins_encode %{
6569 // src2 is imm, so actually call the addiw
6570 __ subiw(as_Register($dst$$reg),
6571 as_Register($src1$$reg),
6572 $src2$$constant);
6573 %}
6574
6575 ins_pipe(ialu_reg_imm);
6576 %}
6577
6578 // Long Subtraction
6579 instruct subL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6580 match(Set dst (SubL src1 src2));
6581 ins_cost(ALU_COST);
6582 format %{ "sub $dst, $src1, $src2\t#@subL_reg_reg" %}
6583
6584 ins_encode %{
6585 __ sub(as_Register($dst$$reg),
6586 as_Register($src1$$reg),
6587 as_Register($src2$$reg));
6588 %}
6589
6590 ins_pipe(ialu_reg_reg);
6591 %}
6592
6593 // No constant pool entries requiredLong Immediate Subtraction.
6594 instruct subL_reg_imm(iRegLNoSp dst, iRegL src1, immLSub src2) %{
6595 match(Set dst (SubL src1 src2));
6596 ins_cost(ALU_COST);
6597 format %{ "addi $dst, $src1, -$src2\t#@subL_reg_imm" %}
6598
6599 ins_encode %{
6600 // src2 is imm, so actually call the addi
6601 __ subi(as_Register($dst$$reg),
6602 as_Register($src1$$reg),
6603 $src2$$constant);
6604 %}
6605
6606 ins_pipe(ialu_reg_imm);
6607 %}
6608
6609 // Integer Negation (special case for sub)
6610
6611 instruct negI_reg(iRegINoSp dst, iRegIorL2I src, immI0 zero) %{
6612 match(Set dst (SubI zero src));
6613 ins_cost(ALU_COST);
6614 format %{ "subw $dst, x0, $src\t# int, #@negI_reg" %}
6615
6616 ins_encode %{
6617 // actually call the subw
6618 __ negw(as_Register($dst$$reg),
6619 as_Register($src$$reg));
6620 %}
6621
6622 ins_pipe(ialu_reg);
6623 %}
6624
6625 // Long Negation
6626
6627 instruct negL_reg(iRegLNoSp dst, iRegL src, immL0 zero) %{
6628 match(Set dst (SubL zero src));
6629 ins_cost(ALU_COST);
6630 format %{ "sub $dst, x0, $src\t# long, #@negL_reg" %}
6631
6632 ins_encode %{
6633 // actually call the sub
6634 __ neg(as_Register($dst$$reg),
6635 as_Register($src$$reg));
6636 %}
6637
6638 ins_pipe(ialu_reg);
6639 %}
6640
6641 // Integer Multiply
6642
6643 instruct mulI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6644 match(Set dst (MulI src1 src2));
6645 ins_cost(IMUL_COST);
6646 format %{ "mulw $dst, $src1, $src2\t#@mulI" %}
6647
6648 //this means 2 word multi, and no sign extend to 64 bits
6649 ins_encode %{
6650 // riscv64 mulw will sign-extension to high 32 bits in dst reg
6651 __ mulw(as_Register($dst$$reg),
6652 as_Register($src1$$reg),
6653 as_Register($src2$$reg));
6654 %}
6655
6656 ins_pipe(imul_reg_reg);
6657 %}
6658
6659 // Long Multiply
6660
6661 instruct mulL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6662 match(Set dst (MulL src1 src2));
6663 ins_cost(IMUL_COST);
6664 format %{ "mul $dst, $src1, $src2\t#@mulL" %}
6665
6666 ins_encode %{
6667 __ mul(as_Register($dst$$reg),
6668 as_Register($src1$$reg),
6669 as_Register($src2$$reg));
6670 %}
6671
6672 ins_pipe(lmul_reg_reg);
6673 %}
6674
6675 instruct mulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
6676 %{
6677 match(Set dst (MulHiL src1 src2));
6678 ins_cost(IMUL_COST);
6679 format %{ "mulh $dst, $src1, $src2\t# mulhi, #@mulHiL_rReg" %}
6680
6681 ins_encode %{
6682 __ mulh(as_Register($dst$$reg),
6683 as_Register($src1$$reg),
6684 as_Register($src2$$reg));
6685 %}
6686
6687 ins_pipe(lmul_reg_reg);
6688 %}
6689
6690 instruct umulHiL_rReg(iRegLNoSp dst, iRegL src1, iRegL src2)
6691 %{
6692 match(Set dst (UMulHiL src1 src2));
6693 ins_cost(IMUL_COST);
6694 format %{ "mulhu $dst, $src1, $src2\t# umulhi, #@umulHiL_rReg" %}
6695
6696 ins_encode %{
6697 __ mulhu(as_Register($dst$$reg),
6698 as_Register($src1$$reg),
6699 as_Register($src2$$reg));
6700 %}
6701
6702 ins_pipe(lmul_reg_reg);
6703 %}
6704
6705 // Integer Divide
6706
6707 instruct divI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6708 match(Set dst (DivI src1 src2));
6709 ins_cost(IDIVSI_COST);
6710 format %{ "divw $dst, $src1, $src2\t#@divI"%}
6711
6712 ins_encode %{
6713 __ divw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6714 %}
6715 ins_pipe(idiv_reg_reg);
6716 %}
6717
6718 instruct UdivI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6719 match(Set dst (UDivI src1 src2));
6720 ins_cost(IDIVSI_COST);
6721 format %{ "divuw $dst, $src1, $src2\t#@UdivI"%}
6722
6723 ins_encode %{
6724 __ divuw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6725 %}
6726 ins_pipe(idiv_reg_reg);
6727 %}
6728
6729 instruct signExtract(iRegINoSp dst, iRegIorL2I src1, immI_31 div1, immI_31 div2) %{
6730 match(Set dst (URShiftI (RShiftI src1 div1) div2));
6731 ins_cost(ALU_COST);
6732 format %{ "srliw $dst, $src1, $div1\t# int signExtract, #@signExtract" %}
6733
6734 ins_encode %{
6735 __ srliw(as_Register($dst$$reg), as_Register($src1$$reg), 31);
6736 %}
6737 ins_pipe(ialu_reg_shift);
6738 %}
6739
6740 // Long Divide
6741
6742 instruct divL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6743 match(Set dst (DivL src1 src2));
6744 ins_cost(IDIVDI_COST);
6745 format %{ "div $dst, $src1, $src2\t#@divL" %}
6746
6747 ins_encode %{
6748 __ div(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6749 %}
6750 ins_pipe(ldiv_reg_reg);
6751 %}
6752
6753 instruct UdivL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6754 match(Set dst (UDivL src1 src2));
6755 ins_cost(IDIVDI_COST);
6756
6757 format %{ "divu $dst, $src1, $src2\t#@UdivL" %}
6758
6759 ins_encode %{
6760 __ divu(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6761 %}
6762 ins_pipe(ldiv_reg_reg);
6763 %}
6764
6765 instruct signExtractL(iRegLNoSp dst, iRegL src1, immI_63 div1, immI_63 div2) %{
6766 match(Set dst (URShiftL (RShiftL src1 div1) div2));
6767 ins_cost(ALU_COST);
6768 format %{ "srli $dst, $src1, $div1\t# long signExtract, #@signExtractL" %}
6769
6770 ins_encode %{
6771 __ srli(as_Register($dst$$reg), as_Register($src1$$reg), 63);
6772 %}
6773 ins_pipe(ialu_reg_shift);
6774 %}
6775
6776 // Integer Remainder
6777
6778 instruct modI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6779 match(Set dst (ModI src1 src2));
6780 ins_cost(IDIVSI_COST);
6781 format %{ "remw $dst, $src1, $src2\t#@modI" %}
6782
6783 ins_encode %{
6784 __ remw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6785 %}
6786 ins_pipe(ialu_reg_reg);
6787 %}
6788
6789 instruct UmodI(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6790 match(Set dst (UModI src1 src2));
6791 ins_cost(IDIVSI_COST);
6792 format %{ "remuw $dst, $src1, $src2\t#@UmodI" %}
6793
6794 ins_encode %{
6795 __ remuw(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6796 %}
6797 ins_pipe(ialu_reg_reg);
6798 %}
6799
6800 // Long Remainder
6801
6802 instruct modL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6803 match(Set dst (ModL src1 src2));
6804 ins_cost(IDIVDI_COST);
6805 format %{ "rem $dst, $src1, $src2\t#@modL" %}
6806
6807 ins_encode %{
6808 __ rem(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6809 %}
6810 ins_pipe(ialu_reg_reg);
6811 %}
6812
6813 instruct UmodL(iRegLNoSp dst, iRegL src1, iRegL src2) %{
6814 match(Set dst (UModL src1 src2));
6815 ins_cost(IDIVDI_COST);
6816 format %{ "remu $dst, $src1, $src2\t#@UmodL" %}
6817
6818 ins_encode %{
6819 __ remu(as_Register($dst$$reg), as_Register($src1$$reg), as_Register($src2$$reg));
6820 %}
6821 ins_pipe(ialu_reg_reg);
6822 %}
6823
6824 // Integer Shifts
6825
6826 // Shift Left Register
6827 // In RV64I, only the low 5 bits of src2 are considered for the shift amount
6828 instruct lShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6829 match(Set dst (LShiftI src1 src2));
6830 ins_cost(ALU_COST);
6831 format %{ "sllw $dst, $src1, $src2\t#@lShiftI_reg_reg" %}
6832
6833 ins_encode %{
6834 __ sllw(as_Register($dst$$reg),
6835 as_Register($src1$$reg),
6836 as_Register($src2$$reg));
6837 %}
6838
6839 ins_pipe(ialu_reg_reg_vshift);
6840 %}
6841
6842 // Shift Left Immediate
6843 instruct lShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
6844 match(Set dst (LShiftI src1 src2));
6845 ins_cost(ALU_COST);
6846 format %{ "slliw $dst, $src1, ($src2 & 0x1f)\t#@lShiftI_reg_imm" %}
6847
6848 ins_encode %{
6849 // the shift amount is encoded in the lower
6850 // 5 bits of the I-immediate field for RV32I
6851 __ slliw(as_Register($dst$$reg),
6852 as_Register($src1$$reg),
6853 (unsigned) $src2$$constant & 0x1f);
6854 %}
6855
6856 ins_pipe(ialu_reg_shift);
6857 %}
6858
6859 // Shift Right Logical Register
6860 // In RV64I, only the low 5 bits of src2 are considered for the shift amount
6861 instruct urShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6862 match(Set dst (URShiftI src1 src2));
6863 ins_cost(ALU_COST);
6864 format %{ "srlw $dst, $src1, $src2\t#@urShiftI_reg_reg" %}
6865
6866 ins_encode %{
6867 __ srlw(as_Register($dst$$reg),
6868 as_Register($src1$$reg),
6869 as_Register($src2$$reg));
6870 %}
6871
6872 ins_pipe(ialu_reg_reg_vshift);
6873 %}
6874
6875 // Shift Right Logical Immediate
6876 instruct urShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
6877 match(Set dst (URShiftI src1 src2));
6878 ins_cost(ALU_COST);
6879 format %{ "srliw $dst, $src1, ($src2 & 0x1f)\t#@urShiftI_reg_imm" %}
6880
6881 ins_encode %{
6882 // the shift amount is encoded in the lower
6883 // 6 bits of the I-immediate field for RV64I
6884 __ srliw(as_Register($dst$$reg),
6885 as_Register($src1$$reg),
6886 (unsigned) $src2$$constant & 0x1f);
6887 %}
6888
6889 ins_pipe(ialu_reg_shift);
6890 %}
6891
6892 // Shift Right Arithmetic Register
6893 // In RV64I, only the low 5 bits of src2 are considered for the shift amount
6894 instruct rShiftI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
6895 match(Set dst (RShiftI src1 src2));
6896 ins_cost(ALU_COST);
6897 format %{ "sraw $dst, $src1, $src2\t#@rShiftI_reg_reg" %}
6898
6899 ins_encode %{
6900 // riscv will sign-ext dst high 32 bits
6901 __ sraw(as_Register($dst$$reg),
6902 as_Register($src1$$reg),
6903 as_Register($src2$$reg));
6904 %}
6905
6906 ins_pipe(ialu_reg_reg_vshift);
6907 %}
6908
6909 // Shift Right Arithmetic Immediate
6910 instruct rShiftI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immI src2) %{
6911 match(Set dst (RShiftI src1 src2));
6912 ins_cost(ALU_COST);
6913 format %{ "sraiw $dst, $src1, ($src2 & 0x1f)\t#@rShiftI_reg_imm" %}
6914
6915 ins_encode %{
6916 // riscv will sign-ext dst high 32 bits
6917 __ sraiw(as_Register($dst$$reg),
6918 as_Register($src1$$reg),
6919 (unsigned) $src2$$constant & 0x1f);
6920 %}
6921
6922 ins_pipe(ialu_reg_shift);
6923 %}
6924
6925 // Long Shifts
6926
6927 // Shift Left Register
6928 // In RV64I, only the low 6 bits of src2 are considered for the shift amount
6929 instruct lShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
6930 match(Set dst (LShiftL src1 src2));
6931
6932 ins_cost(ALU_COST);
6933 format %{ "sll $dst, $src1, $src2\t#@lShiftL_reg_reg" %}
6934
6935 ins_encode %{
6936 __ sll(as_Register($dst$$reg),
6937 as_Register($src1$$reg),
6938 as_Register($src2$$reg));
6939 %}
6940
6941 ins_pipe(ialu_reg_reg_vshift);
6942 %}
6943
6944 // Shift Left Immediate
6945 instruct lShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
6946 match(Set dst (LShiftL src1 src2));
6947
6948 ins_cost(ALU_COST);
6949 format %{ "slli $dst, $src1, ($src2 & 0x3f)\t#@lShiftL_reg_imm" %}
6950
6951 ins_encode %{
6952 // the shift amount is encoded in the lower
6953 // 6 bits of the I-immediate field for RV64I
6954 __ slli(as_Register($dst$$reg),
6955 as_Register($src1$$reg),
6956 (unsigned) $src2$$constant & 0x3f);
6957 %}
6958
6959 ins_pipe(ialu_reg_shift);
6960 %}
6961
6962 // Shift Right Logical Register
6963 // In RV64I, only the low 6 bits of src2 are considered for the shift amount
6964 instruct urShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
6965 match(Set dst (URShiftL src1 src2));
6966
6967 ins_cost(ALU_COST);
6968 format %{ "srl $dst, $src1, $src2\t#@urShiftL_reg_reg" %}
6969
6970 ins_encode %{
6971 __ srl(as_Register($dst$$reg),
6972 as_Register($src1$$reg),
6973 as_Register($src2$$reg));
6974 %}
6975
6976 ins_pipe(ialu_reg_reg_vshift);
6977 %}
6978
6979 // Shift Right Logical Immediate
6980 instruct urShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
6981 match(Set dst (URShiftL src1 src2));
6982
6983 ins_cost(ALU_COST);
6984 format %{ "srli $dst, $src1, ($src2 & 0x3f)\t#@urShiftL_reg_imm" %}
6985
6986 ins_encode %{
6987 // the shift amount is encoded in the lower
6988 // 6 bits of the I-immediate field for RV64I
6989 __ srli(as_Register($dst$$reg),
6990 as_Register($src1$$reg),
6991 (unsigned) $src2$$constant & 0x3f);
6992 %}
6993
6994 ins_pipe(ialu_reg_shift);
6995 %}
6996
6997 // A special-case pattern for card table stores.
6998 instruct urShiftP_reg_imm(iRegLNoSp dst, iRegP src1, immI src2) %{
6999 match(Set dst (URShiftL (CastP2X src1) src2));
7000
7001 ins_cost(ALU_COST);
7002 format %{ "srli $dst, p2x($src1), ($src2 & 0x3f)\t#@urShiftP_reg_imm" %}
7003
7004 ins_encode %{
7005 // the shift amount is encoded in the lower
7006 // 6 bits of the I-immediate field for RV64I
7007 __ srli(as_Register($dst$$reg),
7008 as_Register($src1$$reg),
7009 (unsigned) $src2$$constant & 0x3f);
7010 %}
7011
7012 ins_pipe(ialu_reg_shift);
7013 %}
7014
7015 // Shift Right Arithmetic Register
7016 // In RV64I, only the low 6 bits of src2 are considered for the shift amount
7017 instruct rShiftL_reg_reg(iRegLNoSp dst, iRegL src1, iRegIorL2I src2) %{
7018 match(Set dst (RShiftL src1 src2));
7019
7020 ins_cost(ALU_COST);
7021 format %{ "sra $dst, $src1, $src2\t#@rShiftL_reg_reg" %}
7022
7023 ins_encode %{
7024 __ sra(as_Register($dst$$reg),
7025 as_Register($src1$$reg),
7026 as_Register($src2$$reg));
7027 %}
7028
7029 ins_pipe(ialu_reg_reg_vshift);
7030 %}
7031
7032 // Shift Right Arithmetic Immediate
7033 instruct rShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
7034 match(Set dst (RShiftL src1 src2));
7035
7036 ins_cost(ALU_COST);
7037 format %{ "srai $dst, $src1, ($src2 & 0x3f)\t#@rShiftL_reg_imm" %}
7038
7039 ins_encode %{
7040 // the shift amount is encoded in the lower
7041 // 6 bits of the I-immediate field for RV64I
7042 __ srai(as_Register($dst$$reg),
7043 as_Register($src1$$reg),
7044 (unsigned) $src2$$constant & 0x3f);
7045 %}
7046
7047 ins_pipe(ialu_reg_shift);
7048 %}
7049
7050 instruct regI_not_reg(iRegINoSp dst, iRegI src1, immI_M1 m1) %{
7051 match(Set dst (XorI src1 m1));
7052 ins_cost(ALU_COST);
7053 format %{ "xori $dst, $src1, -1\t#@regI_not_reg" %}
7054
7055 ins_encode %{
7056 __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
7057 %}
7058
7059 ins_pipe(ialu_reg_imm);
7060 %}
7061
7062 instruct regL_not_reg(iRegLNoSp dst, iRegL src1, immL_M1 m1) %{
7063 match(Set dst (XorL src1 m1));
7064 ins_cost(ALU_COST);
7065 format %{ "xori $dst, $src1, -1\t#@regL_not_reg" %}
7066
7067 ins_encode %{
7068 __ xori(as_Register($dst$$reg), as_Register($src1$$reg), -1);
7069 %}
7070
7071 ins_pipe(ialu_reg_imm);
7072 %}
7073
7074
7075 // ============================================================================
7076 // Floating Point Arithmetic Instructions
7077
7078 instruct addF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7079 match(Set dst (AddF src1 src2));
7080
7081 ins_cost(DEFAULT_COST * 5);
7082 format %{ "fadd.s $dst, $src1, $src2\t#@addF_reg_reg" %}
7083
7084 ins_encode %{
7085 __ fadd_s(as_FloatRegister($dst$$reg),
7086 as_FloatRegister($src1$$reg),
7087 as_FloatRegister($src2$$reg));
7088 %}
7089
7090 ins_pipe(fp_dop_reg_reg_s);
7091 %}
7092
7093 instruct addD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7094 match(Set dst (AddD src1 src2));
7095
7096 ins_cost(DEFAULT_COST * 5);
7097 format %{ "fadd.d $dst, $src1, $src2\t#@addD_reg_reg" %}
7098
7099 ins_encode %{
7100 __ fadd_d(as_FloatRegister($dst$$reg),
7101 as_FloatRegister($src1$$reg),
7102 as_FloatRegister($src2$$reg));
7103 %}
7104
7105 ins_pipe(fp_dop_reg_reg_d);
7106 %}
7107
7108 instruct subF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7109 match(Set dst (SubF src1 src2));
7110
7111 ins_cost(DEFAULT_COST * 5);
7112 format %{ "fsub.s $dst, $src1, $src2\t#@subF_reg_reg" %}
7113
7114 ins_encode %{
7115 __ fsub_s(as_FloatRegister($dst$$reg),
7116 as_FloatRegister($src1$$reg),
7117 as_FloatRegister($src2$$reg));
7118 %}
7119
7120 ins_pipe(fp_dop_reg_reg_s);
7121 %}
7122
7123 instruct subD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7124 match(Set dst (SubD src1 src2));
7125
7126 ins_cost(DEFAULT_COST * 5);
7127 format %{ "fsub.d $dst, $src1, $src2\t#@subD_reg_reg" %}
7128
7129 ins_encode %{
7130 __ fsub_d(as_FloatRegister($dst$$reg),
7131 as_FloatRegister($src1$$reg),
7132 as_FloatRegister($src2$$reg));
7133 %}
7134
7135 ins_pipe(fp_dop_reg_reg_d);
7136 %}
7137
7138 instruct mulF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7139 match(Set dst (MulF src1 src2));
7140
7141 ins_cost(FMUL_SINGLE_COST);
7142 format %{ "fmul.s $dst, $src1, $src2\t#@mulF_reg_reg" %}
7143
7144 ins_encode %{
7145 __ fmul_s(as_FloatRegister($dst$$reg),
7146 as_FloatRegister($src1$$reg),
7147 as_FloatRegister($src2$$reg));
7148 %}
7149
7150 ins_pipe(fp_dop_reg_reg_s);
7151 %}
7152
7153 instruct mulD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7154 match(Set dst (MulD src1 src2));
7155
7156 ins_cost(FMUL_DOUBLE_COST);
7157 format %{ "fmul.d $dst, $src1, $src2\t#@mulD_reg_reg" %}
7158
7159 ins_encode %{
7160 __ fmul_d(as_FloatRegister($dst$$reg),
7161 as_FloatRegister($src1$$reg),
7162 as_FloatRegister($src2$$reg));
7163 %}
7164
7165 ins_pipe(fp_dop_reg_reg_d);
7166 %}
7167
7168 // src1 * src2 + src3
7169 instruct maddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7170 match(Set dst (FmaF src3 (Binary src1 src2)));
7171
7172 ins_cost(FMUL_SINGLE_COST);
7173 format %{ "fmadd.s $dst, $src1, $src2, $src3\t#@maddF_reg_reg" %}
7174
7175 ins_encode %{
7176 assert(UseFMA, "Needs FMA instructions support.");
7177 __ fmadd_s(as_FloatRegister($dst$$reg),
7178 as_FloatRegister($src1$$reg),
7179 as_FloatRegister($src2$$reg),
7180 as_FloatRegister($src3$$reg));
7181 %}
7182
7183 ins_pipe(pipe_class_default);
7184 %}
7185
7186 // src1 * src2 + src3
7187 instruct maddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7188 match(Set dst (FmaD src3 (Binary src1 src2)));
7189
7190 ins_cost(FMUL_DOUBLE_COST);
7191 format %{ "fmadd.d $dst, $src1, $src2, $src3\t#@maddD_reg_reg" %}
7192
7193 ins_encode %{
7194 assert(UseFMA, "Needs FMA instructions support.");
7195 __ fmadd_d(as_FloatRegister($dst$$reg),
7196 as_FloatRegister($src1$$reg),
7197 as_FloatRegister($src2$$reg),
7198 as_FloatRegister($src3$$reg));
7199 %}
7200
7201 ins_pipe(pipe_class_default);
7202 %}
7203
7204 // src1 * src2 - src3
7205 instruct msubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7206 match(Set dst (FmaF (NegF src3) (Binary src1 src2)));
7207
7208 ins_cost(FMUL_SINGLE_COST);
7209 format %{ "fmsub.s $dst, $src1, $src2, $src3\t#@msubF_reg_reg" %}
7210
7211 ins_encode %{
7212 assert(UseFMA, "Needs FMA instructions support.");
7213 __ fmsub_s(as_FloatRegister($dst$$reg),
7214 as_FloatRegister($src1$$reg),
7215 as_FloatRegister($src2$$reg),
7216 as_FloatRegister($src3$$reg));
7217 %}
7218
7219 ins_pipe(pipe_class_default);
7220 %}
7221
7222 // src1 * src2 - src3
7223 instruct msubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7224 match(Set dst (FmaD (NegD src3) (Binary src1 src2)));
7225
7226 ins_cost(FMUL_DOUBLE_COST);
7227 format %{ "fmsub.d $dst, $src1, $src2, $src3\t#@msubD_reg_reg" %}
7228
7229 ins_encode %{
7230 assert(UseFMA, "Needs FMA instructions support.");
7231 __ fmsub_d(as_FloatRegister($dst$$reg),
7232 as_FloatRegister($src1$$reg),
7233 as_FloatRegister($src2$$reg),
7234 as_FloatRegister($src3$$reg));
7235 %}
7236
7237 ins_pipe(pipe_class_default);
7238 %}
7239
7240 // src1 * (-src2) + src3
7241 // "(-src1) * src2 + src3" has been idealized to "src2 * (-src1) + src3"
7242 instruct nmsubF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7243 match(Set dst (FmaF src3 (Binary src1 (NegF src2))));
7244
7245 ins_cost(FMUL_SINGLE_COST);
7246 format %{ "fnmsub.s $dst, $src1, $src2, $src3\t#@nmsubF_reg_reg" %}
7247
7248 ins_encode %{
7249 assert(UseFMA, "Needs FMA instructions support.");
7250 __ fnmsub_s(as_FloatRegister($dst$$reg),
7251 as_FloatRegister($src1$$reg),
7252 as_FloatRegister($src2$$reg),
7253 as_FloatRegister($src3$$reg));
7254 %}
7255
7256 ins_pipe(pipe_class_default);
7257 %}
7258
7259 // src1 * (-src2) + src3
7260 // "(-src1) * src2 + src3" has been idealized to "src2 * (-src1) + src3"
7261 instruct nmsubD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7262 match(Set dst (FmaD src3 (Binary src1 (NegD src2))));
7263
7264 ins_cost(FMUL_DOUBLE_COST);
7265 format %{ "fnmsub.d $dst, $src1, $src2, $src3\t#@nmsubD_reg_reg" %}
7266
7267 ins_encode %{
7268 assert(UseFMA, "Needs FMA instructions support.");
7269 __ fnmsub_d(as_FloatRegister($dst$$reg),
7270 as_FloatRegister($src1$$reg),
7271 as_FloatRegister($src2$$reg),
7272 as_FloatRegister($src3$$reg));
7273 %}
7274
7275 ins_pipe(pipe_class_default);
7276 %}
7277
7278 // src1 * (-src2) - src3
7279 // "(-src1) * src2 - src3" has been idealized to "src2 * (-src1) - src3"
7280 instruct nmaddF_reg_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3) %{
7281 match(Set dst (FmaF (NegF src3) (Binary src1 (NegF src2))));
7282
7283 ins_cost(FMUL_SINGLE_COST);
7284 format %{ "fnmadd.s $dst, $src1, $src2, $src3\t#@nmaddF_reg_reg" %}
7285
7286 ins_encode %{
7287 assert(UseFMA, "Needs FMA instructions support.");
7288 __ fnmadd_s(as_FloatRegister($dst$$reg),
7289 as_FloatRegister($src1$$reg),
7290 as_FloatRegister($src2$$reg),
7291 as_FloatRegister($src3$$reg));
7292 %}
7293
7294 ins_pipe(pipe_class_default);
7295 %}
7296
7297 // src1 * (-src2) - src3
7298 // "(-src1) * src2 - src3" has been idealized to "src2 * (-src1) - src3"
7299 instruct nmaddD_reg_reg(fRegD dst, fRegD src1, fRegD src2, fRegD src3) %{
7300 match(Set dst (FmaD (NegD src3) (Binary src1 (NegD src2))));
7301
7302 ins_cost(FMUL_DOUBLE_COST);
7303 format %{ "fnmadd.d $dst, $src1, $src2, $src3\t#@nmaddD_reg_reg" %}
7304
7305 ins_encode %{
7306 assert(UseFMA, "Needs FMA instructions support.");
7307 __ fnmadd_d(as_FloatRegister($dst$$reg),
7308 as_FloatRegister($src1$$reg),
7309 as_FloatRegister($src2$$reg),
7310 as_FloatRegister($src3$$reg));
7311 %}
7312
7313 ins_pipe(pipe_class_default);
7314 %}
7315
7316 // Math.max(FF)F
7317 instruct maxF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
7318 predicate(!UseZfa);
7319 match(Set dst (MaxF src1 src2));
7320 effect(KILL cr);
7321
7322 format %{ "maxF $dst, $src1, $src2" %}
7323
7324 ins_encode %{
7325 __ minmax_fp(as_FloatRegister($dst$$reg),
7326 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7327 __ FLOAT_TYPE::single_precision, false /* is_min */);
7328 %}
7329
7330 ins_pipe(pipe_class_default);
7331 %}
7332
7333 instruct maxF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
7334 predicate(UseZfa);
7335 match(Set dst (MaxF src1 src2));
7336
7337 format %{ "maxF $dst, $src1, $src2" %}
7338
7339 ins_encode %{
7340 __ fmaxm_s(as_FloatRegister($dst$$reg),
7341 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7342 %}
7343
7344 ins_pipe(pipe_class_default);
7345 %}
7346
7347 // Math.min(FF)F
7348 instruct minF_reg_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr) %{
7349 predicate(!UseZfa);
7350 match(Set dst (MinF src1 src2));
7351 effect(KILL cr);
7352
7353 format %{ "minF $dst, $src1, $src2" %}
7354
7355 ins_encode %{
7356 __ minmax_fp(as_FloatRegister($dst$$reg),
7357 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7358 __ FLOAT_TYPE::single_precision, true /* is_min */);
7359 %}
7360
7361 ins_pipe(pipe_class_default);
7362 %}
7363
7364 instruct minF_reg_reg_zfa(fRegF dst, fRegF src1, fRegF src2) %{
7365 predicate(UseZfa);
7366 match(Set dst (MinF src1 src2));
7367
7368 format %{ "minF $dst, $src1, $src2" %}
7369
7370 ins_encode %{
7371 __ fminm_s(as_FloatRegister($dst$$reg),
7372 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7373 %}
7374
7375 ins_pipe(pipe_class_default);
7376 %}
7377
7378 // Math.max(DD)D
7379 instruct maxD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
7380 predicate(!UseZfa);
7381 match(Set dst (MaxD src1 src2));
7382 effect(KILL cr);
7383
7384 format %{ "maxD $dst, $src1, $src2" %}
7385
7386 ins_encode %{
7387 __ minmax_fp(as_FloatRegister($dst$$reg),
7388 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7389 __ FLOAT_TYPE::double_precision, false /* is_min */);
7390 %}
7391
7392 ins_pipe(pipe_class_default);
7393 %}
7394
7395 instruct maxD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
7396 predicate(UseZfa);
7397 match(Set dst (MaxD src1 src2));
7398
7399 format %{ "maxD $dst, $src1, $src2" %}
7400
7401 ins_encode %{
7402 __ fmaxm_d(as_FloatRegister($dst$$reg),
7403 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7404 %}
7405
7406 ins_pipe(pipe_class_default);
7407 %}
7408
7409 // Math.min(DD)D
7410 instruct minD_reg_reg(fRegD dst, fRegD src1, fRegD src2, rFlagsReg cr) %{
7411 predicate(!UseZfa);
7412 match(Set dst (MinD src1 src2));
7413 effect(KILL cr);
7414
7415 format %{ "minD $dst, $src1, $src2" %}
7416
7417 ins_encode %{
7418 __ minmax_fp(as_FloatRegister($dst$$reg),
7419 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg),
7420 __ FLOAT_TYPE::double_precision, true /* is_min */);
7421 %}
7422
7423 ins_pipe(pipe_class_default);
7424 %}
7425
7426 instruct minD_reg_reg_zfa(fRegD dst, fRegD src1, fRegD src2) %{
7427 predicate(UseZfa);
7428 match(Set dst (MinD src1 src2));
7429
7430 format %{ "minD $dst, $src1, $src2" %}
7431
7432 ins_encode %{
7433 __ fminm_d(as_FloatRegister($dst$$reg),
7434 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
7435 %}
7436
7437 ins_pipe(pipe_class_default);
7438 %}
7439
7440 // Float.isInfinite
7441 instruct isInfiniteF_reg_reg(iRegINoSp dst, fRegF src)
7442 %{
7443 match(Set dst (IsInfiniteF src));
7444
7445 format %{ "isInfinite $dst, $src" %}
7446 ins_encode %{
7447 __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7448 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::inf);
7449 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7450 %}
7451
7452 ins_pipe(pipe_class_default);
7453 %}
7454
7455 // Double.isInfinite
7456 instruct isInfiniteD_reg_reg(iRegINoSp dst, fRegD src)
7457 %{
7458 match(Set dst (IsInfiniteD src));
7459
7460 format %{ "isInfinite $dst, $src" %}
7461 ins_encode %{
7462 __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7463 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::inf);
7464 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7465 %}
7466
7467 ins_pipe(pipe_class_default);
7468 %}
7469
7470 // Float.isFinite
7471 instruct isFiniteF_reg_reg(iRegINoSp dst, fRegF src)
7472 %{
7473 match(Set dst (IsFiniteF src));
7474
7475 format %{ "isFinite $dst, $src" %}
7476 ins_encode %{
7477 __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7478 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::finite);
7479 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7480 %}
7481
7482 ins_pipe(pipe_class_default);
7483 %}
7484
7485 // Double.isFinite
7486 instruct isFiniteD_reg_reg(iRegINoSp dst, fRegD src)
7487 %{
7488 match(Set dst (IsFiniteD src));
7489
7490 format %{ "isFinite $dst, $src" %}
7491 ins_encode %{
7492 __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
7493 __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FClassBits::finite);
7494 __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
7495 %}
7496
7497 ins_pipe(pipe_class_default);
7498 %}
7499
7500 instruct divF_reg_reg(fRegF dst, fRegF src1, fRegF src2) %{
7501 match(Set dst (DivF src1 src2));
7502
7503 ins_cost(FDIV_COST);
7504 format %{ "fdiv.s $dst, $src1, $src2\t#@divF_reg_reg" %}
7505
7506 ins_encode %{
7507 __ fdiv_s(as_FloatRegister($dst$$reg),
7508 as_FloatRegister($src1$$reg),
7509 as_FloatRegister($src2$$reg));
7510 %}
7511
7512 ins_pipe(fp_div_s);
7513 %}
7514
7515 instruct divD_reg_reg(fRegD dst, fRegD src1, fRegD src2) %{
7516 match(Set dst (DivD src1 src2));
7517
7518 ins_cost(FDIV_COST);
7519 format %{ "fdiv.d $dst, $src1, $src2\t#@divD_reg_reg" %}
7520
7521 ins_encode %{
7522 __ fdiv_d(as_FloatRegister($dst$$reg),
7523 as_FloatRegister($src1$$reg),
7524 as_FloatRegister($src2$$reg));
7525 %}
7526
7527 ins_pipe(fp_div_d);
7528 %}
7529
7530 instruct negF_reg_reg(fRegF dst, fRegF src) %{
7531 match(Set dst (NegF src));
7532
7533 ins_cost(XFER_COST);
7534 format %{ "fsgnjn.s $dst, $src, $src\t#@negF_reg_reg" %}
7535
7536 ins_encode %{
7537 __ fneg_s(as_FloatRegister($dst$$reg),
7538 as_FloatRegister($src$$reg));
7539 %}
7540
7541 ins_pipe(fp_uop_s);
7542 %}
7543
7544 instruct negD_reg_reg(fRegD dst, fRegD src) %{
7545 match(Set dst (NegD src));
7546
7547 ins_cost(XFER_COST);
7548 format %{ "fsgnjn.d $dst, $src, $src\t#@negD_reg_reg" %}
7549
7550 ins_encode %{
7551 __ fneg_d(as_FloatRegister($dst$$reg),
7552 as_FloatRegister($src$$reg));
7553 %}
7554
7555 ins_pipe(fp_uop_d);
7556 %}
7557
7558 instruct absI_reg(iRegINoSp dst, iRegIorL2I src) %{
7559 match(Set dst (AbsI src));
7560
7561 ins_cost(ALU_COST * 3);
7562 format %{
7563 "sraiw t0, $src, 0x1f\n\t"
7564 "addw $dst, $src, t0\n\t"
7565 "xorr $dst, $dst, t0\t#@absI_reg"
7566 %}
7567
7568 ins_encode %{
7569 __ sraiw(t0, as_Register($src$$reg), 0x1f);
7570 __ addw(as_Register($dst$$reg), as_Register($src$$reg), t0);
7571 __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
7572 %}
7573
7574 ins_pipe(pipe_class_default);
7575 %}
7576
7577 instruct absL_reg(iRegLNoSp dst, iRegL src) %{
7578 match(Set dst (AbsL src));
7579
7580 ins_cost(ALU_COST * 3);
7581 format %{
7582 "srai t0, $src, 0x3f\n\t"
7583 "add $dst, $src, t0\n\t"
7584 "xorr $dst, $dst, t0\t#@absL_reg"
7585 %}
7586
7587 ins_encode %{
7588 __ srai(t0, as_Register($src$$reg), 0x3f);
7589 __ add(as_Register($dst$$reg), as_Register($src$$reg), t0);
7590 __ xorr(as_Register($dst$$reg), as_Register($dst$$reg), t0);
7591 %}
7592
7593 ins_pipe(pipe_class_default);
7594 %}
7595
7596 instruct absF_reg(fRegF dst, fRegF src) %{
7597 match(Set dst (AbsF src));
7598
7599 ins_cost(XFER_COST);
7600 format %{ "fsgnjx.s $dst, $src, $src\t#@absF_reg" %}
7601 ins_encode %{
7602 __ fabs_s(as_FloatRegister($dst$$reg),
7603 as_FloatRegister($src$$reg));
7604 %}
7605
7606 ins_pipe(fp_uop_s);
7607 %}
7608
7609 instruct absD_reg(fRegD dst, fRegD src) %{
7610 match(Set dst (AbsD src));
7611
7612 ins_cost(XFER_COST);
7613 format %{ "fsgnjx.d $dst, $src, $src\t#@absD_reg" %}
7614 ins_encode %{
7615 __ fabs_d(as_FloatRegister($dst$$reg),
7616 as_FloatRegister($src$$reg));
7617 %}
7618
7619 ins_pipe(fp_uop_d);
7620 %}
7621
7622 instruct sqrtF_reg(fRegF dst, fRegF src) %{
7623 match(Set dst (SqrtF src));
7624
7625 ins_cost(FSQRT_COST);
7626 format %{ "fsqrt.s $dst, $src\t#@sqrtF_reg" %}
7627 ins_encode %{
7628 __ fsqrt_s(as_FloatRegister($dst$$reg),
7629 as_FloatRegister($src$$reg));
7630 %}
7631
7632 ins_pipe(fp_sqrt_s);
7633 %}
7634
7635 instruct sqrtD_reg(fRegD dst, fRegD src) %{
7636 match(Set dst (SqrtD src));
7637
7638 ins_cost(FSQRT_COST);
7639 format %{ "fsqrt.d $dst, $src\t#@sqrtD_reg" %}
7640 ins_encode %{
7641 __ fsqrt_d(as_FloatRegister($dst$$reg),
7642 as_FloatRegister($src$$reg));
7643 %}
7644
7645 ins_pipe(fp_sqrt_d);
7646 %}
7647
7648 // Round Instruction
7649 instruct roundD_reg(fRegD dst, fRegD src, immI rmode, iRegLNoSp tmp1, iRegLNoSp tmp2, iRegLNoSp tmp3) %{
7650 match(Set dst (RoundDoubleMode src rmode));
7651 ins_cost(2 * XFER_COST + BRANCH_COST);
7652 effect(TEMP_DEF dst, TEMP tmp1, TEMP tmp2, TEMP tmp3);
7653
7654 format %{ "RoundDoubleMode $src, $rmode" %}
7655 ins_encode %{
7656 __ round_double_mode(as_FloatRegister($dst$$reg),
7657 as_FloatRegister($src$$reg), $rmode$$constant, $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
7658 %}
7659 ins_pipe(pipe_class_default);
7660 %}
7661
7662 // Copysign and signum intrinsics
7663
7664 instruct copySignD_reg(fRegD dst, fRegD src1, fRegD src2, immD zero) %{
7665 match(Set dst (CopySignD src1 (Binary src2 zero)));
7666 format %{ "CopySignD $dst $src1 $src2" %}
7667 ins_encode %{
7668 FloatRegister dst = as_FloatRegister($dst$$reg),
7669 src1 = as_FloatRegister($src1$$reg),
7670 src2 = as_FloatRegister($src2$$reg);
7671 __ fsgnj_d(dst, src1, src2);
7672 %}
7673 ins_pipe(fp_dop_reg_reg_d);
7674 %}
7675
7676 instruct copySignF_reg(fRegF dst, fRegF src1, fRegF src2) %{
7677 match(Set dst (CopySignF src1 src2));
7678 format %{ "CopySignF $dst $src1 $src2" %}
7679 ins_encode %{
7680 FloatRegister dst = as_FloatRegister($dst$$reg),
7681 src1 = as_FloatRegister($src1$$reg),
7682 src2 = as_FloatRegister($src2$$reg);
7683 __ fsgnj_s(dst, src1, src2);
7684 %}
7685 ins_pipe(fp_dop_reg_reg_s);
7686 %}
7687
7688 instruct signumD_reg(fRegD dst, immD zero, fRegD one) %{
7689 match(Set dst (SignumD dst (Binary zero one)));
7690 format %{ "signumD $dst, $dst" %}
7691 ins_encode %{
7692 __ signum_fp(as_FloatRegister($dst$$reg), as_FloatRegister($one$$reg), true /* is_double */);
7693 %}
7694 ins_pipe(pipe_class_default);
7695 %}
7696
7697 instruct signumF_reg(fRegF dst, immF zero, fRegF one) %{
7698 match(Set dst (SignumF dst (Binary zero one)));
7699 format %{ "signumF $dst, $dst" %}
7700 ins_encode %{
7701 __ signum_fp(as_FloatRegister($dst$$reg), as_FloatRegister($one$$reg), false /* is_double */);
7702 %}
7703 ins_pipe(pipe_class_default);
7704 %}
7705
7706 // Arithmetic Instructions End
7707
7708 // ============================================================================
7709 // Logical Instructions
7710
7711 // Register And
7712 instruct andI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7713 match(Set dst (AndI src1 src2));
7714
7715 format %{ "andr $dst, $src1, $src2\t#@andI_reg_reg" %}
7716
7717 ins_cost(ALU_COST);
7718 ins_encode %{
7719 __ andr(as_Register($dst$$reg),
7720 as_Register($src1$$reg),
7721 as_Register($src2$$reg));
7722 %}
7723
7724 ins_pipe(ialu_reg_reg);
7725 %}
7726
7727 // Immediate And
7728 instruct andI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7729 match(Set dst (AndI src1 src2));
7730
7731 format %{ "andi $dst, $src1, $src2\t#@andI_reg_imm" %}
7732
7733 ins_cost(ALU_COST);
7734 ins_encode %{
7735 __ andi(as_Register($dst$$reg),
7736 as_Register($src1$$reg),
7737 (int32_t)($src2$$constant));
7738 %}
7739
7740 ins_pipe(ialu_reg_imm);
7741 %}
7742
7743 // Register Or
7744 instruct orI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7745 match(Set dst (OrI src1 src2));
7746
7747 format %{ "orr $dst, $src1, $src2\t#@orI_reg_reg" %}
7748
7749 ins_cost(ALU_COST);
7750 ins_encode %{
7751 __ orr(as_Register($dst$$reg),
7752 as_Register($src1$$reg),
7753 as_Register($src2$$reg));
7754 %}
7755
7756 ins_pipe(ialu_reg_reg);
7757 %}
7758
7759 // Immediate Or
7760 instruct orI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7761 match(Set dst (OrI src1 src2));
7762
7763 format %{ "ori $dst, $src1, $src2\t#@orI_reg_imm" %}
7764
7765 ins_cost(ALU_COST);
7766 ins_encode %{
7767 __ ori(as_Register($dst$$reg),
7768 as_Register($src1$$reg),
7769 (int32_t)($src2$$constant));
7770 %}
7771
7772 ins_pipe(ialu_reg_imm);
7773 %}
7774
7775 // Register Xor
7776 instruct xorI_reg_reg(iRegINoSp dst, iRegI src1, iRegI src2) %{
7777 match(Set dst (XorI src1 src2));
7778
7779 format %{ "xorr $dst, $src1, $src2\t#@xorI_reg_reg" %}
7780
7781 ins_cost(ALU_COST);
7782 ins_encode %{
7783 __ xorr(as_Register($dst$$reg),
7784 as_Register($src1$$reg),
7785 as_Register($src2$$reg));
7786 %}
7787
7788 ins_pipe(ialu_reg_reg);
7789 %}
7790
7791 // Immediate Xor
7792 instruct xorI_reg_imm(iRegINoSp dst, iRegI src1, immIAdd src2) %{
7793 match(Set dst (XorI src1 src2));
7794
7795 format %{ "xori $dst, $src1, $src2\t#@xorI_reg_imm" %}
7796
7797 ins_cost(ALU_COST);
7798 ins_encode %{
7799 __ xori(as_Register($dst$$reg),
7800 as_Register($src1$$reg),
7801 (int32_t)($src2$$constant));
7802 %}
7803
7804 ins_pipe(ialu_reg_imm);
7805 %}
7806
7807 // Register And Long
7808 instruct andL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7809 match(Set dst (AndL src1 src2));
7810
7811 format %{ "andr $dst, $src1, $src2\t#@andL_reg_reg" %}
7812
7813 ins_cost(ALU_COST);
7814 ins_encode %{
7815 __ andr(as_Register($dst$$reg),
7816 as_Register($src1$$reg),
7817 as_Register($src2$$reg));
7818 %}
7819
7820 ins_pipe(ialu_reg_reg);
7821 %}
7822
7823 // Immediate And Long
7824 instruct andL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
7825 match(Set dst (AndL src1 src2));
7826
7827 format %{ "andi $dst, $src1, $src2\t#@andL_reg_imm" %}
7828
7829 ins_cost(ALU_COST);
7830 ins_encode %{
7831 __ andi(as_Register($dst$$reg),
7832 as_Register($src1$$reg),
7833 (int32_t)($src2$$constant));
7834 %}
7835
7836 ins_pipe(ialu_reg_imm);
7837 %}
7838
7839 // Register Or Long
7840 instruct orL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7841 match(Set dst (OrL src1 src2));
7842
7843 format %{ "orr $dst, $src1, $src2\t#@orL_reg_reg" %}
7844
7845 ins_cost(ALU_COST);
7846 ins_encode %{
7847 __ orr(as_Register($dst$$reg),
7848 as_Register($src1$$reg),
7849 as_Register($src2$$reg));
7850 %}
7851
7852 ins_pipe(ialu_reg_reg);
7853 %}
7854
7855 // Immediate Or Long
7856 instruct orL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
7857 match(Set dst (OrL src1 src2));
7858
7859 format %{ "ori $dst, $src1, $src2\t#@orL_reg_imm" %}
7860
7861 ins_cost(ALU_COST);
7862 ins_encode %{
7863 __ ori(as_Register($dst$$reg),
7864 as_Register($src1$$reg),
7865 (int32_t)($src2$$constant));
7866 %}
7867
7868 ins_pipe(ialu_reg_imm);
7869 %}
7870
7871 // Register Xor Long
7872 instruct xorL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
7873 match(Set dst (XorL src1 src2));
7874
7875 format %{ "xorr $dst, $src1, $src2\t#@xorL_reg_reg" %}
7876
7877 ins_cost(ALU_COST);
7878 ins_encode %{
7879 __ xorr(as_Register($dst$$reg),
7880 as_Register($src1$$reg),
7881 as_Register($src2$$reg));
7882 %}
7883
7884 ins_pipe(ialu_reg_reg);
7885 %}
7886
7887 // Immediate Xor Long
7888 instruct xorL_reg_imm(iRegLNoSp dst, iRegL src1, immLAdd src2) %{
7889 match(Set dst (XorL src1 src2));
7890
7891 ins_cost(ALU_COST);
7892 format %{ "xori $dst, $src1, $src2\t#@xorL_reg_imm" %}
7893
7894 ins_encode %{
7895 __ xori(as_Register($dst$$reg),
7896 as_Register($src1$$reg),
7897 (int32_t)($src2$$constant));
7898 %}
7899
7900 ins_pipe(ialu_reg_imm);
7901 %}
7902
7903 // ============================================================================
7904 // MemBar Instruction
7905
7906 instruct load_fence() %{
7907 match(LoadFence);
7908 ins_cost(ALU_COST);
7909
7910 format %{ "#@load_fence" %}
7911
7912 ins_encode %{
7913 __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
7914 %}
7915 ins_pipe(pipe_serial);
7916 %}
7917
7918 instruct membar_acquire() %{
7919 match(MemBarAcquire);
7920 ins_cost(ALU_COST);
7921
7922 format %{ "#@membar_acquire\n\t"
7923 "fence ir iorw" %}
7924
7925 ins_encode %{
7926 __ block_comment("membar_acquire");
7927 __ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
7928 %}
7929
7930 ins_pipe(pipe_serial);
7931 %}
7932
7933 instruct membar_acquire_lock() %{
7934 match(MemBarAcquireLock);
7935 ins_cost(0);
7936
7937 format %{ "#@membar_acquire_lock (elided)" %}
7938
7939 ins_encode %{
7940 __ block_comment("membar_acquire_lock (elided)");
7941 %}
7942
7943 ins_pipe(pipe_serial);
7944 %}
7945
7946 instruct store_fence() %{
7947 match(StoreFence);
7948 ins_cost(ALU_COST);
7949
7950 format %{ "#@store_fence" %}
7951
7952 ins_encode %{
7953 __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
7954 %}
7955 ins_pipe(pipe_serial);
7956 %}
7957
7958 instruct membar_release() %{
7959 match(MemBarRelease);
7960 ins_cost(ALU_COST);
7961
7962 format %{ "#@membar_release\n\t"
7963 "fence iorw ow" %}
7964
7965 ins_encode %{
7966 __ block_comment("membar_release");
7967 __ membar(MacroAssembler::LoadStore | MacroAssembler::StoreStore);
7968 %}
7969 ins_pipe(pipe_serial);
7970 %}
7971
7972 instruct membar_storestore() %{
7973 match(MemBarStoreStore);
7974 match(StoreStoreFence);
7975 ins_cost(ALU_COST);
7976
7977 format %{ "MEMBAR-store-store\t#@membar_storestore" %}
7978
7979 ins_encode %{
7980 __ membar(MacroAssembler::StoreStore);
7981 %}
7982 ins_pipe(pipe_serial);
7983 %}
7984
7985 instruct membar_release_lock() %{
7986 match(MemBarReleaseLock);
7987 ins_cost(0);
7988
7989 format %{ "#@membar_release_lock (elided)" %}
7990
7991 ins_encode %{
7992 __ block_comment("membar_release_lock (elided)");
7993 %}
7994
7995 ins_pipe(pipe_serial);
7996 %}
7997
7998 instruct membar_volatile() %{
7999 match(MemBarVolatile);
8000 ins_cost(ALU_COST);
8001
8002 format %{ "#@membar_volatile\n\t"
8003 "fence iorw iorw"%}
8004
8005 ins_encode %{
8006 __ block_comment("membar_volatile");
8007 __ membar(MacroAssembler::StoreLoad);
8008 %}
8009
8010 ins_pipe(pipe_serial);
8011 %}
8012
8013 instruct spin_wait() %{
8014 predicate(UseZihintpause);
8015 match(OnSpinWait);
8016 ins_cost(CACHE_MISS_COST);
8017
8018 format %{ "spin_wait" %}
8019
8020 ins_encode %{
8021 __ pause();
8022 %}
8023
8024 ins_pipe(pipe_serial);
8025 %}
8026
8027 // ============================================================================
8028 // Cast Instructions (Java-level type cast)
8029
8030 instruct castX2P(iRegPNoSp dst, iRegL src) %{
8031 match(Set dst (CastX2P src));
8032
8033 ins_cost(ALU_COST);
8034 format %{ "mv $dst, $src\t# long -> ptr, #@castX2P" %}
8035
8036 ins_encode %{
8037 if ($dst$$reg != $src$$reg) {
8038 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
8039 }
8040 %}
8041
8042 ins_pipe(ialu_reg);
8043 %}
8044
8045 instruct castP2X(iRegLNoSp dst, iRegP src) %{
8046 match(Set dst (CastP2X src));
8047
8048 ins_cost(ALU_COST);
8049 format %{ "mv $dst, $src\t# ptr -> long, #@castP2X" %}
8050
8051 ins_encode %{
8052 if ($dst$$reg != $src$$reg) {
8053 __ mv(as_Register($dst$$reg), as_Register($src$$reg));
8054 }
8055 %}
8056
8057 ins_pipe(ialu_reg);
8058 %}
8059
8060 instruct castPP(iRegPNoSp dst)
8061 %{
8062 match(Set dst (CastPP dst));
8063 ins_cost(0);
8064
8065 size(0);
8066 format %{ "# castPP of $dst, #@castPP" %}
8067 ins_encode(/* empty encoding */);
8068 ins_pipe(pipe_class_empty);
8069 %}
8070
8071 instruct castLL(iRegL dst)
8072 %{
8073 match(Set dst (CastLL dst));
8074
8075 size(0);
8076 format %{ "# castLL of $dst, #@castLL" %}
8077 ins_encode(/* empty encoding */);
8078 ins_cost(0);
8079 ins_pipe(pipe_class_empty);
8080 %}
8081
8082 instruct castII(iRegI dst)
8083 %{
8084 match(Set dst (CastII dst));
8085
8086 size(0);
8087 format %{ "# castII of $dst, #@castII" %}
8088 ins_encode(/* empty encoding */);
8089 ins_cost(0);
8090 ins_pipe(pipe_class_empty);
8091 %}
8092
8093 instruct checkCastPP(iRegPNoSp dst)
8094 %{
8095 match(Set dst (CheckCastPP dst));
8096
8097 size(0);
8098 ins_cost(0);
8099 format %{ "# checkcastPP of $dst, #@checkCastPP" %}
8100 ins_encode(/* empty encoding */);
8101 ins_pipe(pipe_class_empty);
8102 %}
8103
8104 instruct castHH(fRegF dst)
8105 %{
8106 match(Set dst (CastHH dst));
8107
8108 size(0);
8109 format %{ "# castHH of $dst" %}
8110 ins_encode(/* empty encoding */);
8111 ins_cost(0);
8112 ins_pipe(pipe_class_empty);
8113 %}
8114
8115 instruct castFF(fRegF dst)
8116 %{
8117 match(Set dst (CastFF dst));
8118
8119 size(0);
8120 format %{ "# castFF of $dst" %}
8121 ins_encode(/* empty encoding */);
8122 ins_cost(0);
8123 ins_pipe(pipe_class_empty);
8124 %}
8125
8126 instruct castDD(fRegD dst)
8127 %{
8128 match(Set dst (CastDD dst));
8129
8130 size(0);
8131 format %{ "# castDD of $dst" %}
8132 ins_encode(/* empty encoding */);
8133 ins_cost(0);
8134 ins_pipe(pipe_class_empty);
8135 %}
8136
8137 instruct castVV(vReg dst)
8138 %{
8139 match(Set dst (CastVV dst));
8140
8141 size(0);
8142 format %{ "# castVV of $dst" %}
8143 ins_encode(/* empty encoding */);
8144 ins_cost(0);
8145 ins_pipe(pipe_class_empty);
8146 %}
8147
8148 // ============================================================================
8149 // Convert Instructions
8150
8151 // int to bool
8152 instruct convI2Bool(iRegINoSp dst, iRegI src)
8153 %{
8154 match(Set dst (Conv2B src));
8155
8156 ins_cost(ALU_COST);
8157 format %{ "snez $dst, $src\t#@convI2Bool" %}
8158
8159 ins_encode %{
8160 __ snez(as_Register($dst$$reg), as_Register($src$$reg));
8161 %}
8162
8163 ins_pipe(ialu_reg);
8164 %}
8165
8166 // pointer to bool
8167 instruct convP2Bool(iRegINoSp dst, iRegP src)
8168 %{
8169 match(Set dst (Conv2B src));
8170
8171 ins_cost(ALU_COST);
8172 format %{ "snez $dst, $src\t#@convP2Bool" %}
8173
8174 ins_encode %{
8175 __ snez(as_Register($dst$$reg), as_Register($src$$reg));
8176 %}
8177
8178 ins_pipe(ialu_reg);
8179 %}
8180
8181 // int <-> long
8182
8183 instruct convI2L_reg_reg(iRegLNoSp dst, iRegIorL2I src)
8184 %{
8185 match(Set dst (ConvI2L src));
8186
8187 ins_cost(ALU_COST);
8188 format %{ "addw $dst, $src, zr\t#@convI2L_reg_reg" %}
8189 ins_encode %{
8190 __ sext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8191 %}
8192 ins_pipe(ialu_reg);
8193 %}
8194
8195 instruct convL2I_reg(iRegINoSp dst, iRegL src) %{
8196 match(Set dst (ConvL2I src));
8197
8198 ins_cost(ALU_COST);
8199 format %{ "addw $dst, $src, zr\t#@convL2I_reg" %}
8200
8201 ins_encode %{
8202 __ sext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8203 %}
8204
8205 ins_pipe(ialu_reg);
8206 %}
8207
8208 // int to unsigned long (Zero-extend)
8209 instruct convI2UL_reg_reg(iRegLNoSp dst, iRegIorL2I src, immL_32bits mask)
8210 %{
8211 match(Set dst (AndL (ConvI2L src) mask));
8212
8213 ins_cost(ALU_COST * 2);
8214 format %{ "zext $dst, $src, 32\t# i2ul, #@convI2UL_reg_reg" %}
8215
8216 ins_encode %{
8217 __ zext(as_Register($dst$$reg), as_Register($src$$reg), 32);
8218 %}
8219
8220 ins_pipe(ialu_reg_shift);
8221 %}
8222
8223 // float <-> double
8224
8225 instruct convF2D_reg(fRegD dst, fRegF src) %{
8226 match(Set dst (ConvF2D src));
8227
8228 ins_cost(XFER_COST);
8229 format %{ "fcvt.d.s $dst, $src\t#@convF2D_reg" %}
8230
8231 ins_encode %{
8232 __ fcvt_d_s(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
8233 %}
8234
8235 ins_pipe(fp_f2d);
8236 %}
8237
8238 instruct convD2F_reg(fRegF dst, fRegD src) %{
8239 match(Set dst (ConvD2F src));
8240
8241 ins_cost(XFER_COST);
8242 format %{ "fcvt.s.d $dst, $src\t#@convD2F_reg" %}
8243
8244 ins_encode %{
8245 __ fcvt_s_d(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
8246 %}
8247
8248 ins_pipe(fp_d2f);
8249 %}
8250
8251 // single <-> half precision
8252
8253 instruct convHF2F_reg_reg(fRegF dst, iRegINoSp src, iRegINoSp tmp) %{
8254 match(Set dst (ConvHF2F src));
8255 effect(TEMP tmp);
8256 format %{ "fmv.h.x $dst, $src\t# move source from $src to $dst\n\t"
8257 "fcvt.s.h $dst, $dst\t# convert half to single precision"
8258 %}
8259 ins_encode %{
8260 __ float16_to_float($dst$$FloatRegister, $src$$Register, $tmp$$Register);
8261 %}
8262 ins_pipe(pipe_slow);
8263 %}
8264
8265 instruct convF2HF_reg_reg(iRegINoSp dst, fRegF src, fRegF ftmp, iRegINoSp xtmp) %{
8266 match(Set dst (ConvF2HF src));
8267 effect(TEMP_DEF dst, TEMP ftmp, TEMP xtmp);
8268 format %{ "fcvt.h.s $ftmp, $src\t# convert single precision to half\n\t"
8269 "fmv.x.h $dst, $ftmp\t# move result from $ftmp to $dst"
8270 %}
8271 ins_encode %{
8272 __ float_to_float16($dst$$Register, $src$$FloatRegister, $ftmp$$FloatRegister, $xtmp$$Register);
8273 %}
8274 ins_pipe(pipe_slow);
8275 %}
8276
8277 // half precision operations
8278
8279 instruct reinterpretS2HF(fRegF dst, iRegI src)
8280 %{
8281 match(Set dst (ReinterpretS2HF src));
8282 format %{ "fmv.h.x $dst, $src" %}
8283 ins_encode %{
8284 __ fmv_h_x($dst$$FloatRegister, $src$$Register);
8285 %}
8286 ins_pipe(fp_i2f);
8287 %}
8288
8289 instruct convF2HFAndS2HF(fRegF dst, fRegF src)
8290 %{
8291 match(Set dst (ReinterpretS2HF (ConvF2HF src)));
8292 format %{ "convF2HFAndS2HF $dst, $src" %}
8293 ins_encode %{
8294 __ fcvt_h_s($dst$$FloatRegister, $src$$FloatRegister);
8295 %}
8296 ins_pipe(fp_uop_s);
8297 %}
8298
8299 instruct reinterpretHF2S(iRegINoSp dst, fRegF src)
8300 %{
8301 match(Set dst (ReinterpretHF2S src));
8302 format %{ "fmv.x.h $dst, $src" %}
8303 ins_encode %{
8304 __ fmv_x_h($dst$$Register, $src$$FloatRegister);
8305 %}
8306 ins_pipe(fp_f2i);
8307 %}
8308
8309 instruct convHF2SAndHF2F(fRegF dst, fRegF src)
8310 %{
8311 match(Set dst (ConvHF2F (ReinterpretHF2S src)));
8312 format %{ "convHF2SAndHF2F $dst, $src" %}
8313 ins_encode %{
8314 __ fcvt_s_h($dst$$FloatRegister, $src$$FloatRegister);
8315 %}
8316 ins_pipe(fp_uop_s);
8317 %}
8318
8319 instruct sqrt_HF_reg(fRegF dst, fRegF src)
8320 %{
8321 match(Set dst (SqrtHF src));
8322 format %{ "fsqrt.h $dst, $src" %}
8323 ins_encode %{
8324 __ fsqrt_h($dst$$FloatRegister, $src$$FloatRegister);
8325 %}
8326 ins_pipe(fp_sqrt_s);
8327 %}
8328
8329 instruct binOps_HF_reg(fRegF dst, fRegF src1, fRegF src2)
8330 %{
8331 match(Set dst (AddHF src1 src2));
8332 match(Set dst (SubHF src1 src2));
8333 match(Set dst (MulHF src1 src2));
8334 match(Set dst (DivHF src1 src2));
8335 format %{ "binop_hf $dst, $src1, $src2" %}
8336 ins_encode %{
8337 int opcode = this->ideal_Opcode();
8338 switch(opcode) {
8339 case Op_AddHF: __ fadd_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8340 case Op_SubHF: __ fsub_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8341 case Op_MulHF: __ fmul_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8342 case Op_DivHF: __ fdiv_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); break;
8343 default: assert(false, "%s is not supported here", NodeClassNames[opcode]); break;
8344 }
8345 %}
8346 ins_pipe(fp_dop_reg_reg_s);
8347 %}
8348
8349 instruct min_HF_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr)
8350 %{
8351 predicate(!UseZfa);
8352 match(Set dst (MinHF src1 src2));
8353 effect(KILL cr);
8354
8355 format %{ "min_hf $dst, $src1, $src2" %}
8356
8357 ins_encode %{
8358 __ minmax_fp($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
8359 __ FLOAT_TYPE::half_precision, true /* is_min */);
8360 %}
8361 ins_pipe(pipe_class_default);
8362 %}
8363
8364 instruct min_HF_reg_zfa(fRegF dst, fRegF src1, fRegF src2)
8365 %{
8366 predicate(UseZfa);
8367 match(Set dst (MinHF src1 src2));
8368
8369 format %{ "min_hf $dst, $src1, $src2" %}
8370
8371 ins_encode %{
8372 __ fminm_h(as_FloatRegister($dst$$reg),
8373 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
8374 %}
8375
8376 ins_pipe(pipe_class_default);
8377 %}
8378
8379 instruct max_HF_reg(fRegF dst, fRegF src1, fRegF src2, rFlagsReg cr)
8380 %{
8381 predicate(!UseZfa);
8382 match(Set dst (MaxHF src1 src2));
8383 effect(KILL cr);
8384
8385 format %{ "max_hf $dst, $src1, $src2" %}
8386
8387 ins_encode %{
8388 __ minmax_fp($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister,
8389 __ FLOAT_TYPE::half_precision, false /* is_min */);
8390 %}
8391 ins_pipe(pipe_class_default);
8392 %}
8393
8394 instruct max_HF_reg_zfa(fRegF dst, fRegF src1, fRegF src2)
8395 %{
8396 predicate(UseZfa);
8397 match(Set dst (MaxHF src1 src2));
8398
8399 format %{ "max_hf $dst, $src1, $src2" %}
8400
8401 ins_encode %{
8402 __ fmaxm_h(as_FloatRegister($dst$$reg),
8403 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
8404 %}
8405
8406 ins_pipe(pipe_class_default);
8407 %}
8408
8409 instruct fma_HF_reg(fRegF dst, fRegF src1, fRegF src2, fRegF src3)
8410 %{
8411 match(Set dst (FmaHF src3 (Binary src1 src2)));
8412 format %{ "fmadd.h $dst, $src1, $src2, $src3\t# $dst = $src1 * $src2 + $src3 fma packedH" %}
8413 ins_encode %{
8414 __ fmadd_h($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
8415 %}
8416 ins_pipe(pipe_class_default);
8417 %}
8418
8419 // float <-> int
8420
8421 instruct convF2I_reg_reg(iRegINoSp dst, fRegF src) %{
8422 match(Set dst (ConvF2I src));
8423
8424 ins_cost(XFER_COST);
8425 format %{ "fcvt.w.s $dst, $src\t#@convF2I_reg_reg" %}
8426
8427 ins_encode %{
8428 __ fcvt_w_s_safe($dst$$Register, $src$$FloatRegister);
8429 %}
8430
8431 ins_pipe(fp_f2i);
8432 %}
8433
8434 instruct convI2F_reg_reg(fRegF dst, iRegIorL2I src) %{
8435 match(Set dst (ConvI2F src));
8436
8437 ins_cost(XFER_COST);
8438 format %{ "fcvt.s.w $dst, $src\t#@convI2F_reg_reg" %}
8439
8440 ins_encode %{
8441 __ fcvt_s_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8442 %}
8443
8444 ins_pipe(fp_i2f);
8445 %}
8446
8447 // float <-> long
8448
8449 instruct convF2L_reg_reg(iRegLNoSp dst, fRegF src) %{
8450 match(Set dst (ConvF2L src));
8451
8452 ins_cost(XFER_COST);
8453 format %{ "fcvt.l.s $dst, $src\t#@convF2L_reg_reg" %}
8454
8455 ins_encode %{
8456 __ fcvt_l_s_safe($dst$$Register, $src$$FloatRegister);
8457 %}
8458
8459 ins_pipe(fp_f2l);
8460 %}
8461
8462 instruct convL2F_reg_reg(fRegF dst, iRegL src) %{
8463 match(Set dst (ConvL2F src));
8464
8465 ins_cost(XFER_COST);
8466 format %{ "fcvt.s.l $dst, $src\t#@convL2F_reg_reg" %}
8467
8468 ins_encode %{
8469 __ fcvt_s_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8470 %}
8471
8472 ins_pipe(fp_l2f);
8473 %}
8474
8475 // double <-> int
8476
8477 instruct convD2I_reg_reg(iRegINoSp dst, fRegD src) %{
8478 match(Set dst (ConvD2I src));
8479
8480 ins_cost(XFER_COST);
8481 format %{ "fcvt.w.d $dst, $src\t#@convD2I_reg_reg" %}
8482
8483 ins_encode %{
8484 __ fcvt_w_d_safe($dst$$Register, $src$$FloatRegister);
8485 %}
8486
8487 ins_pipe(fp_d2i);
8488 %}
8489
8490 instruct convI2D_reg_reg(fRegD dst, iRegIorL2I src) %{
8491 match(Set dst (ConvI2D src));
8492
8493 ins_cost(XFER_COST);
8494 format %{ "fcvt.d.w $dst, $src\t#@convI2D_reg_reg" %}
8495
8496 ins_encode %{
8497 __ fcvt_d_w(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8498 %}
8499
8500 ins_pipe(fp_i2d);
8501 %}
8502
8503 // double <-> long
8504
8505 instruct convD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
8506 match(Set dst (ConvD2L src));
8507
8508 ins_cost(XFER_COST);
8509 format %{ "fcvt.l.d $dst, $src\t#@convD2L_reg_reg" %}
8510
8511 ins_encode %{
8512 __ fcvt_l_d_safe($dst$$Register, $src$$FloatRegister);
8513 %}
8514
8515 ins_pipe(fp_d2l);
8516 %}
8517
8518 instruct convL2D_reg_reg(fRegD dst, iRegL src) %{
8519 match(Set dst (ConvL2D src));
8520
8521 ins_cost(XFER_COST);
8522 format %{ "fcvt.d.l $dst, $src\t#@convL2D_reg_reg" %}
8523
8524 ins_encode %{
8525 __ fcvt_d_l(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8526 %}
8527
8528 ins_pipe(fp_l2d);
8529 %}
8530
8531 // Convert oop into int for vectors alignment masking
8532 instruct convP2I(iRegINoSp dst, iRegP src) %{
8533 match(Set dst (ConvL2I (CastP2X src)));
8534
8535 ins_cost(ALU_COST * 2);
8536 format %{ "zext $dst, $src, 32\t# ptr -> int, #@convP2I" %}
8537
8538 ins_encode %{
8539 __ zext($dst$$Register, $src$$Register, 32);
8540 %}
8541
8542 ins_pipe(ialu_reg);
8543 %}
8544
8545 // Convert compressed oop into int for vectors alignment masking
8546 // in case of 32bit oops (heap < 4Gb).
8547 instruct convN2I(iRegINoSp dst, iRegN src)
8548 %{
8549 predicate(CompressedOops::shift() == 0);
8550 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
8551
8552 ins_cost(ALU_COST);
8553 format %{ "mv $dst, $src\t# compressed ptr -> int, #@convN2I" %}
8554
8555 ins_encode %{
8556 __ mv($dst$$Register, $src$$Register);
8557 %}
8558
8559 ins_pipe(ialu_reg);
8560 %}
8561
8562 instruct round_double_reg(iRegLNoSp dst, fRegD src, fRegD ftmp) %{
8563 match(Set dst (RoundD src));
8564
8565 ins_cost(XFER_COST + BRANCH_COST);
8566 effect(TEMP ftmp);
8567 format %{ "java_round_double $dst, $src\t#@round_double_reg" %}
8568
8569 ins_encode %{
8570 __ java_round_double($dst$$Register, as_FloatRegister($src$$reg), as_FloatRegister($ftmp$$reg));
8571 %}
8572
8573 ins_pipe(pipe_slow);
8574 %}
8575
8576 instruct round_float_reg(iRegINoSp dst, fRegF src, fRegF ftmp) %{
8577 match(Set dst (RoundF src));
8578
8579 ins_cost(XFER_COST + BRANCH_COST);
8580 effect(TEMP ftmp);
8581 format %{ "java_round_float $dst, $src\t#@round_float_reg" %}
8582
8583 ins_encode %{
8584 __ java_round_float($dst$$Register, as_FloatRegister($src$$reg), as_FloatRegister($ftmp$$reg));
8585 %}
8586
8587 ins_pipe(pipe_slow);
8588 %}
8589
8590 // Convert oop pointer into compressed form
8591 instruct encodeHeapOop(iRegNNoSp dst, iRegP src) %{
8592 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
8593 match(Set dst (EncodeP src));
8594 ins_cost(ALU_COST);
8595 format %{ "encode_heap_oop $dst, $src\t#@encodeHeapOop" %}
8596 ins_encode %{
8597 Register s = $src$$Register;
8598 Register d = $dst$$Register;
8599 __ encode_heap_oop(d, s);
8600 %}
8601 ins_pipe(pipe_class_default);
8602 %}
8603
8604 instruct encodeHeapOop_not_null(iRegNNoSp dst, iRegP src) %{
8605 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
8606 match(Set dst (EncodeP src));
8607 ins_cost(ALU_COST);
8608 format %{ "encode_heap_oop_not_null $dst, $src\t#@encodeHeapOop_not_null" %}
8609 ins_encode %{
8610 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
8611 %}
8612 ins_pipe(pipe_class_default);
8613 %}
8614
8615 instruct decodeHeapOop(iRegPNoSp dst, iRegN src) %{
8616 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
8617 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
8618 match(Set dst (DecodeN src));
8619
8620 ins_cost(0);
8621 format %{ "decode_heap_oop $dst, $src\t#@decodeHeapOop" %}
8622 ins_encode %{
8623 Register s = $src$$Register;
8624 Register d = $dst$$Register;
8625 __ decode_heap_oop(d, s);
8626 %}
8627 ins_pipe(pipe_class_default);
8628 %}
8629
8630 instruct decodeHeapOop_not_null(iRegPNoSp dst, iRegN src) %{
8631 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
8632 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
8633 match(Set dst (DecodeN src));
8634
8635 ins_cost(0);
8636 format %{ "decode_heap_oop_not_null $dst, $src\t#@decodeHeapOop_not_null" %}
8637 ins_encode %{
8638 Register s = $src$$Register;
8639 Register d = $dst$$Register;
8640 __ decode_heap_oop_not_null(d, s);
8641 %}
8642 ins_pipe(pipe_class_default);
8643 %}
8644
8645 // Convert klass pointer into compressed form.
8646 instruct encodeKlass_not_null(iRegNNoSp dst, iRegP src) %{
8647 match(Set dst (EncodePKlass src));
8648
8649 ins_cost(ALU_COST);
8650 format %{ "encode_klass_not_null $dst, $src\t#@encodeKlass_not_null" %}
8651
8652 ins_encode %{
8653 Register src_reg = as_Register($src$$reg);
8654 Register dst_reg = as_Register($dst$$reg);
8655 __ encode_klass_not_null(dst_reg, src_reg, t0);
8656 %}
8657
8658 ins_pipe(pipe_class_default);
8659 %}
8660
8661 instruct decodeKlass_not_null(iRegPNoSp dst, iRegN src, iRegPNoSp tmp) %{
8662 match(Set dst (DecodeNKlass src));
8663
8664 effect(TEMP tmp);
8665
8666 ins_cost(ALU_COST);
8667 format %{ "decode_klass_not_null $dst, $src\t#@decodeKlass_not_null" %}
8668
8669 ins_encode %{
8670 Register src_reg = as_Register($src$$reg);
8671 Register dst_reg = as_Register($dst$$reg);
8672 Register tmp_reg = as_Register($tmp$$reg);
8673 __ decode_klass_not_null(dst_reg, src_reg, tmp_reg);
8674 %}
8675
8676 ins_pipe(pipe_class_default);
8677 %}
8678
8679 // stack <-> reg and reg <-> reg shuffles with no conversion
8680
8681 instruct MoveF2I_stack_reg(iRegINoSp dst, stackSlotF src) %{
8682
8683 match(Set dst (MoveF2I src));
8684
8685 effect(DEF dst, USE src);
8686
8687 ins_cost(LOAD_COST);
8688
8689 format %{ "lw $dst, $src\t#@MoveF2I_stack_reg" %}
8690
8691 ins_encode %{
8692 __ lw(as_Register($dst$$reg), Address(sp, $src$$disp));
8693 %}
8694
8695 ins_pipe(iload_reg_reg);
8696
8697 %}
8698
8699 instruct MoveI2F_stack_reg(fRegF dst, stackSlotI src) %{
8700
8701 match(Set dst (MoveI2F src));
8702
8703 effect(DEF dst, USE src);
8704
8705 ins_cost(LOAD_COST);
8706
8707 format %{ "flw $dst, $src\t#@MoveI2F_stack_reg" %}
8708
8709 ins_encode %{
8710 __ flw(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
8711 %}
8712
8713 ins_pipe(fp_load_mem_s);
8714
8715 %}
8716
8717 instruct MoveD2L_stack_reg(iRegLNoSp dst, stackSlotD src) %{
8718
8719 match(Set dst (MoveD2L src));
8720
8721 effect(DEF dst, USE src);
8722
8723 ins_cost(LOAD_COST);
8724
8725 format %{ "ld $dst, $src\t#@MoveD2L_stack_reg" %}
8726
8727 ins_encode %{
8728 __ ld(as_Register($dst$$reg), Address(sp, $src$$disp));
8729 %}
8730
8731 ins_pipe(iload_reg_reg);
8732
8733 %}
8734
8735 instruct MoveL2D_stack_reg(fRegD dst, stackSlotL src) %{
8736
8737 match(Set dst (MoveL2D src));
8738
8739 effect(DEF dst, USE src);
8740
8741 ins_cost(LOAD_COST);
8742
8743 format %{ "fld $dst, $src\t#@MoveL2D_stack_reg" %}
8744
8745 ins_encode %{
8746 __ fld(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
8747 %}
8748
8749 ins_pipe(fp_load_mem_d);
8750
8751 %}
8752
8753 instruct MoveF2I_reg_stack(stackSlotI dst, fRegF src) %{
8754
8755 match(Set dst (MoveF2I src));
8756
8757 effect(DEF dst, USE src);
8758
8759 ins_cost(STORE_COST);
8760
8761 format %{ "fsw $src, $dst\t#@MoveF2I_reg_stack" %}
8762
8763 ins_encode %{
8764 __ fsw(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
8765 %}
8766
8767 ins_pipe(fp_store_reg_s);
8768
8769 %}
8770
8771 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8772
8773 match(Set dst (MoveI2F src));
8774
8775 effect(DEF dst, USE src);
8776
8777 ins_cost(STORE_COST);
8778
8779 format %{ "sw $src, $dst\t#@MoveI2F_reg_stack" %}
8780
8781 ins_encode %{
8782 __ sw(as_Register($src$$reg), Address(sp, $dst$$disp));
8783 %}
8784
8785 ins_pipe(istore_reg_reg);
8786
8787 %}
8788
8789 instruct MoveD2L_reg_stack(stackSlotL dst, fRegD src) %{
8790
8791 match(Set dst (MoveD2L src));
8792
8793 effect(DEF dst, USE src);
8794
8795 ins_cost(STORE_COST);
8796
8797 format %{ "fsd $dst, $src\t#@MoveD2L_reg_stack" %}
8798
8799 ins_encode %{
8800 __ fsd(as_FloatRegister($src$$reg), Address(sp, $dst$$disp));
8801 %}
8802
8803 ins_pipe(fp_store_reg_d);
8804
8805 %}
8806
8807 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8808
8809 match(Set dst (MoveL2D src));
8810
8811 effect(DEF dst, USE src);
8812
8813 ins_cost(STORE_COST);
8814
8815 format %{ "sd $src, $dst\t#@MoveL2D_reg_stack" %}
8816
8817 ins_encode %{
8818 __ sd(as_Register($src$$reg), Address(sp, $dst$$disp));
8819 %}
8820
8821 ins_pipe(istore_reg_reg);
8822
8823 %}
8824
8825 instruct MoveF2I_reg_reg(iRegINoSp dst, fRegF src) %{
8826
8827 match(Set dst (MoveF2I src));
8828
8829 effect(DEF dst, USE src);
8830
8831 ins_cost(FMVX_COST);
8832
8833 format %{ "fmv.x.w $dst, $src\t#@MoveF2I_reg_reg" %}
8834
8835 ins_encode %{
8836 __ fmv_x_w(as_Register($dst$$reg), as_FloatRegister($src$$reg));
8837 %}
8838
8839 ins_pipe(fp_f2i);
8840
8841 %}
8842
8843 instruct MoveI2F_reg_reg(fRegF dst, iRegI src) %{
8844
8845 match(Set dst (MoveI2F src));
8846
8847 effect(DEF dst, USE src);
8848
8849 ins_cost(FMVX_COST);
8850
8851 format %{ "fmv.w.x $dst, $src\t#@MoveI2F_reg_reg" %}
8852
8853 ins_encode %{
8854 __ fmv_w_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8855 %}
8856
8857 ins_pipe(fp_i2f);
8858
8859 %}
8860
8861 instruct MoveD2L_reg_reg(iRegLNoSp dst, fRegD src) %{
8862
8863 match(Set dst (MoveD2L src));
8864
8865 effect(DEF dst, USE src);
8866
8867 ins_cost(FMVX_COST);
8868
8869 format %{ "fmv.x.d $dst, $src\t#@MoveD2L_reg_reg" %}
8870
8871 ins_encode %{
8872 __ fmv_x_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
8873 %}
8874
8875 ins_pipe(fp_d2l);
8876
8877 %}
8878
8879 instruct MoveL2D_reg_reg(fRegD dst, iRegL src) %{
8880
8881 match(Set dst (MoveL2D src));
8882
8883 effect(DEF dst, USE src);
8884
8885 ins_cost(FMVX_COST);
8886
8887 format %{ "fmv.d.x $dst, $src\t#@MoveL2D_reg_reg" %}
8888
8889 ins_encode %{
8890 __ fmv_d_x(as_FloatRegister($dst$$reg), as_Register($src$$reg));
8891 %}
8892
8893 ins_pipe(fp_l2d);
8894
8895 %}
8896
8897 // ============================================================================
8898 // Compare Instructions which set the result float comparisons in dest register.
8899
8900 instruct cmpF3_reg_reg(iRegINoSp dst, fRegF op1, fRegF op2)
8901 %{
8902 match(Set dst (CmpF3 op1 op2));
8903
8904 ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
8905 format %{ "flt.s $dst, $op2, $op1\t#@cmpF3_reg_reg\n\t"
8906 "bgtz $dst, done\n\t"
8907 "feq.s $dst, $op1, $op2\n\t"
8908 "addi $dst, $dst, -1\n\t"
8909 "done:"
8910 %}
8911
8912 ins_encode %{
8913 // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
8914 __ float_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg),
8915 as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
8916 %}
8917
8918 ins_pipe(pipe_class_default);
8919 %}
8920
8921 instruct cmpD3_reg_reg(iRegINoSp dst, fRegD op1, fRegD op2)
8922 %{
8923 match(Set dst (CmpD3 op1 op2));
8924
8925 ins_cost(XFER_COST * 2 + BRANCH_COST + ALU_COST);
8926 format %{ "flt.d $dst, $op2, $op1\t#@cmpD3_reg_reg\n\t"
8927 "bgtz $dst, done\n\t"
8928 "feq.d $dst, $op1, $op2\n\t"
8929 "addi $dst, $dst, -1\n\t"
8930 "done:"
8931 %}
8932
8933 ins_encode %{
8934 // we want -1 for unordered or less than, 0 for equal and 1 for greater than.
8935 __ double_compare(as_Register($dst$$reg), as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), -1 /*unordered_result < 0*/);
8936 %}
8937
8938 ins_pipe(pipe_class_default);
8939 %}
8940
8941 instruct cmpL3_reg_reg(iRegINoSp dst, iRegL op1, iRegL op2)
8942 %{
8943 match(Set dst (CmpL3 op1 op2));
8944
8945 ins_cost(ALU_COST * 3 + BRANCH_COST);
8946 format %{ "slt $dst, $op2, $op1\t#@cmpL3_reg_reg\n\t"
8947 "bnez $dst, done\n\t"
8948 "slt $dst, $op1, $op2\n\t"
8949 "neg $dst, $dst\n\t"
8950 "done:"
8951 %}
8952 ins_encode %{
8953 __ cmp_l2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
8954 __ mv(as_Register($dst$$reg), t0);
8955 %}
8956
8957 ins_pipe(pipe_class_default);
8958 %}
8959
8960 instruct cmpUL3_reg_reg(iRegINoSp dst, iRegL op1, iRegL op2)
8961 %{
8962 match(Set dst (CmpUL3 op1 op2));
8963
8964 ins_cost(ALU_COST * 3 + BRANCH_COST);
8965 format %{ "sltu $dst, $op2, $op1\t#@cmpUL3_reg_reg\n\t"
8966 "bnez $dst, done\n\t"
8967 "sltu $dst, $op1, $op2\n\t"
8968 "neg $dst, $dst\n\t"
8969 "done:"
8970 %}
8971 ins_encode %{
8972 __ cmp_ul2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
8973 __ mv(as_Register($dst$$reg), t0);
8974 %}
8975
8976 ins_pipe(pipe_class_default);
8977 %}
8978
8979 instruct cmpU3_reg_reg(iRegINoSp dst, iRegI op1, iRegI op2)
8980 %{
8981 match(Set dst (CmpU3 op1 op2));
8982
8983 ins_cost(ALU_COST * 3 + BRANCH_COST);
8984 format %{ "sltu $dst, $op2, $op1\t#@cmpU3_reg_reg\n\t"
8985 "bnez $dst, done\n\t"
8986 "sltu $dst, $op1, $op2\n\t"
8987 "neg $dst, $dst\n\t"
8988 "done:"
8989 %}
8990 ins_encode %{
8991 __ cmp_uw2i(t0, as_Register($op1$$reg), as_Register($op2$$reg));
8992 __ mv(as_Register($dst$$reg), t0);
8993 %}
8994
8995 ins_pipe(pipe_class_default);
8996 %}
8997
8998 instruct cmpLTMask_reg_reg(iRegINoSp dst, iRegI p, iRegI q)
8999 %{
9000 match(Set dst (CmpLTMask p q));
9001
9002 ins_cost(2 * ALU_COST);
9003
9004 format %{ "slt $dst, $p, $q\t#@cmpLTMask_reg_reg\n\t"
9005 "subw $dst, zr, $dst\t#@cmpLTMask_reg_reg"
9006 %}
9007
9008 ins_encode %{
9009 __ slt(as_Register($dst$$reg), as_Register($p$$reg), as_Register($q$$reg));
9010 __ subw(as_Register($dst$$reg), zr, as_Register($dst$$reg));
9011 %}
9012
9013 ins_pipe(ialu_reg_reg);
9014 %}
9015
9016 instruct cmpLTMask_reg_zero(iRegINoSp dst, iRegIorL2I op, immI0 zero)
9017 %{
9018 match(Set dst (CmpLTMask op zero));
9019
9020 ins_cost(ALU_COST);
9021
9022 format %{ "sraiw $dst, $dst, 31\t#@cmpLTMask_reg_reg" %}
9023
9024 ins_encode %{
9025 __ sraiw(as_Register($dst$$reg), as_Register($op$$reg), 31);
9026 %}
9027
9028 ins_pipe(ialu_reg_shift);
9029 %}
9030
9031
9032 // ============================================================================
9033 // Max and Min
9034
9035 instruct minI_reg_reg(iRegINoSp dst, iRegI src)
9036 %{
9037 match(Set dst (MinI dst src));
9038
9039 ins_cost(BRANCH_COST + ALU_COST);
9040 format %{"minI_reg_reg $dst, $dst, $src\t#@minI_reg_reg\n\t"%}
9041
9042 ins_encode %{
9043 __ cmov_gt(as_Register($dst$$reg), as_Register($src$$reg),
9044 as_Register($dst$$reg), as_Register($src$$reg));
9045 %}
9046
9047 ins_pipe(pipe_class_compare);
9048 %}
9049
9050 instruct maxI_reg_reg(iRegINoSp dst, iRegI src)
9051 %{
9052 match(Set dst (MaxI dst src));
9053
9054 ins_cost(BRANCH_COST + ALU_COST);
9055 format %{"maxI_reg_reg $dst, $dst, $src\t#@maxI_reg_reg\n\t"%}
9056
9057 ins_encode %{
9058 __ cmov_lt(as_Register($dst$$reg), as_Register($src$$reg),
9059 as_Register($dst$$reg), as_Register($src$$reg));
9060 %}
9061
9062 ins_pipe(pipe_class_compare);
9063 %}
9064
9065 // special case for comparing with zero
9066 // n.b. this is selected in preference to the rule above because it
9067 // avoids loading constant 0 into a source register
9068
9069 instruct minI_reg_zero(iRegINoSp dst, immI0 zero)
9070 %{
9071 match(Set dst (MinI dst zero));
9072 match(Set dst (MinI zero dst));
9073
9074 ins_cost(BRANCH_COST + ALU_COST);
9075 format %{"minI_reg_zero $dst, $dst, zr\t#@minI_reg_zero\n\t"%}
9076
9077 ins_encode %{
9078 __ cmov_gt(as_Register($dst$$reg), zr,
9079 as_Register($dst$$reg), zr);
9080 %}
9081
9082 ins_pipe(pipe_class_compare);
9083 %}
9084
9085 instruct maxI_reg_zero(iRegINoSp dst, immI0 zero)
9086 %{
9087 match(Set dst (MaxI dst zero));
9088 match(Set dst (MaxI zero dst));
9089
9090 ins_cost(BRANCH_COST + ALU_COST);
9091 format %{"maxI_reg_zero $dst, $dst, zr\t#@maxI_reg_zero\n\t"%}
9092
9093 ins_encode %{
9094 __ cmov_lt(as_Register($dst$$reg), zr,
9095 as_Register($dst$$reg), zr);
9096 %}
9097
9098 ins_pipe(pipe_class_compare);
9099 %}
9100
9101 instruct minI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
9102 %{
9103 match(Set dst (MinI src1 src2));
9104
9105 effect(DEF dst, USE src1, USE src2);
9106
9107 ins_cost(BRANCH_COST + ALU_COST * 2);
9108 format %{"minI_rReg $dst, $src1, $src2\t#@minI_rReg\n\t"%}
9109
9110 ins_encode %{
9111 __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
9112 __ cmov_gt(as_Register($src1$$reg), as_Register($src2$$reg),
9113 as_Register($dst$$reg), as_Register($src2$$reg));
9114 %}
9115
9116 ins_pipe(pipe_class_compare);
9117 %}
9118
9119 instruct maxI_rReg(iRegINoSp dst, iRegI src1, iRegI src2)
9120 %{
9121 match(Set dst (MaxI src1 src2));
9122
9123 effect(DEF dst, USE src1, USE src2);
9124
9125 ins_cost(BRANCH_COST + ALU_COST * 2);
9126 format %{"maxI_rReg $dst, $src1, $src2\t#@maxI_rReg\n\t"%}
9127
9128 ins_encode %{
9129 __ mv(as_Register($dst$$reg), as_Register($src1$$reg));
9130 __ cmov_lt(as_Register($src1$$reg), as_Register($src2$$reg),
9131 as_Register($dst$$reg), as_Register($src2$$reg));
9132 %}
9133
9134 ins_pipe(pipe_class_compare);
9135 %}
9136
9137 // ============================================================================
9138 // Branch Instructions
9139 // Direct Branch.
9140 instruct branch(label lbl)
9141 %{
9142 match(Goto);
9143
9144 effect(USE lbl);
9145
9146 ins_cost(BRANCH_COST);
9147 format %{ "j $lbl\t#@branch" %}
9148
9149 ins_encode(riscv_enc_j(lbl));
9150
9151 ins_pipe(pipe_branch);
9152 %}
9153
9154 // ============================================================================
9155 // Compare and Branch Instructions
9156
9157 // Patterns for short (< 12KiB) variants
9158
9159 // Compare flags and branch near instructions.
9160 instruct cmpFlag_branch(cmpOpEqNe cmp, rFlagsReg cr, label lbl) %{
9161 match(If cmp cr);
9162 effect(USE lbl);
9163
9164 ins_cost(BRANCH_COST);
9165 format %{ "b$cmp $cr, zr, $lbl\t#@cmpFlag_branch" %}
9166
9167 ins_encode %{
9168 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label));
9169 %}
9170 ins_pipe(pipe_cmpz_branch);
9171 ins_short_branch(1);
9172 %}
9173
9174 // Compare signed int and branch near instructions
9175 instruct cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
9176 %{
9177 // Same match rule as `far_cmpI_branch'.
9178 match(If cmp (CmpI op1 op2));
9179
9180 effect(USE lbl);
9181
9182 ins_cost(BRANCH_COST);
9183
9184 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpI_branch" %}
9185
9186 ins_encode %{
9187 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9188 %}
9189
9190 ins_pipe(pipe_cmp_branch);
9191 ins_short_branch(1);
9192 %}
9193
9194 instruct cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl)
9195 %{
9196 // Same match rule as `far_cmpI_loop'.
9197 match(CountedLoopEnd cmp (CmpI op1 op2));
9198
9199 effect(USE lbl);
9200
9201 ins_cost(BRANCH_COST);
9202
9203 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpI_loop" %}
9204
9205 ins_encode %{
9206 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9207 %}
9208
9209 ins_pipe(pipe_cmp_branch);
9210 ins_short_branch(1);
9211 %}
9212
9213 // Compare unsigned int and branch near instructions
9214 instruct cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl)
9215 %{
9216 // Same match rule as `far_cmpU_branch'.
9217 match(If cmp (CmpU op1 op2));
9218
9219 effect(USE lbl);
9220
9221 ins_cost(BRANCH_COST);
9222
9223 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpU_branch" %}
9224
9225 ins_encode %{
9226 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9227 as_Register($op2$$reg), *($lbl$$label));
9228 %}
9229
9230 ins_pipe(pipe_cmp_branch);
9231 ins_short_branch(1);
9232 %}
9233
9234 // Compare signed long and branch near instructions
9235 instruct cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
9236 %{
9237 // Same match rule as `far_cmpL_branch'.
9238 match(If cmp (CmpL op1 op2));
9239
9240 effect(USE lbl);
9241
9242 ins_cost(BRANCH_COST);
9243
9244 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpL_branch" %}
9245
9246 ins_encode %{
9247 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9248 %}
9249
9250 ins_pipe(pipe_cmp_branch);
9251 ins_short_branch(1);
9252 %}
9253
9254 instruct cmpL_loop(cmpOp cmp, iRegL op1, iRegL op2, label lbl)
9255 %{
9256 // Same match rule as `far_cmpL_loop'.
9257 match(CountedLoopEnd cmp (CmpL op1 op2));
9258
9259 effect(USE lbl);
9260
9261 ins_cost(BRANCH_COST);
9262
9263 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpL_loop" %}
9264
9265 ins_encode %{
9266 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label));
9267 %}
9268
9269 ins_pipe(pipe_cmp_branch);
9270 ins_short_branch(1);
9271 %}
9272
9273 // Compare unsigned long and branch near instructions
9274 instruct cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl)
9275 %{
9276 // Same match rule as `far_cmpUL_branch'.
9277 match(If cmp (CmpUL op1 op2));
9278
9279 effect(USE lbl);
9280
9281 ins_cost(BRANCH_COST);
9282 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpUL_branch" %}
9283
9284 ins_encode %{
9285 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9286 as_Register($op2$$reg), *($lbl$$label));
9287 %}
9288
9289 ins_pipe(pipe_cmp_branch);
9290 ins_short_branch(1);
9291 %}
9292
9293 // Compare pointer and branch near instructions
9294 instruct cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
9295 %{
9296 // Same match rule as `far_cmpP_branch'.
9297 match(If cmp (CmpP op1 op2));
9298
9299 effect(USE lbl);
9300
9301 ins_cost(BRANCH_COST);
9302
9303 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpP_branch" %}
9304
9305 ins_encode %{
9306 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9307 as_Register($op2$$reg), *($lbl$$label));
9308 %}
9309
9310 ins_pipe(pipe_cmp_branch);
9311 ins_short_branch(1);
9312 %}
9313
9314 // Compare narrow pointer and branch near instructions
9315 instruct cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
9316 %{
9317 // Same match rule as `far_cmpN_branch'.
9318 match(If cmp (CmpN op1 op2));
9319
9320 effect(USE lbl);
9321
9322 ins_cost(BRANCH_COST);
9323
9324 format %{ "b$cmp $op1, $op2, $lbl\t#@cmpN_branch" %}
9325
9326 ins_encode %{
9327 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9328 as_Register($op2$$reg), *($lbl$$label));
9329 %}
9330
9331 ins_pipe(pipe_cmp_branch);
9332 ins_short_branch(1);
9333 %}
9334
9335 // Compare float and branch near instructions
9336 instruct cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
9337 %{
9338 // Same match rule as `far_cmpF_branch'.
9339 match(If cmp (CmpF op1 op2));
9340
9341 effect(USE lbl);
9342
9343 ins_cost(XFER_COST + BRANCH_COST);
9344 format %{ "float_b$cmp $op1, $op2, $lbl \t#@cmpF_branch"%}
9345
9346 ins_encode %{
9347 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg), *($lbl$$label));
9348 %}
9349
9350 ins_pipe(pipe_class_compare);
9351 ins_short_branch(1);
9352 %}
9353
9354 // Compare double and branch near instructions
9355 instruct cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
9356 %{
9357 // Same match rule as `far_cmpD_branch'.
9358 match(If cmp (CmpD op1 op2));
9359 effect(USE lbl);
9360
9361 ins_cost(XFER_COST + BRANCH_COST);
9362 format %{ "double_b$cmp $op1, $op2, $lbl\t#@cmpD_branch"%}
9363
9364 ins_encode %{
9365 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
9366 as_FloatRegister($op2$$reg), *($lbl$$label));
9367 %}
9368
9369 ins_pipe(pipe_class_compare);
9370 ins_short_branch(1);
9371 %}
9372
9373 // Compare signed int with zero and branch near instructions
9374 instruct cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9375 %{
9376 // Same match rule as `far_cmpI_reg_imm0_branch'.
9377 match(If cmp (CmpI op1 zero));
9378
9379 effect(USE op1, USE lbl);
9380
9381 ins_cost(BRANCH_COST);
9382 format %{ "b$cmp $op1, zr, $lbl\t#@cmpI_reg_imm0_branch" %}
9383
9384 ins_encode %{
9385 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9386 %}
9387
9388 ins_pipe(pipe_cmpz_branch);
9389 ins_short_branch(1);
9390 %}
9391
9392 instruct cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9393 %{
9394 // Same match rule as `far_cmpI_reg_imm0_loop'.
9395 match(CountedLoopEnd cmp (CmpI op1 zero));
9396
9397 effect(USE op1, USE lbl);
9398
9399 ins_cost(BRANCH_COST);
9400
9401 format %{ "b$cmp $op1, zr, $lbl\t#@cmpI_reg_imm0_loop" %}
9402
9403 ins_encode %{
9404 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9405 %}
9406
9407 ins_pipe(pipe_cmpz_branch);
9408 ins_short_branch(1);
9409 %}
9410
9411 // Compare unsigned int with zero and branch near instructions
9412 instruct cmpUEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
9413 %{
9414 // Same match rule as `far_cmpUEqNeLeGt_reg_imm0_branch'.
9415 match(If cmp (CmpU op1 zero));
9416
9417 effect(USE op1, USE lbl);
9418
9419 ins_cost(BRANCH_COST);
9420
9421 format %{ "b$cmp $op1, zr, $lbl\t#@cmpUEqNeLeGt_reg_imm0_branch" %}
9422
9423 ins_encode %{
9424 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9425 %}
9426
9427 ins_pipe(pipe_cmpz_branch);
9428 ins_short_branch(1);
9429 %}
9430
9431 // Compare signed long with zero and branch near instructions
9432 instruct cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9433 %{
9434 // Same match rule as `far_cmpL_reg_imm0_branch'.
9435 match(If cmp (CmpL op1 zero));
9436
9437 effect(USE op1, USE lbl);
9438
9439 ins_cost(BRANCH_COST);
9440
9441 format %{ "b$cmp $op1, zr, $lbl\t#@cmpL_reg_imm0_branch" %}
9442
9443 ins_encode %{
9444 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9445 %}
9446
9447 ins_pipe(pipe_cmpz_branch);
9448 ins_short_branch(1);
9449 %}
9450
9451 instruct cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9452 %{
9453 // Same match rule as `far_cmpL_reg_imm0_loop'.
9454 match(CountedLoopEnd cmp (CmpL op1 zero));
9455
9456 effect(USE op1, USE lbl);
9457
9458 ins_cost(BRANCH_COST);
9459
9460 format %{ "b$cmp $op1, zr, $lbl\t#@cmpL_reg_imm0_loop" %}
9461
9462 ins_encode %{
9463 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label));
9464 %}
9465
9466 ins_pipe(pipe_cmpz_branch);
9467 ins_short_branch(1);
9468 %}
9469
9470 // Compare unsigned long with zero and branch near instructions
9471 instruct cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
9472 %{
9473 // Same match rule as `far_cmpULEqNeLeGt_reg_imm0_branch'.
9474 match(If cmp (CmpUL op1 zero));
9475
9476 effect(USE op1, USE lbl);
9477
9478 ins_cost(BRANCH_COST);
9479
9480 format %{ "b$cmp $op1, zr, $lbl\t#@cmpULEqNeLeGt_reg_imm0_branch" %}
9481
9482 ins_encode %{
9483 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9484 %}
9485
9486 ins_pipe(pipe_cmpz_branch);
9487 ins_short_branch(1);
9488 %}
9489
9490 // Compare pointer with zero and branch near instructions
9491 instruct cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
9492 // Same match rule as `far_cmpP_reg_imm0_branch'.
9493 match(If cmp (CmpP op1 zero));
9494 effect(USE lbl);
9495
9496 ins_cost(BRANCH_COST);
9497 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_imm0_branch" %}
9498
9499 ins_encode %{
9500 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9501 %}
9502
9503 ins_pipe(pipe_cmpz_branch);
9504 ins_short_branch(1);
9505 %}
9506
9507 // Compare narrow pointer with zero and branch near instructions
9508 instruct cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
9509 // Same match rule as `far_cmpN_reg_imm0_branch'.
9510 match(If cmp (CmpN op1 zero));
9511 effect(USE lbl);
9512
9513 ins_cost(BRANCH_COST);
9514
9515 format %{ "b$cmp $op1, zr, $lbl\t#@cmpN_imm0_branch" %}
9516
9517 ins_encode %{
9518 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9519 %}
9520
9521 ins_pipe(pipe_cmpz_branch);
9522 ins_short_branch(1);
9523 %}
9524
9525 // Compare narrow pointer with pointer zero and branch near instructions
9526 instruct cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
9527 // Same match rule as `far_cmpP_narrowOop_imm0_branch'.
9528 match(If cmp (CmpP (DecodeN op1) zero));
9529 effect(USE lbl);
9530
9531 ins_cost(BRANCH_COST);
9532 format %{ "b$cmp $op1, zr, $lbl\t#@cmpP_narrowOop_imm0_branch" %}
9533
9534 ins_encode %{
9535 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label));
9536 %}
9537
9538 ins_pipe(pipe_cmpz_branch);
9539 ins_short_branch(1);
9540 %}
9541
9542 // Patterns for far (20KiB) variants
9543
9544 instruct far_cmpFlag_branch(cmpOp cmp, rFlagsReg cr, label lbl) %{
9545 match(If cmp cr);
9546 effect(USE lbl);
9547
9548 ins_cost(BRANCH_COST);
9549 format %{ "far_b$cmp $cr, zr, $lbl\t#@far_cmpFlag_branch"%}
9550
9551 ins_encode %{
9552 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($cr$$reg), *($lbl$$label), /* is_far */ true);
9553 %}
9554
9555 ins_pipe(pipe_cmpz_branch);
9556 %}
9557
9558 // Compare signed int and branch far instructions
9559 instruct far_cmpI_branch(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
9560 match(If cmp (CmpI op1 op2));
9561 effect(USE lbl);
9562
9563 ins_cost(BRANCH_COST * 2);
9564
9565 // the format instruction [far_b$cmp] here is be used as two insructions
9566 // in macroassembler: b$not_cmp(op1, op2, done), j($lbl), bind(done)
9567 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpI_branch" %}
9568
9569 ins_encode %{
9570 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9571 %}
9572
9573 ins_pipe(pipe_cmp_branch);
9574 %}
9575
9576 instruct far_cmpI_loop(cmpOp cmp, iRegI op1, iRegI op2, label lbl) %{
9577 match(CountedLoopEnd cmp (CmpI op1 op2));
9578 effect(USE lbl);
9579
9580 ins_cost(BRANCH_COST * 2);
9581 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpI_loop" %}
9582
9583 ins_encode %{
9584 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9585 %}
9586
9587 ins_pipe(pipe_cmp_branch);
9588 %}
9589
9590 instruct far_cmpU_branch(cmpOpU cmp, iRegI op1, iRegI op2, label lbl) %{
9591 match(If cmp (CmpU op1 op2));
9592 effect(USE lbl);
9593
9594 ins_cost(BRANCH_COST * 2);
9595 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpU_branch" %}
9596
9597 ins_encode %{
9598 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9599 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9600 %}
9601
9602 ins_pipe(pipe_cmp_branch);
9603 %}
9604
9605 instruct far_cmpL_branch(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
9606 match(If cmp (CmpL op1 op2));
9607 effect(USE lbl);
9608
9609 ins_cost(BRANCH_COST * 2);
9610 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpL_branch" %}
9611
9612 ins_encode %{
9613 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9614 %}
9615
9616 ins_pipe(pipe_cmp_branch);
9617 %}
9618
9619 instruct far_cmpLloop(cmpOp cmp, iRegL op1, iRegL op2, label lbl) %{
9620 match(CountedLoopEnd cmp (CmpL op1 op2));
9621 effect(USE lbl);
9622
9623 ins_cost(BRANCH_COST * 2);
9624 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpL_loop" %}
9625
9626 ins_encode %{
9627 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9628 %}
9629
9630 ins_pipe(pipe_cmp_branch);
9631 %}
9632
9633 instruct far_cmpUL_branch(cmpOpU cmp, iRegL op1, iRegL op2, label lbl) %{
9634 match(If cmp (CmpUL op1 op2));
9635 effect(USE lbl);
9636
9637 ins_cost(BRANCH_COST * 2);
9638 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpUL_branch" %}
9639
9640 ins_encode %{
9641 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9642 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9643 %}
9644
9645 ins_pipe(pipe_cmp_branch);
9646 %}
9647
9648 instruct far_cmpP_branch(cmpOpU cmp, iRegP op1, iRegP op2, label lbl)
9649 %{
9650 match(If cmp (CmpP op1 op2));
9651
9652 effect(USE lbl);
9653
9654 ins_cost(BRANCH_COST * 2);
9655
9656 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpP_branch" %}
9657
9658 ins_encode %{
9659 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9660 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9661 %}
9662
9663 ins_pipe(pipe_cmp_branch);
9664 %}
9665
9666 instruct far_cmpN_branch(cmpOpU cmp, iRegN op1, iRegN op2, label lbl)
9667 %{
9668 match(If cmp (CmpN op1 op2));
9669
9670 effect(USE lbl);
9671
9672 ins_cost(BRANCH_COST * 2);
9673
9674 format %{ "far_b$cmp $op1, $op2, $lbl\t#@far_cmpN_branch" %}
9675
9676 ins_encode %{
9677 __ cmp_branch($cmp$$cmpcode | C2_MacroAssembler::unsigned_branch_mask, as_Register($op1$$reg),
9678 as_Register($op2$$reg), *($lbl$$label), /* is_far */ true);
9679 %}
9680
9681 ins_pipe(pipe_cmp_branch);
9682 %}
9683
9684 // Float compare and branch instructions
9685 instruct far_cmpF_branch(cmpOp cmp, fRegF op1, fRegF op2, label lbl)
9686 %{
9687 match(If cmp (CmpF op1 op2));
9688
9689 effect(USE lbl);
9690
9691 ins_cost(XFER_COST + BRANCH_COST * 2);
9692 format %{ "far_float_b$cmp $op1, $op2, $lbl\t#@far_cmpF_branch"%}
9693
9694 ins_encode %{
9695 __ float_cmp_branch($cmp$$cmpcode, as_FloatRegister($op1$$reg), as_FloatRegister($op2$$reg),
9696 *($lbl$$label), /* is_far */ true);
9697 %}
9698
9699 ins_pipe(pipe_class_compare);
9700 %}
9701
9702 // Double compare and branch instructions
9703 instruct far_cmpD_branch(cmpOp cmp, fRegD op1, fRegD op2, label lbl)
9704 %{
9705 match(If cmp (CmpD op1 op2));
9706 effect(USE lbl);
9707
9708 ins_cost(XFER_COST + BRANCH_COST * 2);
9709 format %{ "far_double_b$cmp $op1, $op2, $lbl\t#@far_cmpD_branch"%}
9710
9711 ins_encode %{
9712 __ float_cmp_branch($cmp$$cmpcode | C2_MacroAssembler::double_branch_mask, as_FloatRegister($op1$$reg),
9713 as_FloatRegister($op2$$reg), *($lbl$$label), /* is_far */ true);
9714 %}
9715
9716 ins_pipe(pipe_class_compare);
9717 %}
9718
9719 instruct far_cmpI_reg_imm0_branch(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9720 %{
9721 match(If cmp (CmpI op1 zero));
9722
9723 effect(USE op1, USE lbl);
9724
9725 ins_cost(BRANCH_COST * 2);
9726
9727 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpI_reg_imm0_branch" %}
9728
9729 ins_encode %{
9730 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
9731 %}
9732
9733 ins_pipe(pipe_cmpz_branch);
9734 %}
9735
9736 instruct far_cmpI_reg_imm0_loop(cmpOp cmp, iRegI op1, immI0 zero, label lbl)
9737 %{
9738 match(CountedLoopEnd cmp (CmpI op1 zero));
9739
9740 effect(USE op1, USE lbl);
9741
9742 ins_cost(BRANCH_COST * 2);
9743
9744 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpI_reg_imm0_loop" %}
9745
9746 ins_encode %{
9747 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
9748 %}
9749
9750 ins_pipe(pipe_cmpz_branch);
9751 %}
9752
9753 instruct far_cmpUEqNeLeGt_imm0_branch(cmpOpUEqNeLeGt cmp, iRegI op1, immI0 zero, label lbl)
9754 %{
9755 match(If cmp (CmpU op1 zero));
9756
9757 effect(USE op1, USE lbl);
9758
9759 ins_cost(BRANCH_COST * 2);
9760
9761 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpUEqNeLeGt_imm0_branch" %}
9762
9763 ins_encode %{
9764 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9765 %}
9766
9767 ins_pipe(pipe_cmpz_branch);
9768 %}
9769
9770 // compare lt/ge unsigned instructs has no short instruct with same match
9771 instruct far_cmpULtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegI op1, immI0 zero, label lbl)
9772 %{
9773 match(If cmp (CmpU op1 zero));
9774
9775 effect(USE op1, USE lbl);
9776
9777 ins_cost(BRANCH_COST);
9778
9779 format %{ "j $lbl if $cmp == ge\t#@far_cmpULtGe_reg_imm0_branch" %}
9780
9781 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
9782
9783 ins_pipe(pipe_cmpz_branch);
9784 %}
9785
9786 instruct far_cmpL_reg_imm0_branch(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9787 %{
9788 match(If cmp (CmpL op1 zero));
9789
9790 effect(USE op1, USE lbl);
9791
9792 ins_cost(BRANCH_COST * 2);
9793
9794 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpL_reg_imm0_branch" %}
9795
9796 ins_encode %{
9797 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
9798 %}
9799
9800 ins_pipe(pipe_cmpz_branch);
9801 %}
9802
9803 instruct far_cmpL_reg_imm0_loop(cmpOp cmp, iRegL op1, immL0 zero, label lbl)
9804 %{
9805 match(CountedLoopEnd cmp (CmpL op1 zero));
9806
9807 effect(USE op1, USE lbl);
9808
9809 ins_cost(BRANCH_COST * 2);
9810
9811 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpL_reg_imm0_loop" %}
9812
9813 ins_encode %{
9814 __ cmp_branch($cmp$$cmpcode, as_Register($op1$$reg), zr, *($lbl$$label), /* is_far */ true);
9815 %}
9816
9817 ins_pipe(pipe_cmpz_branch);
9818 %}
9819
9820 instruct far_cmpULEqNeLeGt_reg_imm0_branch(cmpOpUEqNeLeGt cmp, iRegL op1, immL0 zero, label lbl)
9821 %{
9822 match(If cmp (CmpUL op1 zero));
9823
9824 effect(USE op1, USE lbl);
9825
9826 ins_cost(BRANCH_COST * 2);
9827
9828 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpULEqNeLeGt_reg_imm0_branch" %}
9829
9830 ins_encode %{
9831 __ enc_cmpUEqNeLeGt_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9832 %}
9833
9834 ins_pipe(pipe_cmpz_branch);
9835 %}
9836
9837 // compare lt/ge unsigned instructs has no short instruct with same match
9838 instruct far_cmpULLtGe_reg_imm0_branch(cmpOpULtGe cmp, iRegL op1, immL0 zero, label lbl)
9839 %{
9840 match(If cmp (CmpUL op1 zero));
9841
9842 effect(USE op1, USE lbl);
9843
9844 ins_cost(BRANCH_COST);
9845
9846 format %{ "j $lbl if $cmp == ge\t#@far_cmpULLtGe_reg_imm0_branch" %}
9847
9848 ins_encode(riscv_enc_far_cmpULtGe_imm0_branch(cmp, op1, lbl));
9849
9850 ins_pipe(pipe_cmpz_branch);
9851 %}
9852
9853 instruct far_cmpP_imm0_branch(cmpOpEqNe cmp, iRegP op1, immP0 zero, label lbl) %{
9854 match(If cmp (CmpP op1 zero));
9855 effect(USE lbl);
9856
9857 ins_cost(BRANCH_COST * 2);
9858 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_imm0_branch" %}
9859
9860 ins_encode %{
9861 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9862 %}
9863
9864 ins_pipe(pipe_cmpz_branch);
9865 %}
9866
9867 instruct far_cmpN_imm0_branch(cmpOpEqNe cmp, iRegN op1, immN0 zero, label lbl) %{
9868 match(If cmp (CmpN op1 zero));
9869 effect(USE lbl);
9870
9871 ins_cost(BRANCH_COST * 2);
9872
9873 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpN_imm0_branch" %}
9874
9875 ins_encode %{
9876 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9877 %}
9878
9879 ins_pipe(pipe_cmpz_branch);
9880 %}
9881
9882 instruct far_cmpP_narrowOop_imm0_branch(cmpOpEqNe cmp, iRegN op1, immP0 zero, label lbl) %{
9883 match(If cmp (CmpP (DecodeN op1) zero));
9884 effect(USE lbl);
9885
9886 ins_cost(BRANCH_COST * 2);
9887 format %{ "far_b$cmp $op1, zr, $lbl\t#@far_cmpP_narrowOop_imm0_branch" %}
9888
9889 ins_encode %{
9890 __ enc_cmpEqNe_imm0_branch($cmp$$cmpcode, as_Register($op1$$reg), *($lbl$$label), /* is_far */ true);
9891 %}
9892
9893 ins_pipe(pipe_cmpz_branch);
9894 %}
9895
9896 // ============================================================================
9897 // Conditional Move Instructions
9898 instruct cmovI_cmpI(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOp cop) %{
9899 match(Set dst (CMoveI (Binary cop (CmpI op1 op2)) (Binary dst src)));
9900 ins_cost(ALU_COST + BRANCH_COST);
9901
9902 format %{
9903 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpI\n\t"
9904 %}
9905
9906 ins_encode %{
9907 __ enc_cmove($cop$$cmpcode,
9908 as_Register($op1$$reg), as_Register($op2$$reg),
9909 as_Register($dst$$reg), as_Register($src$$reg));
9910 %}
9911
9912 ins_pipe(pipe_class_compare);
9913 %}
9914
9915 instruct cmovI_cmpU(iRegINoSp dst, iRegI src, iRegI op1, iRegI op2, cmpOpU cop) %{
9916 match(Set dst (CMoveI (Binary cop (CmpU op1 op2)) (Binary dst src)));
9917 ins_cost(ALU_COST + BRANCH_COST);
9918
9919 format %{
9920 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpU\n\t"
9921 %}
9922
9923 ins_encode %{
9924 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
9925 as_Register($op1$$reg), as_Register($op2$$reg),
9926 as_Register($dst$$reg), as_Register($src$$reg));
9927 %}
9928
9929 ins_pipe(pipe_class_compare);
9930 %}
9931
9932 instruct cmovI_cmpL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOp cop) %{
9933 match(Set dst (CMoveI (Binary cop (CmpL op1 op2)) (Binary dst src)));
9934 ins_cost(ALU_COST + BRANCH_COST);
9935
9936 format %{
9937 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpL\n\t"
9938 %}
9939
9940 ins_encode %{
9941 __ enc_cmove($cop$$cmpcode,
9942 as_Register($op1$$reg), as_Register($op2$$reg),
9943 as_Register($dst$$reg), as_Register($src$$reg));
9944 %}
9945
9946 ins_pipe(pipe_class_compare);
9947 %}
9948
9949 instruct cmovI_cmpUL(iRegINoSp dst, iRegI src, iRegL op1, iRegL op2, cmpOpU cop) %{
9950 match(Set dst (CMoveI (Binary cop (CmpUL op1 op2)) (Binary dst src)));
9951 ins_cost(ALU_COST + BRANCH_COST);
9952
9953 format %{
9954 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpUL\n\t"
9955 %}
9956
9957 ins_encode %{
9958 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
9959 as_Register($op1$$reg), as_Register($op2$$reg),
9960 as_Register($dst$$reg), as_Register($src$$reg));
9961 %}
9962
9963 ins_pipe(pipe_class_compare);
9964 %}
9965
9966 instruct cmovI_cmpN(iRegINoSp dst, iRegI src, iRegN op1, iRegN op2, cmpOpU cop) %{
9967 match(Set dst (CMoveI (Binary cop (CmpN op1 op2)) (Binary dst src)));
9968 ins_cost(ALU_COST + BRANCH_COST);
9969
9970 format %{
9971 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpN\n\t"
9972 %}
9973
9974 ins_encode %{
9975 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
9976 as_Register($op1$$reg), as_Register($op2$$reg),
9977 as_Register($dst$$reg), as_Register($src$$reg));
9978 %}
9979
9980 ins_pipe(pipe_class_compare);
9981 %}
9982
9983 instruct cmovI_cmpP(iRegINoSp dst, iRegI src, iRegP op1, iRegP op2, cmpOpU cop) %{
9984 match(Set dst (CMoveI (Binary cop (CmpP op1 op2)) (Binary dst src)));
9985 ins_cost(ALU_COST + BRANCH_COST);
9986
9987 format %{
9988 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovI_cmpP\n\t"
9989 %}
9990
9991 ins_encode %{
9992 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
9993 as_Register($op1$$reg), as_Register($op2$$reg),
9994 as_Register($dst$$reg), as_Register($src$$reg));
9995 %}
9996
9997 ins_pipe(pipe_class_compare);
9998 %}
9999
10000 instruct cmovL_cmpL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOp cop) %{
10001 match(Set dst (CMoveL (Binary cop (CmpL op1 op2)) (Binary dst src)));
10002 ins_cost(ALU_COST + BRANCH_COST);
10003
10004 format %{
10005 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpL\n\t"
10006 %}
10007
10008 ins_encode %{
10009 __ enc_cmove($cop$$cmpcode,
10010 as_Register($op1$$reg), as_Register($op2$$reg),
10011 as_Register($dst$$reg), as_Register($src$$reg));
10012 %}
10013
10014 ins_pipe(pipe_class_compare);
10015 %}
10016
10017 instruct cmovL_cmpUL(iRegLNoSp dst, iRegL src, iRegL op1, iRegL op2, cmpOpU cop) %{
10018 match(Set dst (CMoveL (Binary cop (CmpUL op1 op2)) (Binary dst src)));
10019 ins_cost(ALU_COST + BRANCH_COST);
10020
10021 format %{
10022 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpUL\n\t"
10023 %}
10024
10025 ins_encode %{
10026 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10027 as_Register($op1$$reg), as_Register($op2$$reg),
10028 as_Register($dst$$reg), as_Register($src$$reg));
10029 %}
10030
10031 ins_pipe(pipe_class_compare);
10032 %}
10033
10034 instruct cmovL_cmpI(iRegLNoSp dst, iRegL src, iRegI op1, iRegI op2, cmpOp cop) %{
10035 match(Set dst (CMoveL (Binary cop (CmpI op1 op2)) (Binary dst src)));
10036 ins_cost(ALU_COST + BRANCH_COST);
10037
10038 format %{
10039 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpI\n\t"
10040 %}
10041
10042 ins_encode %{
10043 __ enc_cmove($cop$$cmpcode,
10044 as_Register($op1$$reg), as_Register($op2$$reg),
10045 as_Register($dst$$reg), as_Register($src$$reg));
10046 %}
10047
10048 ins_pipe(pipe_class_compare);
10049 %}
10050
10051 instruct cmovL_cmpU(iRegLNoSp dst, iRegL src, iRegI op1, iRegI op2, cmpOpU cop) %{
10052 match(Set dst (CMoveL (Binary cop (CmpU op1 op2)) (Binary dst src)));
10053 ins_cost(ALU_COST + BRANCH_COST);
10054
10055 format %{
10056 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpU\n\t"
10057 %}
10058
10059 ins_encode %{
10060 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10061 as_Register($op1$$reg), as_Register($op2$$reg),
10062 as_Register($dst$$reg), as_Register($src$$reg));
10063 %}
10064
10065 ins_pipe(pipe_class_compare);
10066 %}
10067
10068 instruct cmovL_cmpN(iRegLNoSp dst, iRegL src, iRegN op1, iRegN op2, cmpOpU cop) %{
10069 match(Set dst (CMoveL (Binary cop (CmpN op1 op2)) (Binary dst src)));
10070 ins_cost(ALU_COST + BRANCH_COST);
10071
10072 format %{
10073 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpN\n\t"
10074 %}
10075
10076 ins_encode %{
10077 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10078 as_Register($op1$$reg), as_Register($op2$$reg),
10079 as_Register($dst$$reg), as_Register($src$$reg));
10080 %}
10081
10082 ins_pipe(pipe_class_compare);
10083 %}
10084
10085 instruct cmovL_cmpP(iRegLNoSp dst, iRegL src, iRegP op1, iRegP op2, cmpOpU cop) %{
10086 match(Set dst (CMoveL (Binary cop (CmpP op1 op2)) (Binary dst src)));
10087 ins_cost(ALU_COST + BRANCH_COST);
10088
10089 format %{
10090 "CMove $dst, ($op1 $cop $op2), $dst, $src\t#@cmovL_cmpP\n\t"
10091 %}
10092
10093 ins_encode %{
10094 __ enc_cmove($cop$$cmpcode | C2_MacroAssembler::unsigned_branch_mask,
10095 as_Register($op1$$reg), as_Register($op2$$reg),
10096 as_Register($dst$$reg), as_Register($src$$reg));
10097 %}
10098
10099 ins_pipe(pipe_class_compare);
10100 %}
10101
10102 // ============================================================================
10103 // Procedure Call/Return Instructions
10104
10105 // Call Java Static Instruction
10106 // Note: If this code changes, the corresponding ret_addr_offset() and
10107 // compute_padding() functions will have to be adjusted.
10108 instruct CallStaticJavaDirect(method meth)
10109 %{
10110 match(CallStaticJava);
10111
10112 effect(USE meth);
10113
10114 ins_cost(BRANCH_COST);
10115
10116 format %{ "CALL,static $meth\t#@CallStaticJavaDirect" %}
10117
10118 ins_encode(riscv_enc_java_static_call(meth),
10119 riscv_enc_call_epilog);
10120
10121 ins_pipe(pipe_class_call);
10122 ins_alignment(4);
10123 %}
10124
10125 // TO HERE
10126
10127 // Call Java Dynamic Instruction
10128 // Note: If this code changes, the corresponding ret_addr_offset() and
10129 // compute_padding() functions will have to be adjusted.
10130 instruct CallDynamicJavaDirect(method meth)
10131 %{
10132 match(CallDynamicJava);
10133
10134 effect(USE meth);
10135
10136 ins_cost(BRANCH_COST + ALU_COST * 5);
10137
10138 format %{ "CALL,dynamic $meth\t#@CallDynamicJavaDirect" %}
10139
10140 ins_encode(riscv_enc_java_dynamic_call(meth),
10141 riscv_enc_call_epilog);
10142
10143 ins_pipe(pipe_class_call);
10144 ins_alignment(4);
10145 %}
10146
10147 // Call Runtime Instruction
10148
10149 instruct CallRuntimeDirect(method meth)
10150 %{
10151 match(CallRuntime);
10152
10153 effect(USE meth);
10154
10155 ins_cost(BRANCH_COST);
10156
10157 format %{ "CALL, runtime $meth\t#@CallRuntimeDirect" %}
10158
10159 ins_encode(riscv_enc_java_to_runtime(meth));
10160
10161 ins_pipe(pipe_class_call);
10162 %}
10163
10164 // Call Runtime Instruction
10165
10166 instruct CallLeafDirect(method meth)
10167 %{
10168 match(CallLeaf);
10169
10170 effect(USE meth);
10171
10172 ins_cost(BRANCH_COST);
10173
10174 format %{ "CALL, runtime leaf $meth\t#@CallLeafDirect" %}
10175
10176 ins_encode(riscv_enc_java_to_runtime(meth));
10177
10178 ins_pipe(pipe_class_call);
10179 %}
10180
10181 // Call Runtime Instruction without safepoint and with vector arguments
10182
10183 instruct CallLeafDirectVector(method meth)
10184 %{
10185 match(CallLeafVector);
10186
10187 effect(USE meth);
10188
10189 ins_cost(BRANCH_COST);
10190
10191 format %{ "CALL, runtime leaf vector $meth" %}
10192
10193 ins_encode(riscv_enc_java_to_runtime(meth));
10194
10195 ins_pipe(pipe_class_call);
10196 %}
10197
10198 // Call Runtime Instruction
10199
10200 instruct CallLeafNoFPDirect(method meth)
10201 %{
10202 match(CallLeafNoFP);
10203
10204 effect(USE meth);
10205
10206 ins_cost(BRANCH_COST);
10207
10208 format %{ "CALL, runtime leaf nofp $meth\t#@CallLeafNoFPDirect" %}
10209
10210 ins_encode(riscv_enc_java_to_runtime(meth));
10211
10212 ins_pipe(pipe_class_call);
10213 %}
10214
10215 // ============================================================================
10216 // Partial Subtype Check
10217 //
10218 // superklass array for an instance of the superklass. Set a hidden
10219 // internal cache on a hit (cache is checked with exposed code in
10220 // gen_subtype_check()). Return zero for a hit. The encoding
10221 // ALSO sets flags.
10222
10223 instruct partialSubtypeCheck(iRegP_R15 result, iRegP_R14 sub, iRegP_R10 super, iRegP_R12 tmp, rFlagsReg cr)
10224 %{
10225 predicate(!UseSecondarySupersTable);
10226 match(Set result (PartialSubtypeCheck sub super));
10227 effect(KILL tmp, KILL cr);
10228
10229 ins_cost(20 * DEFAULT_COST);
10230 format %{ "partialSubtypeCheck $result, $sub, $super\t#@partialSubtypeCheck" %}
10231
10232 ins_encode(riscv_enc_partial_subtype_check(sub, super, tmp, result));
10233
10234 opcode(0x1); // Force zero of result reg on hit
10235
10236 ins_pipe(pipe_class_memory);
10237 %}
10238
10239 // Two versions of partialSubtypeCheck, both used when we need to
10240 // search for a super class in the secondary supers array. The first
10241 // is used when we don't know _a priori_ the class being searched
10242 // for. The second, far more common, is used when we do know: this is
10243 // used for instanceof, checkcast, and any case where C2 can determine
10244 // it by constant propagation.
10245
10246 instruct partialSubtypeCheckVarSuper(iRegP_R14 sub, iRegP_R10 super, iRegP_R15 result,
10247 iRegP_R11 tmpR11, iRegP_R12 tmpR12, iRegP_R13 tmpR13,
10248 iRegP_R16 tmpR16, rFlagsReg cr)
10249 %{
10250 predicate(UseSecondarySupersTable);
10251 match(Set result (PartialSubtypeCheck sub super));
10252 effect(TEMP tmpR11, TEMP tmpR12, TEMP tmpR13, TEMP tmpR16, KILL cr);
10253
10254 ins_cost(10 * DEFAULT_COST); // slightly larger than the next version
10255 format %{ "partialSubtypeCheck $result, $sub, $super" %}
10256
10257 ins_encode %{
10258 __ lookup_secondary_supers_table_var($sub$$Register, $super$$Register, $result$$Register,
10259 $tmpR11$$Register, $tmpR12$$Register, $tmpR13$$Register,
10260 $tmpR16$$Register, nullptr /*L_success*/);
10261 %}
10262
10263 ins_pipe(pipe_class_memory);
10264 %}
10265
10266 instruct partialSubtypeCheckConstSuper(iRegP_R14 sub, iRegP_R10 super_reg, immP super_con, iRegP_R15 result,
10267 iRegP_R11 tmpR11, iRegP_R12 tmpR12, iRegP_R13 tmpR13, iRegP_R16 tmpR16, rFlagsReg cr)
10268 %{
10269 predicate(UseSecondarySupersTable);
10270 match(Set result (PartialSubtypeCheck sub (Binary super_reg super_con)));
10271 effect(TEMP tmpR11, TEMP tmpR12, TEMP tmpR13, TEMP tmpR16, KILL cr);
10272
10273 ins_cost(5 * DEFAULT_COST); // needs to be less than competing nodes
10274 format %{ "partialSubtypeCheck $result, $sub, $super_reg, $super_con" %}
10275
10276 ins_encode %{
10277 bool success = false;
10278 u1 super_klass_slot = ((Klass*)$super_con$$constant)->hash_slot();
10279 if (InlineSecondarySupersTest) {
10280 success = __ lookup_secondary_supers_table_const($sub$$Register, $super_reg$$Register, $result$$Register,
10281 $tmpR11$$Register, $tmpR12$$Register, $tmpR13$$Register,
10282 $tmpR16$$Register, super_klass_slot);
10283 } else {
10284 address call = __ reloc_call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_stub(super_klass_slot)));
10285 success = (call != nullptr);
10286 }
10287 if (!success) {
10288 ciEnv::current()->record_failure("CodeCache is full");
10289 return;
10290 }
10291 %}
10292
10293 ins_pipe(pipe_class_memory);
10294 %}
10295
10296 instruct string_compareU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10297 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10298 %{
10299 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UU);
10300 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10301 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10302
10303 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareU" %}
10304 ins_encode %{
10305 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10306 __ string_compare($str1$$Register, $str2$$Register,
10307 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10308 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10309 StrIntrinsicNode::UU);
10310 %}
10311 ins_pipe(pipe_class_memory);
10312 %}
10313
10314 instruct string_compareL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10315 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10316 %{
10317 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LL);
10318 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10319 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10320
10321 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareL" %}
10322 ins_encode %{
10323 __ string_compare($str1$$Register, $str2$$Register,
10324 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10325 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10326 StrIntrinsicNode::LL);
10327 %}
10328 ins_pipe(pipe_class_memory);
10329 %}
10330
10331 instruct string_compareUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10332 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3, rFlagsReg cr)
10333 %{
10334 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::UL);
10335 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10336 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10337
10338 format %{"String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareUL" %}
10339 ins_encode %{
10340 __ string_compare($str1$$Register, $str2$$Register,
10341 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10342 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10343 StrIntrinsicNode::UL);
10344 %}
10345 ins_pipe(pipe_class_memory);
10346 %}
10347
10348 instruct string_compareLU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10349 iRegI_R10 result, iRegP_R28 tmp1, iRegL_R29 tmp2, iRegL_R30 tmp3,
10350 rFlagsReg cr)
10351 %{
10352 predicate(!UseRVV && ((StrCompNode *)n)->encoding() == StrIntrinsicNode::LU);
10353 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10354 effect(KILL tmp1, KILL tmp2, KILL tmp3, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10355
10356 format %{ "String Compare $str1, $cnt1, $str2, $cnt2 -> $result\t#@string_compareLU" %}
10357 ins_encode %{
10358 __ string_compare($str1$$Register, $str2$$Register,
10359 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10360 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10361 StrIntrinsicNode::LU);
10362 %}
10363 ins_pipe(pipe_class_memory);
10364 %}
10365
10366 instruct string_indexofUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10367 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10368 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10369 %{
10370 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
10371 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10372 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10373 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10374
10375 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UU)" %}
10376 ins_encode %{
10377 __ string_indexof($str1$$Register, $str2$$Register,
10378 $cnt1$$Register, $cnt2$$Register,
10379 $tmp1$$Register, $tmp2$$Register,
10380 $tmp3$$Register, $tmp4$$Register,
10381 $tmp5$$Register, $tmp6$$Register,
10382 $result$$Register, StrIntrinsicNode::UU);
10383 %}
10384 ins_pipe(pipe_class_memory);
10385 %}
10386
10387 instruct string_indexofLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10388 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10389 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10390 %{
10391 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10392 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10393 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10394 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10395
10396 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (LL)" %}
10397 ins_encode %{
10398 __ string_indexof($str1$$Register, $str2$$Register,
10399 $cnt1$$Register, $cnt2$$Register,
10400 $tmp1$$Register, $tmp2$$Register,
10401 $tmp3$$Register, $tmp4$$Register,
10402 $tmp5$$Register, $tmp6$$Register,
10403 $result$$Register, StrIntrinsicNode::LL);
10404 %}
10405 ins_pipe(pipe_class_memory);
10406 %}
10407
10408 instruct string_indexofUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2, iRegI_R14 cnt2,
10409 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2, iRegINoSp tmp3,
10410 iRegINoSp tmp4, iRegINoSp tmp5, iRegINoSp tmp6, rFlagsReg cr)
10411 %{
10412 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10413 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10414 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, TEMP_DEF result,
10415 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6, KILL cr);
10416 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result (UL)" %}
10417
10418 ins_encode %{
10419 __ string_indexof($str1$$Register, $str2$$Register,
10420 $cnt1$$Register, $cnt2$$Register,
10421 $tmp1$$Register, $tmp2$$Register,
10422 $tmp3$$Register, $tmp4$$Register,
10423 $tmp5$$Register, $tmp6$$Register,
10424 $result$$Register, StrIntrinsicNode::UL);
10425 %}
10426 ins_pipe(pipe_class_memory);
10427 %}
10428
10429 instruct string_indexof_conUU(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10430 immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10431 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10432 %{
10433 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
10434 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10435 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10436 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10437
10438 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UU)" %}
10439
10440 ins_encode %{
10441 int icnt2 = (int)$int_cnt2$$constant;
10442 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10443 $cnt1$$Register, zr,
10444 $tmp1$$Register, $tmp2$$Register,
10445 $tmp3$$Register, $tmp4$$Register,
10446 icnt2, $result$$Register, StrIntrinsicNode::UU);
10447 %}
10448 ins_pipe(pipe_class_memory);
10449 %}
10450
10451 instruct string_indexof_conLL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10452 immI_le_4 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10453 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10454 %{
10455 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10456 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10457 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10458 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10459
10460 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (LL)" %}
10461 ins_encode %{
10462 int icnt2 = (int)$int_cnt2$$constant;
10463 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10464 $cnt1$$Register, zr,
10465 $tmp1$$Register, $tmp2$$Register,
10466 $tmp3$$Register, $tmp4$$Register,
10467 icnt2, $result$$Register, StrIntrinsicNode::LL);
10468 %}
10469 ins_pipe(pipe_class_memory);
10470 %}
10471
10472 instruct string_indexof_conUL(iRegP_R11 str1, iRegI_R12 cnt1, iRegP_R13 str2,
10473 immI_1 int_cnt2, iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10474 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10475 %{
10476 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10477 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10478 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, TEMP_DEF result,
10479 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10480
10481 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result (UL)" %}
10482 ins_encode %{
10483 int icnt2 = (int)$int_cnt2$$constant;
10484 __ string_indexof_linearscan($str1$$Register, $str2$$Register,
10485 $cnt1$$Register, zr,
10486 $tmp1$$Register, $tmp2$$Register,
10487 $tmp3$$Register, $tmp4$$Register,
10488 icnt2, $result$$Register, StrIntrinsicNode::UL);
10489 %}
10490 ins_pipe(pipe_class_memory);
10491 %}
10492
10493 instruct stringU_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
10494 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10495 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10496 %{
10497 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10498 predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U));
10499 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
10500 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10501
10502 format %{ "StringUTF16 IndexOf char[] $str1, $cnt1, $ch -> $result" %}
10503 ins_encode %{
10504 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
10505 $result$$Register, $tmp1$$Register, $tmp2$$Register,
10506 $tmp3$$Register, $tmp4$$Register, false /* isU */);
10507 %}
10508 ins_pipe(pipe_class_memory);
10509 %}
10510
10511
10512 instruct stringL_indexof_char(iRegP_R11 str1, iRegI_R12 cnt1, iRegI_R13 ch,
10513 iRegI_R10 result, iRegINoSp tmp1, iRegINoSp tmp2,
10514 iRegINoSp tmp3, iRegINoSp tmp4, rFlagsReg cr)
10515 %{
10516 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10517 predicate(!UseRVV && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L));
10518 effect(USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP_DEF result,
10519 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr);
10520
10521 format %{ "StringLatin1 IndexOf char[] $str1, $cnt1, $ch -> $result" %}
10522 ins_encode %{
10523 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register,
10524 $result$$Register, $tmp1$$Register, $tmp2$$Register,
10525 $tmp3$$Register, $tmp4$$Register, true /* isL */);
10526 %}
10527 ins_pipe(pipe_class_memory);
10528 %}
10529
10530 // clearing of an array
10531 instruct clearArray_reg_reg(iRegL_R29 cnt, iRegP_R28 base, iRegP_R30 tmp1,
10532 iRegP_R31 tmp2, rFlagsReg cr, Universe dummy)
10533 %{
10534 // temp registers must match the one used in StubGenerator::generate_zero_blocks()
10535 predicate(UseBlockZeroing || !UseRVV);
10536 match(Set dummy (ClearArray cnt base));
10537 effect(USE_KILL cnt, USE_KILL base, TEMP tmp1, TEMP tmp2, KILL cr);
10538
10539 ins_cost(4 * DEFAULT_COST);
10540 format %{ "ClearArray $cnt, $base\t#@clearArray_reg_reg" %}
10541
10542 ins_encode %{
10543 address tpc = __ zero_words($base$$Register, $cnt$$Register);
10544 if (tpc == nullptr) {
10545 ciEnv::current()->record_failure("CodeCache is full");
10546 return;
10547 }
10548 %}
10549
10550 ins_pipe(pipe_class_memory);
10551 %}
10552
10553 instruct clearArray_imm_reg(immL cnt, iRegP_R28 base, Universe dummy, rFlagsReg cr)
10554 %{
10555 predicate(!UseRVV && (uint64_t)n->in(2)->get_long()
10556 < (uint64_t)(BlockZeroingLowLimit >> LogBytesPerWord));
10557 match(Set dummy (ClearArray cnt base));
10558 effect(USE_KILL base, KILL cr);
10559
10560 ins_cost(4 * DEFAULT_COST);
10561 format %{ "ClearArray $cnt, $base\t#@clearArray_imm_reg" %}
10562
10563 ins_encode %{
10564 __ zero_words($base$$Register, (uint64_t)$cnt$$constant);
10565 %}
10566
10567 ins_pipe(pipe_class_memory);
10568 %}
10569
10570 instruct string_equalsL(iRegP_R11 str1, iRegP_R13 str2, iRegI_R14 cnt,
10571 iRegI_R10 result, rFlagsReg cr)
10572 %{
10573 predicate(!UseRVV && ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10574 match(Set result (StrEquals (Binary str1 str2) cnt));
10575 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL cr);
10576
10577 format %{ "String Equals $str1, $str2, $cnt -> $result\t#@string_equalsL" %}
10578 ins_encode %{
10579 // Count is in 8-bit bytes; non-Compact chars are 16 bits.
10580 __ string_equals($str1$$Register, $str2$$Register,
10581 $result$$Register, $cnt$$Register);
10582 %}
10583 ins_pipe(pipe_class_memory);
10584 %}
10585
10586 instruct array_equalsB(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
10587 iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3)
10588 %{
10589 predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10590 match(Set result (AryEq ary1 ary2));
10591 effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3);
10592
10593 format %{ "Array Equals $ary1, $ary2 -> $result\t#@array_equalsB // KILL all" %}
10594 ins_encode %{
10595 __ arrays_equals($ary1$$Register, $ary2$$Register,
10596 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10597 $result$$Register, 1);
10598 %}
10599 ins_pipe(pipe_class_memory);
10600 %}
10601
10602 instruct array_equalsC(iRegP_R11 ary1, iRegP_R12 ary2, iRegI_R10 result,
10603 iRegP_R13 tmp1, iRegP_R14 tmp2, iRegP_R15 tmp3)
10604 %{
10605 predicate(!UseRVV && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10606 match(Set result (AryEq ary1 ary2));
10607 effect(USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, TEMP tmp3);
10608
10609 format %{ "Array Equals $ary1, $ary2 -> $result\t#@array_equalsC // KILL all" %}
10610 ins_encode %{
10611 __ arrays_equals($ary1$$Register, $ary2$$Register,
10612 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10613 $result$$Register, 2);
10614 %}
10615 ins_pipe(pipe_class_memory);
10616 %}
10617
10618 // fast ArraysSupport.vectorizedHashCode
10619 instruct arrays_hashcode(iRegP_R11 ary, iRegI_R12 cnt, iRegI_R10 result, immI basic_type,
10620 iRegLNoSp tmp1, iRegLNoSp tmp2,
10621 iRegLNoSp tmp3, iRegLNoSp tmp4,
10622 iRegLNoSp tmp5, iRegLNoSp tmp6, rFlagsReg cr)
10623 %{
10624 match(Set result (VectorizedHashCode (Binary ary cnt) (Binary result basic_type)));
10625 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, TEMP tmp6,
10626 USE_KILL ary, USE_KILL cnt, USE basic_type, KILL cr);
10627
10628 format %{ "Array HashCode array[] $ary,$cnt,$result,$basic_type -> $result // KILL all" %}
10629 ins_encode %{
10630 __ arrays_hashcode($ary$$Register, $cnt$$Register, $result$$Register,
10631 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10632 $tmp4$$Register, $tmp5$$Register, $tmp6$$Register,
10633 (BasicType)$basic_type$$constant);
10634 %}
10635 ins_pipe(pipe_class_memory);
10636 %}
10637
10638 // ============================================================================
10639 // Safepoint Instructions
10640
10641 instruct safePoint(iRegP poll)
10642 %{
10643 match(SafePoint poll);
10644
10645 ins_cost(2 * LOAD_COST);
10646 format %{
10647 "lwu zr, [$poll]\t# Safepoint: poll for GC, #@safePoint"
10648 %}
10649 ins_encode %{
10650 __ read_polling_page(as_Register($poll$$reg), 0, relocInfo::poll_type);
10651 %}
10652 ins_pipe(pipe_serial); // ins_pipe(iload_reg_mem);
10653 %}
10654
10655 // ============================================================================
10656 // This name is KNOWN by the ADLC and cannot be changed.
10657 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
10658 // for this guy.
10659 instruct tlsLoadP(javaThread_RegP dst)
10660 %{
10661 match(Set dst (ThreadLocal));
10662
10663 ins_cost(0);
10664
10665 format %{ " -- \t// $dst=Thread::current(), empty, #@tlsLoadP" %}
10666
10667 size(0);
10668
10669 ins_encode( /*empty*/ );
10670
10671 ins_pipe(pipe_class_empty);
10672 %}
10673
10674 // inlined locking and unlocking
10675 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
10676 instruct cmpFastLock(rFlagsReg cr, iRegP object, iRegP box,
10677 iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3, iRegPNoSp tmp4)
10678 %{
10679 predicate(LockingMode != LM_LIGHTWEIGHT);
10680 match(Set cr (FastLock object box));
10681 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4);
10682
10683 ins_cost(10 * DEFAULT_COST);
10684 format %{ "fastlock $object,$box\t! kills $tmp1,$tmp2,$tmp3,$tmp4 #@cmpFastLock" %}
10685
10686 ins_encode %{
10687 __ fast_lock($object$$Register, $box$$Register,
10688 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
10689 %}
10690
10691 ins_pipe(pipe_serial);
10692 %}
10693
10694 // using t1 as the 'flag' register to bridge the BoolNode producers and consumers
10695 instruct cmpFastUnlock(rFlagsReg cr, iRegP object, iRegP box, iRegPNoSp tmp1, iRegPNoSp tmp2)
10696 %{
10697 predicate(LockingMode != LM_LIGHTWEIGHT);
10698 match(Set cr (FastUnlock object box));
10699 effect(TEMP tmp1, TEMP tmp2);
10700
10701 ins_cost(10 * DEFAULT_COST);
10702 format %{ "fastunlock $object,$box\t! kills $tmp1, $tmp2, #@cmpFastUnlock" %}
10703
10704 ins_encode %{
10705 __ fast_unlock($object$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register);
10706 %}
10707
10708 ins_pipe(pipe_serial);
10709 %}
10710
10711 instruct cmpFastLockLightweight(rFlagsReg cr, iRegP object, iRegP box,
10712 iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3, iRegPNoSp tmp4)
10713 %{
10714 predicate(LockingMode == LM_LIGHTWEIGHT);
10715 match(Set cr (FastLock object box));
10716 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4);
10717
10718 ins_cost(10 * DEFAULT_COST);
10719 format %{ "fastlock $object,$box\t! kills $tmp1,$tmp2,$tmp3,$tmp4 #@cmpFastLockLightweight" %}
10720
10721 ins_encode %{
10722 __ fast_lock_lightweight($object$$Register, $box$$Register,
10723 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
10724 %}
10725
10726 ins_pipe(pipe_serial);
10727 %}
10728
10729 instruct cmpFastUnlockLightweight(rFlagsReg cr, iRegP object, iRegP box,
10730 iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3)
10731 %{
10732 predicate(LockingMode == LM_LIGHTWEIGHT);
10733 match(Set cr (FastUnlock object box));
10734 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10735
10736 ins_cost(10 * DEFAULT_COST);
10737 format %{ "fastunlock $object,$box\t! kills $tmp1,$tmp2,$tmp3 #@cmpFastUnlockLightweight" %}
10738
10739 ins_encode %{
10740 __ fast_unlock_lightweight($object$$Register, $box$$Register,
10741 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register);
10742 %}
10743
10744 ins_pipe(pipe_serial);
10745 %}
10746
10747 // Tail Call; Jump from runtime stub to Java code.
10748 // Also known as an 'interprocedural jump'.
10749 // Target of jump will eventually return to caller.
10750 // TailJump below removes the return address.
10751 // Don't use fp for 'jump_target' because a MachEpilogNode has already been
10752 // emitted just above the TailCall which has reset fp to the caller state.
10753 instruct TailCalljmpInd(iRegPNoSpNoFp jump_target, inline_cache_RegP method_oop)
10754 %{
10755 match(TailCall jump_target method_oop);
10756
10757 ins_cost(BRANCH_COST);
10758
10759 format %{ "jalr $jump_target\t# $method_oop holds method oop, #@TailCalljmpInd." %}
10760
10761 ins_encode(riscv_enc_tail_call(jump_target));
10762
10763 ins_pipe(pipe_class_call);
10764 %}
10765
10766 instruct TailjmpInd(iRegPNoSpNoFp jump_target, iRegP_R10 ex_oop)
10767 %{
10768 match(TailJump jump_target ex_oop);
10769
10770 ins_cost(ALU_COST + BRANCH_COST);
10771
10772 format %{ "jalr $jump_target\t# $ex_oop holds exception oop, #@TailjmpInd." %}
10773
10774 ins_encode(riscv_enc_tail_jmp(jump_target));
10775
10776 ins_pipe(pipe_class_call);
10777 %}
10778
10779 // Forward exception.
10780 instruct ForwardExceptionjmp()
10781 %{
10782 match(ForwardException);
10783
10784 ins_cost(BRANCH_COST);
10785
10786 format %{ "j forward_exception_stub\t#@ForwardException" %}
10787
10788 ins_encode %{
10789 __ far_jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
10790 %}
10791
10792 ins_pipe(pipe_class_call);
10793 %}
10794
10795 // Create exception oop: created by stack-crawling runtime code.
10796 // Created exception is now available to this handler, and is setup
10797 // just prior to jumping to this handler. No code emitted.
10798 instruct CreateException(iRegP_R10 ex_oop)
10799 %{
10800 match(Set ex_oop (CreateEx));
10801
10802 ins_cost(0);
10803 format %{ " -- \t// exception oop; no code emitted, #@CreateException" %}
10804
10805 size(0);
10806
10807 ins_encode( /*empty*/ );
10808
10809 ins_pipe(pipe_class_empty);
10810 %}
10811
10812 // Rethrow exception: The exception oop will come in the first
10813 // argument position. Then JUMP (not call) to the rethrow stub code.
10814 instruct RethrowException()
10815 %{
10816 match(Rethrow);
10817
10818 ins_cost(BRANCH_COST);
10819
10820 format %{ "j rethrow_stub\t#@RethrowException" %}
10821
10822 ins_encode(riscv_enc_rethrow());
10823
10824 ins_pipe(pipe_class_call);
10825 %}
10826
10827 // Return Instruction
10828 // epilog node loads ret address into ra as part of frame pop
10829 instruct Ret()
10830 %{
10831 match(Return);
10832
10833 ins_cost(BRANCH_COST);
10834 format %{ "ret\t// return register, #@Ret" %}
10835
10836 ins_encode(riscv_enc_ret());
10837
10838 ins_pipe(pipe_branch);
10839 %}
10840
10841 // Die now.
10842 instruct ShouldNotReachHere() %{
10843 match(Halt);
10844
10845 ins_cost(BRANCH_COST);
10846
10847 format %{ "#@ShouldNotReachHere" %}
10848
10849 ins_encode %{
10850 if (is_reachable()) {
10851 __ stop(_halt_reason);
10852 }
10853 %}
10854
10855 ins_pipe(pipe_class_default);
10856 %}
10857
10858
10859 //----------PEEPHOLE RULES-----------------------------------------------------
10860 // These must follow all instruction definitions as they use the names
10861 // defined in the instructions definitions.
10862 //
10863 // peepmatch ( root_instr_name [preceding_instruction]* );
10864 //
10865 // peepconstraint %{
10866 // (instruction_number.operand_name relational_op instruction_number.operand_name
10867 // [, ...] );
10868 // // instruction numbers are zero-based using left to right order in peepmatch
10869 //
10870 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10871 // // provide an instruction_number.operand_name for each operand that appears
10872 // // in the replacement instruction's match rule
10873 //
10874 // ---------VM FLAGS---------------------------------------------------------
10875 //
10876 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10877 //
10878 // Each peephole rule is given an identifying number starting with zero and
10879 // increasing by one in the order seen by the parser. An individual peephole
10880 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10881 // on the command-line.
10882 //
10883 // ---------CURRENT LIMITATIONS----------------------------------------------
10884 //
10885 // Only match adjacent instructions in same basic block
10886 // Only equality constraints
10887 // Only constraints between operands, not (0.dest_reg == RAX_enc)
10888 // Only one replacement instruction
10889 //
10890 //----------SMARTSPILL RULES---------------------------------------------------
10891 // These must follow all instruction definitions as they use the names
10892 // defined in the instructions definitions.
10893
10894 // Local Variables:
10895 // mode: c++
10896 // End: