1 //
2 // Copyright (c) 2003, 2025, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // architecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131 reg_def R16 (SOC, SOC, Op_RegI, 16, r16->as_VMReg());
132 reg_def R16_H(SOC, SOC, Op_RegI, 16, r16->as_VMReg()->next());
133
134 reg_def R17 (SOC, SOC, Op_RegI, 17, r17->as_VMReg());
135 reg_def R17_H(SOC, SOC, Op_RegI, 17, r17->as_VMReg()->next());
136
137 reg_def R18 (SOC, SOC, Op_RegI, 18, r18->as_VMReg());
138 reg_def R18_H(SOC, SOC, Op_RegI, 18, r18->as_VMReg()->next());
139
140 reg_def R19 (SOC, SOC, Op_RegI, 19, r19->as_VMReg());
141 reg_def R19_H(SOC, SOC, Op_RegI, 19, r19->as_VMReg()->next());
142
143 reg_def R20 (SOC, SOC, Op_RegI, 20, r20->as_VMReg());
144 reg_def R20_H(SOC, SOC, Op_RegI, 20, r20->as_VMReg()->next());
145
146 reg_def R21 (SOC, SOC, Op_RegI, 21, r21->as_VMReg());
147 reg_def R21_H(SOC, SOC, Op_RegI, 21, r21->as_VMReg()->next());
148
149 reg_def R22 (SOC, SOC, Op_RegI, 22, r22->as_VMReg());
150 reg_def R22_H(SOC, SOC, Op_RegI, 22, r22->as_VMReg()->next());
151
152 reg_def R23 (SOC, SOC, Op_RegI, 23, r23->as_VMReg());
153 reg_def R23_H(SOC, SOC, Op_RegI, 23, r23->as_VMReg()->next());
154
155 reg_def R24 (SOC, SOC, Op_RegI, 24, r24->as_VMReg());
156 reg_def R24_H(SOC, SOC, Op_RegI, 24, r24->as_VMReg()->next());
157
158 reg_def R25 (SOC, SOC, Op_RegI, 25, r25->as_VMReg());
159 reg_def R25_H(SOC, SOC, Op_RegI, 25, r25->as_VMReg()->next());
160
161 reg_def R26 (SOC, SOC, Op_RegI, 26, r26->as_VMReg());
162 reg_def R26_H(SOC, SOC, Op_RegI, 26, r26->as_VMReg()->next());
163
164 reg_def R27 (SOC, SOC, Op_RegI, 27, r27->as_VMReg());
165 reg_def R27_H(SOC, SOC, Op_RegI, 27, r27->as_VMReg()->next());
166
167 reg_def R28 (SOC, SOC, Op_RegI, 28, r28->as_VMReg());
168 reg_def R28_H(SOC, SOC, Op_RegI, 28, r28->as_VMReg()->next());
169
170 reg_def R29 (SOC, SOC, Op_RegI, 29, r29->as_VMReg());
171 reg_def R29_H(SOC, SOC, Op_RegI, 29, r29->as_VMReg()->next());
172
173 reg_def R30 (SOC, SOC, Op_RegI, 30, r30->as_VMReg());
174 reg_def R30_H(SOC, SOC, Op_RegI, 30, r30->as_VMReg()->next());
175
176 reg_def R31 (SOC, SOC, Op_RegI, 31, r31->as_VMReg());
177 reg_def R31_H(SOC, SOC, Op_RegI, 31, r31->as_VMReg()->next());
178
179 // Floating Point Registers
180
181 // Specify priority of register selection within phases of register
182 // allocation. Highest priority is first. A useful heuristic is to
183 // give registers a low priority when they are required by machine
184 // instructions, like EAX and EDX on I486, and choose no-save registers
185 // before save-on-call, & save-on-call before save-on-entry. Registers
186 // which participate in fixed calling sequences should come last.
187 // Registers which are used as pairs must fall on an even boundary.
188
189 alloc_class chunk0(R10, R10_H,
190 R11, R11_H,
191 R8, R8_H,
192 R9, R9_H,
193 R12, R12_H,
194 RCX, RCX_H,
195 RBX, RBX_H,
196 RDI, RDI_H,
197 RDX, RDX_H,
198 RSI, RSI_H,
199 RAX, RAX_H,
200 RBP, RBP_H,
201 R13, R13_H,
202 R14, R14_H,
203 R15, R15_H,
204 R16, R16_H,
205 R17, R17_H,
206 R18, R18_H,
207 R19, R19_H,
208 R20, R20_H,
209 R21, R21_H,
210 R22, R22_H,
211 R23, R23_H,
212 R24, R24_H,
213 R25, R25_H,
214 R26, R26_H,
215 R27, R27_H,
216 R28, R28_H,
217 R29, R29_H,
218 R30, R30_H,
219 R31, R31_H,
220 RSP, RSP_H);
221
222
223 //----------Architecture Description Register Classes--------------------------
224 // Several register classes are automatically defined based upon information in
225 // this architecture description.
226 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
227 // 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
228 //
229
230 // Empty register class.
231 reg_class no_reg();
232
233 // Class for all pointer/long registers including APX extended GPRs.
234 reg_class all_reg(RAX, RAX_H,
235 RDX, RDX_H,
236 RBP, RBP_H,
237 RDI, RDI_H,
238 RSI, RSI_H,
239 RCX, RCX_H,
240 RBX, RBX_H,
241 RSP, RSP_H,
242 R8, R8_H,
243 R9, R9_H,
244 R10, R10_H,
245 R11, R11_H,
246 R12, R12_H,
247 R13, R13_H,
248 R14, R14_H,
249 R15, R15_H,
250 R16, R16_H,
251 R17, R17_H,
252 R18, R18_H,
253 R19, R19_H,
254 R20, R20_H,
255 R21, R21_H,
256 R22, R22_H,
257 R23, R23_H,
258 R24, R24_H,
259 R25, R25_H,
260 R26, R26_H,
261 R27, R27_H,
262 R28, R28_H,
263 R29, R29_H,
264 R30, R30_H,
265 R31, R31_H);
266
267 // Class for all int registers including APX extended GPRs.
268 reg_class all_int_reg(RAX
269 RDX,
270 RBP,
271 RDI,
272 RSI,
273 RCX,
274 RBX,
275 R8,
276 R9,
277 R10,
278 R11,
279 R12,
280 R13,
281 R14,
282 R16,
283 R17,
284 R18,
285 R19,
286 R20,
287 R21,
288 R22,
289 R23,
290 R24,
291 R25,
292 R26,
293 R27,
294 R28,
295 R29,
296 R30,
297 R31);
298
299 // Class for all pointer registers
300 reg_class any_reg %{
301 return _ANY_REG_mask;
302 %}
303
304 // Class for all pointer registers (excluding RSP)
305 reg_class ptr_reg %{
306 return _PTR_REG_mask;
307 %}
308
309 // Class for all pointer registers (excluding RSP and RBP)
310 reg_class ptr_reg_no_rbp %{
311 return _PTR_REG_NO_RBP_mask;
312 %}
313
314 // Class for all pointer registers (excluding RAX and RSP)
315 reg_class ptr_no_rax_reg %{
316 return _PTR_NO_RAX_REG_mask;
317 %}
318
319 // Class for all pointer registers (excluding RAX, RBX, and RSP)
320 reg_class ptr_no_rax_rbx_reg %{
321 return _PTR_NO_RAX_RBX_REG_mask;
322 %}
323
324 // Class for all long registers (excluding RSP)
325 reg_class long_reg %{
326 return _LONG_REG_mask;
327 %}
328
329 // Class for all long registers (excluding RAX, RDX and RSP)
330 reg_class long_no_rax_rdx_reg %{
331 return _LONG_NO_RAX_RDX_REG_mask;
332 %}
333
334 // Class for all long registers (excluding RCX and RSP)
335 reg_class long_no_rcx_reg %{
336 return _LONG_NO_RCX_REG_mask;
337 %}
338
339 // Class for all long registers (excluding RBP and R13)
340 reg_class long_no_rbp_r13_reg %{
341 return _LONG_NO_RBP_R13_REG_mask;
342 %}
343
344 // Class for all int registers (excluding RSP)
345 reg_class int_reg %{
346 return _INT_REG_mask;
347 %}
348
349 // Class for all int registers (excluding RAX, RDX, and RSP)
350 reg_class int_no_rax_rdx_reg %{
351 return _INT_NO_RAX_RDX_REG_mask;
352 %}
353
354 // Class for all int registers (excluding RCX and RSP)
355 reg_class int_no_rcx_reg %{
356 return _INT_NO_RCX_REG_mask;
357 %}
358
359 // Class for all int registers (excluding RBP and R13)
360 reg_class int_no_rbp_r13_reg %{
361 return _INT_NO_RBP_R13_REG_mask;
362 %}
363
364 // Singleton class for RAX pointer register
365 reg_class ptr_rax_reg(RAX, RAX_H);
366
367 // Singleton class for RBX pointer register
368 reg_class ptr_rbx_reg(RBX, RBX_H);
369
370 // Singleton class for RSI pointer register
371 reg_class ptr_rsi_reg(RSI, RSI_H);
372
373 // Singleton class for RBP pointer register
374 reg_class ptr_rbp_reg(RBP, RBP_H);
375
376 // Singleton class for RDI pointer register
377 reg_class ptr_rdi_reg(RDI, RDI_H);
378
379 // Singleton class for stack pointer
380 reg_class ptr_rsp_reg(RSP, RSP_H);
381
382 // Singleton class for TLS pointer
383 reg_class ptr_r15_reg(R15, R15_H);
384
385 // Singleton class for RAX long register
386 reg_class long_rax_reg(RAX, RAX_H);
387
388 // Singleton class for RCX long register
389 reg_class long_rcx_reg(RCX, RCX_H);
390
391 // Singleton class for RDX long register
392 reg_class long_rdx_reg(RDX, RDX_H);
393
394 // Singleton class for R11 long register
395 reg_class long_r11_reg(R11, R11_H);
396
397 // Singleton class for RAX int register
398 reg_class int_rax_reg(RAX);
399
400 // Singleton class for RBX int register
401 reg_class int_rbx_reg(RBX);
402
403 // Singleton class for RCX int register
404 reg_class int_rcx_reg(RCX);
405
406 // Singleton class for RDX int register
407 reg_class int_rdx_reg(RDX);
408
409 // Singleton class for RDI int register
410 reg_class int_rdi_reg(RDI);
411
412 // Singleton class for instruction pointer
413 // reg_class ip_reg(RIP);
414
415 %}
416
417 //----------SOURCE BLOCK-------------------------------------------------------
418 // This is a block of C++ code which provides values, functions, and
419 // definitions necessary in the rest of the architecture description
420
421 source_hpp %{
422
423 #include "peephole_x86_64.hpp"
424
425 %}
426
427 // Register masks
428 source_hpp %{
429
430 extern RegMask _ANY_REG_mask;
431 extern RegMask _PTR_REG_mask;
432 extern RegMask _PTR_REG_NO_RBP_mask;
433 extern RegMask _PTR_NO_RAX_REG_mask;
434 extern RegMask _PTR_NO_RAX_RBX_REG_mask;
435 extern RegMask _LONG_REG_mask;
436 extern RegMask _LONG_NO_RAX_RDX_REG_mask;
437 extern RegMask _LONG_NO_RCX_REG_mask;
438 extern RegMask _LONG_NO_RBP_R13_REG_mask;
439 extern RegMask _INT_REG_mask;
440 extern RegMask _INT_NO_RAX_RDX_REG_mask;
441 extern RegMask _INT_NO_RCX_REG_mask;
442 extern RegMask _INT_NO_RBP_R13_REG_mask;
443 extern RegMask _FLOAT_REG_mask;
444
445 extern RegMask _STACK_OR_PTR_REG_mask;
446 extern RegMask _STACK_OR_LONG_REG_mask;
447 extern RegMask _STACK_OR_INT_REG_mask;
448
449 inline const RegMask& STACK_OR_PTR_REG_mask() { return _STACK_OR_PTR_REG_mask; }
450 inline const RegMask& STACK_OR_LONG_REG_mask() { return _STACK_OR_LONG_REG_mask; }
451 inline const RegMask& STACK_OR_INT_REG_mask() { return _STACK_OR_INT_REG_mask; }
452
453 %}
454
455 source %{
456 #define RELOC_IMM64 Assembler::imm_operand
457 #define RELOC_DISP32 Assembler::disp32_operand
458
459 #define __ masm->
460
461 RegMask _ANY_REG_mask;
462 RegMask _PTR_REG_mask;
463 RegMask _PTR_REG_NO_RBP_mask;
464 RegMask _PTR_NO_RAX_REG_mask;
465 RegMask _PTR_NO_RAX_RBX_REG_mask;
466 RegMask _LONG_REG_mask;
467 RegMask _LONG_NO_RAX_RDX_REG_mask;
468 RegMask _LONG_NO_RCX_REG_mask;
469 RegMask _LONG_NO_RBP_R13_REG_mask;
470 RegMask _INT_REG_mask;
471 RegMask _INT_NO_RAX_RDX_REG_mask;
472 RegMask _INT_NO_RCX_REG_mask;
473 RegMask _INT_NO_RBP_R13_REG_mask;
474 RegMask _FLOAT_REG_mask;
475 RegMask _STACK_OR_PTR_REG_mask;
476 RegMask _STACK_OR_LONG_REG_mask;
477 RegMask _STACK_OR_INT_REG_mask;
478
479 static bool need_r12_heapbase() {
480 return UseCompressedOops;
481 }
482
483 void reg_mask_init() {
484 constexpr Register egprs[] = {r16, r17, r18, r19, r20, r21, r22, r23, r24, r25, r26, r27, r28, r29, r30, r31};
485
486 // _ALL_REG_mask is generated by adlc from the all_reg register class below.
487 // We derive a number of subsets from it.
488 _ANY_REG_mask = _ALL_REG_mask;
489
490 if (PreserveFramePointer) {
491 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
492 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
493 }
494 if (need_r12_heapbase()) {
495 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
496 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()->next()));
497 }
498
499 _PTR_REG_mask = _ANY_REG_mask;
500 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()));
501 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()->next()));
502 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()));
503 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()->next()));
504 if (!UseAPX) {
505 for (uint i = 0; i < sizeof(egprs)/sizeof(Register); i++) {
506 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(egprs[i]->as_VMReg()));
507 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(egprs[i]->as_VMReg()->next()));
508 }
509 }
510
511 _STACK_OR_PTR_REG_mask = _PTR_REG_mask;
512 _STACK_OR_PTR_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
513
514 _PTR_REG_NO_RBP_mask = _PTR_REG_mask;
515 _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
516 _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
517
518 _PTR_NO_RAX_REG_mask = _PTR_REG_mask;
519 _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
520 _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
521
522 _PTR_NO_RAX_RBX_REG_mask = _PTR_NO_RAX_REG_mask;
523 _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()));
524 _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()->next()));
525
526
527 _LONG_REG_mask = _PTR_REG_mask;
528 _STACK_OR_LONG_REG_mask = _LONG_REG_mask;
529 _STACK_OR_LONG_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
530
531 _LONG_NO_RAX_RDX_REG_mask = _LONG_REG_mask;
532 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
533 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
534 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
535 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()->next()));
536
537 _LONG_NO_RCX_REG_mask = _LONG_REG_mask;
538 _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
539 _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()->next()));
540
541 _LONG_NO_RBP_R13_REG_mask = _LONG_REG_mask;
542 _LONG_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
543 _LONG_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
544 _LONG_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(r13->as_VMReg()));
545 _LONG_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(r13->as_VMReg()->next()));
546
547 _INT_REG_mask = _ALL_INT_REG_mask;
548 if (!UseAPX) {
549 for (uint i = 0; i < sizeof(egprs)/sizeof(Register); i++) {
550 _INT_REG_mask.Remove(OptoReg::as_OptoReg(egprs[i]->as_VMReg()));
551 }
552 }
553
554 if (PreserveFramePointer) {
555 _INT_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
556 }
557 if (need_r12_heapbase()) {
558 _INT_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
559 }
560
561 _STACK_OR_INT_REG_mask = _INT_REG_mask;
562 _STACK_OR_INT_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
563
564 _INT_NO_RAX_RDX_REG_mask = _INT_REG_mask;
565 _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
566 _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
567
568 _INT_NO_RCX_REG_mask = _INT_REG_mask;
569 _INT_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
570
571 _INT_NO_RBP_R13_REG_mask = _INT_REG_mask;
572 _INT_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
573 _INT_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(r13->as_VMReg()));
574
575 // _FLOAT_REG_LEGACY_mask/_FLOAT_REG_EVEX_mask is generated by adlc
576 // from the float_reg_legacy/float_reg_evex register class.
577 _FLOAT_REG_mask = VM_Version::supports_evex() ? _FLOAT_REG_EVEX_mask : _FLOAT_REG_LEGACY_mask;
578 }
579
580 static bool generate_vzeroupper(Compile* C) {
581 return (VM_Version::supports_vzeroupper() && (C->max_vector_size() > 16 || C->clear_upper_avx() == true)) ? true: false; // Generate vzeroupper
582 }
583
584 static int clear_avx_size() {
585 return generate_vzeroupper(Compile::current()) ? 3: 0; // vzeroupper
586 }
587
588 // !!!!! Special hack to get all types of calls to specify the byte offset
589 // from the start of the call to the point where the return address
590 // will point.
591 int MachCallStaticJavaNode::ret_addr_offset()
592 {
593 int offset = 5; // 5 bytes from start of call to where return address points
594 offset += clear_avx_size();
595 return offset;
596 }
597
598 int MachCallDynamicJavaNode::ret_addr_offset()
599 {
600 int offset = 15; // 15 bytes from start of call to where return address points
601 offset += clear_avx_size();
602 return offset;
603 }
604
605 int MachCallRuntimeNode::ret_addr_offset() {
606 int offset = 13; // movq r10,#addr; callq (r10)
607 if (this->ideal_Opcode() != Op_CallLeafVector) {
608 offset += clear_avx_size();
609 }
610 return offset;
611 }
612 //
613 // Compute padding required for nodes which need alignment
614 //
615
616 // The address of the call instruction needs to be 4-byte aligned to
617 // ensure that it does not span a cache line so that it can be patched.
618 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
619 {
620 current_offset += clear_avx_size(); // skip vzeroupper
621 current_offset += 1; // skip call opcode byte
622 return align_up(current_offset, alignment_required()) - current_offset;
623 }
624
625 // The address of the call instruction needs to be 4-byte aligned to
626 // ensure that it does not span a cache line so that it can be patched.
627 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
628 {
629 current_offset += clear_avx_size(); // skip vzeroupper
630 current_offset += 11; // skip movq instruction + call opcode byte
631 return align_up(current_offset, alignment_required()) - current_offset;
632 }
633
634 // This could be in MacroAssembler but it's fairly C2 specific
635 static void emit_cmpfp_fixup(MacroAssembler* masm) {
636 Label exit;
637 __ jccb(Assembler::noParity, exit);
638 __ pushf();
639 //
640 // comiss/ucomiss instructions set ZF,PF,CF flags and
641 // zero OF,AF,SF for NaN values.
642 // Fixup flags by zeroing ZF,PF so that compare of NaN
643 // values returns 'less than' result (CF is set).
644 // Leave the rest of flags unchanged.
645 //
646 // 7 6 5 4 3 2 1 0
647 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
648 // 0 0 1 0 1 0 1 1 (0x2B)
649 //
650 __ andq(Address(rsp, 0), 0xffffff2b);
651 __ popf();
652 __ bind(exit);
653 }
654
655 static void emit_cmpfp3(MacroAssembler* masm, Register dst) {
656 Label done;
657 __ movl(dst, -1);
658 __ jcc(Assembler::parity, done);
659 __ jcc(Assembler::below, done);
660 __ setcc(Assembler::notEqual, dst);
661 __ bind(done);
662 }
663
664 // Math.min() # Math.max()
665 // --------------------------
666 // ucomis[s/d] #
667 // ja -> b # a
668 // jp -> NaN # NaN
669 // jb -> a # b
670 // je #
671 // |-jz -> a | b # a & b
672 // | -> a #
673 static void emit_fp_min_max(MacroAssembler* masm, XMMRegister dst,
674 XMMRegister a, XMMRegister b,
675 XMMRegister xmmt, Register rt,
676 bool min, bool single) {
677
678 Label nan, zero, below, above, done;
679
680 if (single)
681 __ ucomiss(a, b);
682 else
683 __ ucomisd(a, b);
684
685 if (dst->encoding() != (min ? b : a)->encoding())
686 __ jccb(Assembler::above, above); // CF=0 & ZF=0
687 else
688 __ jccb(Assembler::above, done);
689
690 __ jccb(Assembler::parity, nan); // PF=1
691 __ jccb(Assembler::below, below); // CF=1
692
693 // equal
694 __ vpxor(xmmt, xmmt, xmmt, Assembler::AVX_128bit);
695 if (single) {
696 __ ucomiss(a, xmmt);
697 __ jccb(Assembler::equal, zero);
698
699 __ movflt(dst, a);
700 __ jmp(done);
701 }
702 else {
703 __ ucomisd(a, xmmt);
704 __ jccb(Assembler::equal, zero);
705
706 __ movdbl(dst, a);
707 __ jmp(done);
708 }
709
710 __ bind(zero);
711 if (min)
712 __ vpor(dst, a, b, Assembler::AVX_128bit);
713 else
714 __ vpand(dst, a, b, Assembler::AVX_128bit);
715
716 __ jmp(done);
717
718 __ bind(above);
719 if (single)
720 __ movflt(dst, min ? b : a);
721 else
722 __ movdbl(dst, min ? b : a);
723
724 __ jmp(done);
725
726 __ bind(nan);
727 if (single) {
728 __ movl(rt, 0x7fc00000); // Float.NaN
729 __ movdl(dst, rt);
730 }
731 else {
732 __ mov64(rt, 0x7ff8000000000000L); // Double.NaN
733 __ movdq(dst, rt);
734 }
735 __ jmp(done);
736
737 __ bind(below);
738 if (single)
739 __ movflt(dst, min ? a : b);
740 else
741 __ movdbl(dst, min ? a : b);
742
743 __ bind(done);
744 }
745
746 //=============================================================================
747 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
748
749 int ConstantTable::calculate_table_base_offset() const {
750 return 0; // absolute addressing, no offset
751 }
752
753 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
754 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
755 ShouldNotReachHere();
756 }
757
758 void MachConstantBaseNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const {
759 // Empty encoding
760 }
761
762 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
763 return 0;
764 }
765
766 #ifndef PRODUCT
767 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
768 st->print("# MachConstantBaseNode (empty encoding)");
769 }
770 #endif
771
772
773 //=============================================================================
774 #ifndef PRODUCT
775 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
776 Compile* C = ra_->C;
777
778 int framesize = C->output()->frame_size_in_bytes();
779 int bangsize = C->output()->bang_size_in_bytes();
780 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
781 // Remove wordSize for return addr which is already pushed.
782 framesize -= wordSize;
783
784 if (C->output()->need_stack_bang(bangsize)) {
785 framesize -= wordSize;
786 st->print("# stack bang (%d bytes)", bangsize);
787 st->print("\n\t");
788 st->print("pushq rbp\t# Save rbp");
789 if (PreserveFramePointer) {
790 st->print("\n\t");
791 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
792 }
793 if (framesize) {
794 st->print("\n\t");
795 st->print("subq rsp, #%d\t# Create frame",framesize);
796 }
797 } else {
798 st->print("subq rsp, #%d\t# Create frame",framesize);
799 st->print("\n\t");
800 framesize -= wordSize;
801 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
802 if (PreserveFramePointer) {
803 st->print("\n\t");
804 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
805 if (framesize > 0) {
806 st->print("\n\t");
807 st->print("addq rbp, #%d", framesize);
808 }
809 }
810 }
811
812 if (VerifyStackAtCalls) {
813 st->print("\n\t");
814 framesize -= wordSize;
815 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
816 #ifdef ASSERT
817 st->print("\n\t");
818 st->print("# stack alignment check");
819 #endif
820 }
821 if (C->stub_function() != nullptr) {
822 st->print("\n\t");
823 st->print("cmpl [r15_thread + #disarmed_guard_value_offset], #disarmed_guard_value\t");
824 st->print("\n\t");
825 st->print("je fast_entry\t");
826 st->print("\n\t");
827 st->print("call #nmethod_entry_barrier_stub\t");
828 st->print("\n\tfast_entry:");
829 }
830 st->cr();
831 }
832 #endif
833
834 void MachPrologNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
835 Compile* C = ra_->C;
836
837 int framesize = C->output()->frame_size_in_bytes();
838 int bangsize = C->output()->bang_size_in_bytes();
839
840 if (C->clinit_barrier_on_entry()) {
841 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
842 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
843
844 Label L_skip_barrier;
845 Register klass = rscratch1;
846
847 __ mov_metadata(klass, C->method()->holder()->constant_encoding());
848 __ clinit_barrier(klass, r15_thread, &L_skip_barrier /*L_fast_path*/);
849
850 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); // slow path
851
852 __ bind(L_skip_barrier);
853 }
854
855 __ verified_entry(framesize, C->output()->need_stack_bang(bangsize)?bangsize:0, false, C->stub_function() != nullptr);
856
857 C->output()->set_frame_complete(__ offset());
858
859 if (C->has_mach_constant_base_node()) {
860 // NOTE: We set the table base offset here because users might be
861 // emitted before MachConstantBaseNode.
862 ConstantTable& constant_table = C->output()->constant_table();
863 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
864 }
865 }
866
867 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
868 {
869 return MachNode::size(ra_); // too many variables; just compute it
870 // the hard way
871 }
872
873 int MachPrologNode::reloc() const
874 {
875 return 0; // a large enough number
876 }
877
878 //=============================================================================
879 #ifndef PRODUCT
880 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
881 {
882 Compile* C = ra_->C;
883 if (generate_vzeroupper(C)) {
884 st->print("vzeroupper");
885 st->cr(); st->print("\t");
886 }
887
888 int framesize = C->output()->frame_size_in_bytes();
889 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
890 // Remove word for return adr already pushed
891 // and RBP
892 framesize -= 2*wordSize;
893
894 if (framesize) {
895 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
896 st->print("\t");
897 }
898
899 st->print_cr("popq rbp");
900 if (do_polling() && C->is_method_compilation()) {
901 st->print("\t");
902 st->print_cr("cmpq rsp, poll_offset[r15_thread] \n\t"
903 "ja #safepoint_stub\t"
904 "# Safepoint: poll for GC");
905 }
906 }
907 #endif
908
909 void MachEpilogNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const
910 {
911 Compile* C = ra_->C;
912
913 if (generate_vzeroupper(C)) {
914 // Clear upper bits of YMM registers when current compiled code uses
915 // wide vectors to avoid AVX <-> SSE transition penalty during call.
916 __ vzeroupper();
917 }
918
919 int framesize = C->output()->frame_size_in_bytes();
920 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
921 // Remove word for return adr already pushed
922 // and RBP
923 framesize -= 2*wordSize;
924
925 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
926
927 if (framesize) {
928 __ addq(rsp, framesize);
929 }
930
931 __ popq(rbp);
932
933 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
934 __ reserved_stack_check();
935 }
936
937 if (do_polling() && C->is_method_compilation()) {
938 Label dummy_label;
939 Label* code_stub = &dummy_label;
940 if (!C->output()->in_scratch_emit_size()) {
941 C2SafepointPollStub* stub = new (C->comp_arena()) C2SafepointPollStub(__ offset());
942 C->output()->add_stub(stub);
943 code_stub = &stub->entry();
944 }
945 __ relocate(relocInfo::poll_return_type);
946 __ safepoint_poll(*code_stub, r15_thread, true /* at_return */, true /* in_nmethod */);
947 }
948 }
949
950 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
951 {
952 return MachNode::size(ra_); // too many variables; just compute it
953 // the hard way
954 }
955
956 int MachEpilogNode::reloc() const
957 {
958 return 2; // a large enough number
959 }
960
961 const Pipeline* MachEpilogNode::pipeline() const
962 {
963 return MachNode::pipeline_class();
964 }
965
966 //=============================================================================
967
968 enum RC {
969 rc_bad,
970 rc_int,
971 rc_kreg,
972 rc_float,
973 rc_stack
974 };
975
976 static enum RC rc_class(OptoReg::Name reg)
977 {
978 if( !OptoReg::is_valid(reg) ) return rc_bad;
979
980 if (OptoReg::is_stack(reg)) return rc_stack;
981
982 VMReg r = OptoReg::as_VMReg(reg);
983
984 if (r->is_Register()) return rc_int;
985
986 if (r->is_KRegister()) return rc_kreg;
987
988 assert(r->is_XMMRegister(), "must be");
989 return rc_float;
990 }
991
992 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
993 static void vec_mov_helper(C2_MacroAssembler *masm, int src_lo, int dst_lo,
994 int src_hi, int dst_hi, uint ireg, outputStream* st);
995
996 void vec_spill_helper(C2_MacroAssembler *masm, bool is_load,
997 int stack_offset, int reg, uint ireg, outputStream* st);
998
999 static void vec_stack_to_stack_helper(C2_MacroAssembler *masm, int src_offset,
1000 int dst_offset, uint ireg, outputStream* st) {
1001 if (masm) {
1002 switch (ireg) {
1003 case Op_VecS:
1004 __ movq(Address(rsp, -8), rax);
1005 __ movl(rax, Address(rsp, src_offset));
1006 __ movl(Address(rsp, dst_offset), rax);
1007 __ movq(rax, Address(rsp, -8));
1008 break;
1009 case Op_VecD:
1010 __ pushq(Address(rsp, src_offset));
1011 __ popq (Address(rsp, dst_offset));
1012 break;
1013 case Op_VecX:
1014 __ pushq(Address(rsp, src_offset));
1015 __ popq (Address(rsp, dst_offset));
1016 __ pushq(Address(rsp, src_offset+8));
1017 __ popq (Address(rsp, dst_offset+8));
1018 break;
1019 case Op_VecY:
1020 __ vmovdqu(Address(rsp, -32), xmm0);
1021 __ vmovdqu(xmm0, Address(rsp, src_offset));
1022 __ vmovdqu(Address(rsp, dst_offset), xmm0);
1023 __ vmovdqu(xmm0, Address(rsp, -32));
1024 break;
1025 case Op_VecZ:
1026 __ evmovdquq(Address(rsp, -64), xmm0, 2);
1027 __ evmovdquq(xmm0, Address(rsp, src_offset), 2);
1028 __ evmovdquq(Address(rsp, dst_offset), xmm0, 2);
1029 __ evmovdquq(xmm0, Address(rsp, -64), 2);
1030 break;
1031 default:
1032 ShouldNotReachHere();
1033 }
1034 #ifndef PRODUCT
1035 } else {
1036 switch (ireg) {
1037 case Op_VecS:
1038 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1039 "movl rax, [rsp + #%d]\n\t"
1040 "movl [rsp + #%d], rax\n\t"
1041 "movq rax, [rsp - #8]",
1042 src_offset, dst_offset);
1043 break;
1044 case Op_VecD:
1045 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1046 "popq [rsp + #%d]",
1047 src_offset, dst_offset);
1048 break;
1049 case Op_VecX:
1050 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
1051 "popq [rsp + #%d]\n\t"
1052 "pushq [rsp + #%d]\n\t"
1053 "popq [rsp + #%d]",
1054 src_offset, dst_offset, src_offset+8, dst_offset+8);
1055 break;
1056 case Op_VecY:
1057 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
1058 "vmovdqu xmm0, [rsp + #%d]\n\t"
1059 "vmovdqu [rsp + #%d], xmm0\n\t"
1060 "vmovdqu xmm0, [rsp - #32]",
1061 src_offset, dst_offset);
1062 break;
1063 case Op_VecZ:
1064 st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
1065 "vmovdqu xmm0, [rsp + #%d]\n\t"
1066 "vmovdqu [rsp + #%d], xmm0\n\t"
1067 "vmovdqu xmm0, [rsp - #64]",
1068 src_offset, dst_offset);
1069 break;
1070 default:
1071 ShouldNotReachHere();
1072 }
1073 #endif
1074 }
1075 }
1076
1077 uint MachSpillCopyNode::implementation(C2_MacroAssembler* masm,
1078 PhaseRegAlloc* ra_,
1079 bool do_size,
1080 outputStream* st) const {
1081 assert(masm != nullptr || st != nullptr, "sanity");
1082 // Get registers to move
1083 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1084 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1085 OptoReg::Name dst_second = ra_->get_reg_second(this);
1086 OptoReg::Name dst_first = ra_->get_reg_first(this);
1087
1088 enum RC src_second_rc = rc_class(src_second);
1089 enum RC src_first_rc = rc_class(src_first);
1090 enum RC dst_second_rc = rc_class(dst_second);
1091 enum RC dst_first_rc = rc_class(dst_first);
1092
1093 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1094 "must move at least 1 register" );
1095
1096 if (src_first == dst_first && src_second == dst_second) {
1097 // Self copy, no move
1098 return 0;
1099 }
1100 if (bottom_type()->isa_vect() != nullptr && bottom_type()->isa_vectmask() == nullptr) {
1101 uint ireg = ideal_reg();
1102 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1103 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity");
1104 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1105 // mem -> mem
1106 int src_offset = ra_->reg2offset(src_first);
1107 int dst_offset = ra_->reg2offset(dst_first);
1108 vec_stack_to_stack_helper(masm, src_offset, dst_offset, ireg, st);
1109 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
1110 vec_mov_helper(masm, src_first, dst_first, src_second, dst_second, ireg, st);
1111 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1112 int stack_offset = ra_->reg2offset(dst_first);
1113 vec_spill_helper(masm, false, stack_offset, src_first, ireg, st);
1114 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
1115 int stack_offset = ra_->reg2offset(src_first);
1116 vec_spill_helper(masm, true, stack_offset, dst_first, ireg, st);
1117 } else {
1118 ShouldNotReachHere();
1119 }
1120 return 0;
1121 }
1122 if (src_first_rc == rc_stack) {
1123 // mem ->
1124 if (dst_first_rc == rc_stack) {
1125 // mem -> mem
1126 assert(src_second != dst_first, "overlap");
1127 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1128 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1129 // 64-bit
1130 int src_offset = ra_->reg2offset(src_first);
1131 int dst_offset = ra_->reg2offset(dst_first);
1132 if (masm) {
1133 __ pushq(Address(rsp, src_offset));
1134 __ popq (Address(rsp, dst_offset));
1135 #ifndef PRODUCT
1136 } else {
1137 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1138 "popq [rsp + #%d]",
1139 src_offset, dst_offset);
1140 #endif
1141 }
1142 } else {
1143 // 32-bit
1144 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1145 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1146 // No pushl/popl, so:
1147 int src_offset = ra_->reg2offset(src_first);
1148 int dst_offset = ra_->reg2offset(dst_first);
1149 if (masm) {
1150 __ movq(Address(rsp, -8), rax);
1151 __ movl(rax, Address(rsp, src_offset));
1152 __ movl(Address(rsp, dst_offset), rax);
1153 __ movq(rax, Address(rsp, -8));
1154 #ifndef PRODUCT
1155 } else {
1156 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1157 "movl rax, [rsp + #%d]\n\t"
1158 "movl [rsp + #%d], rax\n\t"
1159 "movq rax, [rsp - #8]",
1160 src_offset, dst_offset);
1161 #endif
1162 }
1163 }
1164 return 0;
1165 } else if (dst_first_rc == rc_int) {
1166 // mem -> gpr
1167 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1168 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1169 // 64-bit
1170 int offset = ra_->reg2offset(src_first);
1171 if (masm) {
1172 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1173 #ifndef PRODUCT
1174 } else {
1175 st->print("movq %s, [rsp + #%d]\t# spill",
1176 Matcher::regName[dst_first],
1177 offset);
1178 #endif
1179 }
1180 } else {
1181 // 32-bit
1182 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1183 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1184 int offset = ra_->reg2offset(src_first);
1185 if (masm) {
1186 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1187 #ifndef PRODUCT
1188 } else {
1189 st->print("movl %s, [rsp + #%d]\t# spill",
1190 Matcher::regName[dst_first],
1191 offset);
1192 #endif
1193 }
1194 }
1195 return 0;
1196 } else if (dst_first_rc == rc_float) {
1197 // mem-> xmm
1198 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1199 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1200 // 64-bit
1201 int offset = ra_->reg2offset(src_first);
1202 if (masm) {
1203 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1204 #ifndef PRODUCT
1205 } else {
1206 st->print("%s %s, [rsp + #%d]\t# spill",
1207 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1208 Matcher::regName[dst_first],
1209 offset);
1210 #endif
1211 }
1212 } else {
1213 // 32-bit
1214 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1215 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1216 int offset = ra_->reg2offset(src_first);
1217 if (masm) {
1218 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1219 #ifndef PRODUCT
1220 } else {
1221 st->print("movss %s, [rsp + #%d]\t# spill",
1222 Matcher::regName[dst_first],
1223 offset);
1224 #endif
1225 }
1226 }
1227 return 0;
1228 } else if (dst_first_rc == rc_kreg) {
1229 // mem -> kreg
1230 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1231 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1232 // 64-bit
1233 int offset = ra_->reg2offset(src_first);
1234 if (masm) {
1235 __ kmov(as_KRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1236 #ifndef PRODUCT
1237 } else {
1238 st->print("kmovq %s, [rsp + #%d]\t# spill",
1239 Matcher::regName[dst_first],
1240 offset);
1241 #endif
1242 }
1243 }
1244 return 0;
1245 }
1246 } else if (src_first_rc == rc_int) {
1247 // gpr ->
1248 if (dst_first_rc == rc_stack) {
1249 // gpr -> mem
1250 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1251 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1252 // 64-bit
1253 int offset = ra_->reg2offset(dst_first);
1254 if (masm) {
1255 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1256 #ifndef PRODUCT
1257 } else {
1258 st->print("movq [rsp + #%d], %s\t# spill",
1259 offset,
1260 Matcher::regName[src_first]);
1261 #endif
1262 }
1263 } else {
1264 // 32-bit
1265 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1266 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1267 int offset = ra_->reg2offset(dst_first);
1268 if (masm) {
1269 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1270 #ifndef PRODUCT
1271 } else {
1272 st->print("movl [rsp + #%d], %s\t# spill",
1273 offset,
1274 Matcher::regName[src_first]);
1275 #endif
1276 }
1277 }
1278 return 0;
1279 } else if (dst_first_rc == rc_int) {
1280 // gpr -> gpr
1281 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1282 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1283 // 64-bit
1284 if (masm) {
1285 __ movq(as_Register(Matcher::_regEncode[dst_first]),
1286 as_Register(Matcher::_regEncode[src_first]));
1287 #ifndef PRODUCT
1288 } else {
1289 st->print("movq %s, %s\t# spill",
1290 Matcher::regName[dst_first],
1291 Matcher::regName[src_first]);
1292 #endif
1293 }
1294 return 0;
1295 } else {
1296 // 32-bit
1297 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1298 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1299 if (masm) {
1300 __ movl(as_Register(Matcher::_regEncode[dst_first]),
1301 as_Register(Matcher::_regEncode[src_first]));
1302 #ifndef PRODUCT
1303 } else {
1304 st->print("movl %s, %s\t# spill",
1305 Matcher::regName[dst_first],
1306 Matcher::regName[src_first]);
1307 #endif
1308 }
1309 return 0;
1310 }
1311 } else if (dst_first_rc == rc_float) {
1312 // gpr -> xmm
1313 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1314 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1315 // 64-bit
1316 if (masm) {
1317 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1318 #ifndef PRODUCT
1319 } else {
1320 st->print("movdq %s, %s\t# spill",
1321 Matcher::regName[dst_first],
1322 Matcher::regName[src_first]);
1323 #endif
1324 }
1325 } else {
1326 // 32-bit
1327 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1328 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1329 if (masm) {
1330 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1331 #ifndef PRODUCT
1332 } else {
1333 st->print("movdl %s, %s\t# spill",
1334 Matcher::regName[dst_first],
1335 Matcher::regName[src_first]);
1336 #endif
1337 }
1338 }
1339 return 0;
1340 } else if (dst_first_rc == rc_kreg) {
1341 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1342 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1343 // 64-bit
1344 if (masm) {
1345 __ kmov(as_KRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1346 #ifndef PRODUCT
1347 } else {
1348 st->print("kmovq %s, %s\t# spill",
1349 Matcher::regName[dst_first],
1350 Matcher::regName[src_first]);
1351 #endif
1352 }
1353 }
1354 Unimplemented();
1355 return 0;
1356 }
1357 } else if (src_first_rc == rc_float) {
1358 // xmm ->
1359 if (dst_first_rc == rc_stack) {
1360 // xmm -> mem
1361 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1362 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1363 // 64-bit
1364 int offset = ra_->reg2offset(dst_first);
1365 if (masm) {
1366 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1367 #ifndef PRODUCT
1368 } else {
1369 st->print("movsd [rsp + #%d], %s\t# spill",
1370 offset,
1371 Matcher::regName[src_first]);
1372 #endif
1373 }
1374 } else {
1375 // 32-bit
1376 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1377 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1378 int offset = ra_->reg2offset(dst_first);
1379 if (masm) {
1380 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1381 #ifndef PRODUCT
1382 } else {
1383 st->print("movss [rsp + #%d], %s\t# spill",
1384 offset,
1385 Matcher::regName[src_first]);
1386 #endif
1387 }
1388 }
1389 return 0;
1390 } else if (dst_first_rc == rc_int) {
1391 // xmm -> gpr
1392 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1393 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1394 // 64-bit
1395 if (masm) {
1396 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1397 #ifndef PRODUCT
1398 } else {
1399 st->print("movdq %s, %s\t# spill",
1400 Matcher::regName[dst_first],
1401 Matcher::regName[src_first]);
1402 #endif
1403 }
1404 } else {
1405 // 32-bit
1406 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1407 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1408 if (masm) {
1409 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1410 #ifndef PRODUCT
1411 } else {
1412 st->print("movdl %s, %s\t# spill",
1413 Matcher::regName[dst_first],
1414 Matcher::regName[src_first]);
1415 #endif
1416 }
1417 }
1418 return 0;
1419 } else if (dst_first_rc == rc_float) {
1420 // xmm -> xmm
1421 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1422 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1423 // 64-bit
1424 if (masm) {
1425 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1426 #ifndef PRODUCT
1427 } else {
1428 st->print("%s %s, %s\t# spill",
1429 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1430 Matcher::regName[dst_first],
1431 Matcher::regName[src_first]);
1432 #endif
1433 }
1434 } else {
1435 // 32-bit
1436 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1437 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1438 if (masm) {
1439 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1440 #ifndef PRODUCT
1441 } else {
1442 st->print("%s %s, %s\t# spill",
1443 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1444 Matcher::regName[dst_first],
1445 Matcher::regName[src_first]);
1446 #endif
1447 }
1448 }
1449 return 0;
1450 } else if (dst_first_rc == rc_kreg) {
1451 assert(false, "Illegal spilling");
1452 return 0;
1453 }
1454 } else if (src_first_rc == rc_kreg) {
1455 if (dst_first_rc == rc_stack) {
1456 // mem -> kreg
1457 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1458 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1459 // 64-bit
1460 int offset = ra_->reg2offset(dst_first);
1461 if (masm) {
1462 __ kmov(Address(rsp, offset), as_KRegister(Matcher::_regEncode[src_first]));
1463 #ifndef PRODUCT
1464 } else {
1465 st->print("kmovq [rsp + #%d] , %s\t# spill",
1466 offset,
1467 Matcher::regName[src_first]);
1468 #endif
1469 }
1470 }
1471 return 0;
1472 } else if (dst_first_rc == rc_int) {
1473 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1474 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1475 // 64-bit
1476 if (masm) {
1477 __ kmov(as_Register(Matcher::_regEncode[dst_first]), as_KRegister(Matcher::_regEncode[src_first]));
1478 #ifndef PRODUCT
1479 } else {
1480 st->print("kmovq %s, %s\t# spill",
1481 Matcher::regName[dst_first],
1482 Matcher::regName[src_first]);
1483 #endif
1484 }
1485 }
1486 Unimplemented();
1487 return 0;
1488 } else if (dst_first_rc == rc_kreg) {
1489 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1490 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1491 // 64-bit
1492 if (masm) {
1493 __ kmov(as_KRegister(Matcher::_regEncode[dst_first]), as_KRegister(Matcher::_regEncode[src_first]));
1494 #ifndef PRODUCT
1495 } else {
1496 st->print("kmovq %s, %s\t# spill",
1497 Matcher::regName[dst_first],
1498 Matcher::regName[src_first]);
1499 #endif
1500 }
1501 }
1502 return 0;
1503 } else if (dst_first_rc == rc_float) {
1504 assert(false, "Illegal spill");
1505 return 0;
1506 }
1507 }
1508
1509 assert(0," foo ");
1510 Unimplemented();
1511 return 0;
1512 }
1513
1514 #ifndef PRODUCT
1515 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1516 implementation(nullptr, ra_, false, st);
1517 }
1518 #endif
1519
1520 void MachSpillCopyNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1521 implementation(masm, ra_, false, nullptr);
1522 }
1523
1524 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1525 return MachNode::size(ra_);
1526 }
1527
1528 //=============================================================================
1529 #ifndef PRODUCT
1530 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1531 {
1532 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1533 int reg = ra_->get_reg_first(this);
1534 st->print("leaq %s, [rsp + #%d]\t# box lock",
1535 Matcher::regName[reg], offset);
1536 }
1537 #endif
1538
1539 void BoxLockNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const
1540 {
1541 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1542 int reg = ra_->get_encode(this);
1543
1544 __ lea(as_Register(reg), Address(rsp, offset));
1545 }
1546
1547 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1548 {
1549 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1550 if (ra_->get_encode(this) > 15) {
1551 return (offset < 0x80) ? 6 : 9; // REX2
1552 } else {
1553 return (offset < 0x80) ? 5 : 8; // REX
1554 }
1555 }
1556
1557 //=============================================================================
1558 #ifndef PRODUCT
1559 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1560 {
1561 if (UseCompressedClassPointers) {
1562 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1563 st->print_cr("\tcmpl rscratch1, [rax + CompiledICData::speculated_klass_offset()]\t # Inline cache check");
1564 } else {
1565 st->print_cr("movq rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1566 st->print_cr("\tcmpq rscratch1, [rax + CompiledICData::speculated_klass_offset()]\t # Inline cache check");
1567 }
1568 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1569 }
1570 #endif
1571
1572 void MachUEPNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const
1573 {
1574 __ ic_check(InteriorEntryAlignment);
1575 }
1576
1577 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1578 {
1579 return MachNode::size(ra_); // too many variables; just compute it
1580 // the hard way
1581 }
1582
1583
1584 //=============================================================================
1585
1586 bool Matcher::supports_vector_calling_convention(void) {
1587 if (EnableVectorSupport && UseVectorStubs) {
1588 return true;
1589 }
1590 return false;
1591 }
1592
1593 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
1594 assert(EnableVectorSupport && UseVectorStubs, "sanity");
1595 int lo = XMM0_num;
1596 int hi = XMM0b_num;
1597 if (ideal_reg == Op_VecX) hi = XMM0d_num;
1598 else if (ideal_reg == Op_VecY) hi = XMM0h_num;
1599 else if (ideal_reg == Op_VecZ) hi = XMM0p_num;
1600 return OptoRegPair(hi, lo);
1601 }
1602
1603 // Is this branch offset short enough that a short branch can be used?
1604 //
1605 // NOTE: If the platform does not provide any short branch variants, then
1606 // this method should return false for offset 0.
1607 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1608 // The passed offset is relative to address of the branch.
1609 // On 86 a branch displacement is calculated relative to address
1610 // of a next instruction.
1611 offset -= br_size;
1612
1613 // the short version of jmpConUCF2 contains multiple branches,
1614 // making the reach slightly less
1615 if (rule == jmpConUCF2_rule)
1616 return (-126 <= offset && offset <= 125);
1617 return (-128 <= offset && offset <= 127);
1618 }
1619
1620 // Return whether or not this register is ever used as an argument.
1621 // This function is used on startup to build the trampoline stubs in
1622 // generateOptoStub. Registers not mentioned will be killed by the VM
1623 // call in the trampoline, and arguments in those registers not be
1624 // available to the callee.
1625 bool Matcher::can_be_java_arg(int reg)
1626 {
1627 return
1628 reg == RDI_num || reg == RDI_H_num ||
1629 reg == RSI_num || reg == RSI_H_num ||
1630 reg == RDX_num || reg == RDX_H_num ||
1631 reg == RCX_num || reg == RCX_H_num ||
1632 reg == R8_num || reg == R8_H_num ||
1633 reg == R9_num || reg == R9_H_num ||
1634 reg == R12_num || reg == R12_H_num ||
1635 reg == XMM0_num || reg == XMM0b_num ||
1636 reg == XMM1_num || reg == XMM1b_num ||
1637 reg == XMM2_num || reg == XMM2b_num ||
1638 reg == XMM3_num || reg == XMM3b_num ||
1639 reg == XMM4_num || reg == XMM4b_num ||
1640 reg == XMM5_num || reg == XMM5b_num ||
1641 reg == XMM6_num || reg == XMM6b_num ||
1642 reg == XMM7_num || reg == XMM7b_num;
1643 }
1644
1645 bool Matcher::is_spillable_arg(int reg)
1646 {
1647 return can_be_java_arg(reg);
1648 }
1649
1650 uint Matcher::int_pressure_limit()
1651 {
1652 return (INTPRESSURE == -1) ? _INT_REG_mask.Size() : INTPRESSURE;
1653 }
1654
1655 uint Matcher::float_pressure_limit()
1656 {
1657 // After experiment around with different values, the following default threshold
1658 // works best for LCM's register pressure scheduling on x64.
1659 uint dec_count = VM_Version::supports_evex() ? 4 : 2;
1660 uint default_float_pressure_threshold = _FLOAT_REG_mask.Size() - dec_count;
1661 return (FLOATPRESSURE == -1) ? default_float_pressure_threshold : FLOATPRESSURE;
1662 }
1663
1664 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1665 // In 64 bit mode a code which use multiply when
1666 // devisor is constant is faster than hardware
1667 // DIV instruction (it uses MulHiL).
1668 return false;
1669 }
1670
1671 // Register for DIVI projection of divmodI
1672 RegMask Matcher::divI_proj_mask() {
1673 return INT_RAX_REG_mask();
1674 }
1675
1676 // Register for MODI projection of divmodI
1677 RegMask Matcher::modI_proj_mask() {
1678 return INT_RDX_REG_mask();
1679 }
1680
1681 // Register for DIVL projection of divmodL
1682 RegMask Matcher::divL_proj_mask() {
1683 return LONG_RAX_REG_mask();
1684 }
1685
1686 // Register for MODL projection of divmodL
1687 RegMask Matcher::modL_proj_mask() {
1688 return LONG_RDX_REG_mask();
1689 }
1690
1691 // Register for saving SP into on method handle invokes. Not used on x86_64.
1692 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1693 return NO_REG_mask();
1694 }
1695
1696 %}
1697
1698 //----------ENCODING BLOCK-----------------------------------------------------
1699 // This block specifies the encoding classes used by the compiler to
1700 // output byte streams. Encoding classes are parameterized macros
1701 // used by Machine Instruction Nodes in order to generate the bit
1702 // encoding of the instruction. Operands specify their base encoding
1703 // interface with the interface keyword. There are currently
1704 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1705 // COND_INTER. REG_INTER causes an operand to generate a function
1706 // which returns its register number when queried. CONST_INTER causes
1707 // an operand to generate a function which returns the value of the
1708 // constant when queried. MEMORY_INTER causes an operand to generate
1709 // four functions which return the Base Register, the Index Register,
1710 // the Scale Value, and the Offset Value of the operand when queried.
1711 // COND_INTER causes an operand to generate six functions which return
1712 // the encoding code (ie - encoding bits for the instruction)
1713 // associated with each basic boolean condition for a conditional
1714 // instruction.
1715 //
1716 // Instructions specify two basic values for encoding. Again, a
1717 // function is available to check if the constant displacement is an
1718 // oop. They use the ins_encode keyword to specify their encoding
1719 // classes (which must be a sequence of enc_class names, and their
1720 // parameters, specified in the encoding block), and they use the
1721 // opcode keyword to specify, in order, their primary, secondary, and
1722 // tertiary opcode. Only the opcode sections which a particular
1723 // instruction needs for encoding need to be specified.
1724 encode %{
1725 enc_class cdql_enc(no_rax_rdx_RegI div)
1726 %{
1727 // Full implementation of Java idiv and irem; checks for
1728 // special case as described in JVM spec., p.243 & p.271.
1729 //
1730 // normal case special case
1731 //
1732 // input : rax: dividend min_int
1733 // reg: divisor -1
1734 //
1735 // output: rax: quotient (= rax idiv reg) min_int
1736 // rdx: remainder (= rax irem reg) 0
1737 //
1738 // Code sequnce:
1739 //
1740 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
1741 // 5: 75 07/08 jne e <normal>
1742 // 7: 33 d2 xor %edx,%edx
1743 // [div >= 8 -> offset + 1]
1744 // [REX_B]
1745 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
1746 // c: 74 03/04 je 11 <done>
1747 // 000000000000000e <normal>:
1748 // e: 99 cltd
1749 // [div >= 8 -> offset + 1]
1750 // [REX_B]
1751 // f: f7 f9 idiv $div
1752 // 0000000000000011 <done>:
1753 Label normal;
1754 Label done;
1755
1756 // cmp $0x80000000,%eax
1757 __ cmpl(as_Register(RAX_enc), 0x80000000);
1758
1759 // jne e <normal>
1760 __ jccb(Assembler::notEqual, normal);
1761
1762 // xor %edx,%edx
1763 __ xorl(as_Register(RDX_enc), as_Register(RDX_enc));
1764
1765 // cmp $0xffffffffffffffff,%ecx
1766 __ cmpl($div$$Register, -1);
1767
1768 // je 11 <done>
1769 __ jccb(Assembler::equal, done);
1770
1771 // <normal>
1772 // cltd
1773 __ bind(normal);
1774 __ cdql();
1775
1776 // idivl
1777 // <done>
1778 __ idivl($div$$Register);
1779 __ bind(done);
1780 %}
1781
1782 enc_class cdqq_enc(no_rax_rdx_RegL div)
1783 %{
1784 // Full implementation of Java ldiv and lrem; checks for
1785 // special case as described in JVM spec., p.243 & p.271.
1786 //
1787 // normal case special case
1788 //
1789 // input : rax: dividend min_long
1790 // reg: divisor -1
1791 //
1792 // output: rax: quotient (= rax idiv reg) min_long
1793 // rdx: remainder (= rax irem reg) 0
1794 //
1795 // Code sequnce:
1796 //
1797 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
1798 // 7: 00 00 80
1799 // a: 48 39 d0 cmp %rdx,%rax
1800 // d: 75 08 jne 17 <normal>
1801 // f: 33 d2 xor %edx,%edx
1802 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
1803 // 15: 74 05 je 1c <done>
1804 // 0000000000000017 <normal>:
1805 // 17: 48 99 cqto
1806 // 19: 48 f7 f9 idiv $div
1807 // 000000000000001c <done>:
1808 Label normal;
1809 Label done;
1810
1811 // mov $0x8000000000000000,%rdx
1812 __ mov64(as_Register(RDX_enc), 0x8000000000000000);
1813
1814 // cmp %rdx,%rax
1815 __ cmpq(as_Register(RAX_enc), as_Register(RDX_enc));
1816
1817 // jne 17 <normal>
1818 __ jccb(Assembler::notEqual, normal);
1819
1820 // xor %edx,%edx
1821 __ xorl(as_Register(RDX_enc), as_Register(RDX_enc));
1822
1823 // cmp $0xffffffffffffffff,$div
1824 __ cmpq($div$$Register, -1);
1825
1826 // je 1e <done>
1827 __ jccb(Assembler::equal, done);
1828
1829 // <normal>
1830 // cqto
1831 __ bind(normal);
1832 __ cdqq();
1833
1834 // idivq (note: must be emitted by the user of this rule)
1835 // <done>
1836 __ idivq($div$$Register);
1837 __ bind(done);
1838 %}
1839
1840 enc_class clear_avx %{
1841 debug_only(int off0 = __ offset());
1842 if (generate_vzeroupper(Compile::current())) {
1843 // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
1844 // Clear upper bits of YMM registers when current compiled code uses
1845 // wide vectors to avoid AVX <-> SSE transition penalty during call.
1846 __ vzeroupper();
1847 }
1848 debug_only(int off1 = __ offset());
1849 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
1850 %}
1851
1852 enc_class Java_To_Runtime(method meth) %{
1853 // No relocation needed
1854 __ mov64(r10, (int64_t) $meth$$method);
1855 __ call(r10);
1856 __ post_call_nop();
1857 %}
1858
1859 enc_class Java_Static_Call(method meth)
1860 %{
1861 // JAVA STATIC CALL
1862 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
1863 // determine who we intended to call.
1864 if (!_method) {
1865 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, $meth$$method)));
1866 } else if (_method->intrinsic_id() == vmIntrinsicID::_ensureMaterializedForStackWalk) {
1867 // The NOP here is purely to ensure that eliding a call to
1868 // JVM_EnsureMaterializedForStackWalk doesn't change the code size.
1869 __ addr_nop_5();
1870 __ block_comment("call JVM_EnsureMaterializedForStackWalk (elided)");
1871 } else {
1872 int method_index = resolved_method_index(masm);
1873 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
1874 : static_call_Relocation::spec(method_index);
1875 address mark = __ pc();
1876 int call_offset = __ offset();
1877 __ call(AddressLiteral(CAST_FROM_FN_PTR(address, $meth$$method), rspec));
1878 if (CodeBuffer::supports_shared_stubs() && _method->can_be_statically_bound()) {
1879 // Calls of the same statically bound method can share
1880 // a stub to the interpreter.
1881 __ code()->shared_stub_to_interp_for(_method, call_offset);
1882 } else {
1883 // Emit stubs for static call.
1884 address stub = CompiledDirectCall::emit_to_interp_stub(masm, mark);
1885 __ clear_inst_mark();
1886 if (stub == nullptr) {
1887 ciEnv::current()->record_failure("CodeCache is full");
1888 return;
1889 }
1890 }
1891 }
1892 __ post_call_nop();
1893 %}
1894
1895 enc_class Java_Dynamic_Call(method meth) %{
1896 __ ic_call((address)$meth$$method, resolved_method_index(masm));
1897 __ post_call_nop();
1898 %}
1899
1900 %}
1901
1902
1903
1904 //----------FRAME--------------------------------------------------------------
1905 // Definition of frame structure and management information.
1906 //
1907 // S T A C K L A Y O U T Allocators stack-slot number
1908 // | (to get allocators register number
1909 // G Owned by | | v add OptoReg::stack0())
1910 // r CALLER | |
1911 // o | +--------+ pad to even-align allocators stack-slot
1912 // w V | pad0 | numbers; owned by CALLER
1913 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
1914 // h ^ | in | 5
1915 // | | args | 4 Holes in incoming args owned by SELF
1916 // | | | | 3
1917 // | | +--------+
1918 // V | | old out| Empty on Intel, window on Sparc
1919 // | old |preserve| Must be even aligned.
1920 // | SP-+--------+----> Matcher::_old_SP, even aligned
1921 // | | in | 3 area for Intel ret address
1922 // Owned by |preserve| Empty on Sparc.
1923 // SELF +--------+
1924 // | | pad2 | 2 pad to align old SP
1925 // | +--------+ 1
1926 // | | locks | 0
1927 // | +--------+----> OptoReg::stack0(), even aligned
1928 // | | pad1 | 11 pad to align new SP
1929 // | +--------+
1930 // | | | 10
1931 // | | spills | 9 spills
1932 // V | | 8 (pad0 slot for callee)
1933 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
1934 // ^ | out | 7
1935 // | | args | 6 Holes in outgoing args owned by CALLEE
1936 // Owned by +--------+
1937 // CALLEE | new out| 6 Empty on Intel, window on Sparc
1938 // | new |preserve| Must be even-aligned.
1939 // | SP-+--------+----> Matcher::_new_SP, even aligned
1940 // | | |
1941 //
1942 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
1943 // known from SELF's arguments and the Java calling convention.
1944 // Region 6-7 is determined per call site.
1945 // Note 2: If the calling convention leaves holes in the incoming argument
1946 // area, those holes are owned by SELF. Holes in the outgoing area
1947 // are owned by the CALLEE. Holes should not be necessary in the
1948 // incoming area, as the Java calling convention is completely under
1949 // the control of the AD file. Doubles can be sorted and packed to
1950 // avoid holes. Holes in the outgoing arguments may be necessary for
1951 // varargs C calling conventions.
1952 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
1953 // even aligned with pad0 as needed.
1954 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
1955 // region 6-11 is even aligned; it may be padded out more so that
1956 // the region from SP to FP meets the minimum stack alignment.
1957 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
1958 // alignment. Region 11, pad1, may be dynamically extended so that
1959 // SP meets the minimum alignment.
1960
1961 frame
1962 %{
1963 // These three registers define part of the calling convention
1964 // between compiled code and the interpreter.
1965 inline_cache_reg(RAX); // Inline Cache Register
1966
1967 // Optional: name the operand used by cisc-spilling to access
1968 // [stack_pointer + offset]
1969 cisc_spilling_operand_name(indOffset32);
1970
1971 // Number of stack slots consumed by locking an object
1972 sync_stack_slots(2);
1973
1974 // Compiled code's Frame Pointer
1975 frame_pointer(RSP);
1976
1977 // Interpreter stores its frame pointer in a register which is
1978 // stored to the stack by I2CAdaptors.
1979 // I2CAdaptors convert from interpreted java to compiled java.
1980 interpreter_frame_pointer(RBP);
1981
1982 // Stack alignment requirement
1983 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
1984
1985 // Number of outgoing stack slots killed above the out_preserve_stack_slots
1986 // for calls to C. Supports the var-args backing area for register parms.
1987 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
1988
1989 // The after-PROLOG location of the return address. Location of
1990 // return address specifies a type (REG or STACK) and a number
1991 // representing the register number (i.e. - use a register name) or
1992 // stack slot.
1993 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
1994 // Otherwise, it is above the locks and verification slot and alignment word
1995 return_addr(STACK - 2 +
1996 align_up((Compile::current()->in_preserve_stack_slots() +
1997 Compile::current()->fixed_slots()),
1998 stack_alignment_in_slots()));
1999
2000 // Location of compiled Java return values. Same as C for now.
2001 return_value
2002 %{
2003 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2004 "only return normal values");
2005
2006 static const int lo[Op_RegL + 1] = {
2007 0,
2008 0,
2009 RAX_num, // Op_RegN
2010 RAX_num, // Op_RegI
2011 RAX_num, // Op_RegP
2012 XMM0_num, // Op_RegF
2013 XMM0_num, // Op_RegD
2014 RAX_num // Op_RegL
2015 };
2016 static const int hi[Op_RegL + 1] = {
2017 0,
2018 0,
2019 OptoReg::Bad, // Op_RegN
2020 OptoReg::Bad, // Op_RegI
2021 RAX_H_num, // Op_RegP
2022 OptoReg::Bad, // Op_RegF
2023 XMM0b_num, // Op_RegD
2024 RAX_H_num // Op_RegL
2025 };
2026 // Excluded flags and vector registers.
2027 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 8, "missing type");
2028 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2029 %}
2030 %}
2031
2032 //----------ATTRIBUTES---------------------------------------------------------
2033 //----------Operand Attributes-------------------------------------------------
2034 op_attrib op_cost(0); // Required cost attribute
2035
2036 //----------Instruction Attributes---------------------------------------------
2037 ins_attrib ins_cost(100); // Required cost attribute
2038 ins_attrib ins_size(8); // Required size attribute (in bits)
2039 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2040 // a non-matching short branch variant
2041 // of some long branch?
2042 ins_attrib ins_alignment(1); // Required alignment attribute (must
2043 // be a power of 2) specifies the
2044 // alignment that some part of the
2045 // instruction (not necessarily the
2046 // start) requires. If > 1, a
2047 // compute_padding() function must be
2048 // provided for the instruction
2049
2050 //----------OPERANDS-----------------------------------------------------------
2051 // Operand definitions must precede instruction definitions for correct parsing
2052 // in the ADLC because operands constitute user defined types which are used in
2053 // instruction definitions.
2054
2055 //----------Simple Operands----------------------------------------------------
2056 // Immediate Operands
2057 // Integer Immediate
2058 operand immI()
2059 %{
2060 match(ConI);
2061
2062 op_cost(10);
2063 format %{ %}
2064 interface(CONST_INTER);
2065 %}
2066
2067 // Constant for test vs zero
2068 operand immI_0()
2069 %{
2070 predicate(n->get_int() == 0);
2071 match(ConI);
2072
2073 op_cost(0);
2074 format %{ %}
2075 interface(CONST_INTER);
2076 %}
2077
2078 // Constant for increment
2079 operand immI_1()
2080 %{
2081 predicate(n->get_int() == 1);
2082 match(ConI);
2083
2084 op_cost(0);
2085 format %{ %}
2086 interface(CONST_INTER);
2087 %}
2088
2089 // Constant for decrement
2090 operand immI_M1()
2091 %{
2092 predicate(n->get_int() == -1);
2093 match(ConI);
2094
2095 op_cost(0);
2096 format %{ %}
2097 interface(CONST_INTER);
2098 %}
2099
2100 operand immI_2()
2101 %{
2102 predicate(n->get_int() == 2);
2103 match(ConI);
2104
2105 op_cost(0);
2106 format %{ %}
2107 interface(CONST_INTER);
2108 %}
2109
2110 operand immI_4()
2111 %{
2112 predicate(n->get_int() == 4);
2113 match(ConI);
2114
2115 op_cost(0);
2116 format %{ %}
2117 interface(CONST_INTER);
2118 %}
2119
2120 operand immI_8()
2121 %{
2122 predicate(n->get_int() == 8);
2123 match(ConI);
2124
2125 op_cost(0);
2126 format %{ %}
2127 interface(CONST_INTER);
2128 %}
2129
2130 // Valid scale values for addressing modes
2131 operand immI2()
2132 %{
2133 predicate(0 <= n->get_int() && (n->get_int() <= 3));
2134 match(ConI);
2135
2136 format %{ %}
2137 interface(CONST_INTER);
2138 %}
2139
2140 operand immU7()
2141 %{
2142 predicate((0 <= n->get_int()) && (n->get_int() <= 0x7F));
2143 match(ConI);
2144
2145 op_cost(5);
2146 format %{ %}
2147 interface(CONST_INTER);
2148 %}
2149
2150 operand immI8()
2151 %{
2152 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2153 match(ConI);
2154
2155 op_cost(5);
2156 format %{ %}
2157 interface(CONST_INTER);
2158 %}
2159
2160 operand immU8()
2161 %{
2162 predicate((0 <= n->get_int()) && (n->get_int() <= 255));
2163 match(ConI);
2164
2165 op_cost(5);
2166 format %{ %}
2167 interface(CONST_INTER);
2168 %}
2169
2170 operand immI16()
2171 %{
2172 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
2173 match(ConI);
2174
2175 op_cost(10);
2176 format %{ %}
2177 interface(CONST_INTER);
2178 %}
2179
2180 // Int Immediate non-negative
2181 operand immU31()
2182 %{
2183 predicate(n->get_int() >= 0);
2184 match(ConI);
2185
2186 op_cost(0);
2187 format %{ %}
2188 interface(CONST_INTER);
2189 %}
2190
2191 // Pointer Immediate
2192 operand immP()
2193 %{
2194 match(ConP);
2195
2196 op_cost(10);
2197 format %{ %}
2198 interface(CONST_INTER);
2199 %}
2200
2201 // Null Pointer Immediate
2202 operand immP0()
2203 %{
2204 predicate(n->get_ptr() == 0);
2205 match(ConP);
2206
2207 op_cost(5);
2208 format %{ %}
2209 interface(CONST_INTER);
2210 %}
2211
2212 // Pointer Immediate
2213 operand immN() %{
2214 match(ConN);
2215
2216 op_cost(10);
2217 format %{ %}
2218 interface(CONST_INTER);
2219 %}
2220
2221 operand immNKlass() %{
2222 match(ConNKlass);
2223
2224 op_cost(10);
2225 format %{ %}
2226 interface(CONST_INTER);
2227 %}
2228
2229 // Null Pointer Immediate
2230 operand immN0() %{
2231 predicate(n->get_narrowcon() == 0);
2232 match(ConN);
2233
2234 op_cost(5);
2235 format %{ %}
2236 interface(CONST_INTER);
2237 %}
2238
2239 operand immP31()
2240 %{
2241 predicate(n->as_Type()->type()->reloc() == relocInfo::none
2242 && (n->get_ptr() >> 31) == 0);
2243 match(ConP);
2244
2245 op_cost(5);
2246 format %{ %}
2247 interface(CONST_INTER);
2248 %}
2249
2250
2251 // Long Immediate
2252 operand immL()
2253 %{
2254 match(ConL);
2255
2256 op_cost(20);
2257 format %{ %}
2258 interface(CONST_INTER);
2259 %}
2260
2261 // Long Immediate 8-bit
2262 operand immL8()
2263 %{
2264 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
2265 match(ConL);
2266
2267 op_cost(5);
2268 format %{ %}
2269 interface(CONST_INTER);
2270 %}
2271
2272 // Long Immediate 32-bit unsigned
2273 operand immUL32()
2274 %{
2275 predicate(n->get_long() == (unsigned int) (n->get_long()));
2276 match(ConL);
2277
2278 op_cost(10);
2279 format %{ %}
2280 interface(CONST_INTER);
2281 %}
2282
2283 // Long Immediate 32-bit signed
2284 operand immL32()
2285 %{
2286 predicate(n->get_long() == (int) (n->get_long()));
2287 match(ConL);
2288
2289 op_cost(15);
2290 format %{ %}
2291 interface(CONST_INTER);
2292 %}
2293
2294 operand immL_Pow2()
2295 %{
2296 predicate(is_power_of_2((julong)n->get_long()));
2297 match(ConL);
2298
2299 op_cost(15);
2300 format %{ %}
2301 interface(CONST_INTER);
2302 %}
2303
2304 operand immL_NotPow2()
2305 %{
2306 predicate(is_power_of_2((julong)~n->get_long()));
2307 match(ConL);
2308
2309 op_cost(15);
2310 format %{ %}
2311 interface(CONST_INTER);
2312 %}
2313
2314 // Long Immediate zero
2315 operand immL0()
2316 %{
2317 predicate(n->get_long() == 0L);
2318 match(ConL);
2319
2320 op_cost(10);
2321 format %{ %}
2322 interface(CONST_INTER);
2323 %}
2324
2325 // Constant for increment
2326 operand immL1()
2327 %{
2328 predicate(n->get_long() == 1);
2329 match(ConL);
2330
2331 format %{ %}
2332 interface(CONST_INTER);
2333 %}
2334
2335 // Constant for decrement
2336 operand immL_M1()
2337 %{
2338 predicate(n->get_long() == -1);
2339 match(ConL);
2340
2341 format %{ %}
2342 interface(CONST_INTER);
2343 %}
2344
2345 // Long Immediate: low 32-bit mask
2346 operand immL_32bits()
2347 %{
2348 predicate(n->get_long() == 0xFFFFFFFFL);
2349 match(ConL);
2350 op_cost(20);
2351
2352 format %{ %}
2353 interface(CONST_INTER);
2354 %}
2355
2356 // Int Immediate: 2^n-1, positive
2357 operand immI_Pow2M1()
2358 %{
2359 predicate((n->get_int() > 0)
2360 && is_power_of_2((juint)n->get_int() + 1));
2361 match(ConI);
2362
2363 op_cost(20);
2364 format %{ %}
2365 interface(CONST_INTER);
2366 %}
2367
2368 // Float Immediate zero
2369 operand immF0()
2370 %{
2371 predicate(jint_cast(n->getf()) == 0);
2372 match(ConF);
2373
2374 op_cost(5);
2375 format %{ %}
2376 interface(CONST_INTER);
2377 %}
2378
2379 // Float Immediate
2380 operand immF()
2381 %{
2382 match(ConF);
2383
2384 op_cost(15);
2385 format %{ %}
2386 interface(CONST_INTER);
2387 %}
2388
2389 // Half Float Immediate
2390 operand immH()
2391 %{
2392 match(ConH);
2393
2394 op_cost(15);
2395 format %{ %}
2396 interface(CONST_INTER);
2397 %}
2398
2399 // Double Immediate zero
2400 operand immD0()
2401 %{
2402 predicate(jlong_cast(n->getd()) == 0);
2403 match(ConD);
2404
2405 op_cost(5);
2406 format %{ %}
2407 interface(CONST_INTER);
2408 %}
2409
2410 // Double Immediate
2411 operand immD()
2412 %{
2413 match(ConD);
2414
2415 op_cost(15);
2416 format %{ %}
2417 interface(CONST_INTER);
2418 %}
2419
2420 // Immediates for special shifts (sign extend)
2421
2422 // Constants for increment
2423 operand immI_16()
2424 %{
2425 predicate(n->get_int() == 16);
2426 match(ConI);
2427
2428 format %{ %}
2429 interface(CONST_INTER);
2430 %}
2431
2432 operand immI_24()
2433 %{
2434 predicate(n->get_int() == 24);
2435 match(ConI);
2436
2437 format %{ %}
2438 interface(CONST_INTER);
2439 %}
2440
2441 // Constant for byte-wide masking
2442 operand immI_255()
2443 %{
2444 predicate(n->get_int() == 255);
2445 match(ConI);
2446
2447 format %{ %}
2448 interface(CONST_INTER);
2449 %}
2450
2451 // Constant for short-wide masking
2452 operand immI_65535()
2453 %{
2454 predicate(n->get_int() == 65535);
2455 match(ConI);
2456
2457 format %{ %}
2458 interface(CONST_INTER);
2459 %}
2460
2461 // Constant for byte-wide masking
2462 operand immL_255()
2463 %{
2464 predicate(n->get_long() == 255);
2465 match(ConL);
2466
2467 format %{ %}
2468 interface(CONST_INTER);
2469 %}
2470
2471 // Constant for short-wide masking
2472 operand immL_65535()
2473 %{
2474 predicate(n->get_long() == 65535);
2475 match(ConL);
2476
2477 format %{ %}
2478 interface(CONST_INTER);
2479 %}
2480
2481 operand kReg()
2482 %{
2483 constraint(ALLOC_IN_RC(vectmask_reg));
2484 match(RegVectMask);
2485 format %{%}
2486 interface(REG_INTER);
2487 %}
2488
2489 // Register Operands
2490 // Integer Register
2491 operand rRegI()
2492 %{
2493 constraint(ALLOC_IN_RC(int_reg));
2494 match(RegI);
2495
2496 match(rax_RegI);
2497 match(rbx_RegI);
2498 match(rcx_RegI);
2499 match(rdx_RegI);
2500 match(rdi_RegI);
2501
2502 format %{ %}
2503 interface(REG_INTER);
2504 %}
2505
2506 // Special Registers
2507 operand rax_RegI()
2508 %{
2509 constraint(ALLOC_IN_RC(int_rax_reg));
2510 match(RegI);
2511 match(rRegI);
2512
2513 format %{ "RAX" %}
2514 interface(REG_INTER);
2515 %}
2516
2517 // Special Registers
2518 operand rbx_RegI()
2519 %{
2520 constraint(ALLOC_IN_RC(int_rbx_reg));
2521 match(RegI);
2522 match(rRegI);
2523
2524 format %{ "RBX" %}
2525 interface(REG_INTER);
2526 %}
2527
2528 operand rcx_RegI()
2529 %{
2530 constraint(ALLOC_IN_RC(int_rcx_reg));
2531 match(RegI);
2532 match(rRegI);
2533
2534 format %{ "RCX" %}
2535 interface(REG_INTER);
2536 %}
2537
2538 operand rdx_RegI()
2539 %{
2540 constraint(ALLOC_IN_RC(int_rdx_reg));
2541 match(RegI);
2542 match(rRegI);
2543
2544 format %{ "RDX" %}
2545 interface(REG_INTER);
2546 %}
2547
2548 operand rdi_RegI()
2549 %{
2550 constraint(ALLOC_IN_RC(int_rdi_reg));
2551 match(RegI);
2552 match(rRegI);
2553
2554 format %{ "RDI" %}
2555 interface(REG_INTER);
2556 %}
2557
2558 operand no_rax_rdx_RegI()
2559 %{
2560 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
2561 match(RegI);
2562 match(rbx_RegI);
2563 match(rcx_RegI);
2564 match(rdi_RegI);
2565
2566 format %{ %}
2567 interface(REG_INTER);
2568 %}
2569
2570 operand no_rbp_r13_RegI()
2571 %{
2572 constraint(ALLOC_IN_RC(int_no_rbp_r13_reg));
2573 match(RegI);
2574 match(rRegI);
2575 match(rax_RegI);
2576 match(rbx_RegI);
2577 match(rcx_RegI);
2578 match(rdx_RegI);
2579 match(rdi_RegI);
2580
2581 format %{ %}
2582 interface(REG_INTER);
2583 %}
2584
2585 // Pointer Register
2586 operand any_RegP()
2587 %{
2588 constraint(ALLOC_IN_RC(any_reg));
2589 match(RegP);
2590 match(rax_RegP);
2591 match(rbx_RegP);
2592 match(rdi_RegP);
2593 match(rsi_RegP);
2594 match(rbp_RegP);
2595 match(r15_RegP);
2596 match(rRegP);
2597
2598 format %{ %}
2599 interface(REG_INTER);
2600 %}
2601
2602 operand rRegP()
2603 %{
2604 constraint(ALLOC_IN_RC(ptr_reg));
2605 match(RegP);
2606 match(rax_RegP);
2607 match(rbx_RegP);
2608 match(rdi_RegP);
2609 match(rsi_RegP);
2610 match(rbp_RegP); // See Q&A below about
2611 match(r15_RegP); // r15_RegP and rbp_RegP.
2612
2613 format %{ %}
2614 interface(REG_INTER);
2615 %}
2616
2617 operand rRegN() %{
2618 constraint(ALLOC_IN_RC(int_reg));
2619 match(RegN);
2620
2621 format %{ %}
2622 interface(REG_INTER);
2623 %}
2624
2625 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
2626 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
2627 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
2628 // The output of an instruction is controlled by the allocator, which respects
2629 // register class masks, not match rules. Unless an instruction mentions
2630 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
2631 // by the allocator as an input.
2632 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
2633 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
2634 // result, RBP is not included in the output of the instruction either.
2635
2636 // This operand is not allowed to use RBP even if
2637 // RBP is not used to hold the frame pointer.
2638 operand no_rbp_RegP()
2639 %{
2640 constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
2641 match(RegP);
2642 match(rbx_RegP);
2643 match(rsi_RegP);
2644 match(rdi_RegP);
2645
2646 format %{ %}
2647 interface(REG_INTER);
2648 %}
2649
2650 // Special Registers
2651 // Return a pointer value
2652 operand rax_RegP()
2653 %{
2654 constraint(ALLOC_IN_RC(ptr_rax_reg));
2655 match(RegP);
2656 match(rRegP);
2657
2658 format %{ %}
2659 interface(REG_INTER);
2660 %}
2661
2662 // Special Registers
2663 // Return a compressed pointer value
2664 operand rax_RegN()
2665 %{
2666 constraint(ALLOC_IN_RC(int_rax_reg));
2667 match(RegN);
2668 match(rRegN);
2669
2670 format %{ %}
2671 interface(REG_INTER);
2672 %}
2673
2674 // Used in AtomicAdd
2675 operand rbx_RegP()
2676 %{
2677 constraint(ALLOC_IN_RC(ptr_rbx_reg));
2678 match(RegP);
2679 match(rRegP);
2680
2681 format %{ %}
2682 interface(REG_INTER);
2683 %}
2684
2685 operand rsi_RegP()
2686 %{
2687 constraint(ALLOC_IN_RC(ptr_rsi_reg));
2688 match(RegP);
2689 match(rRegP);
2690
2691 format %{ %}
2692 interface(REG_INTER);
2693 %}
2694
2695 operand rbp_RegP()
2696 %{
2697 constraint(ALLOC_IN_RC(ptr_rbp_reg));
2698 match(RegP);
2699 match(rRegP);
2700
2701 format %{ %}
2702 interface(REG_INTER);
2703 %}
2704
2705 // Used in rep stosq
2706 operand rdi_RegP()
2707 %{
2708 constraint(ALLOC_IN_RC(ptr_rdi_reg));
2709 match(RegP);
2710 match(rRegP);
2711
2712 format %{ %}
2713 interface(REG_INTER);
2714 %}
2715
2716 operand r15_RegP()
2717 %{
2718 constraint(ALLOC_IN_RC(ptr_r15_reg));
2719 match(RegP);
2720 match(rRegP);
2721
2722 format %{ %}
2723 interface(REG_INTER);
2724 %}
2725
2726 operand rRegL()
2727 %{
2728 constraint(ALLOC_IN_RC(long_reg));
2729 match(RegL);
2730 match(rax_RegL);
2731 match(rdx_RegL);
2732
2733 format %{ %}
2734 interface(REG_INTER);
2735 %}
2736
2737 // Special Registers
2738 operand no_rax_rdx_RegL()
2739 %{
2740 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
2741 match(RegL);
2742 match(rRegL);
2743
2744 format %{ %}
2745 interface(REG_INTER);
2746 %}
2747
2748 operand rax_RegL()
2749 %{
2750 constraint(ALLOC_IN_RC(long_rax_reg));
2751 match(RegL);
2752 match(rRegL);
2753
2754 format %{ "RAX" %}
2755 interface(REG_INTER);
2756 %}
2757
2758 operand rcx_RegL()
2759 %{
2760 constraint(ALLOC_IN_RC(long_rcx_reg));
2761 match(RegL);
2762 match(rRegL);
2763
2764 format %{ %}
2765 interface(REG_INTER);
2766 %}
2767
2768 operand rdx_RegL()
2769 %{
2770 constraint(ALLOC_IN_RC(long_rdx_reg));
2771 match(RegL);
2772 match(rRegL);
2773
2774 format %{ %}
2775 interface(REG_INTER);
2776 %}
2777
2778 operand r11_RegL()
2779 %{
2780 constraint(ALLOC_IN_RC(long_r11_reg));
2781 match(RegL);
2782 match(rRegL);
2783
2784 format %{ %}
2785 interface(REG_INTER);
2786 %}
2787
2788 operand no_rbp_r13_RegL()
2789 %{
2790 constraint(ALLOC_IN_RC(long_no_rbp_r13_reg));
2791 match(RegL);
2792 match(rRegL);
2793 match(rax_RegL);
2794 match(rcx_RegL);
2795 match(rdx_RegL);
2796
2797 format %{ %}
2798 interface(REG_INTER);
2799 %}
2800
2801 // Flags register, used as output of compare instructions
2802 operand rFlagsReg()
2803 %{
2804 constraint(ALLOC_IN_RC(int_flags));
2805 match(RegFlags);
2806
2807 format %{ "RFLAGS" %}
2808 interface(REG_INTER);
2809 %}
2810
2811 // Flags register, used as output of FLOATING POINT compare instructions
2812 operand rFlagsRegU()
2813 %{
2814 constraint(ALLOC_IN_RC(int_flags));
2815 match(RegFlags);
2816
2817 format %{ "RFLAGS_U" %}
2818 interface(REG_INTER);
2819 %}
2820
2821 operand rFlagsRegUCF() %{
2822 constraint(ALLOC_IN_RC(int_flags));
2823 match(RegFlags);
2824 predicate(false);
2825
2826 format %{ "RFLAGS_U_CF" %}
2827 interface(REG_INTER);
2828 %}
2829
2830 // Float register operands
2831 operand regF() %{
2832 constraint(ALLOC_IN_RC(float_reg));
2833 match(RegF);
2834
2835 format %{ %}
2836 interface(REG_INTER);
2837 %}
2838
2839 // Float register operands
2840 operand legRegF() %{
2841 constraint(ALLOC_IN_RC(float_reg_legacy));
2842 match(RegF);
2843
2844 format %{ %}
2845 interface(REG_INTER);
2846 %}
2847
2848 // Float register operands
2849 operand vlRegF() %{
2850 constraint(ALLOC_IN_RC(float_reg_vl));
2851 match(RegF);
2852
2853 format %{ %}
2854 interface(REG_INTER);
2855 %}
2856
2857 // Double register operands
2858 operand regD() %{
2859 constraint(ALLOC_IN_RC(double_reg));
2860 match(RegD);
2861
2862 format %{ %}
2863 interface(REG_INTER);
2864 %}
2865
2866 // Double register operands
2867 operand legRegD() %{
2868 constraint(ALLOC_IN_RC(double_reg_legacy));
2869 match(RegD);
2870
2871 format %{ %}
2872 interface(REG_INTER);
2873 %}
2874
2875 // Double register operands
2876 operand vlRegD() %{
2877 constraint(ALLOC_IN_RC(double_reg_vl));
2878 match(RegD);
2879
2880 format %{ %}
2881 interface(REG_INTER);
2882 %}
2883
2884 //----------Memory Operands----------------------------------------------------
2885 // Direct Memory Operand
2886 // operand direct(immP addr)
2887 // %{
2888 // match(addr);
2889
2890 // format %{ "[$addr]" %}
2891 // interface(MEMORY_INTER) %{
2892 // base(0xFFFFFFFF);
2893 // index(0x4);
2894 // scale(0x0);
2895 // disp($addr);
2896 // %}
2897 // %}
2898
2899 // Indirect Memory Operand
2900 operand indirect(any_RegP reg)
2901 %{
2902 constraint(ALLOC_IN_RC(ptr_reg));
2903 match(reg);
2904
2905 format %{ "[$reg]" %}
2906 interface(MEMORY_INTER) %{
2907 base($reg);
2908 index(0x4);
2909 scale(0x0);
2910 disp(0x0);
2911 %}
2912 %}
2913
2914 // Indirect Memory Plus Short Offset Operand
2915 operand indOffset8(any_RegP reg, immL8 off)
2916 %{
2917 constraint(ALLOC_IN_RC(ptr_reg));
2918 match(AddP reg off);
2919
2920 format %{ "[$reg + $off (8-bit)]" %}
2921 interface(MEMORY_INTER) %{
2922 base($reg);
2923 index(0x4);
2924 scale(0x0);
2925 disp($off);
2926 %}
2927 %}
2928
2929 // Indirect Memory Plus Long Offset Operand
2930 operand indOffset32(any_RegP reg, immL32 off)
2931 %{
2932 constraint(ALLOC_IN_RC(ptr_reg));
2933 match(AddP reg off);
2934
2935 format %{ "[$reg + $off (32-bit)]" %}
2936 interface(MEMORY_INTER) %{
2937 base($reg);
2938 index(0x4);
2939 scale(0x0);
2940 disp($off);
2941 %}
2942 %}
2943
2944 // Indirect Memory Plus Index Register Plus Offset Operand
2945 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
2946 %{
2947 constraint(ALLOC_IN_RC(ptr_reg));
2948 match(AddP (AddP reg lreg) off);
2949
2950 op_cost(10);
2951 format %{"[$reg + $off + $lreg]" %}
2952 interface(MEMORY_INTER) %{
2953 base($reg);
2954 index($lreg);
2955 scale(0x0);
2956 disp($off);
2957 %}
2958 %}
2959
2960 // Indirect Memory Plus Index Register Plus Offset Operand
2961 operand indIndex(any_RegP reg, rRegL lreg)
2962 %{
2963 constraint(ALLOC_IN_RC(ptr_reg));
2964 match(AddP reg lreg);
2965
2966 op_cost(10);
2967 format %{"[$reg + $lreg]" %}
2968 interface(MEMORY_INTER) %{
2969 base($reg);
2970 index($lreg);
2971 scale(0x0);
2972 disp(0x0);
2973 %}
2974 %}
2975
2976 // Indirect Memory Times Scale Plus Index Register
2977 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
2978 %{
2979 constraint(ALLOC_IN_RC(ptr_reg));
2980 match(AddP reg (LShiftL lreg scale));
2981
2982 op_cost(10);
2983 format %{"[$reg + $lreg << $scale]" %}
2984 interface(MEMORY_INTER) %{
2985 base($reg);
2986 index($lreg);
2987 scale($scale);
2988 disp(0x0);
2989 %}
2990 %}
2991
2992 operand indPosIndexScale(any_RegP reg, rRegI idx, immI2 scale)
2993 %{
2994 constraint(ALLOC_IN_RC(ptr_reg));
2995 predicate(n->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
2996 match(AddP reg (LShiftL (ConvI2L idx) scale));
2997
2998 op_cost(10);
2999 format %{"[$reg + pos $idx << $scale]" %}
3000 interface(MEMORY_INTER) %{
3001 base($reg);
3002 index($idx);
3003 scale($scale);
3004 disp(0x0);
3005 %}
3006 %}
3007
3008 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3009 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3010 %{
3011 constraint(ALLOC_IN_RC(ptr_reg));
3012 match(AddP (AddP reg (LShiftL lreg scale)) off);
3013
3014 op_cost(10);
3015 format %{"[$reg + $off + $lreg << $scale]" %}
3016 interface(MEMORY_INTER) %{
3017 base($reg);
3018 index($lreg);
3019 scale($scale);
3020 disp($off);
3021 %}
3022 %}
3023
3024 // Indirect Memory Plus Positive Index Register Plus Offset Operand
3025 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
3026 %{
3027 constraint(ALLOC_IN_RC(ptr_reg));
3028 predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3029 match(AddP (AddP reg (ConvI2L idx)) off);
3030
3031 op_cost(10);
3032 format %{"[$reg + $off + $idx]" %}
3033 interface(MEMORY_INTER) %{
3034 base($reg);
3035 index($idx);
3036 scale(0x0);
3037 disp($off);
3038 %}
3039 %}
3040
3041 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3042 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3043 %{
3044 constraint(ALLOC_IN_RC(ptr_reg));
3045 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3046 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3047
3048 op_cost(10);
3049 format %{"[$reg + $off + $idx << $scale]" %}
3050 interface(MEMORY_INTER) %{
3051 base($reg);
3052 index($idx);
3053 scale($scale);
3054 disp($off);
3055 %}
3056 %}
3057
3058 // Indirect Narrow Oop Plus Offset Operand
3059 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3060 // we can't free r12 even with CompressedOops::base() == nullptr.
3061 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3062 predicate(UseCompressedOops && (CompressedOops::shift() == Address::times_8));
3063 constraint(ALLOC_IN_RC(ptr_reg));
3064 match(AddP (DecodeN reg) off);
3065
3066 op_cost(10);
3067 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3068 interface(MEMORY_INTER) %{
3069 base(0xc); // R12
3070 index($reg);
3071 scale(0x3);
3072 disp($off);
3073 %}
3074 %}
3075
3076 // Indirect Memory Operand
3077 operand indirectNarrow(rRegN reg)
3078 %{
3079 predicate(CompressedOops::shift() == 0);
3080 constraint(ALLOC_IN_RC(ptr_reg));
3081 match(DecodeN reg);
3082
3083 format %{ "[$reg]" %}
3084 interface(MEMORY_INTER) %{
3085 base($reg);
3086 index(0x4);
3087 scale(0x0);
3088 disp(0x0);
3089 %}
3090 %}
3091
3092 // Indirect Memory Plus Short Offset Operand
3093 operand indOffset8Narrow(rRegN reg, immL8 off)
3094 %{
3095 predicate(CompressedOops::shift() == 0);
3096 constraint(ALLOC_IN_RC(ptr_reg));
3097 match(AddP (DecodeN reg) off);
3098
3099 format %{ "[$reg + $off (8-bit)]" %}
3100 interface(MEMORY_INTER) %{
3101 base($reg);
3102 index(0x4);
3103 scale(0x0);
3104 disp($off);
3105 %}
3106 %}
3107
3108 // Indirect Memory Plus Long Offset Operand
3109 operand indOffset32Narrow(rRegN reg, immL32 off)
3110 %{
3111 predicate(CompressedOops::shift() == 0);
3112 constraint(ALLOC_IN_RC(ptr_reg));
3113 match(AddP (DecodeN reg) off);
3114
3115 format %{ "[$reg + $off (32-bit)]" %}
3116 interface(MEMORY_INTER) %{
3117 base($reg);
3118 index(0x4);
3119 scale(0x0);
3120 disp($off);
3121 %}
3122 %}
3123
3124 // Indirect Memory Plus Index Register Plus Offset Operand
3125 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
3126 %{
3127 predicate(CompressedOops::shift() == 0);
3128 constraint(ALLOC_IN_RC(ptr_reg));
3129 match(AddP (AddP (DecodeN reg) lreg) off);
3130
3131 op_cost(10);
3132 format %{"[$reg + $off + $lreg]" %}
3133 interface(MEMORY_INTER) %{
3134 base($reg);
3135 index($lreg);
3136 scale(0x0);
3137 disp($off);
3138 %}
3139 %}
3140
3141 // Indirect Memory Plus Index Register Plus Offset Operand
3142 operand indIndexNarrow(rRegN reg, rRegL lreg)
3143 %{
3144 predicate(CompressedOops::shift() == 0);
3145 constraint(ALLOC_IN_RC(ptr_reg));
3146 match(AddP (DecodeN reg) lreg);
3147
3148 op_cost(10);
3149 format %{"[$reg + $lreg]" %}
3150 interface(MEMORY_INTER) %{
3151 base($reg);
3152 index($lreg);
3153 scale(0x0);
3154 disp(0x0);
3155 %}
3156 %}
3157
3158 // Indirect Memory Times Scale Plus Index Register
3159 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
3160 %{
3161 predicate(CompressedOops::shift() == 0);
3162 constraint(ALLOC_IN_RC(ptr_reg));
3163 match(AddP (DecodeN reg) (LShiftL lreg scale));
3164
3165 op_cost(10);
3166 format %{"[$reg + $lreg << $scale]" %}
3167 interface(MEMORY_INTER) %{
3168 base($reg);
3169 index($lreg);
3170 scale($scale);
3171 disp(0x0);
3172 %}
3173 %}
3174
3175 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3176 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
3177 %{
3178 predicate(CompressedOops::shift() == 0);
3179 constraint(ALLOC_IN_RC(ptr_reg));
3180 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
3181
3182 op_cost(10);
3183 format %{"[$reg + $off + $lreg << $scale]" %}
3184 interface(MEMORY_INTER) %{
3185 base($reg);
3186 index($lreg);
3187 scale($scale);
3188 disp($off);
3189 %}
3190 %}
3191
3192 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
3193 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
3194 %{
3195 constraint(ALLOC_IN_RC(ptr_reg));
3196 predicate(CompressedOops::shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3197 match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
3198
3199 op_cost(10);
3200 format %{"[$reg + $off + $idx]" %}
3201 interface(MEMORY_INTER) %{
3202 base($reg);
3203 index($idx);
3204 scale(0x0);
3205 disp($off);
3206 %}
3207 %}
3208
3209 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3210 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
3211 %{
3212 constraint(ALLOC_IN_RC(ptr_reg));
3213 predicate(CompressedOops::shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3214 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
3215
3216 op_cost(10);
3217 format %{"[$reg + $off + $idx << $scale]" %}
3218 interface(MEMORY_INTER) %{
3219 base($reg);
3220 index($idx);
3221 scale($scale);
3222 disp($off);
3223 %}
3224 %}
3225
3226 //----------Special Memory Operands--------------------------------------------
3227 // Stack Slot Operand - This operand is used for loading and storing temporary
3228 // values on the stack where a match requires a value to
3229 // flow through memory.
3230 operand stackSlotP(sRegP reg)
3231 %{
3232 constraint(ALLOC_IN_RC(stack_slots));
3233 // No match rule because this operand is only generated in matching
3234
3235 format %{ "[$reg]" %}
3236 interface(MEMORY_INTER) %{
3237 base(0x4); // RSP
3238 index(0x4); // No Index
3239 scale(0x0); // No Scale
3240 disp($reg); // Stack Offset
3241 %}
3242 %}
3243
3244 operand stackSlotI(sRegI reg)
3245 %{
3246 constraint(ALLOC_IN_RC(stack_slots));
3247 // No match rule because this operand is only generated in matching
3248
3249 format %{ "[$reg]" %}
3250 interface(MEMORY_INTER) %{
3251 base(0x4); // RSP
3252 index(0x4); // No Index
3253 scale(0x0); // No Scale
3254 disp($reg); // Stack Offset
3255 %}
3256 %}
3257
3258 operand stackSlotF(sRegF reg)
3259 %{
3260 constraint(ALLOC_IN_RC(stack_slots));
3261 // No match rule because this operand is only generated in matching
3262
3263 format %{ "[$reg]" %}
3264 interface(MEMORY_INTER) %{
3265 base(0x4); // RSP
3266 index(0x4); // No Index
3267 scale(0x0); // No Scale
3268 disp($reg); // Stack Offset
3269 %}
3270 %}
3271
3272 operand stackSlotD(sRegD reg)
3273 %{
3274 constraint(ALLOC_IN_RC(stack_slots));
3275 // No match rule because this operand is only generated in matching
3276
3277 format %{ "[$reg]" %}
3278 interface(MEMORY_INTER) %{
3279 base(0x4); // RSP
3280 index(0x4); // No Index
3281 scale(0x0); // No Scale
3282 disp($reg); // Stack Offset
3283 %}
3284 %}
3285 operand stackSlotL(sRegL reg)
3286 %{
3287 constraint(ALLOC_IN_RC(stack_slots));
3288 // No match rule because this operand is only generated in matching
3289
3290 format %{ "[$reg]" %}
3291 interface(MEMORY_INTER) %{
3292 base(0x4); // RSP
3293 index(0x4); // No Index
3294 scale(0x0); // No Scale
3295 disp($reg); // Stack Offset
3296 %}
3297 %}
3298
3299 //----------Conditional Branch Operands----------------------------------------
3300 // Comparison Op - This is the operation of the comparison, and is limited to
3301 // the following set of codes:
3302 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3303 //
3304 // Other attributes of the comparison, such as unsignedness, are specified
3305 // by the comparison instruction that sets a condition code flags register.
3306 // That result is represented by a flags operand whose subtype is appropriate
3307 // to the unsignedness (etc.) of the comparison.
3308 //
3309 // Later, the instruction which matches both the Comparison Op (a Bool) and
3310 // the flags (produced by the Cmp) specifies the coding of the comparison op
3311 // by matching a specific subtype of Bool operand below, such as cmpOpU.
3312
3313 // Comparison Code
3314 operand cmpOp()
3315 %{
3316 match(Bool);
3317
3318 format %{ "" %}
3319 interface(COND_INTER) %{
3320 equal(0x4, "e");
3321 not_equal(0x5, "ne");
3322 less(0xC, "l");
3323 greater_equal(0xD, "ge");
3324 less_equal(0xE, "le");
3325 greater(0xF, "g");
3326 overflow(0x0, "o");
3327 no_overflow(0x1, "no");
3328 %}
3329 %}
3330
3331 // Comparison Code, unsigned compare. Used by FP also, with
3332 // C2 (unordered) turned into GT or LT already. The other bits
3333 // C0 and C3 are turned into Carry & Zero flags.
3334 operand cmpOpU()
3335 %{
3336 match(Bool);
3337
3338 format %{ "" %}
3339 interface(COND_INTER) %{
3340 equal(0x4, "e");
3341 not_equal(0x5, "ne");
3342 less(0x2, "b");
3343 greater_equal(0x3, "ae");
3344 less_equal(0x6, "be");
3345 greater(0x7, "a");
3346 overflow(0x0, "o");
3347 no_overflow(0x1, "no");
3348 %}
3349 %}
3350
3351
3352 // Floating comparisons that don't require any fixup for the unordered case,
3353 // If both inputs of the comparison are the same, ZF is always set so we
3354 // don't need to use cmpOpUCF2 for eq/ne
3355 operand cmpOpUCF() %{
3356 match(Bool);
3357 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
3358 n->as_Bool()->_test._test == BoolTest::ge ||
3359 n->as_Bool()->_test._test == BoolTest::le ||
3360 n->as_Bool()->_test._test == BoolTest::gt ||
3361 n->in(1)->in(1) == n->in(1)->in(2));
3362 format %{ "" %}
3363 interface(COND_INTER) %{
3364 equal(0xb, "np");
3365 not_equal(0xa, "p");
3366 less(0x2, "b");
3367 greater_equal(0x3, "ae");
3368 less_equal(0x6, "be");
3369 greater(0x7, "a");
3370 overflow(0x0, "o");
3371 no_overflow(0x1, "no");
3372 %}
3373 %}
3374
3375
3376 // Floating comparisons that can be fixed up with extra conditional jumps
3377 operand cmpOpUCF2() %{
3378 match(Bool);
3379 predicate((n->as_Bool()->_test._test == BoolTest::ne ||
3380 n->as_Bool()->_test._test == BoolTest::eq) &&
3381 n->in(1)->in(1) != n->in(1)->in(2));
3382 format %{ "" %}
3383 interface(COND_INTER) %{
3384 equal(0x4, "e");
3385 not_equal(0x5, "ne");
3386 less(0x2, "b");
3387 greater_equal(0x3, "ae");
3388 less_equal(0x6, "be");
3389 greater(0x7, "a");
3390 overflow(0x0, "o");
3391 no_overflow(0x1, "no");
3392 %}
3393 %}
3394
3395 //----------OPERAND CLASSES----------------------------------------------------
3396 // Operand Classes are groups of operands that are used as to simplify
3397 // instruction definitions by not requiring the AD writer to specify separate
3398 // instructions for every form of operand when the instruction accepts
3399 // multiple operand types with the same basic encoding and format. The classic
3400 // case of this is memory operands.
3401
3402 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
3403 indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
3404 indCompressedOopOffset,
3405 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
3406 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
3407 indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
3408
3409 //----------PIPELINE-----------------------------------------------------------
3410 // Rules which define the behavior of the target architectures pipeline.
3411 pipeline %{
3412
3413 //----------ATTRIBUTES---------------------------------------------------------
3414 attributes %{
3415 variable_size_instructions; // Fixed size instructions
3416 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
3417 instruction_unit_size = 1; // An instruction is 1 bytes long
3418 instruction_fetch_unit_size = 16; // The processor fetches one line
3419 instruction_fetch_units = 1; // of 16 bytes
3420
3421 // List of nop instructions
3422 nops( MachNop );
3423 %}
3424
3425 //----------RESOURCES----------------------------------------------------------
3426 // Resources are the functional units available to the machine
3427
3428 // Generic P2/P3 pipeline
3429 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
3430 // 3 instructions decoded per cycle.
3431 // 2 load/store ops per cycle, 1 branch, 1 FPU,
3432 // 3 ALU op, only ALU0 handles mul instructions.
3433 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
3434 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
3435 BR, FPU,
3436 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
3437
3438 //----------PIPELINE DESCRIPTION-----------------------------------------------
3439 // Pipeline Description specifies the stages in the machine's pipeline
3440
3441 // Generic P2/P3 pipeline
3442 pipe_desc(S0, S1, S2, S3, S4, S5);
3443
3444 //----------PIPELINE CLASSES---------------------------------------------------
3445 // Pipeline Classes describe the stages in which input and output are
3446 // referenced by the hardware pipeline.
3447
3448 // Naming convention: ialu or fpu
3449 // Then: _reg
3450 // Then: _reg if there is a 2nd register
3451 // Then: _long if it's a pair of instructions implementing a long
3452 // Then: _fat if it requires the big decoder
3453 // Or: _mem if it requires the big decoder and a memory unit.
3454
3455 // Integer ALU reg operation
3456 pipe_class ialu_reg(rRegI dst)
3457 %{
3458 single_instruction;
3459 dst : S4(write);
3460 dst : S3(read);
3461 DECODE : S0; // any decoder
3462 ALU : S3; // any alu
3463 %}
3464
3465 // Long ALU reg operation
3466 pipe_class ialu_reg_long(rRegL dst)
3467 %{
3468 instruction_count(2);
3469 dst : S4(write);
3470 dst : S3(read);
3471 DECODE : S0(2); // any 2 decoders
3472 ALU : S3(2); // both alus
3473 %}
3474
3475 // Integer ALU reg operation using big decoder
3476 pipe_class ialu_reg_fat(rRegI dst)
3477 %{
3478 single_instruction;
3479 dst : S4(write);
3480 dst : S3(read);
3481 D0 : S0; // big decoder only
3482 ALU : S3; // any alu
3483 %}
3484
3485 // Integer ALU reg-reg operation
3486 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
3487 %{
3488 single_instruction;
3489 dst : S4(write);
3490 src : S3(read);
3491 DECODE : S0; // any decoder
3492 ALU : S3; // any alu
3493 %}
3494
3495 // Integer ALU reg-reg operation
3496 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
3497 %{
3498 single_instruction;
3499 dst : S4(write);
3500 src : S3(read);
3501 D0 : S0; // big decoder only
3502 ALU : S3; // any alu
3503 %}
3504
3505 // Integer ALU reg-mem operation
3506 pipe_class ialu_reg_mem(rRegI dst, memory mem)
3507 %{
3508 single_instruction;
3509 dst : S5(write);
3510 mem : S3(read);
3511 D0 : S0; // big decoder only
3512 ALU : S4; // any alu
3513 MEM : S3; // any mem
3514 %}
3515
3516 // Integer mem operation (prefetch)
3517 pipe_class ialu_mem(memory mem)
3518 %{
3519 single_instruction;
3520 mem : S3(read);
3521 D0 : S0; // big decoder only
3522 MEM : S3; // any mem
3523 %}
3524
3525 // Integer Store to Memory
3526 pipe_class ialu_mem_reg(memory mem, rRegI src)
3527 %{
3528 single_instruction;
3529 mem : S3(read);
3530 src : S5(read);
3531 D0 : S0; // big decoder only
3532 ALU : S4; // any alu
3533 MEM : S3;
3534 %}
3535
3536 // // Long Store to Memory
3537 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
3538 // %{
3539 // instruction_count(2);
3540 // mem : S3(read);
3541 // src : S5(read);
3542 // D0 : S0(2); // big decoder only; twice
3543 // ALU : S4(2); // any 2 alus
3544 // MEM : S3(2); // Both mems
3545 // %}
3546
3547 // Integer Store to Memory
3548 pipe_class ialu_mem_imm(memory mem)
3549 %{
3550 single_instruction;
3551 mem : S3(read);
3552 D0 : S0; // big decoder only
3553 ALU : S4; // any alu
3554 MEM : S3;
3555 %}
3556
3557 // Integer ALU0 reg-reg operation
3558 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
3559 %{
3560 single_instruction;
3561 dst : S4(write);
3562 src : S3(read);
3563 D0 : S0; // Big decoder only
3564 ALU0 : S3; // only alu0
3565 %}
3566
3567 // Integer ALU0 reg-mem operation
3568 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
3569 %{
3570 single_instruction;
3571 dst : S5(write);
3572 mem : S3(read);
3573 D0 : S0; // big decoder only
3574 ALU0 : S4; // ALU0 only
3575 MEM : S3; // any mem
3576 %}
3577
3578 // Integer ALU reg-reg operation
3579 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
3580 %{
3581 single_instruction;
3582 cr : S4(write);
3583 src1 : S3(read);
3584 src2 : S3(read);
3585 DECODE : S0; // any decoder
3586 ALU : S3; // any alu
3587 %}
3588
3589 // Integer ALU reg-imm operation
3590 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
3591 %{
3592 single_instruction;
3593 cr : S4(write);
3594 src1 : S3(read);
3595 DECODE : S0; // any decoder
3596 ALU : S3; // any alu
3597 %}
3598
3599 // Integer ALU reg-mem operation
3600 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
3601 %{
3602 single_instruction;
3603 cr : S4(write);
3604 src1 : S3(read);
3605 src2 : S3(read);
3606 D0 : S0; // big decoder only
3607 ALU : S4; // any alu
3608 MEM : S3;
3609 %}
3610
3611 // Conditional move reg-reg
3612 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
3613 %{
3614 instruction_count(4);
3615 y : S4(read);
3616 q : S3(read);
3617 p : S3(read);
3618 DECODE : S0(4); // any decoder
3619 %}
3620
3621 // Conditional move reg-reg
3622 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
3623 %{
3624 single_instruction;
3625 dst : S4(write);
3626 src : S3(read);
3627 cr : S3(read);
3628 DECODE : S0; // any decoder
3629 %}
3630
3631 // Conditional move reg-mem
3632 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
3633 %{
3634 single_instruction;
3635 dst : S4(write);
3636 src : S3(read);
3637 cr : S3(read);
3638 DECODE : S0; // any decoder
3639 MEM : S3;
3640 %}
3641
3642 // Conditional move reg-reg long
3643 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
3644 %{
3645 single_instruction;
3646 dst : S4(write);
3647 src : S3(read);
3648 cr : S3(read);
3649 DECODE : S0(2); // any 2 decoders
3650 %}
3651
3652 // Float reg-reg operation
3653 pipe_class fpu_reg(regD dst)
3654 %{
3655 instruction_count(2);
3656 dst : S3(read);
3657 DECODE : S0(2); // any 2 decoders
3658 FPU : S3;
3659 %}
3660
3661 // Float reg-reg operation
3662 pipe_class fpu_reg_reg(regD dst, regD src)
3663 %{
3664 instruction_count(2);
3665 dst : S4(write);
3666 src : S3(read);
3667 DECODE : S0(2); // any 2 decoders
3668 FPU : S3;
3669 %}
3670
3671 // Float reg-reg operation
3672 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
3673 %{
3674 instruction_count(3);
3675 dst : S4(write);
3676 src1 : S3(read);
3677 src2 : S3(read);
3678 DECODE : S0(3); // any 3 decoders
3679 FPU : S3(2);
3680 %}
3681
3682 // Float reg-reg operation
3683 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
3684 %{
3685 instruction_count(4);
3686 dst : S4(write);
3687 src1 : S3(read);
3688 src2 : S3(read);
3689 src3 : S3(read);
3690 DECODE : S0(4); // any 3 decoders
3691 FPU : S3(2);
3692 %}
3693
3694 // Float reg-reg operation
3695 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
3696 %{
3697 instruction_count(4);
3698 dst : S4(write);
3699 src1 : S3(read);
3700 src2 : S3(read);
3701 src3 : S3(read);
3702 DECODE : S1(3); // any 3 decoders
3703 D0 : S0; // Big decoder only
3704 FPU : S3(2);
3705 MEM : S3;
3706 %}
3707
3708 // Float reg-mem operation
3709 pipe_class fpu_reg_mem(regD dst, memory mem)
3710 %{
3711 instruction_count(2);
3712 dst : S5(write);
3713 mem : S3(read);
3714 D0 : S0; // big decoder only
3715 DECODE : S1; // any decoder for FPU POP
3716 FPU : S4;
3717 MEM : S3; // any mem
3718 %}
3719
3720 // Float reg-mem operation
3721 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
3722 %{
3723 instruction_count(3);
3724 dst : S5(write);
3725 src1 : S3(read);
3726 mem : S3(read);
3727 D0 : S0; // big decoder only
3728 DECODE : S1(2); // any decoder for FPU POP
3729 FPU : S4;
3730 MEM : S3; // any mem
3731 %}
3732
3733 // Float mem-reg operation
3734 pipe_class fpu_mem_reg(memory mem, regD src)
3735 %{
3736 instruction_count(2);
3737 src : S5(read);
3738 mem : S3(read);
3739 DECODE : S0; // any decoder for FPU PUSH
3740 D0 : S1; // big decoder only
3741 FPU : S4;
3742 MEM : S3; // any mem
3743 %}
3744
3745 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
3746 %{
3747 instruction_count(3);
3748 src1 : S3(read);
3749 src2 : S3(read);
3750 mem : S3(read);
3751 DECODE : S0(2); // any decoder for FPU PUSH
3752 D0 : S1; // big decoder only
3753 FPU : S4;
3754 MEM : S3; // any mem
3755 %}
3756
3757 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
3758 %{
3759 instruction_count(3);
3760 src1 : S3(read);
3761 src2 : S3(read);
3762 mem : S4(read);
3763 DECODE : S0; // any decoder for FPU PUSH
3764 D0 : S0(2); // big decoder only
3765 FPU : S4;
3766 MEM : S3(2); // any mem
3767 %}
3768
3769 pipe_class fpu_mem_mem(memory dst, memory src1)
3770 %{
3771 instruction_count(2);
3772 src1 : S3(read);
3773 dst : S4(read);
3774 D0 : S0(2); // big decoder only
3775 MEM : S3(2); // any mem
3776 %}
3777
3778 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
3779 %{
3780 instruction_count(3);
3781 src1 : S3(read);
3782 src2 : S3(read);
3783 dst : S4(read);
3784 D0 : S0(3); // big decoder only
3785 FPU : S4;
3786 MEM : S3(3); // any mem
3787 %}
3788
3789 pipe_class fpu_mem_reg_con(memory mem, regD src1)
3790 %{
3791 instruction_count(3);
3792 src1 : S4(read);
3793 mem : S4(read);
3794 DECODE : S0; // any decoder for FPU PUSH
3795 D0 : S0(2); // big decoder only
3796 FPU : S4;
3797 MEM : S3(2); // any mem
3798 %}
3799
3800 // Float load constant
3801 pipe_class fpu_reg_con(regD dst)
3802 %{
3803 instruction_count(2);
3804 dst : S5(write);
3805 D0 : S0; // big decoder only for the load
3806 DECODE : S1; // any decoder for FPU POP
3807 FPU : S4;
3808 MEM : S3; // any mem
3809 %}
3810
3811 // Float load constant
3812 pipe_class fpu_reg_reg_con(regD dst, regD src)
3813 %{
3814 instruction_count(3);
3815 dst : S5(write);
3816 src : S3(read);
3817 D0 : S0; // big decoder only for the load
3818 DECODE : S1(2); // any decoder for FPU POP
3819 FPU : S4;
3820 MEM : S3; // any mem
3821 %}
3822
3823 // UnConditional branch
3824 pipe_class pipe_jmp(label labl)
3825 %{
3826 single_instruction;
3827 BR : S3;
3828 %}
3829
3830 // Conditional branch
3831 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
3832 %{
3833 single_instruction;
3834 cr : S1(read);
3835 BR : S3;
3836 %}
3837
3838 // Allocation idiom
3839 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
3840 %{
3841 instruction_count(1); force_serialization;
3842 fixed_latency(6);
3843 heap_ptr : S3(read);
3844 DECODE : S0(3);
3845 D0 : S2;
3846 MEM : S3;
3847 ALU : S3(2);
3848 dst : S5(write);
3849 BR : S5;
3850 %}
3851
3852 // Generic big/slow expanded idiom
3853 pipe_class pipe_slow()
3854 %{
3855 instruction_count(10); multiple_bundles; force_serialization;
3856 fixed_latency(100);
3857 D0 : S0(2);
3858 MEM : S3(2);
3859 %}
3860
3861 // The real do-nothing guy
3862 pipe_class empty()
3863 %{
3864 instruction_count(0);
3865 %}
3866
3867 // Define the class for the Nop node
3868 define
3869 %{
3870 MachNop = empty;
3871 %}
3872
3873 %}
3874
3875 //----------INSTRUCTIONS-------------------------------------------------------
3876 //
3877 // match -- States which machine-independent subtree may be replaced
3878 // by this instruction.
3879 // ins_cost -- The estimated cost of this instruction is used by instruction
3880 // selection to identify a minimum cost tree of machine
3881 // instructions that matches a tree of machine-independent
3882 // instructions.
3883 // format -- A string providing the disassembly for this instruction.
3884 // The value of an instruction's operand may be inserted
3885 // by referring to it with a '$' prefix.
3886 // opcode -- Three instruction opcodes may be provided. These are referred
3887 // to within an encode class as $primary, $secondary, and $tertiary
3888 // rrspectively. The primary opcode is commonly used to
3889 // indicate the type of machine instruction, while secondary
3890 // and tertiary are often used for prefix options or addressing
3891 // modes.
3892 // ins_encode -- A list of encode classes with parameters. The encode class
3893 // name must have been defined in an 'enc_class' specification
3894 // in the encode section of the architecture description.
3895
3896 // Dummy reg-to-reg vector moves. Removed during post-selection cleanup.
3897 // Load Float
3898 instruct MoveF2VL(vlRegF dst, regF src) %{
3899 match(Set dst src);
3900 format %{ "movss $dst,$src\t! load float (4 bytes)" %}
3901 ins_encode %{
3902 ShouldNotReachHere();
3903 %}
3904 ins_pipe( fpu_reg_reg );
3905 %}
3906
3907 // Load Float
3908 instruct MoveF2LEG(legRegF dst, regF src) %{
3909 match(Set dst src);
3910 format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
3911 ins_encode %{
3912 ShouldNotReachHere();
3913 %}
3914 ins_pipe( fpu_reg_reg );
3915 %}
3916
3917 // Load Float
3918 instruct MoveVL2F(regF dst, vlRegF src) %{
3919 match(Set dst src);
3920 format %{ "movss $dst,$src\t! load float (4 bytes)" %}
3921 ins_encode %{
3922 ShouldNotReachHere();
3923 %}
3924 ins_pipe( fpu_reg_reg );
3925 %}
3926
3927 // Load Float
3928 instruct MoveLEG2F(regF dst, legRegF src) %{
3929 match(Set dst src);
3930 format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
3931 ins_encode %{
3932 ShouldNotReachHere();
3933 %}
3934 ins_pipe( fpu_reg_reg );
3935 %}
3936
3937 // Load Double
3938 instruct MoveD2VL(vlRegD dst, regD src) %{
3939 match(Set dst src);
3940 format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
3941 ins_encode %{
3942 ShouldNotReachHere();
3943 %}
3944 ins_pipe( fpu_reg_reg );
3945 %}
3946
3947 // Load Double
3948 instruct MoveD2LEG(legRegD dst, regD src) %{
3949 match(Set dst src);
3950 format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
3951 ins_encode %{
3952 ShouldNotReachHere();
3953 %}
3954 ins_pipe( fpu_reg_reg );
3955 %}
3956
3957 // Load Double
3958 instruct MoveVL2D(regD dst, vlRegD src) %{
3959 match(Set dst src);
3960 format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
3961 ins_encode %{
3962 ShouldNotReachHere();
3963 %}
3964 ins_pipe( fpu_reg_reg );
3965 %}
3966
3967 // Load Double
3968 instruct MoveLEG2D(regD dst, legRegD src) %{
3969 match(Set dst src);
3970 format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
3971 ins_encode %{
3972 ShouldNotReachHere();
3973 %}
3974 ins_pipe( fpu_reg_reg );
3975 %}
3976
3977 //----------Load/Store/Move Instructions---------------------------------------
3978 //----------Load Instructions--------------------------------------------------
3979
3980 // Load Byte (8 bit signed)
3981 instruct loadB(rRegI dst, memory mem)
3982 %{
3983 match(Set dst (LoadB mem));
3984
3985 ins_cost(125);
3986 format %{ "movsbl $dst, $mem\t# byte" %}
3987
3988 ins_encode %{
3989 __ movsbl($dst$$Register, $mem$$Address);
3990 %}
3991
3992 ins_pipe(ialu_reg_mem);
3993 %}
3994
3995 // Load Byte (8 bit signed) into Long Register
3996 instruct loadB2L(rRegL dst, memory mem)
3997 %{
3998 match(Set dst (ConvI2L (LoadB mem)));
3999
4000 ins_cost(125);
4001 format %{ "movsbq $dst, $mem\t# byte -> long" %}
4002
4003 ins_encode %{
4004 __ movsbq($dst$$Register, $mem$$Address);
4005 %}
4006
4007 ins_pipe(ialu_reg_mem);
4008 %}
4009
4010 // Load Unsigned Byte (8 bit UNsigned)
4011 instruct loadUB(rRegI dst, memory mem)
4012 %{
4013 match(Set dst (LoadUB mem));
4014
4015 ins_cost(125);
4016 format %{ "movzbl $dst, $mem\t# ubyte" %}
4017
4018 ins_encode %{
4019 __ movzbl($dst$$Register, $mem$$Address);
4020 %}
4021
4022 ins_pipe(ialu_reg_mem);
4023 %}
4024
4025 // Load Unsigned Byte (8 bit UNsigned) into Long Register
4026 instruct loadUB2L(rRegL dst, memory mem)
4027 %{
4028 match(Set dst (ConvI2L (LoadUB mem)));
4029
4030 ins_cost(125);
4031 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
4032
4033 ins_encode %{
4034 __ movzbq($dst$$Register, $mem$$Address);
4035 %}
4036
4037 ins_pipe(ialu_reg_mem);
4038 %}
4039
4040 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
4041 instruct loadUB2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4042 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
4043 effect(KILL cr);
4044
4045 format %{ "movzbq $dst, $mem\t# ubyte & 32-bit mask -> long\n\t"
4046 "andl $dst, right_n_bits($mask, 8)" %}
4047 ins_encode %{
4048 Register Rdst = $dst$$Register;
4049 __ movzbq(Rdst, $mem$$Address);
4050 __ andl(Rdst, $mask$$constant & right_n_bits(8));
4051 %}
4052 ins_pipe(ialu_reg_mem);
4053 %}
4054
4055 // Load Short (16 bit signed)
4056 instruct loadS(rRegI dst, memory mem)
4057 %{
4058 match(Set dst (LoadS mem));
4059
4060 ins_cost(125);
4061 format %{ "movswl $dst, $mem\t# short" %}
4062
4063 ins_encode %{
4064 __ movswl($dst$$Register, $mem$$Address);
4065 %}
4066
4067 ins_pipe(ialu_reg_mem);
4068 %}
4069
4070 // Load Short (16 bit signed) to Byte (8 bit signed)
4071 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4072 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
4073
4074 ins_cost(125);
4075 format %{ "movsbl $dst, $mem\t# short -> byte" %}
4076 ins_encode %{
4077 __ movsbl($dst$$Register, $mem$$Address);
4078 %}
4079 ins_pipe(ialu_reg_mem);
4080 %}
4081
4082 // Load Short (16 bit signed) into Long Register
4083 instruct loadS2L(rRegL dst, memory mem)
4084 %{
4085 match(Set dst (ConvI2L (LoadS mem)));
4086
4087 ins_cost(125);
4088 format %{ "movswq $dst, $mem\t# short -> long" %}
4089
4090 ins_encode %{
4091 __ movswq($dst$$Register, $mem$$Address);
4092 %}
4093
4094 ins_pipe(ialu_reg_mem);
4095 %}
4096
4097 // Load Unsigned Short/Char (16 bit UNsigned)
4098 instruct loadUS(rRegI dst, memory mem)
4099 %{
4100 match(Set dst (LoadUS mem));
4101
4102 ins_cost(125);
4103 format %{ "movzwl $dst, $mem\t# ushort/char" %}
4104
4105 ins_encode %{
4106 __ movzwl($dst$$Register, $mem$$Address);
4107 %}
4108
4109 ins_pipe(ialu_reg_mem);
4110 %}
4111
4112 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
4113 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4114 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
4115
4116 ins_cost(125);
4117 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
4118 ins_encode %{
4119 __ movsbl($dst$$Register, $mem$$Address);
4120 %}
4121 ins_pipe(ialu_reg_mem);
4122 %}
4123
4124 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
4125 instruct loadUS2L(rRegL dst, memory mem)
4126 %{
4127 match(Set dst (ConvI2L (LoadUS mem)));
4128
4129 ins_cost(125);
4130 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
4131
4132 ins_encode %{
4133 __ movzwq($dst$$Register, $mem$$Address);
4134 %}
4135
4136 ins_pipe(ialu_reg_mem);
4137 %}
4138
4139 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
4140 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4141 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4142
4143 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
4144 ins_encode %{
4145 __ movzbq($dst$$Register, $mem$$Address);
4146 %}
4147 ins_pipe(ialu_reg_mem);
4148 %}
4149
4150 // Load Unsigned Short/Char (16 bit UNsigned) with 32-bit mask into Long Register
4151 instruct loadUS2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4152 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4153 effect(KILL cr);
4154
4155 format %{ "movzwq $dst, $mem\t# ushort/char & 32-bit mask -> long\n\t"
4156 "andl $dst, right_n_bits($mask, 16)" %}
4157 ins_encode %{
4158 Register Rdst = $dst$$Register;
4159 __ movzwq(Rdst, $mem$$Address);
4160 __ andl(Rdst, $mask$$constant & right_n_bits(16));
4161 %}
4162 ins_pipe(ialu_reg_mem);
4163 %}
4164
4165 // Load Integer
4166 instruct loadI(rRegI dst, memory mem)
4167 %{
4168 match(Set dst (LoadI mem));
4169
4170 ins_cost(125);
4171 format %{ "movl $dst, $mem\t# int" %}
4172
4173 ins_encode %{
4174 __ movl($dst$$Register, $mem$$Address);
4175 %}
4176
4177 ins_pipe(ialu_reg_mem);
4178 %}
4179
4180 // Load Integer (32 bit signed) to Byte (8 bit signed)
4181 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4182 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
4183
4184 ins_cost(125);
4185 format %{ "movsbl $dst, $mem\t# int -> byte" %}
4186 ins_encode %{
4187 __ movsbl($dst$$Register, $mem$$Address);
4188 %}
4189 ins_pipe(ialu_reg_mem);
4190 %}
4191
4192 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
4193 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
4194 match(Set dst (AndI (LoadI mem) mask));
4195
4196 ins_cost(125);
4197 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
4198 ins_encode %{
4199 __ movzbl($dst$$Register, $mem$$Address);
4200 %}
4201 ins_pipe(ialu_reg_mem);
4202 %}
4203
4204 // Load Integer (32 bit signed) to Short (16 bit signed)
4205 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
4206 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
4207
4208 ins_cost(125);
4209 format %{ "movswl $dst, $mem\t# int -> short" %}
4210 ins_encode %{
4211 __ movswl($dst$$Register, $mem$$Address);
4212 %}
4213 ins_pipe(ialu_reg_mem);
4214 %}
4215
4216 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
4217 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
4218 match(Set dst (AndI (LoadI mem) mask));
4219
4220 ins_cost(125);
4221 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
4222 ins_encode %{
4223 __ movzwl($dst$$Register, $mem$$Address);
4224 %}
4225 ins_pipe(ialu_reg_mem);
4226 %}
4227
4228 // Load Integer into Long Register
4229 instruct loadI2L(rRegL dst, memory mem)
4230 %{
4231 match(Set dst (ConvI2L (LoadI mem)));
4232
4233 ins_cost(125);
4234 format %{ "movslq $dst, $mem\t# int -> long" %}
4235
4236 ins_encode %{
4237 __ movslq($dst$$Register, $mem$$Address);
4238 %}
4239
4240 ins_pipe(ialu_reg_mem);
4241 %}
4242
4243 // Load Integer with mask 0xFF into Long Register
4244 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4245 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4246
4247 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
4248 ins_encode %{
4249 __ movzbq($dst$$Register, $mem$$Address);
4250 %}
4251 ins_pipe(ialu_reg_mem);
4252 %}
4253
4254 // Load Integer with mask 0xFFFF into Long Register
4255 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
4256 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4257
4258 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
4259 ins_encode %{
4260 __ movzwq($dst$$Register, $mem$$Address);
4261 %}
4262 ins_pipe(ialu_reg_mem);
4263 %}
4264
4265 // Load Integer with a 31-bit mask into Long Register
4266 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
4267 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4268 effect(KILL cr);
4269
4270 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t"
4271 "andl $dst, $mask" %}
4272 ins_encode %{
4273 Register Rdst = $dst$$Register;
4274 __ movl(Rdst, $mem$$Address);
4275 __ andl(Rdst, $mask$$constant);
4276 %}
4277 ins_pipe(ialu_reg_mem);
4278 %}
4279
4280 // Load Unsigned Integer into Long Register
4281 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
4282 %{
4283 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
4284
4285 ins_cost(125);
4286 format %{ "movl $dst, $mem\t# uint -> long" %}
4287
4288 ins_encode %{
4289 __ movl($dst$$Register, $mem$$Address);
4290 %}
4291
4292 ins_pipe(ialu_reg_mem);
4293 %}
4294
4295 // Load Long
4296 instruct loadL(rRegL dst, memory mem)
4297 %{
4298 match(Set dst (LoadL mem));
4299
4300 ins_cost(125);
4301 format %{ "movq $dst, $mem\t# long" %}
4302
4303 ins_encode %{
4304 __ movq($dst$$Register, $mem$$Address);
4305 %}
4306
4307 ins_pipe(ialu_reg_mem); // XXX
4308 %}
4309
4310 // Load Range
4311 instruct loadRange(rRegI dst, memory mem)
4312 %{
4313 match(Set dst (LoadRange mem));
4314
4315 ins_cost(125); // XXX
4316 format %{ "movl $dst, $mem\t# range" %}
4317 ins_encode %{
4318 __ movl($dst$$Register, $mem$$Address);
4319 %}
4320 ins_pipe(ialu_reg_mem);
4321 %}
4322
4323 // Load Pointer
4324 instruct loadP(rRegP dst, memory mem)
4325 %{
4326 match(Set dst (LoadP mem));
4327 predicate(n->as_Load()->barrier_data() == 0);
4328
4329 ins_cost(125); // XXX
4330 format %{ "movq $dst, $mem\t# ptr" %}
4331 ins_encode %{
4332 __ movq($dst$$Register, $mem$$Address);
4333 %}
4334 ins_pipe(ialu_reg_mem); // XXX
4335 %}
4336
4337 // Load Compressed Pointer
4338 instruct loadN(rRegN dst, memory mem)
4339 %{
4340 predicate(n->as_Load()->barrier_data() == 0);
4341 match(Set dst (LoadN mem));
4342
4343 ins_cost(125); // XXX
4344 format %{ "movl $dst, $mem\t# compressed ptr" %}
4345 ins_encode %{
4346 __ movl($dst$$Register, $mem$$Address);
4347 %}
4348 ins_pipe(ialu_reg_mem); // XXX
4349 %}
4350
4351
4352 // Load Klass Pointer
4353 instruct loadKlass(rRegP dst, memory mem)
4354 %{
4355 match(Set dst (LoadKlass mem));
4356
4357 ins_cost(125); // XXX
4358 format %{ "movq $dst, $mem\t# class" %}
4359 ins_encode %{
4360 __ movq($dst$$Register, $mem$$Address);
4361 %}
4362 ins_pipe(ialu_reg_mem); // XXX
4363 %}
4364
4365 // Load narrow Klass Pointer
4366 instruct loadNKlass(rRegN dst, memory mem)
4367 %{
4368 predicate(!UseCompactObjectHeaders);
4369 match(Set dst (LoadNKlass mem));
4370
4371 ins_cost(125); // XXX
4372 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
4373 ins_encode %{
4374 __ movl($dst$$Register, $mem$$Address);
4375 %}
4376 ins_pipe(ialu_reg_mem); // XXX
4377 %}
4378
4379 instruct loadNKlassCompactHeaders(rRegN dst, memory mem, rFlagsReg cr)
4380 %{
4381 predicate(UseCompactObjectHeaders);
4382 match(Set dst (LoadNKlass mem));
4383 effect(KILL cr);
4384 ins_cost(125);
4385 format %{
4386 "movl $dst, $mem\t# compressed klass ptr, shifted\n\t"
4387 "shrl $dst, markWord::klass_shift"
4388 %}
4389 ins_encode %{
4390 // The incoming address is pointing into obj-start + Type::klass_offset(). We need to extract
4391 // obj-start, so that we can load from the object's mark-word instead.
4392 Register d = $dst$$Register;
4393 Address s = ($mem$$Address).plus_disp(-Type::klass_offset());
4394 if (UseAPX) {
4395 __ eshrl(d, s, markWord::klass_shift, false);
4396 } else {
4397 __ movl(d, s);
4398 __ shrl(d, markWord::klass_shift);
4399 }
4400 %}
4401 ins_pipe(ialu_reg_mem);
4402 %}
4403
4404 // Load Float
4405 instruct loadF(regF dst, memory mem)
4406 %{
4407 match(Set dst (LoadF mem));
4408
4409 ins_cost(145); // XXX
4410 format %{ "movss $dst, $mem\t# float" %}
4411 ins_encode %{
4412 __ movflt($dst$$XMMRegister, $mem$$Address);
4413 %}
4414 ins_pipe(pipe_slow); // XXX
4415 %}
4416
4417 // Load Double
4418 instruct loadD_partial(regD dst, memory mem)
4419 %{
4420 predicate(!UseXmmLoadAndClearUpper);
4421 match(Set dst (LoadD mem));
4422
4423 ins_cost(145); // XXX
4424 format %{ "movlpd $dst, $mem\t# double" %}
4425 ins_encode %{
4426 __ movdbl($dst$$XMMRegister, $mem$$Address);
4427 %}
4428 ins_pipe(pipe_slow); // XXX
4429 %}
4430
4431 instruct loadD(regD dst, memory mem)
4432 %{
4433 predicate(UseXmmLoadAndClearUpper);
4434 match(Set dst (LoadD mem));
4435
4436 ins_cost(145); // XXX
4437 format %{ "movsd $dst, $mem\t# double" %}
4438 ins_encode %{
4439 __ movdbl($dst$$XMMRegister, $mem$$Address);
4440 %}
4441 ins_pipe(pipe_slow); // XXX
4442 %}
4443
4444 // max = java.lang.Math.max(float a, float b)
4445 instruct maxF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
4446 predicate(UseAVX > 0 && !VLoopReductions::is_reduction(n));
4447 match(Set dst (MaxF a b));
4448 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
4449 format %{ "maxF $dst, $a, $b \t! using $tmp, $atmp and $btmp as TEMP" %}
4450 ins_encode %{
4451 __ vminmax_fp(Op_MaxV, T_FLOAT, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
4452 %}
4453 ins_pipe( pipe_slow );
4454 %}
4455
4456 instruct maxF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xtmp, rRegI rtmp, rFlagsReg cr) %{
4457 predicate(UseAVX > 0 && VLoopReductions::is_reduction(n));
4458 match(Set dst (MaxF a b));
4459 effect(USE a, USE b, TEMP xtmp, TEMP rtmp, KILL cr);
4460
4461 format %{ "maxF_reduction $dst, $a, $b \t!using $xtmp and $rtmp as TEMP" %}
4462 ins_encode %{
4463 emit_fp_min_max(masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xtmp$$XMMRegister, $rtmp$$Register,
4464 false /*min*/, true /*single*/);
4465 %}
4466 ins_pipe( pipe_slow );
4467 %}
4468
4469 // max = java.lang.Math.max(double a, double b)
4470 instruct maxD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
4471 predicate(UseAVX > 0 && !VLoopReductions::is_reduction(n));
4472 match(Set dst (MaxD a b));
4473 effect(USE a, USE b, TEMP atmp, TEMP btmp, TEMP tmp);
4474 format %{ "maxD $dst, $a, $b \t! using $tmp, $atmp and $btmp as TEMP" %}
4475 ins_encode %{
4476 __ vminmax_fp(Op_MaxV, T_DOUBLE, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
4477 %}
4478 ins_pipe( pipe_slow );
4479 %}
4480
4481 instruct maxD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xtmp, rRegL rtmp, rFlagsReg cr) %{
4482 predicate(UseAVX > 0 && VLoopReductions::is_reduction(n));
4483 match(Set dst (MaxD a b));
4484 effect(USE a, USE b, TEMP xtmp, TEMP rtmp, KILL cr);
4485
4486 format %{ "maxD_reduction $dst, $a, $b \t! using $xtmp and $rtmp as TEMP" %}
4487 ins_encode %{
4488 emit_fp_min_max(masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xtmp$$XMMRegister, $rtmp$$Register,
4489 false /*min*/, false /*single*/);
4490 %}
4491 ins_pipe( pipe_slow );
4492 %}
4493
4494 // min = java.lang.Math.min(float a, float b)
4495 instruct minF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
4496 predicate(UseAVX > 0 && !VLoopReductions::is_reduction(n));
4497 match(Set dst (MinF a b));
4498 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
4499 format %{ "minF $dst, $a, $b \t! using $tmp, $atmp and $btmp as TEMP" %}
4500 ins_encode %{
4501 __ vminmax_fp(Op_MinV, T_FLOAT, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
4502 %}
4503 ins_pipe( pipe_slow );
4504 %}
4505
4506 instruct minF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xtmp, rRegI rtmp, rFlagsReg cr) %{
4507 predicate(UseAVX > 0 && VLoopReductions::is_reduction(n));
4508 match(Set dst (MinF a b));
4509 effect(USE a, USE b, TEMP xtmp, TEMP rtmp, KILL cr);
4510
4511 format %{ "minF_reduction $dst, $a, $b \t! using $xtmp and $rtmp as TEMP" %}
4512 ins_encode %{
4513 emit_fp_min_max(masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xtmp$$XMMRegister, $rtmp$$Register,
4514 true /*min*/, true /*single*/);
4515 %}
4516 ins_pipe( pipe_slow );
4517 %}
4518
4519 // min = java.lang.Math.min(double a, double b)
4520 instruct minD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
4521 predicate(UseAVX > 0 && !VLoopReductions::is_reduction(n));
4522 match(Set dst (MinD a b));
4523 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
4524 format %{ "minD $dst, $a, $b \t! using $tmp, $atmp and $btmp as TEMP" %}
4525 ins_encode %{
4526 __ vminmax_fp(Op_MinV, T_DOUBLE, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
4527 %}
4528 ins_pipe( pipe_slow );
4529 %}
4530
4531 instruct minD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xtmp, rRegL rtmp, rFlagsReg cr) %{
4532 predicate(UseAVX > 0 && VLoopReductions::is_reduction(n));
4533 match(Set dst (MinD a b));
4534 effect(USE a, USE b, TEMP xtmp, TEMP rtmp, KILL cr);
4535
4536 format %{ "maxD_reduction $dst, $a, $b \t! using $xtmp and $rtmp as TEMP" %}
4537 ins_encode %{
4538 emit_fp_min_max(masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xtmp$$XMMRegister, $rtmp$$Register,
4539 true /*min*/, false /*single*/);
4540 %}
4541 ins_pipe( pipe_slow );
4542 %}
4543
4544 // Load Effective Address
4545 instruct leaP8(rRegP dst, indOffset8 mem)
4546 %{
4547 match(Set dst mem);
4548
4549 ins_cost(110); // XXX
4550 format %{ "leaq $dst, $mem\t# ptr 8" %}
4551 ins_encode %{
4552 __ leaq($dst$$Register, $mem$$Address);
4553 %}
4554 ins_pipe(ialu_reg_reg_fat);
4555 %}
4556
4557 instruct leaP32(rRegP dst, indOffset32 mem)
4558 %{
4559 match(Set dst mem);
4560
4561 ins_cost(110);
4562 format %{ "leaq $dst, $mem\t# ptr 32" %}
4563 ins_encode %{
4564 __ leaq($dst$$Register, $mem$$Address);
4565 %}
4566 ins_pipe(ialu_reg_reg_fat);
4567 %}
4568
4569 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
4570 %{
4571 match(Set dst mem);
4572
4573 ins_cost(110);
4574 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
4575 ins_encode %{
4576 __ leaq($dst$$Register, $mem$$Address);
4577 %}
4578 ins_pipe(ialu_reg_reg_fat);
4579 %}
4580
4581 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
4582 %{
4583 match(Set dst mem);
4584
4585 ins_cost(110);
4586 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
4587 ins_encode %{
4588 __ leaq($dst$$Register, $mem$$Address);
4589 %}
4590 ins_pipe(ialu_reg_reg_fat);
4591 %}
4592
4593 instruct leaPPosIdxScale(rRegP dst, indPosIndexScale mem)
4594 %{
4595 match(Set dst mem);
4596
4597 ins_cost(110);
4598 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
4599 ins_encode %{
4600 __ leaq($dst$$Register, $mem$$Address);
4601 %}
4602 ins_pipe(ialu_reg_reg_fat);
4603 %}
4604
4605 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
4606 %{
4607 match(Set dst mem);
4608
4609 ins_cost(110);
4610 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
4611 ins_encode %{
4612 __ leaq($dst$$Register, $mem$$Address);
4613 %}
4614 ins_pipe(ialu_reg_reg_fat);
4615 %}
4616
4617 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
4618 %{
4619 match(Set dst mem);
4620
4621 ins_cost(110);
4622 format %{ "leaq $dst, $mem\t# ptr posidxoff" %}
4623 ins_encode %{
4624 __ leaq($dst$$Register, $mem$$Address);
4625 %}
4626 ins_pipe(ialu_reg_reg_fat);
4627 %}
4628
4629 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
4630 %{
4631 match(Set dst mem);
4632
4633 ins_cost(110);
4634 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
4635 ins_encode %{
4636 __ leaq($dst$$Register, $mem$$Address);
4637 %}
4638 ins_pipe(ialu_reg_reg_fat);
4639 %}
4640
4641 // Load Effective Address which uses Narrow (32-bits) oop
4642 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
4643 %{
4644 predicate(UseCompressedOops && (CompressedOops::shift() != 0));
4645 match(Set dst mem);
4646
4647 ins_cost(110);
4648 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
4649 ins_encode %{
4650 __ leaq($dst$$Register, $mem$$Address);
4651 %}
4652 ins_pipe(ialu_reg_reg_fat);
4653 %}
4654
4655 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
4656 %{
4657 predicate(CompressedOops::shift() == 0);
4658 match(Set dst mem);
4659
4660 ins_cost(110); // XXX
4661 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
4662 ins_encode %{
4663 __ leaq($dst$$Register, $mem$$Address);
4664 %}
4665 ins_pipe(ialu_reg_reg_fat);
4666 %}
4667
4668 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
4669 %{
4670 predicate(CompressedOops::shift() == 0);
4671 match(Set dst mem);
4672
4673 ins_cost(110);
4674 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
4675 ins_encode %{
4676 __ leaq($dst$$Register, $mem$$Address);
4677 %}
4678 ins_pipe(ialu_reg_reg_fat);
4679 %}
4680
4681 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
4682 %{
4683 predicate(CompressedOops::shift() == 0);
4684 match(Set dst mem);
4685
4686 ins_cost(110);
4687 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
4688 ins_encode %{
4689 __ leaq($dst$$Register, $mem$$Address);
4690 %}
4691 ins_pipe(ialu_reg_reg_fat);
4692 %}
4693
4694 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
4695 %{
4696 predicate(CompressedOops::shift() == 0);
4697 match(Set dst mem);
4698
4699 ins_cost(110);
4700 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
4701 ins_encode %{
4702 __ leaq($dst$$Register, $mem$$Address);
4703 %}
4704 ins_pipe(ialu_reg_reg_fat);
4705 %}
4706
4707 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
4708 %{
4709 predicate(CompressedOops::shift() == 0);
4710 match(Set dst mem);
4711
4712 ins_cost(110);
4713 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
4714 ins_encode %{
4715 __ leaq($dst$$Register, $mem$$Address);
4716 %}
4717 ins_pipe(ialu_reg_reg_fat);
4718 %}
4719
4720 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
4721 %{
4722 predicate(CompressedOops::shift() == 0);
4723 match(Set dst mem);
4724
4725 ins_cost(110);
4726 format %{ "leaq $dst, $mem\t# ptr posidxoffnarrow" %}
4727 ins_encode %{
4728 __ leaq($dst$$Register, $mem$$Address);
4729 %}
4730 ins_pipe(ialu_reg_reg_fat);
4731 %}
4732
4733 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
4734 %{
4735 predicate(CompressedOops::shift() == 0);
4736 match(Set dst mem);
4737
4738 ins_cost(110);
4739 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
4740 ins_encode %{
4741 __ leaq($dst$$Register, $mem$$Address);
4742 %}
4743 ins_pipe(ialu_reg_reg_fat);
4744 %}
4745
4746 instruct loadConI(rRegI dst, immI src)
4747 %{
4748 match(Set dst src);
4749
4750 format %{ "movl $dst, $src\t# int" %}
4751 ins_encode %{
4752 __ movl($dst$$Register, $src$$constant);
4753 %}
4754 ins_pipe(ialu_reg_fat); // XXX
4755 %}
4756
4757 instruct loadConI0(rRegI dst, immI_0 src, rFlagsReg cr)
4758 %{
4759 match(Set dst src);
4760 effect(KILL cr);
4761
4762 ins_cost(50);
4763 format %{ "xorl $dst, $dst\t# int" %}
4764 ins_encode %{
4765 __ xorl($dst$$Register, $dst$$Register);
4766 %}
4767 ins_pipe(ialu_reg);
4768 %}
4769
4770 instruct loadConL(rRegL dst, immL src)
4771 %{
4772 match(Set dst src);
4773
4774 ins_cost(150);
4775 format %{ "movq $dst, $src\t# long" %}
4776 ins_encode %{
4777 __ mov64($dst$$Register, $src$$constant);
4778 %}
4779 ins_pipe(ialu_reg);
4780 %}
4781
4782 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
4783 %{
4784 match(Set dst src);
4785 effect(KILL cr);
4786
4787 ins_cost(50);
4788 format %{ "xorl $dst, $dst\t# long" %}
4789 ins_encode %{
4790 __ xorl($dst$$Register, $dst$$Register);
4791 %}
4792 ins_pipe(ialu_reg); // XXX
4793 %}
4794
4795 instruct loadConUL32(rRegL dst, immUL32 src)
4796 %{
4797 match(Set dst src);
4798
4799 ins_cost(60);
4800 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
4801 ins_encode %{
4802 __ movl($dst$$Register, $src$$constant);
4803 %}
4804 ins_pipe(ialu_reg);
4805 %}
4806
4807 instruct loadConL32(rRegL dst, immL32 src)
4808 %{
4809 match(Set dst src);
4810
4811 ins_cost(70);
4812 format %{ "movq $dst, $src\t# long (32-bit)" %}
4813 ins_encode %{
4814 __ movq($dst$$Register, $src$$constant);
4815 %}
4816 ins_pipe(ialu_reg);
4817 %}
4818
4819 instruct loadConP(rRegP dst, immP con) %{
4820 match(Set dst con);
4821
4822 format %{ "movq $dst, $con\t# ptr" %}
4823 ins_encode %{
4824 __ mov64($dst$$Register, $con$$constant, $con->constant_reloc(), RELOC_IMM64);
4825 %}
4826 ins_pipe(ialu_reg_fat); // XXX
4827 %}
4828
4829 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
4830 %{
4831 match(Set dst src);
4832 effect(KILL cr);
4833
4834 ins_cost(50);
4835 format %{ "xorl $dst, $dst\t# ptr" %}
4836 ins_encode %{
4837 __ xorl($dst$$Register, $dst$$Register);
4838 %}
4839 ins_pipe(ialu_reg);
4840 %}
4841
4842 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
4843 %{
4844 match(Set dst src);
4845 effect(KILL cr);
4846
4847 ins_cost(60);
4848 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
4849 ins_encode %{
4850 __ movl($dst$$Register, $src$$constant);
4851 %}
4852 ins_pipe(ialu_reg);
4853 %}
4854
4855 instruct loadConF(regF dst, immF con) %{
4856 match(Set dst con);
4857 ins_cost(125);
4858 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
4859 ins_encode %{
4860 __ movflt($dst$$XMMRegister, $constantaddress($con));
4861 %}
4862 ins_pipe(pipe_slow);
4863 %}
4864
4865 instruct loadConH(regF dst, immH con) %{
4866 match(Set dst con);
4867 ins_cost(125);
4868 format %{ "movss $dst, [$constantaddress]\t# load from constant table: halffloat=$con" %}
4869 ins_encode %{
4870 __ movflt($dst$$XMMRegister, $constantaddress($con));
4871 %}
4872 ins_pipe(pipe_slow);
4873 %}
4874
4875 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
4876 match(Set dst src);
4877 effect(KILL cr);
4878 format %{ "xorq $dst, $src\t# compressed null pointer" %}
4879 ins_encode %{
4880 __ xorq($dst$$Register, $dst$$Register);
4881 %}
4882 ins_pipe(ialu_reg);
4883 %}
4884
4885 instruct loadConN(rRegN dst, immN src) %{
4886 match(Set dst src);
4887
4888 ins_cost(125);
4889 format %{ "movl $dst, $src\t# compressed ptr" %}
4890 ins_encode %{
4891 address con = (address)$src$$constant;
4892 if (con == nullptr) {
4893 ShouldNotReachHere();
4894 } else {
4895 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
4896 }
4897 %}
4898 ins_pipe(ialu_reg_fat); // XXX
4899 %}
4900
4901 instruct loadConNKlass(rRegN dst, immNKlass src) %{
4902 match(Set dst src);
4903
4904 ins_cost(125);
4905 format %{ "movl $dst, $src\t# compressed klass ptr" %}
4906 ins_encode %{
4907 address con = (address)$src$$constant;
4908 if (con == nullptr) {
4909 ShouldNotReachHere();
4910 } else {
4911 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
4912 }
4913 %}
4914 ins_pipe(ialu_reg_fat); // XXX
4915 %}
4916
4917 instruct loadConF0(regF dst, immF0 src)
4918 %{
4919 match(Set dst src);
4920 ins_cost(100);
4921
4922 format %{ "xorps $dst, $dst\t# float 0.0" %}
4923 ins_encode %{
4924 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
4925 %}
4926 ins_pipe(pipe_slow);
4927 %}
4928
4929 // Use the same format since predicate() can not be used here.
4930 instruct loadConD(regD dst, immD con) %{
4931 match(Set dst con);
4932 ins_cost(125);
4933 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
4934 ins_encode %{
4935 __ movdbl($dst$$XMMRegister, $constantaddress($con));
4936 %}
4937 ins_pipe(pipe_slow);
4938 %}
4939
4940 instruct loadConD0(regD dst, immD0 src)
4941 %{
4942 match(Set dst src);
4943 ins_cost(100);
4944
4945 format %{ "xorpd $dst, $dst\t# double 0.0" %}
4946 ins_encode %{
4947 __ xorpd($dst$$XMMRegister, $dst$$XMMRegister);
4948 %}
4949 ins_pipe(pipe_slow);
4950 %}
4951
4952 instruct loadSSI(rRegI dst, stackSlotI src)
4953 %{
4954 match(Set dst src);
4955
4956 ins_cost(125);
4957 format %{ "movl $dst, $src\t# int stk" %}
4958 ins_encode %{
4959 __ movl($dst$$Register, $src$$Address);
4960 %}
4961 ins_pipe(ialu_reg_mem);
4962 %}
4963
4964 instruct loadSSL(rRegL dst, stackSlotL src)
4965 %{
4966 match(Set dst src);
4967
4968 ins_cost(125);
4969 format %{ "movq $dst, $src\t# long stk" %}
4970 ins_encode %{
4971 __ movq($dst$$Register, $src$$Address);
4972 %}
4973 ins_pipe(ialu_reg_mem);
4974 %}
4975
4976 instruct loadSSP(rRegP dst, stackSlotP src)
4977 %{
4978 match(Set dst src);
4979
4980 ins_cost(125);
4981 format %{ "movq $dst, $src\t# ptr stk" %}
4982 ins_encode %{
4983 __ movq($dst$$Register, $src$$Address);
4984 %}
4985 ins_pipe(ialu_reg_mem);
4986 %}
4987
4988 instruct loadSSF(regF dst, stackSlotF src)
4989 %{
4990 match(Set dst src);
4991
4992 ins_cost(125);
4993 format %{ "movss $dst, $src\t# float stk" %}
4994 ins_encode %{
4995 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
4996 %}
4997 ins_pipe(pipe_slow); // XXX
4998 %}
4999
5000 // Use the same format since predicate() can not be used here.
5001 instruct loadSSD(regD dst, stackSlotD src)
5002 %{
5003 match(Set dst src);
5004
5005 ins_cost(125);
5006 format %{ "movsd $dst, $src\t# double stk" %}
5007 ins_encode %{
5008 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
5009 %}
5010 ins_pipe(pipe_slow); // XXX
5011 %}
5012
5013 // Prefetch instructions for allocation.
5014 // Must be safe to execute with invalid address (cannot fault).
5015
5016 instruct prefetchAlloc( memory mem ) %{
5017 predicate(AllocatePrefetchInstr==3);
5018 match(PrefetchAllocation mem);
5019 ins_cost(125);
5020
5021 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
5022 ins_encode %{
5023 __ prefetchw($mem$$Address);
5024 %}
5025 ins_pipe(ialu_mem);
5026 %}
5027
5028 instruct prefetchAllocNTA( memory mem ) %{
5029 predicate(AllocatePrefetchInstr==0);
5030 match(PrefetchAllocation mem);
5031 ins_cost(125);
5032
5033 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
5034 ins_encode %{
5035 __ prefetchnta($mem$$Address);
5036 %}
5037 ins_pipe(ialu_mem);
5038 %}
5039
5040 instruct prefetchAllocT0( memory mem ) %{
5041 predicate(AllocatePrefetchInstr==1);
5042 match(PrefetchAllocation mem);
5043 ins_cost(125);
5044
5045 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
5046 ins_encode %{
5047 __ prefetcht0($mem$$Address);
5048 %}
5049 ins_pipe(ialu_mem);
5050 %}
5051
5052 instruct prefetchAllocT2( memory mem ) %{
5053 predicate(AllocatePrefetchInstr==2);
5054 match(PrefetchAllocation mem);
5055 ins_cost(125);
5056
5057 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
5058 ins_encode %{
5059 __ prefetcht2($mem$$Address);
5060 %}
5061 ins_pipe(ialu_mem);
5062 %}
5063
5064 //----------Store Instructions-------------------------------------------------
5065
5066 // Store Byte
5067 instruct storeB(memory mem, rRegI src)
5068 %{
5069 match(Set mem (StoreB mem src));
5070
5071 ins_cost(125); // XXX
5072 format %{ "movb $mem, $src\t# byte" %}
5073 ins_encode %{
5074 __ movb($mem$$Address, $src$$Register);
5075 %}
5076 ins_pipe(ialu_mem_reg);
5077 %}
5078
5079 // Store Char/Short
5080 instruct storeC(memory mem, rRegI src)
5081 %{
5082 match(Set mem (StoreC mem src));
5083
5084 ins_cost(125); // XXX
5085 format %{ "movw $mem, $src\t# char/short" %}
5086 ins_encode %{
5087 __ movw($mem$$Address, $src$$Register);
5088 %}
5089 ins_pipe(ialu_mem_reg);
5090 %}
5091
5092 // Store Integer
5093 instruct storeI(memory mem, rRegI src)
5094 %{
5095 match(Set mem (StoreI mem src));
5096
5097 ins_cost(125); // XXX
5098 format %{ "movl $mem, $src\t# int" %}
5099 ins_encode %{
5100 __ movl($mem$$Address, $src$$Register);
5101 %}
5102 ins_pipe(ialu_mem_reg);
5103 %}
5104
5105 // Store Long
5106 instruct storeL(memory mem, rRegL src)
5107 %{
5108 match(Set mem (StoreL mem src));
5109
5110 ins_cost(125); // XXX
5111 format %{ "movq $mem, $src\t# long" %}
5112 ins_encode %{
5113 __ movq($mem$$Address, $src$$Register);
5114 %}
5115 ins_pipe(ialu_mem_reg); // XXX
5116 %}
5117
5118 // Store Pointer
5119 instruct storeP(memory mem, any_RegP src)
5120 %{
5121 predicate(n->as_Store()->barrier_data() == 0);
5122 match(Set mem (StoreP mem src));
5123
5124 ins_cost(125); // XXX
5125 format %{ "movq $mem, $src\t# ptr" %}
5126 ins_encode %{
5127 __ movq($mem$$Address, $src$$Register);
5128 %}
5129 ins_pipe(ialu_mem_reg);
5130 %}
5131
5132 instruct storeImmP0(memory mem, immP0 zero)
5133 %{
5134 predicate(UseCompressedOops && (CompressedOops::base() == nullptr) && n->as_Store()->barrier_data() == 0);
5135 match(Set mem (StoreP mem zero));
5136
5137 ins_cost(125); // XXX
5138 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
5139 ins_encode %{
5140 __ movq($mem$$Address, r12);
5141 %}
5142 ins_pipe(ialu_mem_reg);
5143 %}
5144
5145 // Store Null Pointer, mark word, or other simple pointer constant.
5146 instruct storeImmP(memory mem, immP31 src)
5147 %{
5148 predicate(n->as_Store()->barrier_data() == 0);
5149 match(Set mem (StoreP mem src));
5150
5151 ins_cost(150); // XXX
5152 format %{ "movq $mem, $src\t# ptr" %}
5153 ins_encode %{
5154 __ movq($mem$$Address, $src$$constant);
5155 %}
5156 ins_pipe(ialu_mem_imm);
5157 %}
5158
5159 // Store Compressed Pointer
5160 instruct storeN(memory mem, rRegN src)
5161 %{
5162 predicate(n->as_Store()->barrier_data() == 0);
5163 match(Set mem (StoreN mem src));
5164
5165 ins_cost(125); // XXX
5166 format %{ "movl $mem, $src\t# compressed ptr" %}
5167 ins_encode %{
5168 __ movl($mem$$Address, $src$$Register);
5169 %}
5170 ins_pipe(ialu_mem_reg);
5171 %}
5172
5173 instruct storeNKlass(memory mem, rRegN src)
5174 %{
5175 match(Set mem (StoreNKlass mem src));
5176
5177 ins_cost(125); // XXX
5178 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5179 ins_encode %{
5180 __ movl($mem$$Address, $src$$Register);
5181 %}
5182 ins_pipe(ialu_mem_reg);
5183 %}
5184
5185 instruct storeImmN0(memory mem, immN0 zero)
5186 %{
5187 predicate(CompressedOops::base() == nullptr && n->as_Store()->barrier_data() == 0);
5188 match(Set mem (StoreN mem zero));
5189
5190 ins_cost(125); // XXX
5191 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
5192 ins_encode %{
5193 __ movl($mem$$Address, r12);
5194 %}
5195 ins_pipe(ialu_mem_reg);
5196 %}
5197
5198 instruct storeImmN(memory mem, immN src)
5199 %{
5200 predicate(n->as_Store()->barrier_data() == 0);
5201 match(Set mem (StoreN mem src));
5202
5203 ins_cost(150); // XXX
5204 format %{ "movl $mem, $src\t# compressed ptr" %}
5205 ins_encode %{
5206 address con = (address)$src$$constant;
5207 if (con == nullptr) {
5208 __ movl($mem$$Address, 0);
5209 } else {
5210 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
5211 }
5212 %}
5213 ins_pipe(ialu_mem_imm);
5214 %}
5215
5216 instruct storeImmNKlass(memory mem, immNKlass src)
5217 %{
5218 match(Set mem (StoreNKlass mem src));
5219
5220 ins_cost(150); // XXX
5221 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5222 ins_encode %{
5223 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
5224 %}
5225 ins_pipe(ialu_mem_imm);
5226 %}
5227
5228 // Store Integer Immediate
5229 instruct storeImmI0(memory mem, immI_0 zero)
5230 %{
5231 predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
5232 match(Set mem (StoreI mem zero));
5233
5234 ins_cost(125); // XXX
5235 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
5236 ins_encode %{
5237 __ movl($mem$$Address, r12);
5238 %}
5239 ins_pipe(ialu_mem_reg);
5240 %}
5241
5242 instruct storeImmI(memory mem, immI src)
5243 %{
5244 match(Set mem (StoreI mem src));
5245
5246 ins_cost(150);
5247 format %{ "movl $mem, $src\t# int" %}
5248 ins_encode %{
5249 __ movl($mem$$Address, $src$$constant);
5250 %}
5251 ins_pipe(ialu_mem_imm);
5252 %}
5253
5254 // Store Long Immediate
5255 instruct storeImmL0(memory mem, immL0 zero)
5256 %{
5257 predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
5258 match(Set mem (StoreL mem zero));
5259
5260 ins_cost(125); // XXX
5261 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
5262 ins_encode %{
5263 __ movq($mem$$Address, r12);
5264 %}
5265 ins_pipe(ialu_mem_reg);
5266 %}
5267
5268 instruct storeImmL(memory mem, immL32 src)
5269 %{
5270 match(Set mem (StoreL mem src));
5271
5272 ins_cost(150);
5273 format %{ "movq $mem, $src\t# long" %}
5274 ins_encode %{
5275 __ movq($mem$$Address, $src$$constant);
5276 %}
5277 ins_pipe(ialu_mem_imm);
5278 %}
5279
5280 // Store Short/Char Immediate
5281 instruct storeImmC0(memory mem, immI_0 zero)
5282 %{
5283 predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
5284 match(Set mem (StoreC mem zero));
5285
5286 ins_cost(125); // XXX
5287 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
5288 ins_encode %{
5289 __ movw($mem$$Address, r12);
5290 %}
5291 ins_pipe(ialu_mem_reg);
5292 %}
5293
5294 instruct storeImmI16(memory mem, immI16 src)
5295 %{
5296 predicate(UseStoreImmI16);
5297 match(Set mem (StoreC mem src));
5298
5299 ins_cost(150);
5300 format %{ "movw $mem, $src\t# short/char" %}
5301 ins_encode %{
5302 __ movw($mem$$Address, $src$$constant);
5303 %}
5304 ins_pipe(ialu_mem_imm);
5305 %}
5306
5307 // Store Byte Immediate
5308 instruct storeImmB0(memory mem, immI_0 zero)
5309 %{
5310 predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
5311 match(Set mem (StoreB mem zero));
5312
5313 ins_cost(125); // XXX
5314 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
5315 ins_encode %{
5316 __ movb($mem$$Address, r12);
5317 %}
5318 ins_pipe(ialu_mem_reg);
5319 %}
5320
5321 instruct storeImmB(memory mem, immI8 src)
5322 %{
5323 match(Set mem (StoreB mem src));
5324
5325 ins_cost(150); // XXX
5326 format %{ "movb $mem, $src\t# byte" %}
5327 ins_encode %{
5328 __ movb($mem$$Address, $src$$constant);
5329 %}
5330 ins_pipe(ialu_mem_imm);
5331 %}
5332
5333 // Store Float
5334 instruct storeF(memory mem, regF src)
5335 %{
5336 match(Set mem (StoreF mem src));
5337
5338 ins_cost(95); // XXX
5339 format %{ "movss $mem, $src\t# float" %}
5340 ins_encode %{
5341 __ movflt($mem$$Address, $src$$XMMRegister);
5342 %}
5343 ins_pipe(pipe_slow); // XXX
5344 %}
5345
5346 // Store immediate Float value (it is faster than store from XMM register)
5347 instruct storeF0(memory mem, immF0 zero)
5348 %{
5349 predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
5350 match(Set mem (StoreF mem zero));
5351
5352 ins_cost(25); // XXX
5353 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
5354 ins_encode %{
5355 __ movl($mem$$Address, r12);
5356 %}
5357 ins_pipe(ialu_mem_reg);
5358 %}
5359
5360 instruct storeF_imm(memory mem, immF src)
5361 %{
5362 match(Set mem (StoreF mem src));
5363
5364 ins_cost(50);
5365 format %{ "movl $mem, $src\t# float" %}
5366 ins_encode %{
5367 __ movl($mem$$Address, jint_cast($src$$constant));
5368 %}
5369 ins_pipe(ialu_mem_imm);
5370 %}
5371
5372 // Store Double
5373 instruct storeD(memory mem, regD src)
5374 %{
5375 match(Set mem (StoreD mem src));
5376
5377 ins_cost(95); // XXX
5378 format %{ "movsd $mem, $src\t# double" %}
5379 ins_encode %{
5380 __ movdbl($mem$$Address, $src$$XMMRegister);
5381 %}
5382 ins_pipe(pipe_slow); // XXX
5383 %}
5384
5385 // Store immediate double 0.0 (it is faster than store from XMM register)
5386 instruct storeD0_imm(memory mem, immD0 src)
5387 %{
5388 predicate(!UseCompressedOops || (CompressedOops::base() != nullptr));
5389 match(Set mem (StoreD mem src));
5390
5391 ins_cost(50);
5392 format %{ "movq $mem, $src\t# double 0." %}
5393 ins_encode %{
5394 __ movq($mem$$Address, $src$$constant);
5395 %}
5396 ins_pipe(ialu_mem_imm);
5397 %}
5398
5399 instruct storeD0(memory mem, immD0 zero)
5400 %{
5401 predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
5402 match(Set mem (StoreD mem zero));
5403
5404 ins_cost(25); // XXX
5405 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
5406 ins_encode %{
5407 __ movq($mem$$Address, r12);
5408 %}
5409 ins_pipe(ialu_mem_reg);
5410 %}
5411
5412 instruct storeSSI(stackSlotI dst, rRegI src)
5413 %{
5414 match(Set dst src);
5415
5416 ins_cost(100);
5417 format %{ "movl $dst, $src\t# int stk" %}
5418 ins_encode %{
5419 __ movl($dst$$Address, $src$$Register);
5420 %}
5421 ins_pipe( ialu_mem_reg );
5422 %}
5423
5424 instruct storeSSL(stackSlotL dst, rRegL src)
5425 %{
5426 match(Set dst src);
5427
5428 ins_cost(100);
5429 format %{ "movq $dst, $src\t# long stk" %}
5430 ins_encode %{
5431 __ movq($dst$$Address, $src$$Register);
5432 %}
5433 ins_pipe(ialu_mem_reg);
5434 %}
5435
5436 instruct storeSSP(stackSlotP dst, rRegP src)
5437 %{
5438 match(Set dst src);
5439
5440 ins_cost(100);
5441 format %{ "movq $dst, $src\t# ptr stk" %}
5442 ins_encode %{
5443 __ movq($dst$$Address, $src$$Register);
5444 %}
5445 ins_pipe(ialu_mem_reg);
5446 %}
5447
5448 instruct storeSSF(stackSlotF dst, regF src)
5449 %{
5450 match(Set dst src);
5451
5452 ins_cost(95); // XXX
5453 format %{ "movss $dst, $src\t# float stk" %}
5454 ins_encode %{
5455 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
5456 %}
5457 ins_pipe(pipe_slow); // XXX
5458 %}
5459
5460 instruct storeSSD(stackSlotD dst, regD src)
5461 %{
5462 match(Set dst src);
5463
5464 ins_cost(95); // XXX
5465 format %{ "movsd $dst, $src\t# double stk" %}
5466 ins_encode %{
5467 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
5468 %}
5469 ins_pipe(pipe_slow); // XXX
5470 %}
5471
5472 instruct cacheWB(indirect addr)
5473 %{
5474 predicate(VM_Version::supports_data_cache_line_flush());
5475 match(CacheWB addr);
5476
5477 ins_cost(100);
5478 format %{"cache wb $addr" %}
5479 ins_encode %{
5480 assert($addr->index_position() < 0, "should be");
5481 assert($addr$$disp == 0, "should be");
5482 __ cache_wb(Address($addr$$base$$Register, 0));
5483 %}
5484 ins_pipe(pipe_slow); // XXX
5485 %}
5486
5487 instruct cacheWBPreSync()
5488 %{
5489 predicate(VM_Version::supports_data_cache_line_flush());
5490 match(CacheWBPreSync);
5491
5492 ins_cost(100);
5493 format %{"cache wb presync" %}
5494 ins_encode %{
5495 __ cache_wbsync(true);
5496 %}
5497 ins_pipe(pipe_slow); // XXX
5498 %}
5499
5500 instruct cacheWBPostSync()
5501 %{
5502 predicate(VM_Version::supports_data_cache_line_flush());
5503 match(CacheWBPostSync);
5504
5505 ins_cost(100);
5506 format %{"cache wb postsync" %}
5507 ins_encode %{
5508 __ cache_wbsync(false);
5509 %}
5510 ins_pipe(pipe_slow); // XXX
5511 %}
5512
5513 //----------BSWAP Instructions-------------------------------------------------
5514 instruct bytes_reverse_int(rRegI dst) %{
5515 match(Set dst (ReverseBytesI dst));
5516
5517 format %{ "bswapl $dst" %}
5518 ins_encode %{
5519 __ bswapl($dst$$Register);
5520 %}
5521 ins_pipe( ialu_reg );
5522 %}
5523
5524 instruct bytes_reverse_long(rRegL dst) %{
5525 match(Set dst (ReverseBytesL dst));
5526
5527 format %{ "bswapq $dst" %}
5528 ins_encode %{
5529 __ bswapq($dst$$Register);
5530 %}
5531 ins_pipe( ialu_reg);
5532 %}
5533
5534 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
5535 match(Set dst (ReverseBytesUS dst));
5536 effect(KILL cr);
5537
5538 format %{ "bswapl $dst\n\t"
5539 "shrl $dst,16\n\t" %}
5540 ins_encode %{
5541 __ bswapl($dst$$Register);
5542 __ shrl($dst$$Register, 16);
5543 %}
5544 ins_pipe( ialu_reg );
5545 %}
5546
5547 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
5548 match(Set dst (ReverseBytesS dst));
5549 effect(KILL cr);
5550
5551 format %{ "bswapl $dst\n\t"
5552 "sar $dst,16\n\t" %}
5553 ins_encode %{
5554 __ bswapl($dst$$Register);
5555 __ sarl($dst$$Register, 16);
5556 %}
5557 ins_pipe( ialu_reg );
5558 %}
5559
5560 //---------- Zeros Count Instructions ------------------------------------------
5561
5562 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
5563 predicate(UseCountLeadingZerosInstruction);
5564 match(Set dst (CountLeadingZerosI src));
5565 effect(KILL cr);
5566
5567 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
5568 ins_encode %{
5569 __ lzcntl($dst$$Register, $src$$Register);
5570 %}
5571 ins_pipe(ialu_reg);
5572 %}
5573
5574 instruct countLeadingZerosI_mem(rRegI dst, memory src, rFlagsReg cr) %{
5575 predicate(UseCountLeadingZerosInstruction);
5576 match(Set dst (CountLeadingZerosI (LoadI src)));
5577 effect(KILL cr);
5578 ins_cost(175);
5579 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
5580 ins_encode %{
5581 __ lzcntl($dst$$Register, $src$$Address);
5582 %}
5583 ins_pipe(ialu_reg_mem);
5584 %}
5585
5586 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
5587 predicate(!UseCountLeadingZerosInstruction);
5588 match(Set dst (CountLeadingZerosI src));
5589 effect(KILL cr);
5590
5591 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
5592 "jnz skip\n\t"
5593 "movl $dst, -1\n"
5594 "skip:\n\t"
5595 "negl $dst\n\t"
5596 "addl $dst, 31" %}
5597 ins_encode %{
5598 Register Rdst = $dst$$Register;
5599 Register Rsrc = $src$$Register;
5600 Label skip;
5601 __ bsrl(Rdst, Rsrc);
5602 __ jccb(Assembler::notZero, skip);
5603 __ movl(Rdst, -1);
5604 __ bind(skip);
5605 __ negl(Rdst);
5606 __ addl(Rdst, BitsPerInt - 1);
5607 %}
5608 ins_pipe(ialu_reg);
5609 %}
5610
5611 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
5612 predicate(UseCountLeadingZerosInstruction);
5613 match(Set dst (CountLeadingZerosL src));
5614 effect(KILL cr);
5615
5616 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
5617 ins_encode %{
5618 __ lzcntq($dst$$Register, $src$$Register);
5619 %}
5620 ins_pipe(ialu_reg);
5621 %}
5622
5623 instruct countLeadingZerosL_mem(rRegI dst, memory src, rFlagsReg cr) %{
5624 predicate(UseCountLeadingZerosInstruction);
5625 match(Set dst (CountLeadingZerosL (LoadL src)));
5626 effect(KILL cr);
5627 ins_cost(175);
5628 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
5629 ins_encode %{
5630 __ lzcntq($dst$$Register, $src$$Address);
5631 %}
5632 ins_pipe(ialu_reg_mem);
5633 %}
5634
5635 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
5636 predicate(!UseCountLeadingZerosInstruction);
5637 match(Set dst (CountLeadingZerosL src));
5638 effect(KILL cr);
5639
5640 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
5641 "jnz skip\n\t"
5642 "movl $dst, -1\n"
5643 "skip:\n\t"
5644 "negl $dst\n\t"
5645 "addl $dst, 63" %}
5646 ins_encode %{
5647 Register Rdst = $dst$$Register;
5648 Register Rsrc = $src$$Register;
5649 Label skip;
5650 __ bsrq(Rdst, Rsrc);
5651 __ jccb(Assembler::notZero, skip);
5652 __ movl(Rdst, -1);
5653 __ bind(skip);
5654 __ negl(Rdst);
5655 __ addl(Rdst, BitsPerLong - 1);
5656 %}
5657 ins_pipe(ialu_reg);
5658 %}
5659
5660 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
5661 predicate(UseCountTrailingZerosInstruction);
5662 match(Set dst (CountTrailingZerosI src));
5663 effect(KILL cr);
5664
5665 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
5666 ins_encode %{
5667 __ tzcntl($dst$$Register, $src$$Register);
5668 %}
5669 ins_pipe(ialu_reg);
5670 %}
5671
5672 instruct countTrailingZerosI_mem(rRegI dst, memory src, rFlagsReg cr) %{
5673 predicate(UseCountTrailingZerosInstruction);
5674 match(Set dst (CountTrailingZerosI (LoadI src)));
5675 effect(KILL cr);
5676 ins_cost(175);
5677 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
5678 ins_encode %{
5679 __ tzcntl($dst$$Register, $src$$Address);
5680 %}
5681 ins_pipe(ialu_reg_mem);
5682 %}
5683
5684 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
5685 predicate(!UseCountTrailingZerosInstruction);
5686 match(Set dst (CountTrailingZerosI src));
5687 effect(KILL cr);
5688
5689 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
5690 "jnz done\n\t"
5691 "movl $dst, 32\n"
5692 "done:" %}
5693 ins_encode %{
5694 Register Rdst = $dst$$Register;
5695 Label done;
5696 __ bsfl(Rdst, $src$$Register);
5697 __ jccb(Assembler::notZero, done);
5698 __ movl(Rdst, BitsPerInt);
5699 __ bind(done);
5700 %}
5701 ins_pipe(ialu_reg);
5702 %}
5703
5704 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
5705 predicate(UseCountTrailingZerosInstruction);
5706 match(Set dst (CountTrailingZerosL src));
5707 effect(KILL cr);
5708
5709 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
5710 ins_encode %{
5711 __ tzcntq($dst$$Register, $src$$Register);
5712 %}
5713 ins_pipe(ialu_reg);
5714 %}
5715
5716 instruct countTrailingZerosL_mem(rRegI dst, memory src, rFlagsReg cr) %{
5717 predicate(UseCountTrailingZerosInstruction);
5718 match(Set dst (CountTrailingZerosL (LoadL src)));
5719 effect(KILL cr);
5720 ins_cost(175);
5721 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
5722 ins_encode %{
5723 __ tzcntq($dst$$Register, $src$$Address);
5724 %}
5725 ins_pipe(ialu_reg_mem);
5726 %}
5727
5728 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
5729 predicate(!UseCountTrailingZerosInstruction);
5730 match(Set dst (CountTrailingZerosL src));
5731 effect(KILL cr);
5732
5733 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
5734 "jnz done\n\t"
5735 "movl $dst, 64\n"
5736 "done:" %}
5737 ins_encode %{
5738 Register Rdst = $dst$$Register;
5739 Label done;
5740 __ bsfq(Rdst, $src$$Register);
5741 __ jccb(Assembler::notZero, done);
5742 __ movl(Rdst, BitsPerLong);
5743 __ bind(done);
5744 %}
5745 ins_pipe(ialu_reg);
5746 %}
5747
5748 //--------------- Reverse Operation Instructions ----------------
5749 instruct bytes_reversebit_int(rRegI dst, rRegI src, rRegI rtmp, rFlagsReg cr) %{
5750 predicate(!VM_Version::supports_gfni());
5751 match(Set dst (ReverseI src));
5752 effect(TEMP dst, TEMP rtmp, KILL cr);
5753 format %{ "reverse_int $dst $src\t! using $rtmp as TEMP" %}
5754 ins_encode %{
5755 __ reverseI($dst$$Register, $src$$Register, xnoreg, xnoreg, $rtmp$$Register);
5756 %}
5757 ins_pipe( ialu_reg );
5758 %}
5759
5760 instruct bytes_reversebit_int_gfni(rRegI dst, rRegI src, vlRegF xtmp1, vlRegF xtmp2, rRegL rtmp, rFlagsReg cr) %{
5761 predicate(VM_Version::supports_gfni());
5762 match(Set dst (ReverseI src));
5763 effect(TEMP dst, TEMP xtmp1, TEMP xtmp2, TEMP rtmp, KILL cr);
5764 format %{ "reverse_int $dst $src\t! using $rtmp, $xtmp1 and $xtmp2 as TEMP" %}
5765 ins_encode %{
5766 __ reverseI($dst$$Register, $src$$Register, $xtmp1$$XMMRegister, $xtmp2$$XMMRegister, $rtmp$$Register);
5767 %}
5768 ins_pipe( ialu_reg );
5769 %}
5770
5771 instruct bytes_reversebit_long(rRegL dst, rRegL src, rRegL rtmp1, rRegL rtmp2, rFlagsReg cr) %{
5772 predicate(!VM_Version::supports_gfni());
5773 match(Set dst (ReverseL src));
5774 effect(TEMP dst, TEMP rtmp1, TEMP rtmp2, KILL cr);
5775 format %{ "reverse_long $dst $src\t! using $rtmp1 and $rtmp2 as TEMP" %}
5776 ins_encode %{
5777 __ reverseL($dst$$Register, $src$$Register, xnoreg, xnoreg, $rtmp1$$Register, $rtmp2$$Register);
5778 %}
5779 ins_pipe( ialu_reg );
5780 %}
5781
5782 instruct bytes_reversebit_long_gfni(rRegL dst, rRegL src, vlRegD xtmp1, vlRegD xtmp2, rRegL rtmp, rFlagsReg cr) %{
5783 predicate(VM_Version::supports_gfni());
5784 match(Set dst (ReverseL src));
5785 effect(TEMP dst, TEMP xtmp1, TEMP xtmp2, TEMP rtmp, KILL cr);
5786 format %{ "reverse_long $dst $src\t! using $rtmp, $xtmp1 and $xtmp2 as TEMP" %}
5787 ins_encode %{
5788 __ reverseL($dst$$Register, $src$$Register, $xtmp1$$XMMRegister, $xtmp2$$XMMRegister, $rtmp$$Register, noreg);
5789 %}
5790 ins_pipe( ialu_reg );
5791 %}
5792
5793 //---------- Population Count Instructions -------------------------------------
5794
5795 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
5796 predicate(UsePopCountInstruction);
5797 match(Set dst (PopCountI src));
5798 effect(KILL cr);
5799
5800 format %{ "popcnt $dst, $src" %}
5801 ins_encode %{
5802 __ popcntl($dst$$Register, $src$$Register);
5803 %}
5804 ins_pipe(ialu_reg);
5805 %}
5806
5807 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
5808 predicate(UsePopCountInstruction);
5809 match(Set dst (PopCountI (LoadI mem)));
5810 effect(KILL cr);
5811
5812 format %{ "popcnt $dst, $mem" %}
5813 ins_encode %{
5814 __ popcntl($dst$$Register, $mem$$Address);
5815 %}
5816 ins_pipe(ialu_reg);
5817 %}
5818
5819 // Note: Long.bitCount(long) returns an int.
5820 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
5821 predicate(UsePopCountInstruction);
5822 match(Set dst (PopCountL src));
5823 effect(KILL cr);
5824
5825 format %{ "popcnt $dst, $src" %}
5826 ins_encode %{
5827 __ popcntq($dst$$Register, $src$$Register);
5828 %}
5829 ins_pipe(ialu_reg);
5830 %}
5831
5832 // Note: Long.bitCount(long) returns an int.
5833 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
5834 predicate(UsePopCountInstruction);
5835 match(Set dst (PopCountL (LoadL mem)));
5836 effect(KILL cr);
5837
5838 format %{ "popcnt $dst, $mem" %}
5839 ins_encode %{
5840 __ popcntq($dst$$Register, $mem$$Address);
5841 %}
5842 ins_pipe(ialu_reg);
5843 %}
5844
5845
5846 //----------MemBar Instructions-----------------------------------------------
5847 // Memory barrier flavors
5848
5849 instruct membar_acquire()
5850 %{
5851 match(MemBarAcquire);
5852 match(LoadFence);
5853 ins_cost(0);
5854
5855 size(0);
5856 format %{ "MEMBAR-acquire ! (empty encoding)" %}
5857 ins_encode();
5858 ins_pipe(empty);
5859 %}
5860
5861 instruct membar_acquire_lock()
5862 %{
5863 match(MemBarAcquireLock);
5864 ins_cost(0);
5865
5866 size(0);
5867 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
5868 ins_encode();
5869 ins_pipe(empty);
5870 %}
5871
5872 instruct membar_release()
5873 %{
5874 match(MemBarRelease);
5875 match(StoreFence);
5876 ins_cost(0);
5877
5878 size(0);
5879 format %{ "MEMBAR-release ! (empty encoding)" %}
5880 ins_encode();
5881 ins_pipe(empty);
5882 %}
5883
5884 instruct membar_release_lock()
5885 %{
5886 match(MemBarReleaseLock);
5887 ins_cost(0);
5888
5889 size(0);
5890 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
5891 ins_encode();
5892 ins_pipe(empty);
5893 %}
5894
5895 instruct membar_volatile(rFlagsReg cr) %{
5896 match(MemBarVolatile);
5897 effect(KILL cr);
5898 ins_cost(400);
5899
5900 format %{
5901 $$template
5902 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
5903 %}
5904 ins_encode %{
5905 __ membar(Assembler::StoreLoad);
5906 %}
5907 ins_pipe(pipe_slow);
5908 %}
5909
5910 instruct unnecessary_membar_volatile()
5911 %{
5912 match(MemBarVolatile);
5913 predicate(Matcher::post_store_load_barrier(n));
5914 ins_cost(0);
5915
5916 size(0);
5917 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
5918 ins_encode();
5919 ins_pipe(empty);
5920 %}
5921
5922 instruct membar_storestore() %{
5923 match(MemBarStoreStore);
5924 match(StoreStoreFence);
5925 ins_cost(0);
5926
5927 size(0);
5928 format %{ "MEMBAR-storestore (empty encoding)" %}
5929 ins_encode( );
5930 ins_pipe(empty);
5931 %}
5932
5933 //----------Move Instructions--------------------------------------------------
5934
5935 instruct castX2P(rRegP dst, rRegL src)
5936 %{
5937 match(Set dst (CastX2P src));
5938
5939 format %{ "movq $dst, $src\t# long->ptr" %}
5940 ins_encode %{
5941 if ($dst$$reg != $src$$reg) {
5942 __ movptr($dst$$Register, $src$$Register);
5943 }
5944 %}
5945 ins_pipe(ialu_reg_reg); // XXX
5946 %}
5947
5948 instruct castP2X(rRegL dst, rRegP src)
5949 %{
5950 match(Set dst (CastP2X src));
5951
5952 format %{ "movq $dst, $src\t# ptr -> long" %}
5953 ins_encode %{
5954 if ($dst$$reg != $src$$reg) {
5955 __ movptr($dst$$Register, $src$$Register);
5956 }
5957 %}
5958 ins_pipe(ialu_reg_reg); // XXX
5959 %}
5960
5961 // Convert oop into int for vectors alignment masking
5962 instruct convP2I(rRegI dst, rRegP src)
5963 %{
5964 match(Set dst (ConvL2I (CastP2X src)));
5965
5966 format %{ "movl $dst, $src\t# ptr -> int" %}
5967 ins_encode %{
5968 __ movl($dst$$Register, $src$$Register);
5969 %}
5970 ins_pipe(ialu_reg_reg); // XXX
5971 %}
5972
5973 // Convert compressed oop into int for vectors alignment masking
5974 // in case of 32bit oops (heap < 4Gb).
5975 instruct convN2I(rRegI dst, rRegN src)
5976 %{
5977 predicate(CompressedOops::shift() == 0);
5978 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
5979
5980 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
5981 ins_encode %{
5982 __ movl($dst$$Register, $src$$Register);
5983 %}
5984 ins_pipe(ialu_reg_reg); // XXX
5985 %}
5986
5987 // Convert oop pointer into compressed form
5988 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
5989 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
5990 match(Set dst (EncodeP src));
5991 effect(KILL cr);
5992 format %{ "encode_heap_oop $dst,$src" %}
5993 ins_encode %{
5994 Register s = $src$$Register;
5995 Register d = $dst$$Register;
5996 if (s != d) {
5997 __ movq(d, s);
5998 }
5999 __ encode_heap_oop(d);
6000 %}
6001 ins_pipe(ialu_reg_long);
6002 %}
6003
6004 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6005 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6006 match(Set dst (EncodeP src));
6007 effect(KILL cr);
6008 format %{ "encode_heap_oop_not_null $dst,$src" %}
6009 ins_encode %{
6010 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6011 %}
6012 ins_pipe(ialu_reg_long);
6013 %}
6014
6015 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6016 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
6017 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
6018 match(Set dst (DecodeN src));
6019 effect(KILL cr);
6020 format %{ "decode_heap_oop $dst,$src" %}
6021 ins_encode %{
6022 Register s = $src$$Register;
6023 Register d = $dst$$Register;
6024 if (s != d) {
6025 __ movq(d, s);
6026 }
6027 __ decode_heap_oop(d);
6028 %}
6029 ins_pipe(ialu_reg_long);
6030 %}
6031
6032 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6033 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
6034 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
6035 match(Set dst (DecodeN src));
6036 effect(KILL cr);
6037 format %{ "decode_heap_oop_not_null $dst,$src" %}
6038 ins_encode %{
6039 Register s = $src$$Register;
6040 Register d = $dst$$Register;
6041 if (s != d) {
6042 __ decode_heap_oop_not_null(d, s);
6043 } else {
6044 __ decode_heap_oop_not_null(d);
6045 }
6046 %}
6047 ins_pipe(ialu_reg_long);
6048 %}
6049
6050 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6051 match(Set dst (EncodePKlass src));
6052 effect(TEMP dst, KILL cr);
6053 format %{ "encode_and_move_klass_not_null $dst,$src" %}
6054 ins_encode %{
6055 __ encode_and_move_klass_not_null($dst$$Register, $src$$Register);
6056 %}
6057 ins_pipe(ialu_reg_long);
6058 %}
6059
6060 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6061 match(Set dst (DecodeNKlass src));
6062 effect(TEMP dst, KILL cr);
6063 format %{ "decode_and_move_klass_not_null $dst,$src" %}
6064 ins_encode %{
6065 __ decode_and_move_klass_not_null($dst$$Register, $src$$Register);
6066 %}
6067 ins_pipe(ialu_reg_long);
6068 %}
6069
6070 //----------Conditional Move---------------------------------------------------
6071 // Jump
6072 // dummy instruction for generating temp registers
6073 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6074 match(Jump (LShiftL switch_val shift));
6075 ins_cost(350);
6076 predicate(false);
6077 effect(TEMP dest);
6078
6079 format %{ "leaq $dest, [$constantaddress]\n\t"
6080 "jmp [$dest + $switch_val << $shift]\n\t" %}
6081 ins_encode %{
6082 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6083 // to do that and the compiler is using that register as one it can allocate.
6084 // So we build it all by hand.
6085 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6086 // ArrayAddress dispatch(table, index);
6087 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6088 __ lea($dest$$Register, $constantaddress);
6089 __ jmp(dispatch);
6090 %}
6091 ins_pipe(pipe_jmp);
6092 %}
6093
6094 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6095 match(Jump (AddL (LShiftL switch_val shift) offset));
6096 ins_cost(350);
6097 effect(TEMP dest);
6098
6099 format %{ "leaq $dest, [$constantaddress]\n\t"
6100 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
6101 ins_encode %{
6102 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6103 // to do that and the compiler is using that register as one it can allocate.
6104 // So we build it all by hand.
6105 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6106 // ArrayAddress dispatch(table, index);
6107 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6108 __ lea($dest$$Register, $constantaddress);
6109 __ jmp(dispatch);
6110 %}
6111 ins_pipe(pipe_jmp);
6112 %}
6113
6114 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
6115 match(Jump switch_val);
6116 ins_cost(350);
6117 effect(TEMP dest);
6118
6119 format %{ "leaq $dest, [$constantaddress]\n\t"
6120 "jmp [$dest + $switch_val]\n\t" %}
6121 ins_encode %{
6122 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6123 // to do that and the compiler is using that register as one it can allocate.
6124 // So we build it all by hand.
6125 // Address index(noreg, switch_reg, Address::times_1);
6126 // ArrayAddress dispatch(table, index);
6127 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
6128 __ lea($dest$$Register, $constantaddress);
6129 __ jmp(dispatch);
6130 %}
6131 ins_pipe(pipe_jmp);
6132 %}
6133
6134 // Conditional move
6135 instruct cmovI_imm_01(rRegI dst, immI_1 src, rFlagsReg cr, cmpOp cop)
6136 %{
6137 predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_int() == 0);
6138 match(Set dst (CMoveI (Binary cop cr) (Binary src dst)));
6139
6140 ins_cost(100); // XXX
6141 format %{ "setbn$cop $dst\t# signed, int" %}
6142 ins_encode %{
6143 Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
6144 __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
6145 %}
6146 ins_pipe(ialu_reg);
6147 %}
6148
6149 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
6150 %{
6151 predicate(!UseAPX);
6152 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6153
6154 ins_cost(200); // XXX
6155 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6156 ins_encode %{
6157 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6158 %}
6159 ins_pipe(pipe_cmov_reg);
6160 %}
6161
6162 instruct cmovI_reg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr, cmpOp cop)
6163 %{
6164 predicate(UseAPX);
6165 match(Set dst (CMoveI (Binary cop cr) (Binary src1 src2)));
6166
6167 ins_cost(200);
6168 format %{ "ecmovl$cop $dst, $src1, $src2\t# signed, int ndd" %}
6169 ins_encode %{
6170 __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6171 %}
6172 ins_pipe(pipe_cmov_reg);
6173 %}
6174
6175 instruct cmovI_imm_01U(rRegI dst, immI_1 src, rFlagsRegU cr, cmpOpU cop)
6176 %{
6177 predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_int() == 0);
6178 match(Set dst (CMoveI (Binary cop cr) (Binary src dst)));
6179
6180 ins_cost(100); // XXX
6181 format %{ "setbn$cop $dst\t# unsigned, int" %}
6182 ins_encode %{
6183 Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
6184 __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
6185 %}
6186 ins_pipe(ialu_reg);
6187 %}
6188
6189 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
6190 predicate(!UseAPX);
6191 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6192
6193 ins_cost(200); // XXX
6194 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6195 ins_encode %{
6196 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6197 %}
6198 ins_pipe(pipe_cmov_reg);
6199 %}
6200
6201 instruct cmovI_regU_ndd(rRegI dst, cmpOpU cop, rFlagsRegU cr, rRegI src1, rRegI src2) %{
6202 predicate(UseAPX);
6203 match(Set dst (CMoveI (Binary cop cr) (Binary src1 src2)));
6204
6205 ins_cost(200);
6206 format %{ "ecmovl$cop $dst, $src1, $src2\t# unsigned, int ndd" %}
6207 ins_encode %{
6208 __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6209 %}
6210 ins_pipe(pipe_cmov_reg);
6211 %}
6212
6213 instruct cmovI_imm_01UCF(rRegI dst, immI_1 src, rFlagsRegUCF cr, cmpOpUCF cop)
6214 %{
6215 predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_int() == 0);
6216 match(Set dst (CMoveI (Binary cop cr) (Binary src dst)));
6217
6218 ins_cost(100); // XXX
6219 format %{ "setbn$cop $dst\t# unsigned, int" %}
6220 ins_encode %{
6221 Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
6222 __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
6223 %}
6224 ins_pipe(ialu_reg);
6225 %}
6226
6227 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6228 predicate(!UseAPX);
6229 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6230 ins_cost(200);
6231 expand %{
6232 cmovI_regU(cop, cr, dst, src);
6233 %}
6234 %}
6235
6236 instruct cmovI_regUCF_ndd(rRegI dst, cmpOpUCF cop, rFlagsRegUCF cr, rRegI src1, rRegI src2) %{
6237 predicate(UseAPX);
6238 match(Set dst (CMoveI (Binary cop cr) (Binary src1 src2)));
6239 ins_cost(200);
6240 format %{ "ecmovl$cop $dst, $src1, $src2\t# unsigned, int ndd" %}
6241 ins_encode %{
6242 __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6243 %}
6244 ins_pipe(pipe_cmov_reg);
6245 %}
6246
6247 instruct cmovI_regUCF2_ne(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6248 predicate(!UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
6249 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6250
6251 ins_cost(200); // XXX
6252 format %{ "cmovpl $dst, $src\n\t"
6253 "cmovnel $dst, $src" %}
6254 ins_encode %{
6255 __ cmovl(Assembler::parity, $dst$$Register, $src$$Register);
6256 __ cmovl(Assembler::notEqual, $dst$$Register, $src$$Register);
6257 %}
6258 ins_pipe(pipe_cmov_reg);
6259 %}
6260
6261 instruct cmovI_regUCF2_ne_ndd(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegI dst, rRegI src1, rRegI src2) %{
6262 predicate(UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
6263 match(Set dst (CMoveI (Binary cop cr) (Binary src1 src2)));
6264
6265 ins_cost(200);
6266 format %{ "ecmovpl $dst, $src1, $src2\n\t"
6267 "ecmovnel $dst, $src1, $src2" %}
6268 ins_encode %{
6269 __ ecmovl(Assembler::parity, $dst$$Register, $src1$$Register, $src2$$Register);
6270 __ ecmovl(Assembler::notEqual, $dst$$Register, $src1$$Register, $src2$$Register);
6271 %}
6272 ins_pipe(pipe_cmov_reg);
6273 %}
6274
6275 // Since (x == y) == !(x != y), we can flip the sense of the test by flipping the
6276 // inputs of the CMove
6277 instruct cmovI_regUCF2_eq(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6278 predicate(!UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
6279 match(Set dst (CMoveI (Binary cop cr) (Binary src dst)));
6280
6281 ins_cost(200); // XXX
6282 format %{ "cmovpl $dst, $src\n\t"
6283 "cmovnel $dst, $src" %}
6284 ins_encode %{
6285 __ cmovl(Assembler::parity, $dst$$Register, $src$$Register);
6286 __ cmovl(Assembler::notEqual, $dst$$Register, $src$$Register);
6287 %}
6288 ins_pipe(pipe_cmov_reg);
6289 %}
6290
6291 // We need this special handling for only eq / neq comparison since NaN == NaN is false,
6292 // and parity flag bit is set if any of the operand is a NaN.
6293 instruct cmovI_regUCF2_eq_ndd(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegI dst, rRegI src1, rRegI src2) %{
6294 predicate(UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
6295 match(Set dst (CMoveI (Binary cop cr) (Binary src1 src2)));
6296
6297 ins_cost(200);
6298 format %{ "ecmovpl $dst, $src1, $src2\n\t"
6299 "ecmovnel $dst, $src1, $src2" %}
6300 ins_encode %{
6301 __ ecmovl(Assembler::parity, $dst$$Register, $src1$$Register, $src2$$Register);
6302 __ ecmovl(Assembler::notEqual, $dst$$Register, $src1$$Register, $src2$$Register);
6303 %}
6304 ins_pipe(pipe_cmov_reg);
6305 %}
6306
6307 // Conditional move
6308 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
6309 predicate(!UseAPX);
6310 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6311
6312 ins_cost(250); // XXX
6313 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6314 ins_encode %{
6315 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
6316 %}
6317 ins_pipe(pipe_cmov_mem);
6318 %}
6319
6320 // Conditional move
6321 instruct cmovI_rReg_rReg_mem_ndd(rRegI dst, cmpOp cop, rFlagsReg cr, rRegI src1, memory src2)
6322 %{
6323 predicate(UseAPX);
6324 match(Set dst (CMoveI (Binary cop cr) (Binary src1 (LoadI src2))));
6325
6326 ins_cost(250);
6327 format %{ "ecmovl$cop $dst, $src1, $src2\t# signed, int ndd" %}
6328 ins_encode %{
6329 __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Address);
6330 %}
6331 ins_pipe(pipe_cmov_mem);
6332 %}
6333
6334 // Conditional move
6335 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
6336 %{
6337 predicate(!UseAPX);
6338 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6339
6340 ins_cost(250); // XXX
6341 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6342 ins_encode %{
6343 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
6344 %}
6345 ins_pipe(pipe_cmov_mem);
6346 %}
6347
6348 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
6349 predicate(!UseAPX);
6350 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6351 ins_cost(250);
6352 expand %{
6353 cmovI_memU(cop, cr, dst, src);
6354 %}
6355 %}
6356
6357 instruct cmovI_rReg_rReg_memU_ndd(rRegI dst, cmpOpU cop, rFlagsRegU cr, rRegI src1, memory src2)
6358 %{
6359 predicate(UseAPX);
6360 match(Set dst (CMoveI (Binary cop cr) (Binary src1 (LoadI src2))));
6361
6362 ins_cost(250);
6363 format %{ "ecmovl$cop $dst, $src1, $src2\t# unsigned, int ndd" %}
6364 ins_encode %{
6365 __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Address);
6366 %}
6367 ins_pipe(pipe_cmov_mem);
6368 %}
6369
6370 instruct cmovI_rReg_rReg_memUCF_ndd(rRegI dst, cmpOpUCF cop, rFlagsRegUCF cr, rRegI src1, memory src2)
6371 %{
6372 predicate(UseAPX);
6373 match(Set dst (CMoveI (Binary cop cr) (Binary src1 (LoadI src2))));
6374 ins_cost(250);
6375 format %{ "ecmovl$cop $dst, $src1, $src2\t# unsigned, int ndd" %}
6376 ins_encode %{
6377 __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Address);
6378 %}
6379 ins_pipe(pipe_cmov_mem);
6380 %}
6381
6382 // Conditional move
6383 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
6384 %{
6385 predicate(!UseAPX);
6386 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6387
6388 ins_cost(200); // XXX
6389 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
6390 ins_encode %{
6391 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6392 %}
6393 ins_pipe(pipe_cmov_reg);
6394 %}
6395
6396 // Conditional move ndd
6397 instruct cmovN_reg_ndd(rRegN dst, rRegN src1, rRegN src2, rFlagsReg cr, cmpOp cop)
6398 %{
6399 predicate(UseAPX);
6400 match(Set dst (CMoveN (Binary cop cr) (Binary src1 src2)));
6401
6402 ins_cost(200);
6403 format %{ "ecmovl$cop $dst, $src1, $src2\t# signed, compressed ptr ndd" %}
6404 ins_encode %{
6405 __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6406 %}
6407 ins_pipe(pipe_cmov_reg);
6408 %}
6409
6410 // Conditional move
6411 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
6412 %{
6413 predicate(!UseAPX);
6414 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6415
6416 ins_cost(200); // XXX
6417 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
6418 ins_encode %{
6419 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6420 %}
6421 ins_pipe(pipe_cmov_reg);
6422 %}
6423
6424 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6425 predicate(!UseAPX);
6426 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6427 ins_cost(200);
6428 expand %{
6429 cmovN_regU(cop, cr, dst, src);
6430 %}
6431 %}
6432
6433 // Conditional move ndd
6434 instruct cmovN_regU_ndd(rRegN dst, cmpOpU cop, rFlagsRegU cr, rRegN src1, rRegN src2)
6435 %{
6436 predicate(UseAPX);
6437 match(Set dst (CMoveN (Binary cop cr) (Binary src1 src2)));
6438
6439 ins_cost(200);
6440 format %{ "ecmovl$cop $dst, $src1, $src2\t# unsigned, compressed ptr ndd" %}
6441 ins_encode %{
6442 __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6443 %}
6444 ins_pipe(pipe_cmov_reg);
6445 %}
6446
6447 instruct cmovN_regUCF_ndd(rRegN dst, cmpOpUCF cop, rFlagsRegUCF cr, rRegN src1, rRegN src2) %{
6448 predicate(UseAPX);
6449 match(Set dst (CMoveN (Binary cop cr) (Binary src1 src2)));
6450 ins_cost(200);
6451 format %{ "ecmovl$cop $dst, $src1, $src2\t# unsigned, compressed ptr ndd" %}
6452 ins_encode %{
6453 __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6454 %}
6455 ins_pipe(pipe_cmov_reg);
6456 %}
6457
6458 instruct cmovN_regUCF2_ne(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6459 predicate(n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
6460 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6461
6462 ins_cost(200); // XXX
6463 format %{ "cmovpl $dst, $src\n\t"
6464 "cmovnel $dst, $src" %}
6465 ins_encode %{
6466 __ cmovl(Assembler::parity, $dst$$Register, $src$$Register);
6467 __ cmovl(Assembler::notEqual, $dst$$Register, $src$$Register);
6468 %}
6469 ins_pipe(pipe_cmov_reg);
6470 %}
6471
6472 // Since (x == y) == !(x != y), we can flip the sense of the test by flipping the
6473 // inputs of the CMove
6474 instruct cmovN_regUCF2_eq(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6475 predicate(n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
6476 match(Set dst (CMoveN (Binary cop cr) (Binary src dst)));
6477
6478 ins_cost(200); // XXX
6479 format %{ "cmovpl $dst, $src\n\t"
6480 "cmovnel $dst, $src" %}
6481 ins_encode %{
6482 __ cmovl(Assembler::parity, $dst$$Register, $src$$Register);
6483 __ cmovl(Assembler::notEqual, $dst$$Register, $src$$Register);
6484 %}
6485 ins_pipe(pipe_cmov_reg);
6486 %}
6487
6488 // Conditional move
6489 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
6490 %{
6491 predicate(!UseAPX);
6492 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6493
6494 ins_cost(200); // XXX
6495 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
6496 ins_encode %{
6497 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6498 %}
6499 ins_pipe(pipe_cmov_reg); // XXX
6500 %}
6501
6502 // Conditional move ndd
6503 instruct cmovP_reg_ndd(rRegP dst, rRegP src1, rRegP src2, rFlagsReg cr, cmpOp cop)
6504 %{
6505 predicate(UseAPX);
6506 match(Set dst (CMoveP (Binary cop cr) (Binary src1 src2)));
6507
6508 ins_cost(200);
6509 format %{ "ecmovq$cop $dst, $src1, $src2\t# signed, ptr ndd" %}
6510 ins_encode %{
6511 __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6512 %}
6513 ins_pipe(pipe_cmov_reg);
6514 %}
6515
6516 // Conditional move
6517 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
6518 %{
6519 predicate(!UseAPX);
6520 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6521
6522 ins_cost(200); // XXX
6523 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
6524 ins_encode %{
6525 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6526 %}
6527 ins_pipe(pipe_cmov_reg); // XXX
6528 %}
6529
6530 // Conditional move ndd
6531 instruct cmovP_regU_ndd(rRegP dst, cmpOpU cop, rFlagsRegU cr, rRegP src1, rRegP src2)
6532 %{
6533 predicate(UseAPX);
6534 match(Set dst (CMoveP (Binary cop cr) (Binary src1 src2)));
6535
6536 ins_cost(200);
6537 format %{ "ecmovq$cop $dst, $src1, $src2\t# unsigned, ptr ndd" %}
6538 ins_encode %{
6539 __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6540 %}
6541 ins_pipe(pipe_cmov_reg);
6542 %}
6543
6544 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6545 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6546 ins_cost(200);
6547 expand %{
6548 cmovP_regU(cop, cr, dst, src);
6549 %}
6550 %}
6551
6552 instruct cmovP_regUCF_ndd(rRegP dst, cmpOpUCF cop, rFlagsRegUCF cr, rRegP src1, rRegP src2) %{
6553 match(Set dst (CMoveP (Binary cop cr) (Binary src1 src2)));
6554 ins_cost(200);
6555 format %{ "ecmovq$cop $dst, $src1, $src2\t# unsigned, ptr ndd" %}
6556 ins_encode %{
6557 __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6558 %}
6559 ins_pipe(pipe_cmov_reg);
6560 %}
6561
6562 instruct cmovP_regUCF2_ne(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6563 predicate(!UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
6564 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6565
6566 ins_cost(200); // XXX
6567 format %{ "cmovpq $dst, $src\n\t"
6568 "cmovneq $dst, $src" %}
6569 ins_encode %{
6570 __ cmovq(Assembler::parity, $dst$$Register, $src$$Register);
6571 __ cmovq(Assembler::notEqual, $dst$$Register, $src$$Register);
6572 %}
6573 ins_pipe(pipe_cmov_reg);
6574 %}
6575
6576 instruct cmovP_regUCF2_ne_ndd(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegP dst, rRegP src1, rRegP src2) %{
6577 predicate(UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
6578 match(Set dst (CMoveP (Binary cop cr) (Binary src1 src2)));
6579
6580 ins_cost(200);
6581 format %{ "ecmovpq $dst, $src1, $src2\n\t"
6582 "ecmovneq $dst, $src1, $src2" %}
6583 ins_encode %{
6584 __ ecmovq(Assembler::parity, $dst$$Register, $src1$$Register, $src2$$Register);
6585 __ ecmovq(Assembler::notEqual, $dst$$Register, $src1$$Register, $src2$$Register);
6586 %}
6587 ins_pipe(pipe_cmov_reg);
6588 %}
6589
6590 // Since (x == y) == !(x != y), we can flip the sense of the test by flipping the
6591 // inputs of the CMove
6592 instruct cmovP_regUCF2_eq(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6593 predicate(!UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
6594 match(Set dst (CMoveP (Binary cop cr) (Binary src dst)));
6595
6596 ins_cost(200); // XXX
6597 format %{ "cmovpq $dst, $src\n\t"
6598 "cmovneq $dst, $src" %}
6599 ins_encode %{
6600 __ cmovq(Assembler::parity, $dst$$Register, $src$$Register);
6601 __ cmovq(Assembler::notEqual, $dst$$Register, $src$$Register);
6602 %}
6603 ins_pipe(pipe_cmov_reg);
6604 %}
6605
6606 instruct cmovP_regUCF2_eq_ndd(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegP dst, rRegP src1, rRegP src2) %{
6607 predicate(UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
6608 match(Set dst (CMoveP (Binary cop cr) (Binary src1 src2)));
6609
6610 ins_cost(200);
6611 format %{ "ecmovpq $dst, $src1, $src2\n\t"
6612 "ecmovneq $dst, $src1, $src2" %}
6613 ins_encode %{
6614 __ ecmovq(Assembler::parity, $dst$$Register, $src1$$Register, $src2$$Register);
6615 __ ecmovq(Assembler::notEqual, $dst$$Register, $src1$$Register, $src2$$Register);
6616 %}
6617 ins_pipe(pipe_cmov_reg);
6618 %}
6619
6620 instruct cmovL_imm_01(rRegL dst, immL1 src, rFlagsReg cr, cmpOp cop)
6621 %{
6622 predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_long() == 0);
6623 match(Set dst (CMoveL (Binary cop cr) (Binary src dst)));
6624
6625 ins_cost(100); // XXX
6626 format %{ "setbn$cop $dst\t# signed, long" %}
6627 ins_encode %{
6628 Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
6629 __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
6630 %}
6631 ins_pipe(ialu_reg);
6632 %}
6633
6634 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
6635 %{
6636 predicate(!UseAPX);
6637 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6638
6639 ins_cost(200); // XXX
6640 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6641 ins_encode %{
6642 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6643 %}
6644 ins_pipe(pipe_cmov_reg); // XXX
6645 %}
6646
6647 instruct cmovL_reg_ndd(rRegL dst, cmpOp cop, rFlagsReg cr, rRegL src1, rRegL src2)
6648 %{
6649 predicate(UseAPX);
6650 match(Set dst (CMoveL (Binary cop cr) (Binary src1 src2)));
6651
6652 ins_cost(200);
6653 format %{ "ecmovq$cop $dst, $src1, $src2\t# signed, long ndd" %}
6654 ins_encode %{
6655 __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6656 %}
6657 ins_pipe(pipe_cmov_reg);
6658 %}
6659
6660 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
6661 %{
6662 predicate(!UseAPX);
6663 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6664
6665 ins_cost(200); // XXX
6666 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6667 ins_encode %{
6668 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
6669 %}
6670 ins_pipe(pipe_cmov_mem); // XXX
6671 %}
6672
6673 instruct cmovL_rReg_rReg_mem_ndd(rRegL dst, cmpOp cop, rFlagsReg cr, rRegL src1, memory src2)
6674 %{
6675 predicate(UseAPX);
6676 match(Set dst (CMoveL (Binary cop cr) (Binary src1 (LoadL src2))));
6677
6678 ins_cost(200);
6679 format %{ "ecmovq$cop $dst, $src1, $src2\t# signed, long ndd" %}
6680 ins_encode %{
6681 __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Address);
6682 %}
6683 ins_pipe(pipe_cmov_mem);
6684 %}
6685
6686 instruct cmovL_imm_01U(rRegL dst, immL1 src, rFlagsRegU cr, cmpOpU cop)
6687 %{
6688 predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_long() == 0);
6689 match(Set dst (CMoveL (Binary cop cr) (Binary src dst)));
6690
6691 ins_cost(100); // XXX
6692 format %{ "setbn$cop $dst\t# unsigned, long" %}
6693 ins_encode %{
6694 Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
6695 __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
6696 %}
6697 ins_pipe(ialu_reg);
6698 %}
6699
6700 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
6701 %{
6702 predicate(!UseAPX);
6703 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6704
6705 ins_cost(200); // XXX
6706 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6707 ins_encode %{
6708 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6709 %}
6710 ins_pipe(pipe_cmov_reg); // XXX
6711 %}
6712
6713 instruct cmovL_regU_ndd(rRegL dst, cmpOpU cop, rFlagsRegU cr, rRegL src1, rRegL src2)
6714 %{
6715 predicate(UseAPX);
6716 match(Set dst (CMoveL (Binary cop cr) (Binary src1 src2)));
6717
6718 ins_cost(200);
6719 format %{ "ecmovq$cop $dst, $src1, $src2\t# unsigned, long ndd" %}
6720 ins_encode %{
6721 __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6722 %}
6723 ins_pipe(pipe_cmov_reg);
6724 %}
6725
6726 instruct cmovL_imm_01UCF(rRegL dst, immL1 src, rFlagsRegUCF cr, cmpOpUCF cop)
6727 %{
6728 predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_long() == 0);
6729 match(Set dst (CMoveL (Binary cop cr) (Binary src dst)));
6730
6731 ins_cost(100); // XXX
6732 format %{ "setbn$cop $dst\t# unsigned, long" %}
6733 ins_encode %{
6734 Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
6735 __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
6736 %}
6737 ins_pipe(ialu_reg);
6738 %}
6739
6740 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
6741 predicate(!UseAPX);
6742 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6743 ins_cost(200);
6744 expand %{
6745 cmovL_regU(cop, cr, dst, src);
6746 %}
6747 %}
6748
6749 instruct cmovL_regUCF_ndd(rRegL dst, cmpOpUCF cop, rFlagsRegUCF cr, rRegL src1, rRegL src2)
6750 %{
6751 predicate(UseAPX);
6752 match(Set dst (CMoveL (Binary cop cr) (Binary src1 src2)));
6753 ins_cost(200);
6754 format %{ "ecmovq$cop $dst, $src1, $src2\t# unsigned, long ndd" %}
6755 ins_encode %{
6756 __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
6757 %}
6758 ins_pipe(pipe_cmov_reg);
6759 %}
6760
6761 instruct cmovL_regUCF2_ne(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
6762 predicate(!UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
6763 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6764
6765 ins_cost(200); // XXX
6766 format %{ "cmovpq $dst, $src\n\t"
6767 "cmovneq $dst, $src" %}
6768 ins_encode %{
6769 __ cmovq(Assembler::parity, $dst$$Register, $src$$Register);
6770 __ cmovq(Assembler::notEqual, $dst$$Register, $src$$Register);
6771 %}
6772 ins_pipe(pipe_cmov_reg);
6773 %}
6774
6775 instruct cmovL_regUCF2_ne_ndd(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegL dst, rRegL src1, rRegL src2) %{
6776 predicate(UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
6777 match(Set dst (CMoveL (Binary cop cr) (Binary src1 src2)));
6778
6779 ins_cost(200);
6780 format %{ "ecmovpq $dst, $src1, $src2\n\t"
6781 "ecmovneq $dst, $src1, $src2" %}
6782 ins_encode %{
6783 __ ecmovq(Assembler::parity, $dst$$Register, $src1$$Register, $src2$$Register);
6784 __ ecmovq(Assembler::notEqual, $dst$$Register, $src1$$Register, $src2$$Register);
6785 %}
6786 ins_pipe(pipe_cmov_reg);
6787 %}
6788
6789 // Since (x == y) == !(x != y), we can flip the sense of the test by flipping the
6790 // inputs of the CMove
6791 instruct cmovL_regUCF2_eq(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
6792 predicate(!UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
6793 match(Set dst (CMoveL (Binary cop cr) (Binary src dst)));
6794
6795 ins_cost(200); // XXX
6796 format %{ "cmovpq $dst, $src\n\t"
6797 "cmovneq $dst, $src" %}
6798 ins_encode %{
6799 __ cmovq(Assembler::parity, $dst$$Register, $src$$Register);
6800 __ cmovq(Assembler::notEqual, $dst$$Register, $src$$Register);
6801 %}
6802 ins_pipe(pipe_cmov_reg);
6803 %}
6804
6805 instruct cmovL_regUCF2_eq_ndd(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegL dst, rRegL src1, rRegL src2) %{
6806 predicate(UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
6807 match(Set dst (CMoveL (Binary cop cr) (Binary src1 src2)));
6808
6809 ins_cost(200);
6810 format %{ "ecmovpq $dst, $src1, $src2\n\t"
6811 "ecmovneq $dst, $src1, $src2" %}
6812 ins_encode %{
6813 __ ecmovq(Assembler::parity, $dst$$Register, $src1$$Register, $src2$$Register);
6814 __ ecmovq(Assembler::notEqual, $dst$$Register, $src1$$Register, $src2$$Register);
6815 %}
6816 ins_pipe(pipe_cmov_reg);
6817 %}
6818
6819 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
6820 %{
6821 predicate(!UseAPX);
6822 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6823
6824 ins_cost(200); // XXX
6825 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6826 ins_encode %{
6827 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
6828 %}
6829 ins_pipe(pipe_cmov_mem); // XXX
6830 %}
6831
6832 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
6833 predicate(!UseAPX);
6834 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6835 ins_cost(200);
6836 expand %{
6837 cmovL_memU(cop, cr, dst, src);
6838 %}
6839 %}
6840
6841 instruct cmovL_rReg_rReg_memU_ndd(rRegL dst, cmpOpU cop, rFlagsRegU cr, rRegL src1, memory src2)
6842 %{
6843 predicate(UseAPX);
6844 match(Set dst (CMoveL (Binary cop cr) (Binary src1 (LoadL src2))));
6845
6846 ins_cost(200);
6847 format %{ "ecmovq$cop $dst, $src1, $src2\t# unsigned, long ndd" %}
6848 ins_encode %{
6849 __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Address);
6850 %}
6851 ins_pipe(pipe_cmov_mem);
6852 %}
6853
6854 instruct cmovL_rReg_rReg_memUCF_ndd(rRegL dst, cmpOpUCF cop, rFlagsRegUCF cr, rRegL src1, memory src2)
6855 %{
6856 predicate(UseAPX);
6857 match(Set dst (CMoveL (Binary cop cr) (Binary src1 (LoadL src2))));
6858 ins_cost(200);
6859 format %{ "ecmovq$cop $dst, $src1, $src2\t# unsigned, long ndd" %}
6860 ins_encode %{
6861 __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Address);
6862 %}
6863 ins_pipe(pipe_cmov_mem);
6864 %}
6865
6866 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
6867 %{
6868 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6869
6870 ins_cost(200); // XXX
6871 format %{ "jn$cop skip\t# signed cmove float\n\t"
6872 "movss $dst, $src\n"
6873 "skip:" %}
6874 ins_encode %{
6875 Label Lskip;
6876 // Invert sense of branch from sense of CMOV
6877 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6878 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6879 __ bind(Lskip);
6880 %}
6881 ins_pipe(pipe_slow);
6882 %}
6883
6884 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
6885 %{
6886 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6887
6888 ins_cost(200); // XXX
6889 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
6890 "movss $dst, $src\n"
6891 "skip:" %}
6892 ins_encode %{
6893 Label Lskip;
6894 // Invert sense of branch from sense of CMOV
6895 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6896 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6897 __ bind(Lskip);
6898 %}
6899 ins_pipe(pipe_slow);
6900 %}
6901
6902 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
6903 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6904 ins_cost(200);
6905 expand %{
6906 cmovF_regU(cop, cr, dst, src);
6907 %}
6908 %}
6909
6910 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
6911 %{
6912 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6913
6914 ins_cost(200); // XXX
6915 format %{ "jn$cop skip\t# signed cmove double\n\t"
6916 "movsd $dst, $src\n"
6917 "skip:" %}
6918 ins_encode %{
6919 Label Lskip;
6920 // Invert sense of branch from sense of CMOV
6921 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6922 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6923 __ bind(Lskip);
6924 %}
6925 ins_pipe(pipe_slow);
6926 %}
6927
6928 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
6929 %{
6930 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6931
6932 ins_cost(200); // XXX
6933 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
6934 "movsd $dst, $src\n"
6935 "skip:" %}
6936 ins_encode %{
6937 Label Lskip;
6938 // Invert sense of branch from sense of CMOV
6939 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6940 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6941 __ bind(Lskip);
6942 %}
6943 ins_pipe(pipe_slow);
6944 %}
6945
6946 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
6947 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6948 ins_cost(200);
6949 expand %{
6950 cmovD_regU(cop, cr, dst, src);
6951 %}
6952 %}
6953
6954 //----------Arithmetic Instructions--------------------------------------------
6955 //----------Addition Instructions----------------------------------------------
6956
6957 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
6958 %{
6959 predicate(!UseAPX);
6960 match(Set dst (AddI dst src));
6961 effect(KILL cr);
6962 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
6963 format %{ "addl $dst, $src\t# int" %}
6964 ins_encode %{
6965 __ addl($dst$$Register, $src$$Register);
6966 %}
6967 ins_pipe(ialu_reg_reg);
6968 %}
6969
6970 instruct addI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
6971 %{
6972 predicate(UseAPX);
6973 match(Set dst (AddI src1 src2));
6974 effect(KILL cr);
6975 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
6976
6977 format %{ "eaddl $dst, $src1, $src2\t# int ndd" %}
6978 ins_encode %{
6979 __ eaddl($dst$$Register, $src1$$Register, $src2$$Register, false);
6980 %}
6981 ins_pipe(ialu_reg_reg);
6982 %}
6983
6984 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
6985 %{
6986 predicate(!UseAPX);
6987 match(Set dst (AddI dst src));
6988 effect(KILL cr);
6989 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
6990
6991 format %{ "addl $dst, $src\t# int" %}
6992 ins_encode %{
6993 __ addl($dst$$Register, $src$$constant);
6994 %}
6995 ins_pipe( ialu_reg );
6996 %}
6997
6998 instruct addI_rReg_rReg_imm_ndd(rRegI dst, rRegI src1, immI src2, rFlagsReg cr)
6999 %{
7000 predicate(UseAPX);
7001 match(Set dst (AddI src1 src2));
7002 effect(KILL cr);
7003 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7004
7005 format %{ "eaddl $dst, $src1, $src2\t# int ndd" %}
7006 ins_encode %{
7007 __ eaddl($dst$$Register, $src1$$Register, $src2$$constant, false);
7008 %}
7009 ins_pipe( ialu_reg );
7010 %}
7011
7012 instruct addI_rReg_mem_imm_ndd(rRegI dst, memory src1, immI src2, rFlagsReg cr)
7013 %{
7014 predicate(UseAPX);
7015 match(Set dst (AddI (LoadI src1) src2));
7016 effect(KILL cr);
7017 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7018
7019 format %{ "eaddl $dst, $src1, $src2\t# int ndd" %}
7020 ins_encode %{
7021 __ eaddl($dst$$Register, $src1$$Address, $src2$$constant, false);
7022 %}
7023 ins_pipe( ialu_reg );
7024 %}
7025
7026 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7027 %{
7028 predicate(!UseAPX);
7029 match(Set dst (AddI dst (LoadI src)));
7030 effect(KILL cr);
7031 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7032
7033 ins_cost(150); // XXX
7034 format %{ "addl $dst, $src\t# int" %}
7035 ins_encode %{
7036 __ addl($dst$$Register, $src$$Address);
7037 %}
7038 ins_pipe(ialu_reg_mem);
7039 %}
7040
7041 instruct addI_rReg_mem_rReg_ndd(rRegI dst, memory src1, rRegI src2, rFlagsReg cr)
7042 %{
7043 predicate(UseAPX);
7044 match(Set dst (AddI (LoadI src1) src2));
7045 effect(KILL cr);
7046 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7047
7048 ins_cost(150);
7049 format %{ "eaddl $dst, $src1, $src2\t# int ndd" %}
7050 ins_encode %{
7051 __ eaddl($dst$$Register, $src1$$Address, $src2$$Register, false);
7052 %}
7053 ins_pipe(ialu_reg_mem);
7054 %}
7055
7056 instruct addI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr)
7057 %{
7058 predicate(UseAPX);
7059 match(Set dst (AddI src1 (LoadI src2)));
7060 effect(KILL cr);
7061 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7062
7063 ins_cost(150);
7064 format %{ "eaddl $dst, $src1, $src2\t# int ndd" %}
7065 ins_encode %{
7066 __ eaddl($dst$$Register, $src1$$Register, $src2$$Address, false);
7067 %}
7068 ins_pipe(ialu_reg_mem);
7069 %}
7070
7071 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7072 %{
7073 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7074 effect(KILL cr);
7075 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7076
7077 ins_cost(150); // XXX
7078 format %{ "addl $dst, $src\t# int" %}
7079 ins_encode %{
7080 __ addl($dst$$Address, $src$$Register);
7081 %}
7082 ins_pipe(ialu_mem_reg);
7083 %}
7084
7085 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
7086 %{
7087 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7088 effect(KILL cr);
7089 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7090
7091
7092 ins_cost(125); // XXX
7093 format %{ "addl $dst, $src\t# int" %}
7094 ins_encode %{
7095 __ addl($dst$$Address, $src$$constant);
7096 %}
7097 ins_pipe(ialu_mem_imm);
7098 %}
7099
7100 instruct incI_rReg(rRegI dst, immI_1 src, rFlagsReg cr)
7101 %{
7102 predicate(!UseAPX && UseIncDec);
7103 match(Set dst (AddI dst src));
7104 effect(KILL cr);
7105
7106 format %{ "incl $dst\t# int" %}
7107 ins_encode %{
7108 __ incrementl($dst$$Register);
7109 %}
7110 ins_pipe(ialu_reg);
7111 %}
7112
7113 instruct incI_rReg_ndd(rRegI dst, rRegI src, immI_1 val, rFlagsReg cr)
7114 %{
7115 predicate(UseAPX && UseIncDec);
7116 match(Set dst (AddI src val));
7117 effect(KILL cr);
7118
7119 format %{ "eincl $dst, $src\t# int ndd" %}
7120 ins_encode %{
7121 __ eincl($dst$$Register, $src$$Register, false);
7122 %}
7123 ins_pipe(ialu_reg);
7124 %}
7125
7126 instruct incI_rReg_mem_ndd(rRegI dst, memory src, immI_1 val, rFlagsReg cr)
7127 %{
7128 predicate(UseAPX && UseIncDec);
7129 match(Set dst (AddI (LoadI src) val));
7130 effect(KILL cr);
7131
7132 format %{ "eincl $dst, $src\t# int ndd" %}
7133 ins_encode %{
7134 __ eincl($dst$$Register, $src$$Address, false);
7135 %}
7136 ins_pipe(ialu_reg);
7137 %}
7138
7139 instruct incI_mem(memory dst, immI_1 src, rFlagsReg cr)
7140 %{
7141 predicate(UseIncDec);
7142 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7143 effect(KILL cr);
7144
7145 ins_cost(125); // XXX
7146 format %{ "incl $dst\t# int" %}
7147 ins_encode %{
7148 __ incrementl($dst$$Address);
7149 %}
7150 ins_pipe(ialu_mem_imm);
7151 %}
7152
7153 // XXX why does that use AddI
7154 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
7155 %{
7156 predicate(!UseAPX && UseIncDec);
7157 match(Set dst (AddI dst src));
7158 effect(KILL cr);
7159
7160 format %{ "decl $dst\t# int" %}
7161 ins_encode %{
7162 __ decrementl($dst$$Register);
7163 %}
7164 ins_pipe(ialu_reg);
7165 %}
7166
7167 instruct decI_rReg_ndd(rRegI dst, rRegI src, immI_M1 val, rFlagsReg cr)
7168 %{
7169 predicate(UseAPX && UseIncDec);
7170 match(Set dst (AddI src val));
7171 effect(KILL cr);
7172
7173 format %{ "edecl $dst, $src\t# int ndd" %}
7174 ins_encode %{
7175 __ edecl($dst$$Register, $src$$Register, false);
7176 %}
7177 ins_pipe(ialu_reg);
7178 %}
7179
7180 instruct decI_rReg_mem_ndd(rRegI dst, memory src, immI_M1 val, rFlagsReg cr)
7181 %{
7182 predicate(UseAPX && UseIncDec);
7183 match(Set dst (AddI (LoadI src) val));
7184 effect(KILL cr);
7185
7186 format %{ "edecl $dst, $src\t# int ndd" %}
7187 ins_encode %{
7188 __ edecl($dst$$Register, $src$$Address, false);
7189 %}
7190 ins_pipe(ialu_reg);
7191 %}
7192
7193 // XXX why does that use AddI
7194 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
7195 %{
7196 predicate(UseIncDec);
7197 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7198 effect(KILL cr);
7199
7200 ins_cost(125); // XXX
7201 format %{ "decl $dst\t# int" %}
7202 ins_encode %{
7203 __ decrementl($dst$$Address);
7204 %}
7205 ins_pipe(ialu_mem_imm);
7206 %}
7207
7208 instruct leaI_rReg_immI2_immI(rRegI dst, rRegI index, immI2 scale, immI disp)
7209 %{
7210 predicate(VM_Version::supports_fast_2op_lea());
7211 match(Set dst (AddI (LShiftI index scale) disp));
7212
7213 format %{ "leal $dst, [$index << $scale + $disp]\t# int" %}
7214 ins_encode %{
7215 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
7216 __ leal($dst$$Register, Address(noreg, $index$$Register, scale, $disp$$constant));
7217 %}
7218 ins_pipe(ialu_reg_reg);
7219 %}
7220
7221 instruct leaI_rReg_rReg_immI(rRegI dst, rRegI base, rRegI index, immI disp)
7222 %{
7223 predicate(VM_Version::supports_fast_3op_lea());
7224 match(Set dst (AddI (AddI base index) disp));
7225
7226 format %{ "leal $dst, [$base + $index + $disp]\t# int" %}
7227 ins_encode %{
7228 __ leal($dst$$Register, Address($base$$Register, $index$$Register, Address::times_1, $disp$$constant));
7229 %}
7230 ins_pipe(ialu_reg_reg);
7231 %}
7232
7233 instruct leaI_rReg_rReg_immI2(rRegI dst, no_rbp_r13_RegI base, rRegI index, immI2 scale)
7234 %{
7235 predicate(VM_Version::supports_fast_2op_lea());
7236 match(Set dst (AddI base (LShiftI index scale)));
7237
7238 format %{ "leal $dst, [$base + $index << $scale]\t# int" %}
7239 ins_encode %{
7240 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
7241 __ leal($dst$$Register, Address($base$$Register, $index$$Register, scale));
7242 %}
7243 ins_pipe(ialu_reg_reg);
7244 %}
7245
7246 instruct leaI_rReg_rReg_immI2_immI(rRegI dst, rRegI base, rRegI index, immI2 scale, immI disp)
7247 %{
7248 predicate(VM_Version::supports_fast_3op_lea());
7249 match(Set dst (AddI (AddI base (LShiftI index scale)) disp));
7250
7251 format %{ "leal $dst, [$base + $index << $scale + $disp]\t# int" %}
7252 ins_encode %{
7253 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
7254 __ leal($dst$$Register, Address($base$$Register, $index$$Register, scale, $disp$$constant));
7255 %}
7256 ins_pipe(ialu_reg_reg);
7257 %}
7258
7259 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7260 %{
7261 predicate(!UseAPX);
7262 match(Set dst (AddL dst src));
7263 effect(KILL cr);
7264 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7265
7266 format %{ "addq $dst, $src\t# long" %}
7267 ins_encode %{
7268 __ addq($dst$$Register, $src$$Register);
7269 %}
7270 ins_pipe(ialu_reg_reg);
7271 %}
7272
7273 instruct addL_rReg_ndd(rRegL dst, rRegL src1, rRegL src2, rFlagsReg cr)
7274 %{
7275 predicate(UseAPX);
7276 match(Set dst (AddL src1 src2));
7277 effect(KILL cr);
7278 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7279
7280 format %{ "eaddq $dst, $src1, $src2\t# long ndd" %}
7281 ins_encode %{
7282 __ eaddq($dst$$Register, $src1$$Register, $src2$$Register, false);
7283 %}
7284 ins_pipe(ialu_reg_reg);
7285 %}
7286
7287 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7288 %{
7289 predicate(!UseAPX);
7290 match(Set dst (AddL dst src));
7291 effect(KILL cr);
7292 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7293
7294 format %{ "addq $dst, $src\t# long" %}
7295 ins_encode %{
7296 __ addq($dst$$Register, $src$$constant);
7297 %}
7298 ins_pipe( ialu_reg );
7299 %}
7300
7301 instruct addL_rReg_rReg_imm_ndd(rRegL dst, rRegL src1, immL32 src2, rFlagsReg cr)
7302 %{
7303 predicate(UseAPX);
7304 match(Set dst (AddL src1 src2));
7305 effect(KILL cr);
7306 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7307
7308 format %{ "eaddq $dst, $src1, $src2\t# long ndd" %}
7309 ins_encode %{
7310 __ eaddq($dst$$Register, $src1$$Register, $src2$$constant, false);
7311 %}
7312 ins_pipe( ialu_reg );
7313 %}
7314
7315 instruct addL_rReg_mem_imm_ndd(rRegL dst, memory src1, immL32 src2, rFlagsReg cr)
7316 %{
7317 predicate(UseAPX);
7318 match(Set dst (AddL (LoadL src1) src2));
7319 effect(KILL cr);
7320 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7321
7322 format %{ "eaddq $dst, $src1, $src2\t# long ndd" %}
7323 ins_encode %{
7324 __ eaddq($dst$$Register, $src1$$Address, $src2$$constant, false);
7325 %}
7326 ins_pipe( ialu_reg );
7327 %}
7328
7329 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7330 %{
7331 predicate(!UseAPX);
7332 match(Set dst (AddL dst (LoadL src)));
7333 effect(KILL cr);
7334 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7335
7336 ins_cost(150); // XXX
7337 format %{ "addq $dst, $src\t# long" %}
7338 ins_encode %{
7339 __ addq($dst$$Register, $src$$Address);
7340 %}
7341 ins_pipe(ialu_reg_mem);
7342 %}
7343
7344 instruct addL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr)
7345 %{
7346 predicate(UseAPX);
7347 match(Set dst (AddL src1 (LoadL src2)));
7348 effect(KILL cr);
7349 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7350
7351 ins_cost(150);
7352 format %{ "eaddq $dst, $src1, $src2\t# long ndd" %}
7353 ins_encode %{
7354 __ eaddq($dst$$Register, $src1$$Register, $src2$$Address, false);
7355 %}
7356 ins_pipe(ialu_reg_mem);
7357 %}
7358
7359 instruct addL_rReg_mem_rReg_ndd(rRegL dst, memory src1, rRegL src2, rFlagsReg cr)
7360 %{
7361 predicate(UseAPX);
7362 match(Set dst (AddL (LoadL src1) src2));
7363 effect(KILL cr);
7364 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7365
7366 ins_cost(150);
7367 format %{ "eaddq $dst, $src1, $src2\t# long ndd" %}
7368 ins_encode %{
7369 __ eaddq($dst$$Register, $src1$$Address, $src2$$Register, false);
7370 %}
7371 ins_pipe(ialu_reg_mem);
7372 %}
7373
7374 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7375 %{
7376 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7377 effect(KILL cr);
7378 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7379
7380 ins_cost(150); // XXX
7381 format %{ "addq $dst, $src\t# long" %}
7382 ins_encode %{
7383 __ addq($dst$$Address, $src$$Register);
7384 %}
7385 ins_pipe(ialu_mem_reg);
7386 %}
7387
7388 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7389 %{
7390 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7391 effect(KILL cr);
7392 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7393
7394 ins_cost(125); // XXX
7395 format %{ "addq $dst, $src\t# long" %}
7396 ins_encode %{
7397 __ addq($dst$$Address, $src$$constant);
7398 %}
7399 ins_pipe(ialu_mem_imm);
7400 %}
7401
7402 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7403 %{
7404 predicate(!UseAPX && UseIncDec);
7405 match(Set dst (AddL dst src));
7406 effect(KILL cr);
7407
7408 format %{ "incq $dst\t# long" %}
7409 ins_encode %{
7410 __ incrementq($dst$$Register);
7411 %}
7412 ins_pipe(ialu_reg);
7413 %}
7414
7415 instruct incL_rReg_ndd(rRegI dst, rRegI src, immL1 val, rFlagsReg cr)
7416 %{
7417 predicate(UseAPX && UseIncDec);
7418 match(Set dst (AddL src val));
7419 effect(KILL cr);
7420
7421 format %{ "eincq $dst, $src\t# long ndd" %}
7422 ins_encode %{
7423 __ eincq($dst$$Register, $src$$Register, false);
7424 %}
7425 ins_pipe(ialu_reg);
7426 %}
7427
7428 instruct incL_rReg_mem_ndd(rRegI dst, memory src, immL1 val, rFlagsReg cr)
7429 %{
7430 predicate(UseAPX && UseIncDec);
7431 match(Set dst (AddL (LoadL src) val));
7432 effect(KILL cr);
7433
7434 format %{ "eincq $dst, $src\t# long ndd" %}
7435 ins_encode %{
7436 __ eincq($dst$$Register, $src$$Address, false);
7437 %}
7438 ins_pipe(ialu_reg);
7439 %}
7440
7441 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7442 %{
7443 predicate(UseIncDec);
7444 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7445 effect(KILL cr);
7446
7447 ins_cost(125); // XXX
7448 format %{ "incq $dst\t# long" %}
7449 ins_encode %{
7450 __ incrementq($dst$$Address);
7451 %}
7452 ins_pipe(ialu_mem_imm);
7453 %}
7454
7455 // XXX why does that use AddL
7456 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7457 %{
7458 predicate(!UseAPX && UseIncDec);
7459 match(Set dst (AddL dst src));
7460 effect(KILL cr);
7461
7462 format %{ "decq $dst\t# long" %}
7463 ins_encode %{
7464 __ decrementq($dst$$Register);
7465 %}
7466 ins_pipe(ialu_reg);
7467 %}
7468
7469 instruct decL_rReg_ndd(rRegL dst, rRegL src, immL_M1 val, rFlagsReg cr)
7470 %{
7471 predicate(UseAPX && UseIncDec);
7472 match(Set dst (AddL src val));
7473 effect(KILL cr);
7474
7475 format %{ "edecq $dst, $src\t# long ndd" %}
7476 ins_encode %{
7477 __ edecq($dst$$Register, $src$$Register, false);
7478 %}
7479 ins_pipe(ialu_reg);
7480 %}
7481
7482 instruct decL_rReg_mem_ndd(rRegL dst, memory src, immL_M1 val, rFlagsReg cr)
7483 %{
7484 predicate(UseAPX && UseIncDec);
7485 match(Set dst (AddL (LoadL src) val));
7486 effect(KILL cr);
7487
7488 format %{ "edecq $dst, $src\t# long ndd" %}
7489 ins_encode %{
7490 __ edecq($dst$$Register, $src$$Address, false);
7491 %}
7492 ins_pipe(ialu_reg);
7493 %}
7494
7495 // XXX why does that use AddL
7496 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7497 %{
7498 predicate(UseIncDec);
7499 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7500 effect(KILL cr);
7501
7502 ins_cost(125); // XXX
7503 format %{ "decq $dst\t# long" %}
7504 ins_encode %{
7505 __ decrementq($dst$$Address);
7506 %}
7507 ins_pipe(ialu_mem_imm);
7508 %}
7509
7510 instruct leaL_rReg_immI2_immL32(rRegL dst, rRegL index, immI2 scale, immL32 disp)
7511 %{
7512 predicate(VM_Version::supports_fast_2op_lea());
7513 match(Set dst (AddL (LShiftL index scale) disp));
7514
7515 format %{ "leaq $dst, [$index << $scale + $disp]\t# long" %}
7516 ins_encode %{
7517 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
7518 __ leaq($dst$$Register, Address(noreg, $index$$Register, scale, $disp$$constant));
7519 %}
7520 ins_pipe(ialu_reg_reg);
7521 %}
7522
7523 instruct leaL_rReg_rReg_immL32(rRegL dst, rRegL base, rRegL index, immL32 disp)
7524 %{
7525 predicate(VM_Version::supports_fast_3op_lea());
7526 match(Set dst (AddL (AddL base index) disp));
7527
7528 format %{ "leaq $dst, [$base + $index + $disp]\t# long" %}
7529 ins_encode %{
7530 __ leaq($dst$$Register, Address($base$$Register, $index$$Register, Address::times_1, $disp$$constant));
7531 %}
7532 ins_pipe(ialu_reg_reg);
7533 %}
7534
7535 instruct leaL_rReg_rReg_immI2(rRegL dst, no_rbp_r13_RegL base, rRegL index, immI2 scale)
7536 %{
7537 predicate(VM_Version::supports_fast_2op_lea());
7538 match(Set dst (AddL base (LShiftL index scale)));
7539
7540 format %{ "leaq $dst, [$base + $index << $scale]\t# long" %}
7541 ins_encode %{
7542 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
7543 __ leaq($dst$$Register, Address($base$$Register, $index$$Register, scale));
7544 %}
7545 ins_pipe(ialu_reg_reg);
7546 %}
7547
7548 instruct leaL_rReg_rReg_immI2_immL32(rRegL dst, rRegL base, rRegL index, immI2 scale, immL32 disp)
7549 %{
7550 predicate(VM_Version::supports_fast_3op_lea());
7551 match(Set dst (AddL (AddL base (LShiftL index scale)) disp));
7552
7553 format %{ "leaq $dst, [$base + $index << $scale + $disp]\t# long" %}
7554 ins_encode %{
7555 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
7556 __ leaq($dst$$Register, Address($base$$Register, $index$$Register, scale, $disp$$constant));
7557 %}
7558 ins_pipe(ialu_reg_reg);
7559 %}
7560
7561 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7562 %{
7563 match(Set dst (AddP dst src));
7564 effect(KILL cr);
7565 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7566
7567 format %{ "addq $dst, $src\t# ptr" %}
7568 ins_encode %{
7569 __ addq($dst$$Register, $src$$Register);
7570 %}
7571 ins_pipe(ialu_reg_reg);
7572 %}
7573
7574 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7575 %{
7576 match(Set dst (AddP dst src));
7577 effect(KILL cr);
7578 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7579
7580 format %{ "addq $dst, $src\t# ptr" %}
7581 ins_encode %{
7582 __ addq($dst$$Register, $src$$constant);
7583 %}
7584 ins_pipe( ialu_reg );
7585 %}
7586
7587 // XXX addP mem ops ????
7588
7589 instruct checkCastPP(rRegP dst)
7590 %{
7591 match(Set dst (CheckCastPP dst));
7592
7593 size(0);
7594 format %{ "# checkcastPP of $dst" %}
7595 ins_encode(/* empty encoding */);
7596 ins_pipe(empty);
7597 %}
7598
7599 instruct castPP(rRegP dst)
7600 %{
7601 match(Set dst (CastPP dst));
7602
7603 size(0);
7604 format %{ "# castPP of $dst" %}
7605 ins_encode(/* empty encoding */);
7606 ins_pipe(empty);
7607 %}
7608
7609 instruct castII(rRegI dst)
7610 %{
7611 match(Set dst (CastII dst));
7612
7613 size(0);
7614 format %{ "# castII of $dst" %}
7615 ins_encode(/* empty encoding */);
7616 ins_cost(0);
7617 ins_pipe(empty);
7618 %}
7619
7620 instruct castLL(rRegL dst)
7621 %{
7622 match(Set dst (CastLL dst));
7623
7624 size(0);
7625 format %{ "# castLL of $dst" %}
7626 ins_encode(/* empty encoding */);
7627 ins_cost(0);
7628 ins_pipe(empty);
7629 %}
7630
7631 instruct castFF(regF dst)
7632 %{
7633 match(Set dst (CastFF dst));
7634
7635 size(0);
7636 format %{ "# castFF of $dst" %}
7637 ins_encode(/* empty encoding */);
7638 ins_cost(0);
7639 ins_pipe(empty);
7640 %}
7641
7642 instruct castHH(regF dst)
7643 %{
7644 match(Set dst (CastHH dst));
7645
7646 size(0);
7647 format %{ "# castHH of $dst" %}
7648 ins_encode(/* empty encoding */);
7649 ins_cost(0);
7650 ins_pipe(empty);
7651 %}
7652
7653 instruct castDD(regD dst)
7654 %{
7655 match(Set dst (CastDD dst));
7656
7657 size(0);
7658 format %{ "# castDD of $dst" %}
7659 ins_encode(/* empty encoding */);
7660 ins_cost(0);
7661 ins_pipe(empty);
7662 %}
7663
7664 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7665 instruct compareAndSwapP(rRegI res,
7666 memory mem_ptr,
7667 rax_RegP oldval, rRegP newval,
7668 rFlagsReg cr)
7669 %{
7670 predicate(n->as_LoadStore()->barrier_data() == 0);
7671 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7672 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval)));
7673 effect(KILL cr, KILL oldval);
7674
7675 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7676 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7677 "setcc $res \t# emits sete + movzbl or setzue for APX" %}
7678 ins_encode %{
7679 __ lock();
7680 __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
7681 __ setcc(Assembler::equal, $res$$Register);
7682 %}
7683 ins_pipe( pipe_cmpxchg );
7684 %}
7685
7686 instruct compareAndSwapL(rRegI res,
7687 memory mem_ptr,
7688 rax_RegL oldval, rRegL newval,
7689 rFlagsReg cr)
7690 %{
7691 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7692 match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval)));
7693 effect(KILL cr, KILL oldval);
7694
7695 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7696 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7697 "setcc $res \t# emits sete + movzbl or setzue for APX" %}
7698 ins_encode %{
7699 __ lock();
7700 __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
7701 __ setcc(Assembler::equal, $res$$Register);
7702 %}
7703 ins_pipe( pipe_cmpxchg );
7704 %}
7705
7706 instruct compareAndSwapI(rRegI res,
7707 memory mem_ptr,
7708 rax_RegI oldval, rRegI newval,
7709 rFlagsReg cr)
7710 %{
7711 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7712 match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval)));
7713 effect(KILL cr, KILL oldval);
7714
7715 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7716 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7717 "setcc $res \t# emits sete + movzbl or setzue for APX" %}
7718 ins_encode %{
7719 __ lock();
7720 __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
7721 __ setcc(Assembler::equal, $res$$Register);
7722 %}
7723 ins_pipe( pipe_cmpxchg );
7724 %}
7725
7726 instruct compareAndSwapB(rRegI res,
7727 memory mem_ptr,
7728 rax_RegI oldval, rRegI newval,
7729 rFlagsReg cr)
7730 %{
7731 match(Set res (CompareAndSwapB mem_ptr (Binary oldval newval)));
7732 match(Set res (WeakCompareAndSwapB mem_ptr (Binary oldval newval)));
7733 effect(KILL cr, KILL oldval);
7734
7735 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7736 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7737 "setcc $res \t# emits sete + movzbl or setzue for APX" %}
7738 ins_encode %{
7739 __ lock();
7740 __ cmpxchgb($newval$$Register, $mem_ptr$$Address);
7741 __ setcc(Assembler::equal, $res$$Register);
7742 %}
7743 ins_pipe( pipe_cmpxchg );
7744 %}
7745
7746 instruct compareAndSwapS(rRegI res,
7747 memory mem_ptr,
7748 rax_RegI oldval, rRegI newval,
7749 rFlagsReg cr)
7750 %{
7751 match(Set res (CompareAndSwapS mem_ptr (Binary oldval newval)));
7752 match(Set res (WeakCompareAndSwapS mem_ptr (Binary oldval newval)));
7753 effect(KILL cr, KILL oldval);
7754
7755 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7756 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7757 "setcc $res \t# emits sete + movzbl or setzue for APX" %}
7758 ins_encode %{
7759 __ lock();
7760 __ cmpxchgw($newval$$Register, $mem_ptr$$Address);
7761 __ setcc(Assembler::equal, $res$$Register);
7762 %}
7763 ins_pipe( pipe_cmpxchg );
7764 %}
7765
7766 instruct compareAndSwapN(rRegI res,
7767 memory mem_ptr,
7768 rax_RegN oldval, rRegN newval,
7769 rFlagsReg cr) %{
7770 predicate(n->as_LoadStore()->barrier_data() == 0);
7771 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7772 match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval)));
7773 effect(KILL cr, KILL oldval);
7774
7775 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7776 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7777 "setcc $res \t# emits sete + movzbl or setzue for APX" %}
7778 ins_encode %{
7779 __ lock();
7780 __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
7781 __ setcc(Assembler::equal, $res$$Register);
7782 %}
7783 ins_pipe( pipe_cmpxchg );
7784 %}
7785
7786 instruct compareAndExchangeB(
7787 memory mem_ptr,
7788 rax_RegI oldval, rRegI newval,
7789 rFlagsReg cr)
7790 %{
7791 match(Set oldval (CompareAndExchangeB mem_ptr (Binary oldval newval)));
7792 effect(KILL cr);
7793
7794 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7795 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7796 ins_encode %{
7797 __ lock();
7798 __ cmpxchgb($newval$$Register, $mem_ptr$$Address);
7799 %}
7800 ins_pipe( pipe_cmpxchg );
7801 %}
7802
7803 instruct compareAndExchangeS(
7804 memory mem_ptr,
7805 rax_RegI oldval, rRegI newval,
7806 rFlagsReg cr)
7807 %{
7808 match(Set oldval (CompareAndExchangeS mem_ptr (Binary oldval newval)));
7809 effect(KILL cr);
7810
7811 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7812 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7813 ins_encode %{
7814 __ lock();
7815 __ cmpxchgw($newval$$Register, $mem_ptr$$Address);
7816 %}
7817 ins_pipe( pipe_cmpxchg );
7818 %}
7819
7820 instruct compareAndExchangeI(
7821 memory mem_ptr,
7822 rax_RegI oldval, rRegI newval,
7823 rFlagsReg cr)
7824 %{
7825 match(Set oldval (CompareAndExchangeI mem_ptr (Binary oldval newval)));
7826 effect(KILL cr);
7827
7828 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7829 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7830 ins_encode %{
7831 __ lock();
7832 __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
7833 %}
7834 ins_pipe( pipe_cmpxchg );
7835 %}
7836
7837 instruct compareAndExchangeL(
7838 memory mem_ptr,
7839 rax_RegL oldval, rRegL newval,
7840 rFlagsReg cr)
7841 %{
7842 match(Set oldval (CompareAndExchangeL mem_ptr (Binary oldval newval)));
7843 effect(KILL cr);
7844
7845 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7846 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7847 ins_encode %{
7848 __ lock();
7849 __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
7850 %}
7851 ins_pipe( pipe_cmpxchg );
7852 %}
7853
7854 instruct compareAndExchangeN(
7855 memory mem_ptr,
7856 rax_RegN oldval, rRegN newval,
7857 rFlagsReg cr) %{
7858 predicate(n->as_LoadStore()->barrier_data() == 0);
7859 match(Set oldval (CompareAndExchangeN mem_ptr (Binary oldval newval)));
7860 effect(KILL cr);
7861
7862 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7863 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7864 ins_encode %{
7865 __ lock();
7866 __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
7867 %}
7868 ins_pipe( pipe_cmpxchg );
7869 %}
7870
7871 instruct compareAndExchangeP(
7872 memory mem_ptr,
7873 rax_RegP oldval, rRegP newval,
7874 rFlagsReg cr)
7875 %{
7876 predicate(n->as_LoadStore()->barrier_data() == 0);
7877 match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval)));
7878 effect(KILL cr);
7879
7880 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7881 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7882 ins_encode %{
7883 __ lock();
7884 __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
7885 %}
7886 ins_pipe( pipe_cmpxchg );
7887 %}
7888
7889 instruct xaddB_reg_no_res(memory mem, Universe dummy, rRegI add, rFlagsReg cr) %{
7890 predicate(n->as_LoadStore()->result_not_used());
7891 match(Set dummy (GetAndAddB mem add));
7892 effect(KILL cr);
7893 format %{ "addb_lock $mem, $add" %}
7894 ins_encode %{
7895 __ lock();
7896 __ addb($mem$$Address, $add$$Register);
7897 %}
7898 ins_pipe(pipe_cmpxchg);
7899 %}
7900
7901 instruct xaddB_imm_no_res(memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7902 predicate(n->as_LoadStore()->result_not_used());
7903 match(Set dummy (GetAndAddB mem add));
7904 effect(KILL cr);
7905 format %{ "addb_lock $mem, $add" %}
7906 ins_encode %{
7907 __ lock();
7908 __ addb($mem$$Address, $add$$constant);
7909 %}
7910 ins_pipe(pipe_cmpxchg);
7911 %}
7912
7913 instruct xaddB(memory mem, rRegI newval, rFlagsReg cr) %{
7914 predicate(!n->as_LoadStore()->result_not_used());
7915 match(Set newval (GetAndAddB mem newval));
7916 effect(KILL cr);
7917 format %{ "xaddb_lock $mem, $newval" %}
7918 ins_encode %{
7919 __ lock();
7920 __ xaddb($mem$$Address, $newval$$Register);
7921 %}
7922 ins_pipe(pipe_cmpxchg);
7923 %}
7924
7925 instruct xaddS_reg_no_res(memory mem, Universe dummy, rRegI add, rFlagsReg cr) %{
7926 predicate(n->as_LoadStore()->result_not_used());
7927 match(Set dummy (GetAndAddS mem add));
7928 effect(KILL cr);
7929 format %{ "addw_lock $mem, $add" %}
7930 ins_encode %{
7931 __ lock();
7932 __ addw($mem$$Address, $add$$Register);
7933 %}
7934 ins_pipe(pipe_cmpxchg);
7935 %}
7936
7937 instruct xaddS_imm_no_res(memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7938 predicate(UseStoreImmI16 && n->as_LoadStore()->result_not_used());
7939 match(Set dummy (GetAndAddS mem add));
7940 effect(KILL cr);
7941 format %{ "addw_lock $mem, $add" %}
7942 ins_encode %{
7943 __ lock();
7944 __ addw($mem$$Address, $add$$constant);
7945 %}
7946 ins_pipe(pipe_cmpxchg);
7947 %}
7948
7949 instruct xaddS(memory mem, rRegI newval, rFlagsReg cr) %{
7950 predicate(!n->as_LoadStore()->result_not_used());
7951 match(Set newval (GetAndAddS mem newval));
7952 effect(KILL cr);
7953 format %{ "xaddw_lock $mem, $newval" %}
7954 ins_encode %{
7955 __ lock();
7956 __ xaddw($mem$$Address, $newval$$Register);
7957 %}
7958 ins_pipe(pipe_cmpxchg);
7959 %}
7960
7961 instruct xaddI_reg_no_res(memory mem, Universe dummy, rRegI add, rFlagsReg cr) %{
7962 predicate(n->as_LoadStore()->result_not_used());
7963 match(Set dummy (GetAndAddI mem add));
7964 effect(KILL cr);
7965 format %{ "addl_lock $mem, $add" %}
7966 ins_encode %{
7967 __ lock();
7968 __ addl($mem$$Address, $add$$Register);
7969 %}
7970 ins_pipe(pipe_cmpxchg);
7971 %}
7972
7973 instruct xaddI_imm_no_res(memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7974 predicate(n->as_LoadStore()->result_not_used());
7975 match(Set dummy (GetAndAddI mem add));
7976 effect(KILL cr);
7977 format %{ "addl_lock $mem, $add" %}
7978 ins_encode %{
7979 __ lock();
7980 __ addl($mem$$Address, $add$$constant);
7981 %}
7982 ins_pipe(pipe_cmpxchg);
7983 %}
7984
7985 instruct xaddI(memory mem, rRegI newval, rFlagsReg cr) %{
7986 predicate(!n->as_LoadStore()->result_not_used());
7987 match(Set newval (GetAndAddI mem newval));
7988 effect(KILL cr);
7989 format %{ "xaddl_lock $mem, $newval" %}
7990 ins_encode %{
7991 __ lock();
7992 __ xaddl($mem$$Address, $newval$$Register);
7993 %}
7994 ins_pipe(pipe_cmpxchg);
7995 %}
7996
7997 instruct xaddL_reg_no_res(memory mem, Universe dummy, rRegL add, rFlagsReg cr) %{
7998 predicate(n->as_LoadStore()->result_not_used());
7999 match(Set dummy (GetAndAddL mem add));
8000 effect(KILL cr);
8001 format %{ "addq_lock $mem, $add" %}
8002 ins_encode %{
8003 __ lock();
8004 __ addq($mem$$Address, $add$$Register);
8005 %}
8006 ins_pipe(pipe_cmpxchg);
8007 %}
8008
8009 instruct xaddL_imm_no_res(memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
8010 predicate(n->as_LoadStore()->result_not_used());
8011 match(Set dummy (GetAndAddL mem add));
8012 effect(KILL cr);
8013 format %{ "addq_lock $mem, $add" %}
8014 ins_encode %{
8015 __ lock();
8016 __ addq($mem$$Address, $add$$constant);
8017 %}
8018 ins_pipe(pipe_cmpxchg);
8019 %}
8020
8021 instruct xaddL(memory mem, rRegL newval, rFlagsReg cr) %{
8022 predicate(!n->as_LoadStore()->result_not_used());
8023 match(Set newval (GetAndAddL mem newval));
8024 effect(KILL cr);
8025 format %{ "xaddq_lock $mem, $newval" %}
8026 ins_encode %{
8027 __ lock();
8028 __ xaddq($mem$$Address, $newval$$Register);
8029 %}
8030 ins_pipe(pipe_cmpxchg);
8031 %}
8032
8033 instruct xchgB( memory mem, rRegI newval) %{
8034 match(Set newval (GetAndSetB mem newval));
8035 format %{ "XCHGB $newval,[$mem]" %}
8036 ins_encode %{
8037 __ xchgb($newval$$Register, $mem$$Address);
8038 %}
8039 ins_pipe( pipe_cmpxchg );
8040 %}
8041
8042 instruct xchgS( memory mem, rRegI newval) %{
8043 match(Set newval (GetAndSetS mem newval));
8044 format %{ "XCHGW $newval,[$mem]" %}
8045 ins_encode %{
8046 __ xchgw($newval$$Register, $mem$$Address);
8047 %}
8048 ins_pipe( pipe_cmpxchg );
8049 %}
8050
8051 instruct xchgI( memory mem, rRegI newval) %{
8052 match(Set newval (GetAndSetI mem newval));
8053 format %{ "XCHGL $newval,[$mem]" %}
8054 ins_encode %{
8055 __ xchgl($newval$$Register, $mem$$Address);
8056 %}
8057 ins_pipe( pipe_cmpxchg );
8058 %}
8059
8060 instruct xchgL( memory mem, rRegL newval) %{
8061 match(Set newval (GetAndSetL mem newval));
8062 format %{ "XCHGL $newval,[$mem]" %}
8063 ins_encode %{
8064 __ xchgq($newval$$Register, $mem$$Address);
8065 %}
8066 ins_pipe( pipe_cmpxchg );
8067 %}
8068
8069 instruct xchgP( memory mem, rRegP newval) %{
8070 match(Set newval (GetAndSetP mem newval));
8071 predicate(n->as_LoadStore()->barrier_data() == 0);
8072 format %{ "XCHGQ $newval,[$mem]" %}
8073 ins_encode %{
8074 __ xchgq($newval$$Register, $mem$$Address);
8075 %}
8076 ins_pipe( pipe_cmpxchg );
8077 %}
8078
8079 instruct xchgN( memory mem, rRegN newval) %{
8080 predicate(n->as_LoadStore()->barrier_data() == 0);
8081 match(Set newval (GetAndSetN mem newval));
8082 format %{ "XCHGL $newval,$mem]" %}
8083 ins_encode %{
8084 __ xchgl($newval$$Register, $mem$$Address);
8085 %}
8086 ins_pipe( pipe_cmpxchg );
8087 %}
8088
8089 //----------Abs Instructions-------------------------------------------
8090
8091 // Integer Absolute Instructions
8092 instruct absI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8093 %{
8094 match(Set dst (AbsI src));
8095 effect(TEMP dst, KILL cr);
8096 format %{ "xorl $dst, $dst\t# abs int\n\t"
8097 "subl $dst, $src\n\t"
8098 "cmovll $dst, $src" %}
8099 ins_encode %{
8100 __ xorl($dst$$Register, $dst$$Register);
8101 __ subl($dst$$Register, $src$$Register);
8102 __ cmovl(Assembler::less, $dst$$Register, $src$$Register);
8103 %}
8104
8105 ins_pipe(ialu_reg_reg);
8106 %}
8107
8108 // Long Absolute Instructions
8109 instruct absL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8110 %{
8111 match(Set dst (AbsL src));
8112 effect(TEMP dst, KILL cr);
8113 format %{ "xorl $dst, $dst\t# abs long\n\t"
8114 "subq $dst, $src\n\t"
8115 "cmovlq $dst, $src" %}
8116 ins_encode %{
8117 __ xorl($dst$$Register, $dst$$Register);
8118 __ subq($dst$$Register, $src$$Register);
8119 __ cmovq(Assembler::less, $dst$$Register, $src$$Register);
8120 %}
8121
8122 ins_pipe(ialu_reg_reg);
8123 %}
8124
8125 //----------Subtraction Instructions-------------------------------------------
8126
8127 // Integer Subtraction Instructions
8128 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8129 %{
8130 predicate(!UseAPX);
8131 match(Set dst (SubI dst src));
8132 effect(KILL cr);
8133 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8134
8135 format %{ "subl $dst, $src\t# int" %}
8136 ins_encode %{
8137 __ subl($dst$$Register, $src$$Register);
8138 %}
8139 ins_pipe(ialu_reg_reg);
8140 %}
8141
8142 instruct subI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
8143 %{
8144 predicate(UseAPX);
8145 match(Set dst (SubI src1 src2));
8146 effect(KILL cr);
8147 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8148
8149 format %{ "esubl $dst, $src1, $src2\t# int ndd" %}
8150 ins_encode %{
8151 __ esubl($dst$$Register, $src1$$Register, $src2$$Register, false);
8152 %}
8153 ins_pipe(ialu_reg_reg);
8154 %}
8155
8156 instruct subI_rReg_rReg_imm_ndd(rRegI dst, rRegI src1, immI src2, rFlagsReg cr)
8157 %{
8158 predicate(UseAPX);
8159 match(Set dst (SubI src1 src2));
8160 effect(KILL cr);
8161 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8162
8163 format %{ "esubl $dst, $src1, $src2\t# int ndd" %}
8164 ins_encode %{
8165 __ esubl($dst$$Register, $src1$$Register, $src2$$constant, false);
8166 %}
8167 ins_pipe(ialu_reg_reg);
8168 %}
8169
8170 instruct subI_rReg_mem_imm_ndd(rRegI dst, memory src1, immI src2, rFlagsReg cr)
8171 %{
8172 predicate(UseAPX);
8173 match(Set dst (SubI (LoadI src1) src2));
8174 effect(KILL cr);
8175 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8176
8177 format %{ "esubl $dst, $src1, $src2\t# int ndd" %}
8178 ins_encode %{
8179 __ esubl($dst$$Register, $src1$$Address, $src2$$constant, false);
8180 %}
8181 ins_pipe(ialu_reg_reg);
8182 %}
8183
8184 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8185 %{
8186 predicate(!UseAPX);
8187 match(Set dst (SubI dst (LoadI src)));
8188 effect(KILL cr);
8189 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8190
8191 ins_cost(150);
8192 format %{ "subl $dst, $src\t# int" %}
8193 ins_encode %{
8194 __ subl($dst$$Register, $src$$Address);
8195 %}
8196 ins_pipe(ialu_reg_mem);
8197 %}
8198
8199 instruct subI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr)
8200 %{
8201 predicate(UseAPX);
8202 match(Set dst (SubI src1 (LoadI src2)));
8203 effect(KILL cr);
8204 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8205
8206 ins_cost(150);
8207 format %{ "esubl $dst, $src1, $src2\t# int ndd" %}
8208 ins_encode %{
8209 __ esubl($dst$$Register, $src1$$Register, $src2$$Address, false);
8210 %}
8211 ins_pipe(ialu_reg_mem);
8212 %}
8213
8214 instruct subI_rReg_mem_rReg_ndd(rRegI dst, memory src1, rRegI src2, rFlagsReg cr)
8215 %{
8216 predicate(UseAPX);
8217 match(Set dst (SubI (LoadI src1) src2));
8218 effect(KILL cr);
8219 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8220
8221 ins_cost(150);
8222 format %{ "esubl $dst, $src1, $src2\t# int ndd" %}
8223 ins_encode %{
8224 __ esubl($dst$$Register, $src1$$Address, $src2$$Register, false);
8225 %}
8226 ins_pipe(ialu_reg_mem);
8227 %}
8228
8229 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8230 %{
8231 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8232 effect(KILL cr);
8233 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8234
8235 ins_cost(150);
8236 format %{ "subl $dst, $src\t# int" %}
8237 ins_encode %{
8238 __ subl($dst$$Address, $src$$Register);
8239 %}
8240 ins_pipe(ialu_mem_reg);
8241 %}
8242
8243 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8244 %{
8245 predicate(!UseAPX);
8246 match(Set dst (SubL dst src));
8247 effect(KILL cr);
8248 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8249
8250 format %{ "subq $dst, $src\t# long" %}
8251 ins_encode %{
8252 __ subq($dst$$Register, $src$$Register);
8253 %}
8254 ins_pipe(ialu_reg_reg);
8255 %}
8256
8257 instruct subL_rReg_ndd(rRegL dst, rRegL src1, rRegL src2, rFlagsReg cr)
8258 %{
8259 predicate(UseAPX);
8260 match(Set dst (SubL src1 src2));
8261 effect(KILL cr);
8262 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8263
8264 format %{ "esubq $dst, $src1, $src2\t# long ndd" %}
8265 ins_encode %{
8266 __ esubq($dst$$Register, $src1$$Register, $src2$$Register, false);
8267 %}
8268 ins_pipe(ialu_reg_reg);
8269 %}
8270
8271 instruct subL_rReg_rReg_imm_ndd(rRegL dst, rRegL src1, immL32 src2, rFlagsReg cr)
8272 %{
8273 predicate(UseAPX);
8274 match(Set dst (SubL src1 src2));
8275 effect(KILL cr);
8276 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8277
8278 format %{ "esubq $dst, $src1, $src2\t# long ndd" %}
8279 ins_encode %{
8280 __ esubq($dst$$Register, $src1$$Register, $src2$$constant, false);
8281 %}
8282 ins_pipe(ialu_reg_reg);
8283 %}
8284
8285 instruct subL_rReg_mem_imm_ndd(rRegL dst, memory src1, immL32 src2, rFlagsReg cr)
8286 %{
8287 predicate(UseAPX);
8288 match(Set dst (SubL (LoadL src1) src2));
8289 effect(KILL cr);
8290 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8291
8292 format %{ "esubq $dst, $src1, $src2\t# long ndd" %}
8293 ins_encode %{
8294 __ esubq($dst$$Register, $src1$$Address, $src2$$constant, false);
8295 %}
8296 ins_pipe(ialu_reg_reg);
8297 %}
8298
8299 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
8300 %{
8301 predicate(!UseAPX);
8302 match(Set dst (SubL dst (LoadL src)));
8303 effect(KILL cr);
8304 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8305
8306 ins_cost(150);
8307 format %{ "subq $dst, $src\t# long" %}
8308 ins_encode %{
8309 __ subq($dst$$Register, $src$$Address);
8310 %}
8311 ins_pipe(ialu_reg_mem);
8312 %}
8313
8314 instruct subL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr)
8315 %{
8316 predicate(UseAPX);
8317 match(Set dst (SubL src1 (LoadL src2)));
8318 effect(KILL cr);
8319 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8320
8321 ins_cost(150);
8322 format %{ "esubq $dst, $src1, $src2\t# long ndd" %}
8323 ins_encode %{
8324 __ esubq($dst$$Register, $src1$$Register, $src2$$Address, false);
8325 %}
8326 ins_pipe(ialu_reg_mem);
8327 %}
8328
8329 instruct subL_rReg_mem_rReg_ndd(rRegL dst, memory src1, rRegL src2, rFlagsReg cr)
8330 %{
8331 predicate(UseAPX);
8332 match(Set dst (SubL (LoadL src1) src2));
8333 effect(KILL cr);
8334 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8335
8336 ins_cost(150);
8337 format %{ "esubq $dst, $src1, $src2\t# long ndd" %}
8338 ins_encode %{
8339 __ esubq($dst$$Register, $src1$$Address, $src2$$Register, false);
8340 %}
8341 ins_pipe(ialu_reg_mem);
8342 %}
8343
8344 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
8345 %{
8346 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8347 effect(KILL cr);
8348 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
8349
8350 ins_cost(150);
8351 format %{ "subq $dst, $src\t# long" %}
8352 ins_encode %{
8353 __ subq($dst$$Address, $src$$Register);
8354 %}
8355 ins_pipe(ialu_mem_reg);
8356 %}
8357
8358 // Subtract from a pointer
8359 // XXX hmpf???
8360 instruct subP_rReg(rRegP dst, rRegI src, immI_0 zero, rFlagsReg cr)
8361 %{
8362 match(Set dst (AddP dst (SubI zero src)));
8363 effect(KILL cr);
8364
8365 format %{ "subq $dst, $src\t# ptr - int" %}
8366 ins_encode %{
8367 __ subq($dst$$Register, $src$$Register);
8368 %}
8369 ins_pipe(ialu_reg_reg);
8370 %}
8371
8372 instruct negI_rReg(rRegI dst, immI_0 zero, rFlagsReg cr)
8373 %{
8374 predicate(!UseAPX);
8375 match(Set dst (SubI zero dst));
8376 effect(KILL cr);
8377 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
8378
8379 format %{ "negl $dst\t# int" %}
8380 ins_encode %{
8381 __ negl($dst$$Register);
8382 %}
8383 ins_pipe(ialu_reg);
8384 %}
8385
8386 instruct negI_rReg_ndd(rRegI dst, rRegI src, immI_0 zero, rFlagsReg cr)
8387 %{
8388 predicate(UseAPX);
8389 match(Set dst (SubI zero src));
8390 effect(KILL cr);
8391 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
8392
8393 format %{ "enegl $dst, $src\t# int ndd" %}
8394 ins_encode %{
8395 __ enegl($dst$$Register, $src$$Register, false);
8396 %}
8397 ins_pipe(ialu_reg);
8398 %}
8399
8400 instruct negI_rReg_2(rRegI dst, rFlagsReg cr)
8401 %{
8402 predicate(!UseAPX);
8403 match(Set dst (NegI dst));
8404 effect(KILL cr);
8405 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
8406
8407 format %{ "negl $dst\t# int" %}
8408 ins_encode %{
8409 __ negl($dst$$Register);
8410 %}
8411 ins_pipe(ialu_reg);
8412 %}
8413
8414 instruct negI_rReg_2_ndd(rRegI dst, rRegI src, rFlagsReg cr)
8415 %{
8416 predicate(UseAPX);
8417 match(Set dst (NegI src));
8418 effect(KILL cr);
8419 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
8420
8421 format %{ "enegl $dst, $src\t# int ndd" %}
8422 ins_encode %{
8423 __ enegl($dst$$Register, $src$$Register, false);
8424 %}
8425 ins_pipe(ialu_reg);
8426 %}
8427
8428 instruct negI_mem(memory dst, immI_0 zero, rFlagsReg cr)
8429 %{
8430 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
8431 effect(KILL cr);
8432 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
8433
8434 format %{ "negl $dst\t# int" %}
8435 ins_encode %{
8436 __ negl($dst$$Address);
8437 %}
8438 ins_pipe(ialu_reg);
8439 %}
8440
8441 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
8442 %{
8443 predicate(!UseAPX);
8444 match(Set dst (SubL zero dst));
8445 effect(KILL cr);
8446 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
8447
8448 format %{ "negq $dst\t# long" %}
8449 ins_encode %{
8450 __ negq($dst$$Register);
8451 %}
8452 ins_pipe(ialu_reg);
8453 %}
8454
8455 instruct negL_rReg_ndd(rRegL dst, rRegL src, immL0 zero, rFlagsReg cr)
8456 %{
8457 predicate(UseAPX);
8458 match(Set dst (SubL zero src));
8459 effect(KILL cr);
8460 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
8461
8462 format %{ "enegq $dst, $src\t# long ndd" %}
8463 ins_encode %{
8464 __ enegq($dst$$Register, $src$$Register, false);
8465 %}
8466 ins_pipe(ialu_reg);
8467 %}
8468
8469 instruct negL_rReg_2(rRegL dst, rFlagsReg cr)
8470 %{
8471 predicate(!UseAPX);
8472 match(Set dst (NegL dst));
8473 effect(KILL cr);
8474 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
8475
8476 format %{ "negq $dst\t# int" %}
8477 ins_encode %{
8478 __ negq($dst$$Register);
8479 %}
8480 ins_pipe(ialu_reg);
8481 %}
8482
8483 instruct negL_rReg_2_ndd(rRegL dst, rRegL src, rFlagsReg cr)
8484 %{
8485 predicate(UseAPX);
8486 match(Set dst (NegL src));
8487 effect(KILL cr);
8488 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
8489
8490 format %{ "enegq $dst, $src\t# long ndd" %}
8491 ins_encode %{
8492 __ enegq($dst$$Register, $src$$Register, false);
8493 %}
8494 ins_pipe(ialu_reg);
8495 %}
8496
8497 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
8498 %{
8499 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
8500 effect(KILL cr);
8501 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
8502
8503 format %{ "negq $dst\t# long" %}
8504 ins_encode %{
8505 __ negq($dst$$Address);
8506 %}
8507 ins_pipe(ialu_reg);
8508 %}
8509
8510 //----------Multiplication/Division Instructions-------------------------------
8511 // Integer Multiplication Instructions
8512 // Multiply Register
8513
8514 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8515 %{
8516 predicate(!UseAPX);
8517 match(Set dst (MulI dst src));
8518 effect(KILL cr);
8519
8520 ins_cost(300);
8521 format %{ "imull $dst, $src\t# int" %}
8522 ins_encode %{
8523 __ imull($dst$$Register, $src$$Register);
8524 %}
8525 ins_pipe(ialu_reg_reg_alu0);
8526 %}
8527
8528 instruct mulI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
8529 %{
8530 predicate(UseAPX);
8531 match(Set dst (MulI src1 src2));
8532 effect(KILL cr);
8533
8534 ins_cost(300);
8535 format %{ "eimull $dst, $src1, $src2\t# int ndd" %}
8536 ins_encode %{
8537 __ eimull($dst$$Register, $src1$$Register, $src2$$Register, false);
8538 %}
8539 ins_pipe(ialu_reg_reg_alu0);
8540 %}
8541
8542 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
8543 %{
8544 predicate(!UseAPX);
8545 match(Set dst (MulI src imm));
8546 effect(KILL cr);
8547
8548 ins_cost(300);
8549 format %{ "imull $dst, $src, $imm\t# int" %}
8550 ins_encode %{
8551 __ imull($dst$$Register, $src$$Register, $imm$$constant);
8552 %}
8553 ins_pipe(ialu_reg_reg_alu0);
8554 %}
8555
8556 instruct mulI_rReg_rReg_imm_ndd(rRegI dst, rRegI src1, immI src2, rFlagsReg cr)
8557 %{
8558 predicate(UseAPX);
8559 match(Set dst (MulI src1 src2));
8560 effect(KILL cr);
8561
8562 ins_cost(300);
8563 format %{ "eimull $dst, $src1, $src2\t# int ndd" %}
8564 ins_encode %{
8565 __ eimull($dst$$Register, $src1$$Register, $src2$$constant, false);
8566 %}
8567 ins_pipe(ialu_reg_reg_alu0);
8568 %}
8569
8570 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
8571 %{
8572 predicate(!UseAPX);
8573 match(Set dst (MulI dst (LoadI src)));
8574 effect(KILL cr);
8575
8576 ins_cost(350);
8577 format %{ "imull $dst, $src\t# int" %}
8578 ins_encode %{
8579 __ imull($dst$$Register, $src$$Address);
8580 %}
8581 ins_pipe(ialu_reg_mem_alu0);
8582 %}
8583
8584 instruct mulI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr)
8585 %{
8586 predicate(UseAPX);
8587 match(Set dst (MulI src1 (LoadI src2)));
8588 effect(KILL cr);
8589
8590 ins_cost(350);
8591 format %{ "eimull $dst, $src1, $src2\t# int ndd" %}
8592 ins_encode %{
8593 __ eimull($dst$$Register, $src1$$Register, $src2$$Address, false);
8594 %}
8595 ins_pipe(ialu_reg_mem_alu0);
8596 %}
8597
8598 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
8599 %{
8600 predicate(!UseAPX);
8601 match(Set dst (MulI (LoadI src) imm));
8602 effect(KILL cr);
8603
8604 ins_cost(300);
8605 format %{ "imull $dst, $src, $imm\t# int" %}
8606 ins_encode %{
8607 __ imull($dst$$Register, $src$$Address, $imm$$constant);
8608 %}
8609 ins_pipe(ialu_reg_mem_alu0);
8610 %}
8611
8612 instruct mulI_rReg_mem_imm(rRegI dst, memory src1, immI src2, rFlagsReg cr)
8613 %{
8614 predicate(UseAPX);
8615 match(Set dst (MulI (LoadI src1) src2));
8616 effect(KILL cr);
8617
8618 ins_cost(300);
8619 format %{ "eimull $dst, $src1, $src2\t# int ndd" %}
8620 ins_encode %{
8621 __ eimull($dst$$Register, $src1$$Address, $src2$$constant, false);
8622 %}
8623 ins_pipe(ialu_reg_mem_alu0);
8624 %}
8625
8626 instruct mulAddS2I_rReg(rRegI dst, rRegI src1, rRegI src2, rRegI src3, rFlagsReg cr)
8627 %{
8628 match(Set dst (MulAddS2I (Binary dst src1) (Binary src2 src3)));
8629 effect(KILL cr, KILL src2);
8630
8631 expand %{ mulI_rReg(dst, src1, cr);
8632 mulI_rReg(src2, src3, cr);
8633 addI_rReg(dst, src2, cr); %}
8634 %}
8635
8636 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8637 %{
8638 predicate(!UseAPX);
8639 match(Set dst (MulL dst src));
8640 effect(KILL cr);
8641
8642 ins_cost(300);
8643 format %{ "imulq $dst, $src\t# long" %}
8644 ins_encode %{
8645 __ imulq($dst$$Register, $src$$Register);
8646 %}
8647 ins_pipe(ialu_reg_reg_alu0);
8648 %}
8649
8650 instruct mulL_rReg_ndd(rRegL dst, rRegL src1, rRegL src2, rFlagsReg cr)
8651 %{
8652 predicate(UseAPX);
8653 match(Set dst (MulL src1 src2));
8654 effect(KILL cr);
8655
8656 ins_cost(300);
8657 format %{ "eimulq $dst, $src1, $src2\t# long ndd" %}
8658 ins_encode %{
8659 __ eimulq($dst$$Register, $src1$$Register, $src2$$Register, false);
8660 %}
8661 ins_pipe(ialu_reg_reg_alu0);
8662 %}
8663
8664 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
8665 %{
8666 predicate(!UseAPX);
8667 match(Set dst (MulL src imm));
8668 effect(KILL cr);
8669
8670 ins_cost(300);
8671 format %{ "imulq $dst, $src, $imm\t# long" %}
8672 ins_encode %{
8673 __ imulq($dst$$Register, $src$$Register, $imm$$constant);
8674 %}
8675 ins_pipe(ialu_reg_reg_alu0);
8676 %}
8677
8678 instruct mulL_rReg_rReg_imm_ndd(rRegL dst, rRegL src1, immL32 src2, rFlagsReg cr)
8679 %{
8680 predicate(UseAPX);
8681 match(Set dst (MulL src1 src2));
8682 effect(KILL cr);
8683
8684 ins_cost(300);
8685 format %{ "eimulq $dst, $src1, $src2\t# long ndd" %}
8686 ins_encode %{
8687 __ eimulq($dst$$Register, $src1$$Register, $src2$$constant, false);
8688 %}
8689 ins_pipe(ialu_reg_reg_alu0);
8690 %}
8691
8692 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
8693 %{
8694 predicate(!UseAPX);
8695 match(Set dst (MulL dst (LoadL src)));
8696 effect(KILL cr);
8697
8698 ins_cost(350);
8699 format %{ "imulq $dst, $src\t# long" %}
8700 ins_encode %{
8701 __ imulq($dst$$Register, $src$$Address);
8702 %}
8703 ins_pipe(ialu_reg_mem_alu0);
8704 %}
8705
8706 instruct mulL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr)
8707 %{
8708 predicate(UseAPX);
8709 match(Set dst (MulL src1 (LoadL src2)));
8710 effect(KILL cr);
8711
8712 ins_cost(350);
8713 format %{ "eimulq $dst, $src1, $src2 \t# long" %}
8714 ins_encode %{
8715 __ eimulq($dst$$Register, $src1$$Register, $src2$$Address, false);
8716 %}
8717 ins_pipe(ialu_reg_mem_alu0);
8718 %}
8719
8720 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
8721 %{
8722 predicate(!UseAPX);
8723 match(Set dst (MulL (LoadL src) imm));
8724 effect(KILL cr);
8725
8726 ins_cost(300);
8727 format %{ "imulq $dst, $src, $imm\t# long" %}
8728 ins_encode %{
8729 __ imulq($dst$$Register, $src$$Address, $imm$$constant);
8730 %}
8731 ins_pipe(ialu_reg_mem_alu0);
8732 %}
8733
8734 instruct mulL_rReg_mem_imm_ndd(rRegL dst, memory src1, immL32 src2, rFlagsReg cr)
8735 %{
8736 predicate(UseAPX);
8737 match(Set dst (MulL (LoadL src1) src2));
8738 effect(KILL cr);
8739
8740 ins_cost(300);
8741 format %{ "eimulq $dst, $src1, $src2\t# long ndd" %}
8742 ins_encode %{
8743 __ eimulq($dst$$Register, $src1$$Address, $src2$$constant, false);
8744 %}
8745 ins_pipe(ialu_reg_mem_alu0);
8746 %}
8747
8748 instruct mulHiL_rReg(rdx_RegL dst, rRegL src, rax_RegL rax, rFlagsReg cr)
8749 %{
8750 match(Set dst (MulHiL src rax));
8751 effect(USE_KILL rax, KILL cr);
8752
8753 ins_cost(300);
8754 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
8755 ins_encode %{
8756 __ imulq($src$$Register);
8757 %}
8758 ins_pipe(ialu_reg_reg_alu0);
8759 %}
8760
8761 instruct umulHiL_rReg(rdx_RegL dst, rRegL src, rax_RegL rax, rFlagsReg cr)
8762 %{
8763 match(Set dst (UMulHiL src rax));
8764 effect(USE_KILL rax, KILL cr);
8765
8766 ins_cost(300);
8767 format %{ "mulq RDX:RAX, RAX, $src\t# umulhi" %}
8768 ins_encode %{
8769 __ mulq($src$$Register);
8770 %}
8771 ins_pipe(ialu_reg_reg_alu0);
8772 %}
8773
8774 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8775 rFlagsReg cr)
8776 %{
8777 match(Set rax (DivI rax div));
8778 effect(KILL rdx, KILL cr);
8779
8780 ins_cost(30*100+10*100); // XXX
8781 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8782 "jne,s normal\n\t"
8783 "xorl rdx, rdx\n\t"
8784 "cmpl $div, -1\n\t"
8785 "je,s done\n"
8786 "normal: cdql\n\t"
8787 "idivl $div\n"
8788 "done:" %}
8789 ins_encode(cdql_enc(div));
8790 ins_pipe(ialu_reg_reg_alu0);
8791 %}
8792
8793 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8794 rFlagsReg cr)
8795 %{
8796 match(Set rax (DivL rax div));
8797 effect(KILL rdx, KILL cr);
8798
8799 ins_cost(30*100+10*100); // XXX
8800 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8801 "cmpq rax, rdx\n\t"
8802 "jne,s normal\n\t"
8803 "xorl rdx, rdx\n\t"
8804 "cmpq $div, -1\n\t"
8805 "je,s done\n"
8806 "normal: cdqq\n\t"
8807 "idivq $div\n"
8808 "done:" %}
8809 ins_encode(cdqq_enc(div));
8810 ins_pipe(ialu_reg_reg_alu0);
8811 %}
8812
8813 instruct udivI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, rFlagsReg cr)
8814 %{
8815 match(Set rax (UDivI rax div));
8816 effect(KILL rdx, KILL cr);
8817
8818 ins_cost(300);
8819 format %{ "udivl $rax,$rax,$div\t# UDivI\n" %}
8820 ins_encode %{
8821 __ udivI($rax$$Register, $div$$Register, $rdx$$Register);
8822 %}
8823 ins_pipe(ialu_reg_reg_alu0);
8824 %}
8825
8826 instruct udivL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, rFlagsReg cr)
8827 %{
8828 match(Set rax (UDivL rax div));
8829 effect(KILL rdx, KILL cr);
8830
8831 ins_cost(300);
8832 format %{ "udivq $rax,$rax,$div\t# UDivL\n" %}
8833 ins_encode %{
8834 __ udivL($rax$$Register, $div$$Register, $rdx$$Register);
8835 %}
8836 ins_pipe(ialu_reg_reg_alu0);
8837 %}
8838
8839 // Integer DIVMOD with Register, both quotient and mod results
8840 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8841 rFlagsReg cr)
8842 %{
8843 match(DivModI rax div);
8844 effect(KILL cr);
8845
8846 ins_cost(30*100+10*100); // XXX
8847 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8848 "jne,s normal\n\t"
8849 "xorl rdx, rdx\n\t"
8850 "cmpl $div, -1\n\t"
8851 "je,s done\n"
8852 "normal: cdql\n\t"
8853 "idivl $div\n"
8854 "done:" %}
8855 ins_encode(cdql_enc(div));
8856 ins_pipe(pipe_slow);
8857 %}
8858
8859 // Long DIVMOD with Register, both quotient and mod results
8860 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8861 rFlagsReg cr)
8862 %{
8863 match(DivModL rax div);
8864 effect(KILL cr);
8865
8866 ins_cost(30*100+10*100); // XXX
8867 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8868 "cmpq rax, rdx\n\t"
8869 "jne,s normal\n\t"
8870 "xorl rdx, rdx\n\t"
8871 "cmpq $div, -1\n\t"
8872 "je,s done\n"
8873 "normal: cdqq\n\t"
8874 "idivq $div\n"
8875 "done:" %}
8876 ins_encode(cdqq_enc(div));
8877 ins_pipe(pipe_slow);
8878 %}
8879
8880 // Unsigned integer DIVMOD with Register, both quotient and mod results
8881 instruct udivModI_rReg_divmod(rax_RegI rax, no_rax_rdx_RegI tmp, rdx_RegI rdx,
8882 no_rax_rdx_RegI div, rFlagsReg cr)
8883 %{
8884 match(UDivModI rax div);
8885 effect(TEMP tmp, KILL cr);
8886
8887 ins_cost(300);
8888 format %{ "udivl $rax,$rax,$div\t# begin UDivModI\n\t"
8889 "umodl $rdx,$rax,$div\t! using $tmp as TEMP # end UDivModI\n"
8890 %}
8891 ins_encode %{
8892 __ udivmodI($rax$$Register, $div$$Register, $rdx$$Register, $tmp$$Register);
8893 %}
8894 ins_pipe(pipe_slow);
8895 %}
8896
8897 // Unsigned long DIVMOD with Register, both quotient and mod results
8898 instruct udivModL_rReg_divmod(rax_RegL rax, no_rax_rdx_RegL tmp, rdx_RegL rdx,
8899 no_rax_rdx_RegL div, rFlagsReg cr)
8900 %{
8901 match(UDivModL rax div);
8902 effect(TEMP tmp, KILL cr);
8903
8904 ins_cost(300);
8905 format %{ "udivq $rax,$rax,$div\t# begin UDivModL\n\t"
8906 "umodq $rdx,$rax,$div\t! using $tmp as TEMP # end UDivModL\n"
8907 %}
8908 ins_encode %{
8909 __ udivmodL($rax$$Register, $div$$Register, $rdx$$Register, $tmp$$Register);
8910 %}
8911 ins_pipe(pipe_slow);
8912 %}
8913
8914 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
8915 rFlagsReg cr)
8916 %{
8917 match(Set rdx (ModI rax div));
8918 effect(KILL rax, KILL cr);
8919
8920 ins_cost(300); // XXX
8921 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
8922 "jne,s normal\n\t"
8923 "xorl rdx, rdx\n\t"
8924 "cmpl $div, -1\n\t"
8925 "je,s done\n"
8926 "normal: cdql\n\t"
8927 "idivl $div\n"
8928 "done:" %}
8929 ins_encode(cdql_enc(div));
8930 ins_pipe(ialu_reg_reg_alu0);
8931 %}
8932
8933 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
8934 rFlagsReg cr)
8935 %{
8936 match(Set rdx (ModL rax div));
8937 effect(KILL rax, KILL cr);
8938
8939 ins_cost(300); // XXX
8940 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
8941 "cmpq rax, rdx\n\t"
8942 "jne,s normal\n\t"
8943 "xorl rdx, rdx\n\t"
8944 "cmpq $div, -1\n\t"
8945 "je,s done\n"
8946 "normal: cdqq\n\t"
8947 "idivq $div\n"
8948 "done:" %}
8949 ins_encode(cdqq_enc(div));
8950 ins_pipe(ialu_reg_reg_alu0);
8951 %}
8952
8953 instruct umodI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div, rFlagsReg cr)
8954 %{
8955 match(Set rdx (UModI rax div));
8956 effect(KILL rax, KILL cr);
8957
8958 ins_cost(300);
8959 format %{ "umodl $rdx,$rax,$div\t# UModI\n" %}
8960 ins_encode %{
8961 __ umodI($rax$$Register, $div$$Register, $rdx$$Register);
8962 %}
8963 ins_pipe(ialu_reg_reg_alu0);
8964 %}
8965
8966 instruct umodL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div, rFlagsReg cr)
8967 %{
8968 match(Set rdx (UModL rax div));
8969 effect(KILL rax, KILL cr);
8970
8971 ins_cost(300);
8972 format %{ "umodq $rdx,$rax,$div\t# UModL\n" %}
8973 ins_encode %{
8974 __ umodL($rax$$Register, $div$$Register, $rdx$$Register);
8975 %}
8976 ins_pipe(ialu_reg_reg_alu0);
8977 %}
8978
8979 // Integer Shift Instructions
8980 // Shift Left by one, two, three
8981 instruct salI_rReg_immI2(rRegI dst, immI2 shift, rFlagsReg cr)
8982 %{
8983 predicate(!UseAPX);
8984 match(Set dst (LShiftI dst shift));
8985 effect(KILL cr);
8986
8987 format %{ "sall $dst, $shift" %}
8988 ins_encode %{
8989 __ sall($dst$$Register, $shift$$constant);
8990 %}
8991 ins_pipe(ialu_reg);
8992 %}
8993
8994 // Shift Left by one, two, three
8995 instruct salI_rReg_immI2_ndd(rRegI dst, rRegI src, immI2 shift, rFlagsReg cr)
8996 %{
8997 predicate(UseAPX);
8998 match(Set dst (LShiftI src shift));
8999 effect(KILL cr);
9000
9001 format %{ "esall $dst, $src, $shift\t# int(ndd)" %}
9002 ins_encode %{
9003 __ esall($dst$$Register, $src$$Register, $shift$$constant, false);
9004 %}
9005 ins_pipe(ialu_reg);
9006 %}
9007
9008 // Shift Left by 8-bit immediate
9009 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
9010 %{
9011 predicate(!UseAPX);
9012 match(Set dst (LShiftI dst shift));
9013 effect(KILL cr);
9014
9015 format %{ "sall $dst, $shift" %}
9016 ins_encode %{
9017 __ sall($dst$$Register, $shift$$constant);
9018 %}
9019 ins_pipe(ialu_reg);
9020 %}
9021
9022 // Shift Left by 8-bit immediate
9023 instruct salI_rReg_imm_ndd(rRegI dst, rRegI src, immI8 shift, rFlagsReg cr)
9024 %{
9025 predicate(UseAPX);
9026 match(Set dst (LShiftI src shift));
9027 effect(KILL cr);
9028
9029 format %{ "esall $dst, $src, $shift\t# int (ndd)" %}
9030 ins_encode %{
9031 __ esall($dst$$Register, $src$$Register, $shift$$constant, false);
9032 %}
9033 ins_pipe(ialu_reg);
9034 %}
9035
9036 instruct salI_rReg_mem_imm_ndd(rRegI dst, memory src, immI8 shift, rFlagsReg cr)
9037 %{
9038 predicate(UseAPX);
9039 match(Set dst (LShiftI (LoadI src) shift));
9040 effect(KILL cr);
9041
9042 format %{ "esall $dst, $src, $shift\t# int (ndd)" %}
9043 ins_encode %{
9044 __ esall($dst$$Register, $src$$Address, $shift$$constant, false);
9045 %}
9046 ins_pipe(ialu_reg);
9047 %}
9048
9049 // Shift Left by 8-bit immediate
9050 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9051 %{
9052 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
9053 effect(KILL cr);
9054
9055 format %{ "sall $dst, $shift" %}
9056 ins_encode %{
9057 __ sall($dst$$Address, $shift$$constant);
9058 %}
9059 ins_pipe(ialu_mem_imm);
9060 %}
9061
9062 // Shift Left by variable
9063 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
9064 %{
9065 predicate(!VM_Version::supports_bmi2());
9066 match(Set dst (LShiftI dst shift));
9067 effect(KILL cr);
9068
9069 format %{ "sall $dst, $shift" %}
9070 ins_encode %{
9071 __ sall($dst$$Register);
9072 %}
9073 ins_pipe(ialu_reg_reg);
9074 %}
9075
9076 // Shift Left by variable
9077 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9078 %{
9079 predicate(!VM_Version::supports_bmi2());
9080 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
9081 effect(KILL cr);
9082
9083 format %{ "sall $dst, $shift" %}
9084 ins_encode %{
9085 __ sall($dst$$Address);
9086 %}
9087 ins_pipe(ialu_mem_reg);
9088 %}
9089
9090 instruct salI_rReg_rReg(rRegI dst, rRegI src, rRegI shift)
9091 %{
9092 predicate(VM_Version::supports_bmi2());
9093 match(Set dst (LShiftI src shift));
9094
9095 format %{ "shlxl $dst, $src, $shift" %}
9096 ins_encode %{
9097 __ shlxl($dst$$Register, $src$$Register, $shift$$Register);
9098 %}
9099 ins_pipe(ialu_reg_reg);
9100 %}
9101
9102 instruct salI_mem_rReg(rRegI dst, memory src, rRegI shift)
9103 %{
9104 predicate(VM_Version::supports_bmi2());
9105 match(Set dst (LShiftI (LoadI src) shift));
9106 ins_cost(175);
9107 format %{ "shlxl $dst, $src, $shift" %}
9108 ins_encode %{
9109 __ shlxl($dst$$Register, $src$$Address, $shift$$Register);
9110 %}
9111 ins_pipe(ialu_reg_mem);
9112 %}
9113
9114 // Arithmetic Shift Right by 8-bit immediate
9115 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
9116 %{
9117 predicate(!UseAPX);
9118 match(Set dst (RShiftI dst shift));
9119 effect(KILL cr);
9120
9121 format %{ "sarl $dst, $shift" %}
9122 ins_encode %{
9123 __ sarl($dst$$Register, $shift$$constant);
9124 %}
9125 ins_pipe(ialu_mem_imm);
9126 %}
9127
9128 // Arithmetic Shift Right by 8-bit immediate
9129 instruct sarI_rReg_imm_ndd(rRegI dst, rRegI src, immI8 shift, rFlagsReg cr)
9130 %{
9131 predicate(UseAPX);
9132 match(Set dst (RShiftI src shift));
9133 effect(KILL cr);
9134
9135 format %{ "esarl $dst, $src, $shift\t# int (ndd)" %}
9136 ins_encode %{
9137 __ esarl($dst$$Register, $src$$Register, $shift$$constant, false);
9138 %}
9139 ins_pipe(ialu_mem_imm);
9140 %}
9141
9142 instruct sarI_rReg_mem_imm_ndd(rRegI dst, memory src, immI8 shift, rFlagsReg cr)
9143 %{
9144 predicate(UseAPX);
9145 match(Set dst (RShiftI (LoadI src) shift));
9146 effect(KILL cr);
9147
9148 format %{ "esarl $dst, $src, $shift\t# int (ndd)" %}
9149 ins_encode %{
9150 __ esarl($dst$$Register, $src$$Address, $shift$$constant, false);
9151 %}
9152 ins_pipe(ialu_mem_imm);
9153 %}
9154
9155 // Arithmetic Shift Right by 8-bit immediate
9156 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9157 %{
9158 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
9159 effect(KILL cr);
9160
9161 format %{ "sarl $dst, $shift" %}
9162 ins_encode %{
9163 __ sarl($dst$$Address, $shift$$constant);
9164 %}
9165 ins_pipe(ialu_mem_imm);
9166 %}
9167
9168 // Arithmetic Shift Right by variable
9169 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
9170 %{
9171 predicate(!VM_Version::supports_bmi2());
9172 match(Set dst (RShiftI dst shift));
9173 effect(KILL cr);
9174
9175 format %{ "sarl $dst, $shift" %}
9176 ins_encode %{
9177 __ sarl($dst$$Register);
9178 %}
9179 ins_pipe(ialu_reg_reg);
9180 %}
9181
9182 // Arithmetic Shift Right by variable
9183 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9184 %{
9185 predicate(!VM_Version::supports_bmi2());
9186 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
9187 effect(KILL cr);
9188
9189 format %{ "sarl $dst, $shift" %}
9190 ins_encode %{
9191 __ sarl($dst$$Address);
9192 %}
9193 ins_pipe(ialu_mem_reg);
9194 %}
9195
9196 instruct sarI_rReg_rReg(rRegI dst, rRegI src, rRegI shift)
9197 %{
9198 predicate(VM_Version::supports_bmi2());
9199 match(Set dst (RShiftI src shift));
9200
9201 format %{ "sarxl $dst, $src, $shift" %}
9202 ins_encode %{
9203 __ sarxl($dst$$Register, $src$$Register, $shift$$Register);
9204 %}
9205 ins_pipe(ialu_reg_reg);
9206 %}
9207
9208 instruct sarI_mem_rReg(rRegI dst, memory src, rRegI shift)
9209 %{
9210 predicate(VM_Version::supports_bmi2());
9211 match(Set dst (RShiftI (LoadI src) shift));
9212 ins_cost(175);
9213 format %{ "sarxl $dst, $src, $shift" %}
9214 ins_encode %{
9215 __ sarxl($dst$$Register, $src$$Address, $shift$$Register);
9216 %}
9217 ins_pipe(ialu_reg_mem);
9218 %}
9219
9220 // Logical Shift Right by 8-bit immediate
9221 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
9222 %{
9223 predicate(!UseAPX);
9224 match(Set dst (URShiftI dst shift));
9225 effect(KILL cr);
9226
9227 format %{ "shrl $dst, $shift" %}
9228 ins_encode %{
9229 __ shrl($dst$$Register, $shift$$constant);
9230 %}
9231 ins_pipe(ialu_reg);
9232 %}
9233
9234 // Logical Shift Right by 8-bit immediate
9235 instruct shrI_rReg_imm_ndd(rRegI dst, rRegI src, immI8 shift, rFlagsReg cr)
9236 %{
9237 predicate(UseAPX);
9238 match(Set dst (URShiftI src shift));
9239 effect(KILL cr);
9240
9241 format %{ "eshrl $dst, $src, $shift\t # int (ndd)" %}
9242 ins_encode %{
9243 __ eshrl($dst$$Register, $src$$Register, $shift$$constant, false);
9244 %}
9245 ins_pipe(ialu_reg);
9246 %}
9247
9248 instruct shrI_rReg_mem_imm_ndd(rRegI dst, memory src, immI8 shift, rFlagsReg cr)
9249 %{
9250 predicate(UseAPX);
9251 match(Set dst (URShiftI (LoadI src) shift));
9252 effect(KILL cr);
9253
9254 format %{ "eshrl $dst, $src, $shift\t # int (ndd)" %}
9255 ins_encode %{
9256 __ eshrl($dst$$Register, $src$$Address, $shift$$constant, false);
9257 %}
9258 ins_pipe(ialu_reg);
9259 %}
9260
9261 // Logical Shift Right by 8-bit immediate
9262 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9263 %{
9264 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
9265 effect(KILL cr);
9266
9267 format %{ "shrl $dst, $shift" %}
9268 ins_encode %{
9269 __ shrl($dst$$Address, $shift$$constant);
9270 %}
9271 ins_pipe(ialu_mem_imm);
9272 %}
9273
9274 // Logical Shift Right by variable
9275 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
9276 %{
9277 predicate(!VM_Version::supports_bmi2());
9278 match(Set dst (URShiftI dst shift));
9279 effect(KILL cr);
9280
9281 format %{ "shrl $dst, $shift" %}
9282 ins_encode %{
9283 __ shrl($dst$$Register);
9284 %}
9285 ins_pipe(ialu_reg_reg);
9286 %}
9287
9288 // Logical Shift Right by variable
9289 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9290 %{
9291 predicate(!VM_Version::supports_bmi2());
9292 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
9293 effect(KILL cr);
9294
9295 format %{ "shrl $dst, $shift" %}
9296 ins_encode %{
9297 __ shrl($dst$$Address);
9298 %}
9299 ins_pipe(ialu_mem_reg);
9300 %}
9301
9302 instruct shrI_rReg_rReg(rRegI dst, rRegI src, rRegI shift)
9303 %{
9304 predicate(VM_Version::supports_bmi2());
9305 match(Set dst (URShiftI src shift));
9306
9307 format %{ "shrxl $dst, $src, $shift" %}
9308 ins_encode %{
9309 __ shrxl($dst$$Register, $src$$Register, $shift$$Register);
9310 %}
9311 ins_pipe(ialu_reg_reg);
9312 %}
9313
9314 instruct shrI_mem_rReg(rRegI dst, memory src, rRegI shift)
9315 %{
9316 predicate(VM_Version::supports_bmi2());
9317 match(Set dst (URShiftI (LoadI src) shift));
9318 ins_cost(175);
9319 format %{ "shrxl $dst, $src, $shift" %}
9320 ins_encode %{
9321 __ shrxl($dst$$Register, $src$$Address, $shift$$Register);
9322 %}
9323 ins_pipe(ialu_reg_mem);
9324 %}
9325
9326 // Long Shift Instructions
9327 // Shift Left by one, two, three
9328 instruct salL_rReg_immI2(rRegL dst, immI2 shift, rFlagsReg cr)
9329 %{
9330 predicate(!UseAPX);
9331 match(Set dst (LShiftL dst shift));
9332 effect(KILL cr);
9333
9334 format %{ "salq $dst, $shift" %}
9335 ins_encode %{
9336 __ salq($dst$$Register, $shift$$constant);
9337 %}
9338 ins_pipe(ialu_reg);
9339 %}
9340
9341 // Shift Left by one, two, three
9342 instruct salL_rReg_immI2_ndd(rRegL dst, rRegL src, immI2 shift, rFlagsReg cr)
9343 %{
9344 predicate(UseAPX);
9345 match(Set dst (LShiftL src shift));
9346 effect(KILL cr);
9347
9348 format %{ "esalq $dst, $src, $shift\t# long (ndd)" %}
9349 ins_encode %{
9350 __ esalq($dst$$Register, $src$$Register, $shift$$constant, false);
9351 %}
9352 ins_pipe(ialu_reg);
9353 %}
9354
9355 // Shift Left by 8-bit immediate
9356 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
9357 %{
9358 predicate(!UseAPX);
9359 match(Set dst (LShiftL dst shift));
9360 effect(KILL cr);
9361
9362 format %{ "salq $dst, $shift" %}
9363 ins_encode %{
9364 __ salq($dst$$Register, $shift$$constant);
9365 %}
9366 ins_pipe(ialu_reg);
9367 %}
9368
9369 // Shift Left by 8-bit immediate
9370 instruct salL_rReg_imm_ndd(rRegL dst, rRegL src, immI8 shift, rFlagsReg cr)
9371 %{
9372 predicate(UseAPX);
9373 match(Set dst (LShiftL src shift));
9374 effect(KILL cr);
9375
9376 format %{ "esalq $dst, $src, $shift\t# long (ndd)" %}
9377 ins_encode %{
9378 __ esalq($dst$$Register, $src$$Register, $shift$$constant, false);
9379 %}
9380 ins_pipe(ialu_reg);
9381 %}
9382
9383 instruct salL_rReg_mem_imm_ndd(rRegL dst, memory src, immI8 shift, rFlagsReg cr)
9384 %{
9385 predicate(UseAPX);
9386 match(Set dst (LShiftL (LoadL src) shift));
9387 effect(KILL cr);
9388
9389 format %{ "esalq $dst, $src, $shift\t# long (ndd)" %}
9390 ins_encode %{
9391 __ esalq($dst$$Register, $src$$Address, $shift$$constant, false);
9392 %}
9393 ins_pipe(ialu_reg);
9394 %}
9395
9396 // Shift Left by 8-bit immediate
9397 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9398 %{
9399 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
9400 effect(KILL cr);
9401
9402 format %{ "salq $dst, $shift" %}
9403 ins_encode %{
9404 __ salq($dst$$Address, $shift$$constant);
9405 %}
9406 ins_pipe(ialu_mem_imm);
9407 %}
9408
9409 // Shift Left by variable
9410 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9411 %{
9412 predicate(!VM_Version::supports_bmi2());
9413 match(Set dst (LShiftL dst shift));
9414 effect(KILL cr);
9415
9416 format %{ "salq $dst, $shift" %}
9417 ins_encode %{
9418 __ salq($dst$$Register);
9419 %}
9420 ins_pipe(ialu_reg_reg);
9421 %}
9422
9423 // Shift Left by variable
9424 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9425 %{
9426 predicate(!VM_Version::supports_bmi2());
9427 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
9428 effect(KILL cr);
9429
9430 format %{ "salq $dst, $shift" %}
9431 ins_encode %{
9432 __ salq($dst$$Address);
9433 %}
9434 ins_pipe(ialu_mem_reg);
9435 %}
9436
9437 instruct salL_rReg_rReg(rRegL dst, rRegL src, rRegI shift)
9438 %{
9439 predicate(VM_Version::supports_bmi2());
9440 match(Set dst (LShiftL src shift));
9441
9442 format %{ "shlxq $dst, $src, $shift" %}
9443 ins_encode %{
9444 __ shlxq($dst$$Register, $src$$Register, $shift$$Register);
9445 %}
9446 ins_pipe(ialu_reg_reg);
9447 %}
9448
9449 instruct salL_mem_rReg(rRegL dst, memory src, rRegI shift)
9450 %{
9451 predicate(VM_Version::supports_bmi2());
9452 match(Set dst (LShiftL (LoadL src) shift));
9453 ins_cost(175);
9454 format %{ "shlxq $dst, $src, $shift" %}
9455 ins_encode %{
9456 __ shlxq($dst$$Register, $src$$Address, $shift$$Register);
9457 %}
9458 ins_pipe(ialu_reg_mem);
9459 %}
9460
9461 // Arithmetic Shift Right by 8-bit immediate
9462 instruct sarL_rReg_imm(rRegL dst, immI shift, rFlagsReg cr)
9463 %{
9464 predicate(!UseAPX);
9465 match(Set dst (RShiftL dst shift));
9466 effect(KILL cr);
9467
9468 format %{ "sarq $dst, $shift" %}
9469 ins_encode %{
9470 __ sarq($dst$$Register, (unsigned char)($shift$$constant & 0x3F));
9471 %}
9472 ins_pipe(ialu_mem_imm);
9473 %}
9474
9475 // Arithmetic Shift Right by 8-bit immediate
9476 instruct sarL_rReg_imm_ndd(rRegL dst, rRegL src, immI shift, rFlagsReg cr)
9477 %{
9478 predicate(UseAPX);
9479 match(Set dst (RShiftL src shift));
9480 effect(KILL cr);
9481
9482 format %{ "esarq $dst, $src, $shift\t# long (ndd)" %}
9483 ins_encode %{
9484 __ esarq($dst$$Register, $src$$Register, (unsigned char)($shift$$constant & 0x3F), false);
9485 %}
9486 ins_pipe(ialu_mem_imm);
9487 %}
9488
9489 instruct sarL_rReg_mem_imm_ndd(rRegL dst, memory src, immI shift, rFlagsReg cr)
9490 %{
9491 predicate(UseAPX);
9492 match(Set dst (RShiftL (LoadL src) shift));
9493 effect(KILL cr);
9494
9495 format %{ "esarq $dst, $src, $shift\t# long (ndd)" %}
9496 ins_encode %{
9497 __ esarq($dst$$Register, $src$$Address, (unsigned char)($shift$$constant & 0x3F), false);
9498 %}
9499 ins_pipe(ialu_mem_imm);
9500 %}
9501
9502 // Arithmetic Shift Right by 8-bit immediate
9503 instruct sarL_mem_imm(memory dst, immI shift, rFlagsReg cr)
9504 %{
9505 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
9506 effect(KILL cr);
9507
9508 format %{ "sarq $dst, $shift" %}
9509 ins_encode %{
9510 __ sarq($dst$$Address, (unsigned char)($shift$$constant & 0x3F));
9511 %}
9512 ins_pipe(ialu_mem_imm);
9513 %}
9514
9515 // Arithmetic Shift Right by variable
9516 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9517 %{
9518 predicate(!VM_Version::supports_bmi2());
9519 match(Set dst (RShiftL dst shift));
9520 effect(KILL cr);
9521
9522 format %{ "sarq $dst, $shift" %}
9523 ins_encode %{
9524 __ sarq($dst$$Register);
9525 %}
9526 ins_pipe(ialu_reg_reg);
9527 %}
9528
9529 // Arithmetic Shift Right by variable
9530 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9531 %{
9532 predicate(!VM_Version::supports_bmi2());
9533 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
9534 effect(KILL cr);
9535
9536 format %{ "sarq $dst, $shift" %}
9537 ins_encode %{
9538 __ sarq($dst$$Address);
9539 %}
9540 ins_pipe(ialu_mem_reg);
9541 %}
9542
9543 instruct sarL_rReg_rReg(rRegL dst, rRegL src, rRegI shift)
9544 %{
9545 predicate(VM_Version::supports_bmi2());
9546 match(Set dst (RShiftL src shift));
9547
9548 format %{ "sarxq $dst, $src, $shift" %}
9549 ins_encode %{
9550 __ sarxq($dst$$Register, $src$$Register, $shift$$Register);
9551 %}
9552 ins_pipe(ialu_reg_reg);
9553 %}
9554
9555 instruct sarL_mem_rReg(rRegL dst, memory src, rRegI shift)
9556 %{
9557 predicate(VM_Version::supports_bmi2());
9558 match(Set dst (RShiftL (LoadL src) shift));
9559 ins_cost(175);
9560 format %{ "sarxq $dst, $src, $shift" %}
9561 ins_encode %{
9562 __ sarxq($dst$$Register, $src$$Address, $shift$$Register);
9563 %}
9564 ins_pipe(ialu_reg_mem);
9565 %}
9566
9567 // Logical Shift Right by 8-bit immediate
9568 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
9569 %{
9570 predicate(!UseAPX);
9571 match(Set dst (URShiftL dst shift));
9572 effect(KILL cr);
9573
9574 format %{ "shrq $dst, $shift" %}
9575 ins_encode %{
9576 __ shrq($dst$$Register, $shift$$constant);
9577 %}
9578 ins_pipe(ialu_reg);
9579 %}
9580
9581 // Logical Shift Right by 8-bit immediate
9582 instruct shrL_rReg_imm_ndd(rRegL dst, rRegL src, immI8 shift, rFlagsReg cr)
9583 %{
9584 predicate(UseAPX);
9585 match(Set dst (URShiftL src shift));
9586 effect(KILL cr);
9587
9588 format %{ "eshrq $dst, $src, $shift\t# long (ndd)" %}
9589 ins_encode %{
9590 __ eshrq($dst$$Register, $src$$Register, $shift$$constant, false);
9591 %}
9592 ins_pipe(ialu_reg);
9593 %}
9594
9595 instruct shrL_rReg_mem_imm_ndd(rRegL dst, memory src, immI8 shift, rFlagsReg cr)
9596 %{
9597 predicate(UseAPX);
9598 match(Set dst (URShiftL (LoadL src) shift));
9599 effect(KILL cr);
9600
9601 format %{ "eshrq $dst, $src, $shift\t# long (ndd)" %}
9602 ins_encode %{
9603 __ eshrq($dst$$Register, $src$$Address, $shift$$constant, false);
9604 %}
9605 ins_pipe(ialu_reg);
9606 %}
9607
9608 // Logical Shift Right by 8-bit immediate
9609 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9610 %{
9611 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9612 effect(KILL cr);
9613
9614 format %{ "shrq $dst, $shift" %}
9615 ins_encode %{
9616 __ shrq($dst$$Address, $shift$$constant);
9617 %}
9618 ins_pipe(ialu_mem_imm);
9619 %}
9620
9621 // Logical Shift Right by variable
9622 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9623 %{
9624 predicate(!VM_Version::supports_bmi2());
9625 match(Set dst (URShiftL dst shift));
9626 effect(KILL cr);
9627
9628 format %{ "shrq $dst, $shift" %}
9629 ins_encode %{
9630 __ shrq($dst$$Register);
9631 %}
9632 ins_pipe(ialu_reg_reg);
9633 %}
9634
9635 // Logical Shift Right by variable
9636 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9637 %{
9638 predicate(!VM_Version::supports_bmi2());
9639 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9640 effect(KILL cr);
9641
9642 format %{ "shrq $dst, $shift" %}
9643 ins_encode %{
9644 __ shrq($dst$$Address);
9645 %}
9646 ins_pipe(ialu_mem_reg);
9647 %}
9648
9649 instruct shrL_rReg_rReg(rRegL dst, rRegL src, rRegI shift)
9650 %{
9651 predicate(VM_Version::supports_bmi2());
9652 match(Set dst (URShiftL src shift));
9653
9654 format %{ "shrxq $dst, $src, $shift" %}
9655 ins_encode %{
9656 __ shrxq($dst$$Register, $src$$Register, $shift$$Register);
9657 %}
9658 ins_pipe(ialu_reg_reg);
9659 %}
9660
9661 instruct shrL_mem_rReg(rRegL dst, memory src, rRegI shift)
9662 %{
9663 predicate(VM_Version::supports_bmi2());
9664 match(Set dst (URShiftL (LoadL src) shift));
9665 ins_cost(175);
9666 format %{ "shrxq $dst, $src, $shift" %}
9667 ins_encode %{
9668 __ shrxq($dst$$Register, $src$$Address, $shift$$Register);
9669 %}
9670 ins_pipe(ialu_reg_mem);
9671 %}
9672
9673 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
9674 // This idiom is used by the compiler for the i2b bytecode.
9675 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
9676 %{
9677 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
9678
9679 format %{ "movsbl $dst, $src\t# i2b" %}
9680 ins_encode %{
9681 __ movsbl($dst$$Register, $src$$Register);
9682 %}
9683 ins_pipe(ialu_reg_reg);
9684 %}
9685
9686 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
9687 // This idiom is used by the compiler the i2s bytecode.
9688 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
9689 %{
9690 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
9691
9692 format %{ "movswl $dst, $src\t# i2s" %}
9693 ins_encode %{
9694 __ movswl($dst$$Register, $src$$Register);
9695 %}
9696 ins_pipe(ialu_reg_reg);
9697 %}
9698
9699 // ROL/ROR instructions
9700
9701 // Rotate left by constant.
9702 instruct rolI_immI8_legacy(rRegI dst, immI8 shift, rFlagsReg cr)
9703 %{
9704 predicate(!VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
9705 match(Set dst (RotateLeft dst shift));
9706 effect(KILL cr);
9707 format %{ "roll $dst, $shift" %}
9708 ins_encode %{
9709 __ roll($dst$$Register, $shift$$constant);
9710 %}
9711 ins_pipe(ialu_reg);
9712 %}
9713
9714 instruct rolI_immI8(rRegI dst, rRegI src, immI8 shift)
9715 %{
9716 predicate(!UseAPX && VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
9717 match(Set dst (RotateLeft src shift));
9718 format %{ "rolxl $dst, $src, $shift" %}
9719 ins_encode %{
9720 int shift = 32 - ($shift$$constant & 31);
9721 __ rorxl($dst$$Register, $src$$Register, shift);
9722 %}
9723 ins_pipe(ialu_reg_reg);
9724 %}
9725
9726 instruct rolI_mem_immI8(rRegI dst, memory src, immI8 shift)
9727 %{
9728 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
9729 match(Set dst (RotateLeft (LoadI src) shift));
9730 ins_cost(175);
9731 format %{ "rolxl $dst, $src, $shift" %}
9732 ins_encode %{
9733 int shift = 32 - ($shift$$constant & 31);
9734 __ rorxl($dst$$Register, $src$$Address, shift);
9735 %}
9736 ins_pipe(ialu_reg_mem);
9737 %}
9738
9739 // Rotate Left by variable
9740 instruct rolI_rReg_Var(rRegI dst, rcx_RegI shift, rFlagsReg cr)
9741 %{
9742 predicate(!UseAPX && n->bottom_type()->basic_type() == T_INT);
9743 match(Set dst (RotateLeft dst shift));
9744 effect(KILL cr);
9745 format %{ "roll $dst, $shift" %}
9746 ins_encode %{
9747 __ roll($dst$$Register);
9748 %}
9749 ins_pipe(ialu_reg_reg);
9750 %}
9751
9752 // Rotate Left by variable
9753 instruct rolI_rReg_Var_ndd(rRegI dst, rRegI src, rcx_RegI shift, rFlagsReg cr)
9754 %{
9755 predicate(UseAPX && n->bottom_type()->basic_type() == T_INT);
9756 match(Set dst (RotateLeft src shift));
9757 effect(KILL cr);
9758
9759 format %{ "eroll $dst, $src, $shift\t# rotate left (int ndd)" %}
9760 ins_encode %{
9761 __ eroll($dst$$Register, $src$$Register, false);
9762 %}
9763 ins_pipe(ialu_reg_reg);
9764 %}
9765
9766 // Rotate Right by constant.
9767 instruct rorI_immI8_legacy(rRegI dst, immI8 shift, rFlagsReg cr)
9768 %{
9769 predicate(!VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
9770 match(Set dst (RotateRight dst shift));
9771 effect(KILL cr);
9772 format %{ "rorl $dst, $shift" %}
9773 ins_encode %{
9774 __ rorl($dst$$Register, $shift$$constant);
9775 %}
9776 ins_pipe(ialu_reg);
9777 %}
9778
9779 // Rotate Right by constant.
9780 instruct rorI_immI8(rRegI dst, rRegI src, immI8 shift)
9781 %{
9782 predicate(!UseAPX && VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
9783 match(Set dst (RotateRight src shift));
9784 format %{ "rorxl $dst, $src, $shift" %}
9785 ins_encode %{
9786 __ rorxl($dst$$Register, $src$$Register, $shift$$constant);
9787 %}
9788 ins_pipe(ialu_reg_reg);
9789 %}
9790
9791 instruct rorI_mem_immI8(rRegI dst, memory src, immI8 shift)
9792 %{
9793 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
9794 match(Set dst (RotateRight (LoadI src) shift));
9795 ins_cost(175);
9796 format %{ "rorxl $dst, $src, $shift" %}
9797 ins_encode %{
9798 __ rorxl($dst$$Register, $src$$Address, $shift$$constant);
9799 %}
9800 ins_pipe(ialu_reg_mem);
9801 %}
9802
9803 // Rotate Right by variable
9804 instruct rorI_rReg_Var(rRegI dst, rcx_RegI shift, rFlagsReg cr)
9805 %{
9806 predicate(!UseAPX && n->bottom_type()->basic_type() == T_INT);
9807 match(Set dst (RotateRight dst shift));
9808 effect(KILL cr);
9809 format %{ "rorl $dst, $shift" %}
9810 ins_encode %{
9811 __ rorl($dst$$Register);
9812 %}
9813 ins_pipe(ialu_reg_reg);
9814 %}
9815
9816 // Rotate Right by variable
9817 instruct rorI_rReg_Var_ndd(rRegI dst, rRegI src, rcx_RegI shift, rFlagsReg cr)
9818 %{
9819 predicate(UseAPX && n->bottom_type()->basic_type() == T_INT);
9820 match(Set dst (RotateRight src shift));
9821 effect(KILL cr);
9822
9823 format %{ "erorl $dst, $src, $shift\t# rotate right(int ndd)" %}
9824 ins_encode %{
9825 __ erorl($dst$$Register, $src$$Register, false);
9826 %}
9827 ins_pipe(ialu_reg_reg);
9828 %}
9829
9830 // Rotate Left by constant.
9831 instruct rolL_immI8_legacy(rRegL dst, immI8 shift, rFlagsReg cr)
9832 %{
9833 predicate(!VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
9834 match(Set dst (RotateLeft dst shift));
9835 effect(KILL cr);
9836 format %{ "rolq $dst, $shift" %}
9837 ins_encode %{
9838 __ rolq($dst$$Register, $shift$$constant);
9839 %}
9840 ins_pipe(ialu_reg);
9841 %}
9842
9843 instruct rolL_immI8(rRegL dst, rRegL src, immI8 shift)
9844 %{
9845 predicate(!UseAPX && VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
9846 match(Set dst (RotateLeft src shift));
9847 format %{ "rolxq $dst, $src, $shift" %}
9848 ins_encode %{
9849 int shift = 64 - ($shift$$constant & 63);
9850 __ rorxq($dst$$Register, $src$$Register, shift);
9851 %}
9852 ins_pipe(ialu_reg_reg);
9853 %}
9854
9855 instruct rolL_mem_immI8(rRegL dst, memory src, immI8 shift)
9856 %{
9857 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
9858 match(Set dst (RotateLeft (LoadL src) shift));
9859 ins_cost(175);
9860 format %{ "rolxq $dst, $src, $shift" %}
9861 ins_encode %{
9862 int shift = 64 - ($shift$$constant & 63);
9863 __ rorxq($dst$$Register, $src$$Address, shift);
9864 %}
9865 ins_pipe(ialu_reg_mem);
9866 %}
9867
9868 // Rotate Left by variable
9869 instruct rolL_rReg_Var(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9870 %{
9871 predicate(!UseAPX && n->bottom_type()->basic_type() == T_LONG);
9872 match(Set dst (RotateLeft dst shift));
9873 effect(KILL cr);
9874 format %{ "rolq $dst, $shift" %}
9875 ins_encode %{
9876 __ rolq($dst$$Register);
9877 %}
9878 ins_pipe(ialu_reg_reg);
9879 %}
9880
9881 // Rotate Left by variable
9882 instruct rolL_rReg_Var_ndd(rRegL dst, rRegL src, rcx_RegI shift, rFlagsReg cr)
9883 %{
9884 predicate(UseAPX && n->bottom_type()->basic_type() == T_LONG);
9885 match(Set dst (RotateLeft src shift));
9886 effect(KILL cr);
9887
9888 format %{ "erolq $dst, $src, $shift\t# rotate left(long ndd)" %}
9889 ins_encode %{
9890 __ erolq($dst$$Register, $src$$Register, false);
9891 %}
9892 ins_pipe(ialu_reg_reg);
9893 %}
9894
9895 // Rotate Right by constant.
9896 instruct rorL_immI8_legacy(rRegL dst, immI8 shift, rFlagsReg cr)
9897 %{
9898 predicate(!VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
9899 match(Set dst (RotateRight dst shift));
9900 effect(KILL cr);
9901 format %{ "rorq $dst, $shift" %}
9902 ins_encode %{
9903 __ rorq($dst$$Register, $shift$$constant);
9904 %}
9905 ins_pipe(ialu_reg);
9906 %}
9907
9908 // Rotate Right by constant
9909 instruct rorL_immI8(rRegL dst, rRegL src, immI8 shift)
9910 %{
9911 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
9912 match(Set dst (RotateRight src shift));
9913 format %{ "rorxq $dst, $src, $shift" %}
9914 ins_encode %{
9915 __ rorxq($dst$$Register, $src$$Register, $shift$$constant);
9916 %}
9917 ins_pipe(ialu_reg_reg);
9918 %}
9919
9920 instruct rorL_mem_immI8(rRegL dst, memory src, immI8 shift)
9921 %{
9922 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
9923 match(Set dst (RotateRight (LoadL src) shift));
9924 ins_cost(175);
9925 format %{ "rorxq $dst, $src, $shift" %}
9926 ins_encode %{
9927 __ rorxq($dst$$Register, $src$$Address, $shift$$constant);
9928 %}
9929 ins_pipe(ialu_reg_mem);
9930 %}
9931
9932 // Rotate Right by variable
9933 instruct rorL_rReg_Var(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9934 %{
9935 predicate(!UseAPX && n->bottom_type()->basic_type() == T_LONG);
9936 match(Set dst (RotateRight dst shift));
9937 effect(KILL cr);
9938 format %{ "rorq $dst, $shift" %}
9939 ins_encode %{
9940 __ rorq($dst$$Register);
9941 %}
9942 ins_pipe(ialu_reg_reg);
9943 %}
9944
9945 // Rotate Right by variable
9946 instruct rorL_rReg_Var_ndd(rRegL dst, rRegL src, rcx_RegI shift, rFlagsReg cr)
9947 %{
9948 predicate(UseAPX && n->bottom_type()->basic_type() == T_LONG);
9949 match(Set dst (RotateRight src shift));
9950 effect(KILL cr);
9951
9952 format %{ "erorq $dst, $src, $shift\t# rotate right(long ndd)" %}
9953 ins_encode %{
9954 __ erorq($dst$$Register, $src$$Register, false);
9955 %}
9956 ins_pipe(ialu_reg_reg);
9957 %}
9958
9959 //----------------------------- CompressBits/ExpandBits ------------------------
9960
9961 instruct compressBitsL_reg(rRegL dst, rRegL src, rRegL mask) %{
9962 predicate(n->bottom_type()->isa_long());
9963 match(Set dst (CompressBits src mask));
9964 format %{ "pextq $dst, $src, $mask\t! parallel bit extract" %}
9965 ins_encode %{
9966 __ pextq($dst$$Register, $src$$Register, $mask$$Register);
9967 %}
9968 ins_pipe( pipe_slow );
9969 %}
9970
9971 instruct expandBitsL_reg(rRegL dst, rRegL src, rRegL mask) %{
9972 predicate(n->bottom_type()->isa_long());
9973 match(Set dst (ExpandBits src mask));
9974 format %{ "pdepq $dst, $src, $mask\t! parallel bit deposit" %}
9975 ins_encode %{
9976 __ pdepq($dst$$Register, $src$$Register, $mask$$Register);
9977 %}
9978 ins_pipe( pipe_slow );
9979 %}
9980
9981 instruct compressBitsL_mem(rRegL dst, rRegL src, memory mask) %{
9982 predicate(n->bottom_type()->isa_long());
9983 match(Set dst (CompressBits src (LoadL mask)));
9984 format %{ "pextq $dst, $src, $mask\t! parallel bit extract" %}
9985 ins_encode %{
9986 __ pextq($dst$$Register, $src$$Register, $mask$$Address);
9987 %}
9988 ins_pipe( pipe_slow );
9989 %}
9990
9991 instruct expandBitsL_mem(rRegL dst, rRegL src, memory mask) %{
9992 predicate(n->bottom_type()->isa_long());
9993 match(Set dst (ExpandBits src (LoadL mask)));
9994 format %{ "pdepq $dst, $src, $mask\t! parallel bit deposit" %}
9995 ins_encode %{
9996 __ pdepq($dst$$Register, $src$$Register, $mask$$Address);
9997 %}
9998 ins_pipe( pipe_slow );
9999 %}
10000
10001
10002 // Logical Instructions
10003
10004 // Integer Logical Instructions
10005
10006 // And Instructions
10007 // And Register with Register
10008 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
10009 %{
10010 predicate(!UseAPX);
10011 match(Set dst (AndI dst src));
10012 effect(KILL cr);
10013 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10014
10015 format %{ "andl $dst, $src\t# int" %}
10016 ins_encode %{
10017 __ andl($dst$$Register, $src$$Register);
10018 %}
10019 ins_pipe(ialu_reg_reg);
10020 %}
10021
10022 // And Register with Register using New Data Destination (NDD)
10023 instruct andI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
10024 %{
10025 predicate(UseAPX);
10026 match(Set dst (AndI src1 src2));
10027 effect(KILL cr);
10028 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10029
10030 format %{ "eandl $dst, $src1, $src2\t# int ndd" %}
10031 ins_encode %{
10032 __ eandl($dst$$Register, $src1$$Register, $src2$$Register, false);
10033
10034 %}
10035 ins_pipe(ialu_reg_reg);
10036 %}
10037
10038 // And Register with Immediate 255
10039 instruct andI_rReg_imm255(rRegI dst, rRegI src, immI_255 mask)
10040 %{
10041 match(Set dst (AndI src mask));
10042
10043 format %{ "movzbl $dst, $src\t# int & 0xFF" %}
10044 ins_encode %{
10045 __ movzbl($dst$$Register, $src$$Register);
10046 %}
10047 ins_pipe(ialu_reg);
10048 %}
10049
10050 // And Register with Immediate 255 and promote to long
10051 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
10052 %{
10053 match(Set dst (ConvI2L (AndI src mask)));
10054
10055 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
10056 ins_encode %{
10057 __ movzbl($dst$$Register, $src$$Register);
10058 %}
10059 ins_pipe(ialu_reg);
10060 %}
10061
10062 // And Register with Immediate 65535
10063 instruct andI_rReg_imm65535(rRegI dst, rRegI src, immI_65535 mask)
10064 %{
10065 match(Set dst (AndI src mask));
10066
10067 format %{ "movzwl $dst, $src\t# int & 0xFFFF" %}
10068 ins_encode %{
10069 __ movzwl($dst$$Register, $src$$Register);
10070 %}
10071 ins_pipe(ialu_reg);
10072 %}
10073
10074 // And Register with Immediate 65535 and promote to long
10075 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
10076 %{
10077 match(Set dst (ConvI2L (AndI src mask)));
10078
10079 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
10080 ins_encode %{
10081 __ movzwl($dst$$Register, $src$$Register);
10082 %}
10083 ins_pipe(ialu_reg);
10084 %}
10085
10086 // Can skip int2long conversions after AND with small bitmask
10087 instruct convI2LAndI_reg_immIbitmask(rRegL dst, rRegI src, immI_Pow2M1 mask, rRegI tmp, rFlagsReg cr)
10088 %{
10089 predicate(VM_Version::supports_bmi2());
10090 ins_cost(125);
10091 effect(TEMP tmp, KILL cr);
10092 match(Set dst (ConvI2L (AndI src mask)));
10093 format %{ "bzhiq $dst, $src, $mask \t# using $tmp as TEMP, int & immI_Pow2M1 -> long" %}
10094 ins_encode %{
10095 __ movl($tmp$$Register, exact_log2($mask$$constant + 1));
10096 __ bzhiq($dst$$Register, $src$$Register, $tmp$$Register);
10097 %}
10098 ins_pipe(ialu_reg_reg);
10099 %}
10100
10101 // And Register with Immediate
10102 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
10103 %{
10104 predicate(!UseAPX);
10105 match(Set dst (AndI dst src));
10106 effect(KILL cr);
10107 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10108
10109 format %{ "andl $dst, $src\t# int" %}
10110 ins_encode %{
10111 __ andl($dst$$Register, $src$$constant);
10112 %}
10113 ins_pipe(ialu_reg);
10114 %}
10115
10116 instruct andI_rReg_rReg_imm_ndd(rRegI dst, rRegI src1, immI src2, rFlagsReg cr)
10117 %{
10118 predicate(UseAPX);
10119 match(Set dst (AndI src1 src2));
10120 effect(KILL cr);
10121 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10122
10123 format %{ "eandl $dst, $src1, $src2\t# int ndd" %}
10124 ins_encode %{
10125 __ eandl($dst$$Register, $src1$$Register, $src2$$constant, false);
10126 %}
10127 ins_pipe(ialu_reg);
10128 %}
10129
10130 instruct andI_rReg_mem_imm_ndd(rRegI dst, memory src1, immI src2, rFlagsReg cr)
10131 %{
10132 predicate(UseAPX);
10133 match(Set dst (AndI (LoadI src1) src2));
10134 effect(KILL cr);
10135 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10136
10137 format %{ "eandl $dst, $src1, $src2\t# int ndd" %}
10138 ins_encode %{
10139 __ eandl($dst$$Register, $src1$$Address, $src2$$constant, false);
10140 %}
10141 ins_pipe(ialu_reg);
10142 %}
10143
10144 // And Register with Memory
10145 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
10146 %{
10147 predicate(!UseAPX);
10148 match(Set dst (AndI dst (LoadI src)));
10149 effect(KILL cr);
10150 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10151
10152 ins_cost(150);
10153 format %{ "andl $dst, $src\t# int" %}
10154 ins_encode %{
10155 __ andl($dst$$Register, $src$$Address);
10156 %}
10157 ins_pipe(ialu_reg_mem);
10158 %}
10159
10160 instruct andI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr)
10161 %{
10162 predicate(UseAPX);
10163 match(Set dst (AndI src1 (LoadI src2)));
10164 effect(KILL cr);
10165 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10166
10167 ins_cost(150);
10168 format %{ "eandl $dst, $src1, $src2\t# int ndd" %}
10169 ins_encode %{
10170 __ eandl($dst$$Register, $src1$$Register, $src2$$Address, false);
10171 %}
10172 ins_pipe(ialu_reg_mem);
10173 %}
10174
10175 // And Memory with Register
10176 instruct andB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
10177 %{
10178 match(Set dst (StoreB dst (AndI (LoadB dst) src)));
10179 effect(KILL cr);
10180 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10181
10182 ins_cost(150);
10183 format %{ "andb $dst, $src\t# byte" %}
10184 ins_encode %{
10185 __ andb($dst$$Address, $src$$Register);
10186 %}
10187 ins_pipe(ialu_mem_reg);
10188 %}
10189
10190 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
10191 %{
10192 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
10193 effect(KILL cr);
10194 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10195
10196 ins_cost(150);
10197 format %{ "andl $dst, $src\t# int" %}
10198 ins_encode %{
10199 __ andl($dst$$Address, $src$$Register);
10200 %}
10201 ins_pipe(ialu_mem_reg);
10202 %}
10203
10204 // And Memory with Immediate
10205 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
10206 %{
10207 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
10208 effect(KILL cr);
10209 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10210
10211 ins_cost(125);
10212 format %{ "andl $dst, $src\t# int" %}
10213 ins_encode %{
10214 __ andl($dst$$Address, $src$$constant);
10215 %}
10216 ins_pipe(ialu_mem_imm);
10217 %}
10218
10219 // BMI1 instructions
10220 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
10221 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
10222 predicate(UseBMI1Instructions);
10223 effect(KILL cr);
10224 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10225
10226 ins_cost(125);
10227 format %{ "andnl $dst, $src1, $src2" %}
10228
10229 ins_encode %{
10230 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
10231 %}
10232 ins_pipe(ialu_reg_mem);
10233 %}
10234
10235 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
10236 match(Set dst (AndI (XorI src1 minus_1) src2));
10237 predicate(UseBMI1Instructions);
10238 effect(KILL cr);
10239 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10240
10241 format %{ "andnl $dst, $src1, $src2" %}
10242
10243 ins_encode %{
10244 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
10245 %}
10246 ins_pipe(ialu_reg);
10247 %}
10248
10249 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI_0 imm_zero, rFlagsReg cr) %{
10250 match(Set dst (AndI (SubI imm_zero src) src));
10251 predicate(UseBMI1Instructions);
10252 effect(KILL cr);
10253 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
10254
10255 format %{ "blsil $dst, $src" %}
10256
10257 ins_encode %{
10258 __ blsil($dst$$Register, $src$$Register);
10259 %}
10260 ins_pipe(ialu_reg);
10261 %}
10262
10263 instruct blsiI_rReg_mem(rRegI dst, memory src, immI_0 imm_zero, rFlagsReg cr) %{
10264 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
10265 predicate(UseBMI1Instructions);
10266 effect(KILL cr);
10267 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
10268
10269 ins_cost(125);
10270 format %{ "blsil $dst, $src" %}
10271
10272 ins_encode %{
10273 __ blsil($dst$$Register, $src$$Address);
10274 %}
10275 ins_pipe(ialu_reg_mem);
10276 %}
10277
10278 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
10279 %{
10280 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
10281 predicate(UseBMI1Instructions);
10282 effect(KILL cr);
10283 flag(PD::Flag_sets_sign_flag, PD::Flag_clears_zero_flag, PD::Flag_clears_overflow_flag);
10284
10285 ins_cost(125);
10286 format %{ "blsmskl $dst, $src" %}
10287
10288 ins_encode %{
10289 __ blsmskl($dst$$Register, $src$$Address);
10290 %}
10291 ins_pipe(ialu_reg_mem);
10292 %}
10293
10294 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
10295 %{
10296 match(Set dst (XorI (AddI src minus_1) src));
10297 predicate(UseBMI1Instructions);
10298 effect(KILL cr);
10299 flag(PD::Flag_sets_sign_flag, PD::Flag_clears_zero_flag, PD::Flag_clears_overflow_flag);
10300
10301 format %{ "blsmskl $dst, $src" %}
10302
10303 ins_encode %{
10304 __ blsmskl($dst$$Register, $src$$Register);
10305 %}
10306
10307 ins_pipe(ialu_reg);
10308 %}
10309
10310 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
10311 %{
10312 match(Set dst (AndI (AddI src minus_1) src) );
10313 predicate(UseBMI1Instructions);
10314 effect(KILL cr);
10315 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
10316
10317 format %{ "blsrl $dst, $src" %}
10318
10319 ins_encode %{
10320 __ blsrl($dst$$Register, $src$$Register);
10321 %}
10322
10323 ins_pipe(ialu_reg_mem);
10324 %}
10325
10326 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
10327 %{
10328 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
10329 predicate(UseBMI1Instructions);
10330 effect(KILL cr);
10331 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
10332
10333 ins_cost(125);
10334 format %{ "blsrl $dst, $src" %}
10335
10336 ins_encode %{
10337 __ blsrl($dst$$Register, $src$$Address);
10338 %}
10339
10340 ins_pipe(ialu_reg);
10341 %}
10342
10343 // Or Instructions
10344 // Or Register with Register
10345 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
10346 %{
10347 predicate(!UseAPX);
10348 match(Set dst (OrI dst src));
10349 effect(KILL cr);
10350 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10351
10352 format %{ "orl $dst, $src\t# int" %}
10353 ins_encode %{
10354 __ orl($dst$$Register, $src$$Register);
10355 %}
10356 ins_pipe(ialu_reg_reg);
10357 %}
10358
10359 // Or Register with Register using New Data Destination (NDD)
10360 instruct orI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
10361 %{
10362 predicate(UseAPX);
10363 match(Set dst (OrI src1 src2));
10364 effect(KILL cr);
10365 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10366
10367 format %{ "eorl $dst, $src1, $src2\t# int ndd" %}
10368 ins_encode %{
10369 __ eorl($dst$$Register, $src1$$Register, $src2$$Register, false);
10370 %}
10371 ins_pipe(ialu_reg_reg);
10372 %}
10373
10374 // Or Register with Immediate
10375 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
10376 %{
10377 predicate(!UseAPX);
10378 match(Set dst (OrI dst src));
10379 effect(KILL cr);
10380 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10381
10382 format %{ "orl $dst, $src\t# int" %}
10383 ins_encode %{
10384 __ orl($dst$$Register, $src$$constant);
10385 %}
10386 ins_pipe(ialu_reg);
10387 %}
10388
10389 instruct orI_rReg_rReg_imm_ndd(rRegI dst, rRegI src1, immI src2, rFlagsReg cr)
10390 %{
10391 predicate(UseAPX);
10392 match(Set dst (OrI src1 src2));
10393 effect(KILL cr);
10394 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10395
10396 format %{ "eorl $dst, $src1, $src2\t# int ndd" %}
10397 ins_encode %{
10398 __ eorl($dst$$Register, $src1$$Register, $src2$$constant, false);
10399 %}
10400 ins_pipe(ialu_reg);
10401 %}
10402
10403 instruct orI_rReg_imm_rReg_ndd(rRegI dst, immI src1, rRegI src2, rFlagsReg cr)
10404 %{
10405 predicate(UseAPX);
10406 match(Set dst (OrI src1 src2));
10407 effect(KILL cr);
10408 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10409
10410 format %{ "eorl $dst, $src2, $src1\t# int ndd" %}
10411 ins_encode %{
10412 __ eorl($dst$$Register, $src2$$Register, $src1$$constant, false);
10413 %}
10414 ins_pipe(ialu_reg);
10415 %}
10416
10417 instruct orI_rReg_mem_imm_ndd(rRegI dst, memory src1, immI src2, rFlagsReg cr)
10418 %{
10419 predicate(UseAPX);
10420 match(Set dst (OrI (LoadI src1) src2));
10421 effect(KILL cr);
10422 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10423
10424 format %{ "eorl $dst, $src1, $src2\t# int ndd" %}
10425 ins_encode %{
10426 __ eorl($dst$$Register, $src1$$Address, $src2$$constant, false);
10427 %}
10428 ins_pipe(ialu_reg);
10429 %}
10430
10431 // Or Register with Memory
10432 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
10433 %{
10434 predicate(!UseAPX);
10435 match(Set dst (OrI dst (LoadI src)));
10436 effect(KILL cr);
10437 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10438
10439 ins_cost(150);
10440 format %{ "orl $dst, $src\t# int" %}
10441 ins_encode %{
10442 __ orl($dst$$Register, $src$$Address);
10443 %}
10444 ins_pipe(ialu_reg_mem);
10445 %}
10446
10447 instruct orI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr)
10448 %{
10449 predicate(UseAPX);
10450 match(Set dst (OrI src1 (LoadI src2)));
10451 effect(KILL cr);
10452 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10453
10454 ins_cost(150);
10455 format %{ "eorl $dst, $src1, $src2\t# int ndd" %}
10456 ins_encode %{
10457 __ eorl($dst$$Register, $src1$$Register, $src2$$Address, false);
10458 %}
10459 ins_pipe(ialu_reg_mem);
10460 %}
10461
10462 // Or Memory with Register
10463 instruct orB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
10464 %{
10465 match(Set dst (StoreB dst (OrI (LoadB dst) src)));
10466 effect(KILL cr);
10467 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10468
10469 ins_cost(150);
10470 format %{ "orb $dst, $src\t# byte" %}
10471 ins_encode %{
10472 __ orb($dst$$Address, $src$$Register);
10473 %}
10474 ins_pipe(ialu_mem_reg);
10475 %}
10476
10477 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
10478 %{
10479 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
10480 effect(KILL cr);
10481 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10482
10483 ins_cost(150);
10484 format %{ "orl $dst, $src\t# int" %}
10485 ins_encode %{
10486 __ orl($dst$$Address, $src$$Register);
10487 %}
10488 ins_pipe(ialu_mem_reg);
10489 %}
10490
10491 // Or Memory with Immediate
10492 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
10493 %{
10494 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
10495 effect(KILL cr);
10496 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10497
10498 ins_cost(125);
10499 format %{ "orl $dst, $src\t# int" %}
10500 ins_encode %{
10501 __ orl($dst$$Address, $src$$constant);
10502 %}
10503 ins_pipe(ialu_mem_imm);
10504 %}
10505
10506 // Xor Instructions
10507 // Xor Register with Register
10508 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
10509 %{
10510 predicate(!UseAPX);
10511 match(Set dst (XorI dst src));
10512 effect(KILL cr);
10513 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10514
10515 format %{ "xorl $dst, $src\t# int" %}
10516 ins_encode %{
10517 __ xorl($dst$$Register, $src$$Register);
10518 %}
10519 ins_pipe(ialu_reg_reg);
10520 %}
10521
10522 // Xor Register with Register using New Data Destination (NDD)
10523 instruct xorI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
10524 %{
10525 predicate(UseAPX);
10526 match(Set dst (XorI src1 src2));
10527 effect(KILL cr);
10528 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10529
10530 format %{ "exorl $dst, $src1, $src2\t# int ndd" %}
10531 ins_encode %{
10532 __ exorl($dst$$Register, $src1$$Register, $src2$$Register, false);
10533 %}
10534 ins_pipe(ialu_reg_reg);
10535 %}
10536
10537 // Xor Register with Immediate -1
10538 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm)
10539 %{
10540 predicate(!UseAPX);
10541 match(Set dst (XorI dst imm));
10542
10543 format %{ "notl $dst" %}
10544 ins_encode %{
10545 __ notl($dst$$Register);
10546 %}
10547 ins_pipe(ialu_reg);
10548 %}
10549
10550 instruct xorI_rReg_im1_ndd(rRegI dst, rRegI src, immI_M1 imm)
10551 %{
10552 match(Set dst (XorI src imm));
10553 predicate(UseAPX);
10554
10555 format %{ "enotl $dst, $src" %}
10556 ins_encode %{
10557 __ enotl($dst$$Register, $src$$Register);
10558 %}
10559 ins_pipe(ialu_reg);
10560 %}
10561
10562 // Xor Register with Immediate
10563 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
10564 %{
10565 predicate(!UseAPX);
10566 match(Set dst (XorI dst src));
10567 effect(KILL cr);
10568 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10569
10570 format %{ "xorl $dst, $src\t# int" %}
10571 ins_encode %{
10572 __ xorl($dst$$Register, $src$$constant);
10573 %}
10574 ins_pipe(ialu_reg);
10575 %}
10576
10577 instruct xorI_rReg_rReg_imm_ndd(rRegI dst, rRegI src1, immI src2, rFlagsReg cr)
10578 %{
10579 predicate(UseAPX);
10580 match(Set dst (XorI src1 src2));
10581 effect(KILL cr);
10582 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10583
10584 format %{ "exorl $dst, $src1, $src2\t# int ndd" %}
10585 ins_encode %{
10586 __ exorl($dst$$Register, $src1$$Register, $src2$$constant, false);
10587 %}
10588 ins_pipe(ialu_reg);
10589 %}
10590
10591 // Xor Memory with Immediate
10592 instruct xorI_rReg_mem_imm_ndd(rRegI dst, memory src1, immI src2, rFlagsReg cr)
10593 %{
10594 predicate(UseAPX);
10595 match(Set dst (XorI (LoadI src1) src2));
10596 effect(KILL cr);
10597 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10598
10599 format %{ "exorl $dst, $src1, $src2\t# int ndd" %}
10600 ins_encode %{
10601 __ exorl($dst$$Register, $src1$$Address, $src2$$constant, false);
10602 %}
10603 ins_pipe(ialu_reg);
10604 %}
10605
10606 // Xor Register with Memory
10607 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
10608 %{
10609 predicate(!UseAPX);
10610 match(Set dst (XorI dst (LoadI src)));
10611 effect(KILL cr);
10612 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10613
10614 ins_cost(150);
10615 format %{ "xorl $dst, $src\t# int" %}
10616 ins_encode %{
10617 __ xorl($dst$$Register, $src$$Address);
10618 %}
10619 ins_pipe(ialu_reg_mem);
10620 %}
10621
10622 instruct xorI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr)
10623 %{
10624 predicate(UseAPX);
10625 match(Set dst (XorI src1 (LoadI src2)));
10626 effect(KILL cr);
10627 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10628
10629 ins_cost(150);
10630 format %{ "exorl $dst, $src1, $src2\t# int ndd" %}
10631 ins_encode %{
10632 __ exorl($dst$$Register, $src1$$Register, $src2$$Address, false);
10633 %}
10634 ins_pipe(ialu_reg_mem);
10635 %}
10636
10637 instruct xorI_rReg_mem_rReg_ndd(rRegI dst, memory src1, rRegI src2, rFlagsReg cr)
10638 %{
10639 predicate(UseAPX);
10640 match(Set dst (XorI (LoadI src1) src2));
10641 effect(KILL cr);
10642 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10643
10644 ins_cost(150);
10645 format %{ "exorl $dst, $src1, $src2\t# int ndd" %}
10646 ins_encode %{
10647 __ exorl($dst$$Register, $src1$$Address, $src2$$Register, false);
10648 %}
10649 ins_pipe(ialu_reg_mem);
10650 %}
10651
10652 // Xor Memory with Register
10653 instruct xorB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
10654 %{
10655 match(Set dst (StoreB dst (XorI (LoadB dst) src)));
10656 effect(KILL cr);
10657 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10658
10659 ins_cost(150);
10660 format %{ "xorb $dst, $src\t# byte" %}
10661 ins_encode %{
10662 __ xorb($dst$$Address, $src$$Register);
10663 %}
10664 ins_pipe(ialu_mem_reg);
10665 %}
10666
10667 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
10668 %{
10669 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
10670 effect(KILL cr);
10671 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10672
10673 ins_cost(150);
10674 format %{ "xorl $dst, $src\t# int" %}
10675 ins_encode %{
10676 __ xorl($dst$$Address, $src$$Register);
10677 %}
10678 ins_pipe(ialu_mem_reg);
10679 %}
10680
10681 // Xor Memory with Immediate
10682 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
10683 %{
10684 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
10685 effect(KILL cr);
10686 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10687
10688 ins_cost(125);
10689 format %{ "xorl $dst, $src\t# int" %}
10690 ins_encode %{
10691 __ xorl($dst$$Address, $src$$constant);
10692 %}
10693 ins_pipe(ialu_mem_imm);
10694 %}
10695
10696
10697 // Long Logical Instructions
10698
10699 // And Instructions
10700 // And Register with Register
10701 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
10702 %{
10703 predicate(!UseAPX);
10704 match(Set dst (AndL dst src));
10705 effect(KILL cr);
10706 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10707
10708 format %{ "andq $dst, $src\t# long" %}
10709 ins_encode %{
10710 __ andq($dst$$Register, $src$$Register);
10711 %}
10712 ins_pipe(ialu_reg_reg);
10713 %}
10714
10715 // And Register with Register using New Data Destination (NDD)
10716 instruct andL_rReg_ndd(rRegL dst, rRegL src1, rRegL src2, rFlagsReg cr)
10717 %{
10718 predicate(UseAPX);
10719 match(Set dst (AndL src1 src2));
10720 effect(KILL cr);
10721 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10722
10723 format %{ "eandq $dst, $src1, $src2\t# long ndd" %}
10724 ins_encode %{
10725 __ eandq($dst$$Register, $src1$$Register, $src2$$Register, false);
10726
10727 %}
10728 ins_pipe(ialu_reg_reg);
10729 %}
10730
10731 // And Register with Immediate 255
10732 instruct andL_rReg_imm255(rRegL dst, rRegL src, immL_255 mask)
10733 %{
10734 match(Set dst (AndL src mask));
10735
10736 format %{ "movzbl $dst, $src\t# long & 0xFF" %}
10737 ins_encode %{
10738 // movzbl zeroes out the upper 32-bit and does not need REX.W
10739 __ movzbl($dst$$Register, $src$$Register);
10740 %}
10741 ins_pipe(ialu_reg);
10742 %}
10743
10744 // And Register with Immediate 65535
10745 instruct andL_rReg_imm65535(rRegL dst, rRegL src, immL_65535 mask)
10746 %{
10747 match(Set dst (AndL src mask));
10748
10749 format %{ "movzwl $dst, $src\t# long & 0xFFFF" %}
10750 ins_encode %{
10751 // movzwl zeroes out the upper 32-bit and does not need REX.W
10752 __ movzwl($dst$$Register, $src$$Register);
10753 %}
10754 ins_pipe(ialu_reg);
10755 %}
10756
10757 // And Register with Immediate
10758 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
10759 %{
10760 predicate(!UseAPX);
10761 match(Set dst (AndL dst src));
10762 effect(KILL cr);
10763 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10764
10765 format %{ "andq $dst, $src\t# long" %}
10766 ins_encode %{
10767 __ andq($dst$$Register, $src$$constant);
10768 %}
10769 ins_pipe(ialu_reg);
10770 %}
10771
10772 instruct andL_rReg_rReg_imm_ndd(rRegL dst, rRegL src1, immL32 src2, rFlagsReg cr)
10773 %{
10774 predicate(UseAPX);
10775 match(Set dst (AndL src1 src2));
10776 effect(KILL cr);
10777 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10778
10779 format %{ "eandq $dst, $src1, $src2\t# long ndd" %}
10780 ins_encode %{
10781 __ eandq($dst$$Register, $src1$$Register, $src2$$constant, false);
10782 %}
10783 ins_pipe(ialu_reg);
10784 %}
10785
10786 instruct andL_rReg_mem_imm_ndd(rRegL dst, memory src1, immL32 src2, rFlagsReg cr)
10787 %{
10788 predicate(UseAPX);
10789 match(Set dst (AndL (LoadL src1) src2));
10790 effect(KILL cr);
10791 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10792
10793 format %{ "eandq $dst, $src1, $src2\t# long ndd" %}
10794 ins_encode %{
10795 __ eandq($dst$$Register, $src1$$Address, $src2$$constant, false);
10796 %}
10797 ins_pipe(ialu_reg);
10798 %}
10799
10800 // And Register with Memory
10801 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
10802 %{
10803 predicate(!UseAPX);
10804 match(Set dst (AndL dst (LoadL src)));
10805 effect(KILL cr);
10806 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10807
10808 ins_cost(150);
10809 format %{ "andq $dst, $src\t# long" %}
10810 ins_encode %{
10811 __ andq($dst$$Register, $src$$Address);
10812 %}
10813 ins_pipe(ialu_reg_mem);
10814 %}
10815
10816 instruct andL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr)
10817 %{
10818 predicate(UseAPX);
10819 match(Set dst (AndL src1 (LoadL src2)));
10820 effect(KILL cr);
10821 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10822
10823 ins_cost(150);
10824 format %{ "eandq $dst, $src1, $src2\t# long ndd" %}
10825 ins_encode %{
10826 __ eandq($dst$$Register, $src1$$Register, $src2$$Address, false);
10827 %}
10828 ins_pipe(ialu_reg_mem);
10829 %}
10830
10831 instruct andL_rReg_mem_rReg_ndd(rRegL dst, memory src1, rRegL src2, rFlagsReg cr)
10832 %{
10833 predicate(UseAPX);
10834 match(Set dst (AndL (LoadL src1) src2));
10835 effect(KILL cr);
10836 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10837
10838 ins_cost(150);
10839 format %{ "eandq $dst, $src1, $src2\t# long ndd" %}
10840 ins_encode %{
10841 __ eandq($dst$$Register, $src1$$Address, $src2$$Register, false);
10842 %}
10843 ins_pipe(ialu_reg_mem);
10844 %}
10845
10846 // And Memory with Register
10847 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
10848 %{
10849 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
10850 effect(KILL cr);
10851 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10852
10853 ins_cost(150);
10854 format %{ "andq $dst, $src\t# long" %}
10855 ins_encode %{
10856 __ andq($dst$$Address, $src$$Register);
10857 %}
10858 ins_pipe(ialu_mem_reg);
10859 %}
10860
10861 // And Memory with Immediate
10862 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10863 %{
10864 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
10865 effect(KILL cr);
10866 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10867
10868 ins_cost(125);
10869 format %{ "andq $dst, $src\t# long" %}
10870 ins_encode %{
10871 __ andq($dst$$Address, $src$$constant);
10872 %}
10873 ins_pipe(ialu_mem_imm);
10874 %}
10875
10876 instruct btrL_mem_imm(memory dst, immL_NotPow2 con, rFlagsReg cr)
10877 %{
10878 // con should be a pure 64-bit immediate given that not(con) is a power of 2
10879 // because AND/OR works well enough for 8/32-bit values.
10880 predicate(log2i_graceful(~n->in(3)->in(2)->get_long()) > 30);
10881
10882 match(Set dst (StoreL dst (AndL (LoadL dst) con)));
10883 effect(KILL cr);
10884
10885 ins_cost(125);
10886 format %{ "btrq $dst, log2(not($con))\t# long" %}
10887 ins_encode %{
10888 __ btrq($dst$$Address, log2i_exact((julong)~$con$$constant));
10889 %}
10890 ins_pipe(ialu_mem_imm);
10891 %}
10892
10893 // BMI1 instructions
10894 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
10895 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
10896 predicate(UseBMI1Instructions);
10897 effect(KILL cr);
10898 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10899
10900 ins_cost(125);
10901 format %{ "andnq $dst, $src1, $src2" %}
10902
10903 ins_encode %{
10904 __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
10905 %}
10906 ins_pipe(ialu_reg_mem);
10907 %}
10908
10909 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
10910 match(Set dst (AndL (XorL src1 minus_1) src2));
10911 predicate(UseBMI1Instructions);
10912 effect(KILL cr);
10913 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10914
10915 format %{ "andnq $dst, $src1, $src2" %}
10916
10917 ins_encode %{
10918 __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
10919 %}
10920 ins_pipe(ialu_reg_mem);
10921 %}
10922
10923 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
10924 match(Set dst (AndL (SubL imm_zero src) src));
10925 predicate(UseBMI1Instructions);
10926 effect(KILL cr);
10927 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
10928
10929 format %{ "blsiq $dst, $src" %}
10930
10931 ins_encode %{
10932 __ blsiq($dst$$Register, $src$$Register);
10933 %}
10934 ins_pipe(ialu_reg);
10935 %}
10936
10937 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
10938 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
10939 predicate(UseBMI1Instructions);
10940 effect(KILL cr);
10941 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
10942
10943 ins_cost(125);
10944 format %{ "blsiq $dst, $src" %}
10945
10946 ins_encode %{
10947 __ blsiq($dst$$Register, $src$$Address);
10948 %}
10949 ins_pipe(ialu_reg_mem);
10950 %}
10951
10952 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
10953 %{
10954 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
10955 predicate(UseBMI1Instructions);
10956 effect(KILL cr);
10957 flag(PD::Flag_sets_sign_flag, PD::Flag_clears_zero_flag, PD::Flag_clears_overflow_flag);
10958
10959 ins_cost(125);
10960 format %{ "blsmskq $dst, $src" %}
10961
10962 ins_encode %{
10963 __ blsmskq($dst$$Register, $src$$Address);
10964 %}
10965 ins_pipe(ialu_reg_mem);
10966 %}
10967
10968 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
10969 %{
10970 match(Set dst (XorL (AddL src minus_1) src));
10971 predicate(UseBMI1Instructions);
10972 effect(KILL cr);
10973 flag(PD::Flag_sets_sign_flag, PD::Flag_clears_zero_flag, PD::Flag_clears_overflow_flag);
10974
10975 format %{ "blsmskq $dst, $src" %}
10976
10977 ins_encode %{
10978 __ blsmskq($dst$$Register, $src$$Register);
10979 %}
10980
10981 ins_pipe(ialu_reg);
10982 %}
10983
10984 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
10985 %{
10986 match(Set dst (AndL (AddL src minus_1) src) );
10987 predicate(UseBMI1Instructions);
10988 effect(KILL cr);
10989 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
10990
10991 format %{ "blsrq $dst, $src" %}
10992
10993 ins_encode %{
10994 __ blsrq($dst$$Register, $src$$Register);
10995 %}
10996
10997 ins_pipe(ialu_reg);
10998 %}
10999
11000 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
11001 %{
11002 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
11003 predicate(UseBMI1Instructions);
11004 effect(KILL cr);
11005 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
11006
11007 ins_cost(125);
11008 format %{ "blsrq $dst, $src" %}
11009
11010 ins_encode %{
11011 __ blsrq($dst$$Register, $src$$Address);
11012 %}
11013
11014 ins_pipe(ialu_reg);
11015 %}
11016
11017 // Or Instructions
11018 // Or Register with Register
11019 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
11020 %{
11021 predicate(!UseAPX);
11022 match(Set dst (OrL dst src));
11023 effect(KILL cr);
11024 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11025
11026 format %{ "orq $dst, $src\t# long" %}
11027 ins_encode %{
11028 __ orq($dst$$Register, $src$$Register);
11029 %}
11030 ins_pipe(ialu_reg_reg);
11031 %}
11032
11033 // Or Register with Register using New Data Destination (NDD)
11034 instruct orL_rReg_ndd(rRegL dst, rRegL src1, rRegL src2, rFlagsReg cr)
11035 %{
11036 predicate(UseAPX);
11037 match(Set dst (OrL src1 src2));
11038 effect(KILL cr);
11039 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11040
11041 format %{ "eorq $dst, $src1, $src2\t# long ndd" %}
11042 ins_encode %{
11043 __ eorq($dst$$Register, $src1$$Register, $src2$$Register, false);
11044
11045 %}
11046 ins_pipe(ialu_reg_reg);
11047 %}
11048
11049 // Use any_RegP to match R15 (TLS register) without spilling.
11050 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
11051 match(Set dst (OrL dst (CastP2X src)));
11052 effect(KILL cr);
11053 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11054
11055 format %{ "orq $dst, $src\t# long" %}
11056 ins_encode %{
11057 __ orq($dst$$Register, $src$$Register);
11058 %}
11059 ins_pipe(ialu_reg_reg);
11060 %}
11061
11062 instruct orL_rReg_castP2X_ndd(rRegL dst, any_RegP src1, any_RegP src2, rFlagsReg cr) %{
11063 match(Set dst (OrL src1 (CastP2X src2)));
11064 effect(KILL cr);
11065 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11066
11067 format %{ "eorq $dst, $src1, $src2\t# long ndd" %}
11068 ins_encode %{
11069 __ eorq($dst$$Register, $src1$$Register, $src2$$Register, false);
11070 %}
11071 ins_pipe(ialu_reg_reg);
11072 %}
11073
11074 // Or Register with Immediate
11075 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
11076 %{
11077 predicate(!UseAPX);
11078 match(Set dst (OrL dst src));
11079 effect(KILL cr);
11080 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11081
11082 format %{ "orq $dst, $src\t# long" %}
11083 ins_encode %{
11084 __ orq($dst$$Register, $src$$constant);
11085 %}
11086 ins_pipe(ialu_reg);
11087 %}
11088
11089 instruct orL_rReg_rReg_imm_ndd(rRegL dst, rRegL src1, immL32 src2, rFlagsReg cr)
11090 %{
11091 predicate(UseAPX);
11092 match(Set dst (OrL src1 src2));
11093 effect(KILL cr);
11094 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11095
11096 format %{ "eorq $dst, $src1, $src2\t# long ndd" %}
11097 ins_encode %{
11098 __ eorq($dst$$Register, $src1$$Register, $src2$$constant, false);
11099 %}
11100 ins_pipe(ialu_reg);
11101 %}
11102
11103 instruct orL_rReg_imm_rReg_ndd(rRegL dst, immL32 src1, rRegL src2, rFlagsReg cr)
11104 %{
11105 predicate(UseAPX);
11106 match(Set dst (OrL src1 src2));
11107 effect(KILL cr);
11108 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11109
11110 format %{ "eorq $dst, $src2, $src1\t# long ndd" %}
11111 ins_encode %{
11112 __ eorq($dst$$Register, $src2$$Register, $src1$$constant, false);
11113 %}
11114 ins_pipe(ialu_reg);
11115 %}
11116
11117 // Or Memory with Immediate
11118 instruct orL_rReg_mem_imm_ndd(rRegL dst, memory src1, immL32 src2, rFlagsReg cr)
11119 %{
11120 predicate(UseAPX);
11121 match(Set dst (OrL (LoadL src1) src2));
11122 effect(KILL cr);
11123 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11124
11125 format %{ "eorq $dst, $src1, $src2\t# long ndd" %}
11126 ins_encode %{
11127 __ eorq($dst$$Register, $src1$$Address, $src2$$constant, false);
11128 %}
11129 ins_pipe(ialu_reg);
11130 %}
11131
11132 // Or Register with Memory
11133 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
11134 %{
11135 predicate(!UseAPX);
11136 match(Set dst (OrL dst (LoadL src)));
11137 effect(KILL cr);
11138 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11139
11140 ins_cost(150);
11141 format %{ "orq $dst, $src\t# long" %}
11142 ins_encode %{
11143 __ orq($dst$$Register, $src$$Address);
11144 %}
11145 ins_pipe(ialu_reg_mem);
11146 %}
11147
11148 instruct orL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr)
11149 %{
11150 predicate(UseAPX);
11151 match(Set dst (OrL src1 (LoadL src2)));
11152 effect(KILL cr);
11153 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11154
11155 ins_cost(150);
11156 format %{ "eorq $dst, $src1, $src2\t# long ndd" %}
11157 ins_encode %{
11158 __ eorq($dst$$Register, $src1$$Register, $src2$$Address, false);
11159 %}
11160 ins_pipe(ialu_reg_mem);
11161 %}
11162
11163 // Or Memory with Register
11164 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
11165 %{
11166 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
11167 effect(KILL cr);
11168 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11169
11170 ins_cost(150);
11171 format %{ "orq $dst, $src\t# long" %}
11172 ins_encode %{
11173 __ orq($dst$$Address, $src$$Register);
11174 %}
11175 ins_pipe(ialu_mem_reg);
11176 %}
11177
11178 // Or Memory with Immediate
11179 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
11180 %{
11181 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
11182 effect(KILL cr);
11183 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11184
11185 ins_cost(125);
11186 format %{ "orq $dst, $src\t# long" %}
11187 ins_encode %{
11188 __ orq($dst$$Address, $src$$constant);
11189 %}
11190 ins_pipe(ialu_mem_imm);
11191 %}
11192
11193 instruct btsL_mem_imm(memory dst, immL_Pow2 con, rFlagsReg cr)
11194 %{
11195 // con should be a pure 64-bit power of 2 immediate
11196 // because AND/OR works well enough for 8/32-bit values.
11197 predicate(log2i_graceful(n->in(3)->in(2)->get_long()) > 31);
11198
11199 match(Set dst (StoreL dst (OrL (LoadL dst) con)));
11200 effect(KILL cr);
11201
11202 ins_cost(125);
11203 format %{ "btsq $dst, log2($con)\t# long" %}
11204 ins_encode %{
11205 __ btsq($dst$$Address, log2i_exact((julong)$con$$constant));
11206 %}
11207 ins_pipe(ialu_mem_imm);
11208 %}
11209
11210 // Xor Instructions
11211 // Xor Register with Register
11212 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
11213 %{
11214 predicate(!UseAPX);
11215 match(Set dst (XorL dst src));
11216 effect(KILL cr);
11217 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11218
11219 format %{ "xorq $dst, $src\t# long" %}
11220 ins_encode %{
11221 __ xorq($dst$$Register, $src$$Register);
11222 %}
11223 ins_pipe(ialu_reg_reg);
11224 %}
11225
11226 // Xor Register with Register using New Data Destination (NDD)
11227 instruct xorL_rReg_ndd(rRegL dst, rRegL src1, rRegL src2, rFlagsReg cr)
11228 %{
11229 predicate(UseAPX);
11230 match(Set dst (XorL src1 src2));
11231 effect(KILL cr);
11232 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11233
11234 format %{ "exorq $dst, $src1, $src2\t# long ndd" %}
11235 ins_encode %{
11236 __ exorq($dst$$Register, $src1$$Register, $src2$$Register, false);
11237 %}
11238 ins_pipe(ialu_reg_reg);
11239 %}
11240
11241 // Xor Register with Immediate -1
11242 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm)
11243 %{
11244 predicate(!UseAPX);
11245 match(Set dst (XorL dst imm));
11246
11247 format %{ "notq $dst" %}
11248 ins_encode %{
11249 __ notq($dst$$Register);
11250 %}
11251 ins_pipe(ialu_reg);
11252 %}
11253
11254 instruct xorL_rReg_im1_ndd(rRegL dst,rRegL src, immL_M1 imm)
11255 %{
11256 predicate(UseAPX);
11257 match(Set dst (XorL src imm));
11258
11259 format %{ "enotq $dst, $src" %}
11260 ins_encode %{
11261 __ enotq($dst$$Register, $src$$Register);
11262 %}
11263 ins_pipe(ialu_reg);
11264 %}
11265
11266 // Xor Register with Immediate
11267 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
11268 %{
11269 predicate(!UseAPX);
11270 match(Set dst (XorL dst src));
11271 effect(KILL cr);
11272 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11273
11274 format %{ "xorq $dst, $src\t# long" %}
11275 ins_encode %{
11276 __ xorq($dst$$Register, $src$$constant);
11277 %}
11278 ins_pipe(ialu_reg);
11279 %}
11280
11281 instruct xorL_rReg_rReg_imm(rRegL dst, rRegL src1, immL32 src2, rFlagsReg cr)
11282 %{
11283 predicate(UseAPX);
11284 match(Set dst (XorL src1 src2));
11285 effect(KILL cr);
11286 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11287
11288 format %{ "exorq $dst, $src1, $src2\t# long ndd" %}
11289 ins_encode %{
11290 __ exorq($dst$$Register, $src1$$Register, $src2$$constant, false);
11291 %}
11292 ins_pipe(ialu_reg);
11293 %}
11294
11295 // Xor Memory with Immediate
11296 instruct xorL_rReg_mem_imm(rRegL dst, memory src1, immL32 src2, rFlagsReg cr)
11297 %{
11298 predicate(UseAPX);
11299 match(Set dst (XorL (LoadL src1) src2));
11300 effect(KILL cr);
11301 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11302
11303 format %{ "exorq $dst, $src1, $src2\t# long ndd" %}
11304 ins_encode %{
11305 __ exorq($dst$$Register, $src1$$Address, $src2$$constant, false);
11306 %}
11307 ins_pipe(ialu_reg);
11308 %}
11309
11310 // Xor Register with Memory
11311 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
11312 %{
11313 predicate(!UseAPX);
11314 match(Set dst (XorL dst (LoadL src)));
11315 effect(KILL cr);
11316 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11317
11318 ins_cost(150);
11319 format %{ "xorq $dst, $src\t# long" %}
11320 ins_encode %{
11321 __ xorq($dst$$Register, $src$$Address);
11322 %}
11323 ins_pipe(ialu_reg_mem);
11324 %}
11325
11326 instruct xorL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr)
11327 %{
11328 predicate(UseAPX);
11329 match(Set dst (XorL src1 (LoadL src2)));
11330 effect(KILL cr);
11331 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11332
11333 ins_cost(150);
11334 format %{ "exorq $dst, $src1, $src2\t# long ndd" %}
11335 ins_encode %{
11336 __ exorq($dst$$Register, $src1$$Register, $src2$$Address, false);
11337 %}
11338 ins_pipe(ialu_reg_mem);
11339 %}
11340
11341 instruct xorL_rReg_mem_rReg_ndd(rRegL dst, memory src1, rRegL src2, rFlagsReg cr)
11342 %{
11343 predicate(UseAPX);
11344 match(Set dst (XorL (LoadL src1) src2));
11345 effect(KILL cr);
11346 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11347
11348 ins_cost(150);
11349 format %{ "exorq $dst, $src1, $src2\t# long ndd" %}
11350 ins_encode %{
11351 __ exorq($dst$$Register, $src1$$Address, $src1$$Register, false);
11352 %}
11353 ins_pipe(ialu_reg_mem);
11354 %}
11355
11356 // Xor Memory with Register
11357 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
11358 %{
11359 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
11360 effect(KILL cr);
11361 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11362
11363 ins_cost(150);
11364 format %{ "xorq $dst, $src\t# long" %}
11365 ins_encode %{
11366 __ xorq($dst$$Address, $src$$Register);
11367 %}
11368 ins_pipe(ialu_mem_reg);
11369 %}
11370
11371 // Xor Memory with Immediate
11372 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
11373 %{
11374 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
11375 effect(KILL cr);
11376 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11377
11378 ins_cost(125);
11379 format %{ "xorq $dst, $src\t# long" %}
11380 ins_encode %{
11381 __ xorq($dst$$Address, $src$$constant);
11382 %}
11383 ins_pipe(ialu_mem_imm);
11384 %}
11385
11386 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
11387 %{
11388 match(Set dst (CmpLTMask p q));
11389 effect(KILL cr);
11390
11391 ins_cost(400);
11392 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
11393 "setcc $dst \t# emits setlt + movzbl or setzul for APX"
11394 "negl $dst" %}
11395 ins_encode %{
11396 __ cmpl($p$$Register, $q$$Register);
11397 __ setcc(Assembler::less, $dst$$Register);
11398 __ negl($dst$$Register);
11399 %}
11400 ins_pipe(pipe_slow);
11401 %}
11402
11403 instruct cmpLTMask0(rRegI dst, immI_0 zero, rFlagsReg cr)
11404 %{
11405 match(Set dst (CmpLTMask dst zero));
11406 effect(KILL cr);
11407
11408 ins_cost(100);
11409 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
11410 ins_encode %{
11411 __ sarl($dst$$Register, 31);
11412 %}
11413 ins_pipe(ialu_reg);
11414 %}
11415
11416 /* Better to save a register than avoid a branch */
11417 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
11418 %{
11419 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
11420 effect(KILL cr);
11421 ins_cost(300);
11422 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t"
11423 "jge done\n\t"
11424 "addl $p,$y\n"
11425 "done: " %}
11426 ins_encode %{
11427 Register Rp = $p$$Register;
11428 Register Rq = $q$$Register;
11429 Register Ry = $y$$Register;
11430 Label done;
11431 __ subl(Rp, Rq);
11432 __ jccb(Assembler::greaterEqual, done);
11433 __ addl(Rp, Ry);
11434 __ bind(done);
11435 %}
11436 ins_pipe(pipe_cmplt);
11437 %}
11438
11439 /* Better to save a register than avoid a branch */
11440 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
11441 %{
11442 match(Set y (AndI (CmpLTMask p q) y));
11443 effect(KILL cr);
11444
11445 ins_cost(300);
11446
11447 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t"
11448 "jlt done\n\t"
11449 "xorl $y, $y\n"
11450 "done: " %}
11451 ins_encode %{
11452 Register Rp = $p$$Register;
11453 Register Rq = $q$$Register;
11454 Register Ry = $y$$Register;
11455 Label done;
11456 __ cmpl(Rp, Rq);
11457 __ jccb(Assembler::less, done);
11458 __ xorl(Ry, Ry);
11459 __ bind(done);
11460 %}
11461 ins_pipe(pipe_cmplt);
11462 %}
11463
11464
11465 //---------- FP Instructions------------------------------------------------
11466
11467 // Really expensive, avoid
11468 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
11469 %{
11470 match(Set cr (CmpF src1 src2));
11471
11472 ins_cost(500);
11473 format %{ "ucomiss $src1, $src2\n\t"
11474 "jnp,s exit\n\t"
11475 "pushfq\t# saw NaN, set CF\n\t"
11476 "andq [rsp], #0xffffff2b\n\t"
11477 "popfq\n"
11478 "exit:" %}
11479 ins_encode %{
11480 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
11481 emit_cmpfp_fixup(masm);
11482 %}
11483 ins_pipe(pipe_slow);
11484 %}
11485
11486 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
11487 match(Set cr (CmpF src1 src2));
11488
11489 ins_cost(100);
11490 format %{ "ucomiss $src1, $src2" %}
11491 ins_encode %{
11492 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
11493 %}
11494 ins_pipe(pipe_slow);
11495 %}
11496
11497 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
11498 match(Set cr (CmpF src1 (LoadF src2)));
11499
11500 ins_cost(100);
11501 format %{ "ucomiss $src1, $src2" %}
11502 ins_encode %{
11503 __ ucomiss($src1$$XMMRegister, $src2$$Address);
11504 %}
11505 ins_pipe(pipe_slow);
11506 %}
11507
11508 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
11509 match(Set cr (CmpF src con));
11510 ins_cost(100);
11511 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
11512 ins_encode %{
11513 __ ucomiss($src$$XMMRegister, $constantaddress($con));
11514 %}
11515 ins_pipe(pipe_slow);
11516 %}
11517
11518 // Really expensive, avoid
11519 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
11520 %{
11521 match(Set cr (CmpD src1 src2));
11522
11523 ins_cost(500);
11524 format %{ "ucomisd $src1, $src2\n\t"
11525 "jnp,s exit\n\t"
11526 "pushfq\t# saw NaN, set CF\n\t"
11527 "andq [rsp], #0xffffff2b\n\t"
11528 "popfq\n"
11529 "exit:" %}
11530 ins_encode %{
11531 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
11532 emit_cmpfp_fixup(masm);
11533 %}
11534 ins_pipe(pipe_slow);
11535 %}
11536
11537 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
11538 match(Set cr (CmpD src1 src2));
11539
11540 ins_cost(100);
11541 format %{ "ucomisd $src1, $src2 test" %}
11542 ins_encode %{
11543 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
11544 %}
11545 ins_pipe(pipe_slow);
11546 %}
11547
11548 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
11549 match(Set cr (CmpD src1 (LoadD src2)));
11550
11551 ins_cost(100);
11552 format %{ "ucomisd $src1, $src2" %}
11553 ins_encode %{
11554 __ ucomisd($src1$$XMMRegister, $src2$$Address);
11555 %}
11556 ins_pipe(pipe_slow);
11557 %}
11558
11559 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
11560 match(Set cr (CmpD src con));
11561 ins_cost(100);
11562 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
11563 ins_encode %{
11564 __ ucomisd($src$$XMMRegister, $constantaddress($con));
11565 %}
11566 ins_pipe(pipe_slow);
11567 %}
11568
11569 // Compare into -1,0,1
11570 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
11571 %{
11572 match(Set dst (CmpF3 src1 src2));
11573 effect(KILL cr);
11574
11575 ins_cost(275);
11576 format %{ "ucomiss $src1, $src2\n\t"
11577 "movl $dst, #-1\n\t"
11578 "jp,s done\n\t"
11579 "jb,s done\n\t"
11580 "setne $dst\n\t"
11581 "movzbl $dst, $dst\n"
11582 "done:" %}
11583 ins_encode %{
11584 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
11585 emit_cmpfp3(masm, $dst$$Register);
11586 %}
11587 ins_pipe(pipe_slow);
11588 %}
11589
11590 // Compare into -1,0,1
11591 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
11592 %{
11593 match(Set dst (CmpF3 src1 (LoadF src2)));
11594 effect(KILL cr);
11595
11596 ins_cost(275);
11597 format %{ "ucomiss $src1, $src2\n\t"
11598 "movl $dst, #-1\n\t"
11599 "jp,s done\n\t"
11600 "jb,s done\n\t"
11601 "setne $dst\n\t"
11602 "movzbl $dst, $dst\n"
11603 "done:" %}
11604 ins_encode %{
11605 __ ucomiss($src1$$XMMRegister, $src2$$Address);
11606 emit_cmpfp3(masm, $dst$$Register);
11607 %}
11608 ins_pipe(pipe_slow);
11609 %}
11610
11611 // Compare into -1,0,1
11612 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
11613 match(Set dst (CmpF3 src con));
11614 effect(KILL cr);
11615
11616 ins_cost(275);
11617 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
11618 "movl $dst, #-1\n\t"
11619 "jp,s done\n\t"
11620 "jb,s done\n\t"
11621 "setne $dst\n\t"
11622 "movzbl $dst, $dst\n"
11623 "done:" %}
11624 ins_encode %{
11625 __ ucomiss($src$$XMMRegister, $constantaddress($con));
11626 emit_cmpfp3(masm, $dst$$Register);
11627 %}
11628 ins_pipe(pipe_slow);
11629 %}
11630
11631 // Compare into -1,0,1
11632 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
11633 %{
11634 match(Set dst (CmpD3 src1 src2));
11635 effect(KILL cr);
11636
11637 ins_cost(275);
11638 format %{ "ucomisd $src1, $src2\n\t"
11639 "movl $dst, #-1\n\t"
11640 "jp,s done\n\t"
11641 "jb,s done\n\t"
11642 "setne $dst\n\t"
11643 "movzbl $dst, $dst\n"
11644 "done:" %}
11645 ins_encode %{
11646 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
11647 emit_cmpfp3(masm, $dst$$Register);
11648 %}
11649 ins_pipe(pipe_slow);
11650 %}
11651
11652 // Compare into -1,0,1
11653 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
11654 %{
11655 match(Set dst (CmpD3 src1 (LoadD src2)));
11656 effect(KILL cr);
11657
11658 ins_cost(275);
11659 format %{ "ucomisd $src1, $src2\n\t"
11660 "movl $dst, #-1\n\t"
11661 "jp,s done\n\t"
11662 "jb,s done\n\t"
11663 "setne $dst\n\t"
11664 "movzbl $dst, $dst\n"
11665 "done:" %}
11666 ins_encode %{
11667 __ ucomisd($src1$$XMMRegister, $src2$$Address);
11668 emit_cmpfp3(masm, $dst$$Register);
11669 %}
11670 ins_pipe(pipe_slow);
11671 %}
11672
11673 // Compare into -1,0,1
11674 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
11675 match(Set dst (CmpD3 src con));
11676 effect(KILL cr);
11677
11678 ins_cost(275);
11679 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
11680 "movl $dst, #-1\n\t"
11681 "jp,s done\n\t"
11682 "jb,s done\n\t"
11683 "setne $dst\n\t"
11684 "movzbl $dst, $dst\n"
11685 "done:" %}
11686 ins_encode %{
11687 __ ucomisd($src$$XMMRegister, $constantaddress($con));
11688 emit_cmpfp3(masm, $dst$$Register);
11689 %}
11690 ins_pipe(pipe_slow);
11691 %}
11692
11693 //----------Arithmetic Conversion Instructions---------------------------------
11694
11695 instruct convF2D_reg_reg(regD dst, regF src)
11696 %{
11697 match(Set dst (ConvF2D src));
11698
11699 format %{ "cvtss2sd $dst, $src" %}
11700 ins_encode %{
11701 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
11702 %}
11703 ins_pipe(pipe_slow); // XXX
11704 %}
11705
11706 instruct convF2D_reg_mem(regD dst, memory src)
11707 %{
11708 predicate(UseAVX == 0);
11709 match(Set dst (ConvF2D (LoadF src)));
11710
11711 format %{ "cvtss2sd $dst, $src" %}
11712 ins_encode %{
11713 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
11714 %}
11715 ins_pipe(pipe_slow); // XXX
11716 %}
11717
11718 instruct convD2F_reg_reg(regF dst, regD src)
11719 %{
11720 match(Set dst (ConvD2F src));
11721
11722 format %{ "cvtsd2ss $dst, $src" %}
11723 ins_encode %{
11724 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
11725 %}
11726 ins_pipe(pipe_slow); // XXX
11727 %}
11728
11729 instruct convD2F_reg_mem(regF dst, memory src)
11730 %{
11731 predicate(UseAVX == 0);
11732 match(Set dst (ConvD2F (LoadD src)));
11733
11734 format %{ "cvtsd2ss $dst, $src" %}
11735 ins_encode %{
11736 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
11737 %}
11738 ins_pipe(pipe_slow); // XXX
11739 %}
11740
11741 // XXX do mem variants
11742 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
11743 %{
11744 match(Set dst (ConvF2I src));
11745 effect(KILL cr);
11746 format %{ "convert_f2i $dst, $src" %}
11747 ins_encode %{
11748 __ convertF2I(T_INT, T_FLOAT, $dst$$Register, $src$$XMMRegister);
11749 %}
11750 ins_pipe(pipe_slow);
11751 %}
11752
11753 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
11754 %{
11755 match(Set dst (ConvF2L src));
11756 effect(KILL cr);
11757 format %{ "convert_f2l $dst, $src"%}
11758 ins_encode %{
11759 __ convertF2I(T_LONG, T_FLOAT, $dst$$Register, $src$$XMMRegister);
11760 %}
11761 ins_pipe(pipe_slow);
11762 %}
11763
11764 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
11765 %{
11766 match(Set dst (ConvD2I src));
11767 effect(KILL cr);
11768 format %{ "convert_d2i $dst, $src"%}
11769 ins_encode %{
11770 __ convertF2I(T_INT, T_DOUBLE, $dst$$Register, $src$$XMMRegister);
11771 %}
11772 ins_pipe(pipe_slow);
11773 %}
11774
11775 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
11776 %{
11777 match(Set dst (ConvD2L src));
11778 effect(KILL cr);
11779 format %{ "convert_d2l $dst, $src"%}
11780 ins_encode %{
11781 __ convertF2I(T_LONG, T_DOUBLE, $dst$$Register, $src$$XMMRegister);
11782 %}
11783 ins_pipe(pipe_slow);
11784 %}
11785
11786 instruct round_double_reg(rRegL dst, regD src, rRegL rtmp, rcx_RegL rcx, rFlagsReg cr)
11787 %{
11788 match(Set dst (RoundD src));
11789 effect(TEMP dst, TEMP rtmp, TEMP rcx, KILL cr);
11790 format %{ "round_double $dst,$src \t! using $rtmp and $rcx as TEMP"%}
11791 ins_encode %{
11792 __ round_double($dst$$Register, $src$$XMMRegister, $rtmp$$Register, $rcx$$Register);
11793 %}
11794 ins_pipe(pipe_slow);
11795 %}
11796
11797 instruct round_float_reg(rRegI dst, regF src, rRegL rtmp, rcx_RegL rcx, rFlagsReg cr)
11798 %{
11799 match(Set dst (RoundF src));
11800 effect(TEMP dst, TEMP rtmp, TEMP rcx, KILL cr);
11801 format %{ "round_float $dst,$src" %}
11802 ins_encode %{
11803 __ round_float($dst$$Register, $src$$XMMRegister, $rtmp$$Register, $rcx$$Register);
11804 %}
11805 ins_pipe(pipe_slow);
11806 %}
11807
11808 instruct convI2F_reg_reg(vlRegF dst, rRegI src)
11809 %{
11810 predicate(!UseXmmI2F);
11811 match(Set dst (ConvI2F src));
11812
11813 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
11814 ins_encode %{
11815 if (UseAVX > 0) {
11816 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11817 }
11818 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11819 %}
11820 ins_pipe(pipe_slow); // XXX
11821 %}
11822
11823 instruct convI2F_reg_mem(regF dst, memory src)
11824 %{
11825 predicate(UseAVX == 0);
11826 match(Set dst (ConvI2F (LoadI src)));
11827
11828 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
11829 ins_encode %{
11830 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
11831 %}
11832 ins_pipe(pipe_slow); // XXX
11833 %}
11834
11835 instruct convI2D_reg_reg(vlRegD dst, rRegI src)
11836 %{
11837 predicate(!UseXmmI2D);
11838 match(Set dst (ConvI2D src));
11839
11840 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
11841 ins_encode %{
11842 if (UseAVX > 0) {
11843 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11844 }
11845 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
11846 %}
11847 ins_pipe(pipe_slow); // XXX
11848 %}
11849
11850 instruct convI2D_reg_mem(regD dst, memory src)
11851 %{
11852 predicate(UseAVX == 0);
11853 match(Set dst (ConvI2D (LoadI src)));
11854
11855 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
11856 ins_encode %{
11857 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
11858 %}
11859 ins_pipe(pipe_slow); // XXX
11860 %}
11861
11862 instruct convXI2F_reg(regF dst, rRegI src)
11863 %{
11864 predicate(UseXmmI2F);
11865 match(Set dst (ConvI2F src));
11866
11867 format %{ "movdl $dst, $src\n\t"
11868 "cvtdq2psl $dst, $dst\t# i2f" %}
11869 ins_encode %{
11870 __ movdl($dst$$XMMRegister, $src$$Register);
11871 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11872 %}
11873 ins_pipe(pipe_slow); // XXX
11874 %}
11875
11876 instruct convXI2D_reg(regD dst, rRegI src)
11877 %{
11878 predicate(UseXmmI2D);
11879 match(Set dst (ConvI2D src));
11880
11881 format %{ "movdl $dst, $src\n\t"
11882 "cvtdq2pdl $dst, $dst\t# i2d" %}
11883 ins_encode %{
11884 __ movdl($dst$$XMMRegister, $src$$Register);
11885 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11886 %}
11887 ins_pipe(pipe_slow); // XXX
11888 %}
11889
11890 instruct convL2F_reg_reg(vlRegF dst, rRegL src)
11891 %{
11892 match(Set dst (ConvL2F src));
11893
11894 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
11895 ins_encode %{
11896 if (UseAVX > 0) {
11897 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11898 }
11899 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
11900 %}
11901 ins_pipe(pipe_slow); // XXX
11902 %}
11903
11904 instruct convL2F_reg_mem(regF dst, memory src)
11905 %{
11906 predicate(UseAVX == 0);
11907 match(Set dst (ConvL2F (LoadL src)));
11908
11909 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
11910 ins_encode %{
11911 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
11912 %}
11913 ins_pipe(pipe_slow); // XXX
11914 %}
11915
11916 instruct convL2D_reg_reg(vlRegD dst, rRegL src)
11917 %{
11918 match(Set dst (ConvL2D src));
11919
11920 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
11921 ins_encode %{
11922 if (UseAVX > 0) {
11923 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11924 }
11925 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
11926 %}
11927 ins_pipe(pipe_slow); // XXX
11928 %}
11929
11930 instruct convL2D_reg_mem(regD dst, memory src)
11931 %{
11932 predicate(UseAVX == 0);
11933 match(Set dst (ConvL2D (LoadL src)));
11934
11935 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
11936 ins_encode %{
11937 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
11938 %}
11939 ins_pipe(pipe_slow); // XXX
11940 %}
11941
11942 instruct convI2L_reg_reg(rRegL dst, rRegI src)
11943 %{
11944 match(Set dst (ConvI2L src));
11945
11946 ins_cost(125);
11947 format %{ "movslq $dst, $src\t# i2l" %}
11948 ins_encode %{
11949 __ movslq($dst$$Register, $src$$Register);
11950 %}
11951 ins_pipe(ialu_reg_reg);
11952 %}
11953
11954 // Zero-extend convert int to long
11955 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
11956 %{
11957 match(Set dst (AndL (ConvI2L src) mask));
11958
11959 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
11960 ins_encode %{
11961 if ($dst$$reg != $src$$reg) {
11962 __ movl($dst$$Register, $src$$Register);
11963 }
11964 %}
11965 ins_pipe(ialu_reg_reg);
11966 %}
11967
11968 // Zero-extend convert int to long
11969 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
11970 %{
11971 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
11972
11973 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
11974 ins_encode %{
11975 __ movl($dst$$Register, $src$$Address);
11976 %}
11977 ins_pipe(ialu_reg_mem);
11978 %}
11979
11980 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
11981 %{
11982 match(Set dst (AndL src mask));
11983
11984 format %{ "movl $dst, $src\t# zero-extend long" %}
11985 ins_encode %{
11986 __ movl($dst$$Register, $src$$Register);
11987 %}
11988 ins_pipe(ialu_reg_reg);
11989 %}
11990
11991 instruct convL2I_reg_reg(rRegI dst, rRegL src)
11992 %{
11993 match(Set dst (ConvL2I src));
11994
11995 format %{ "movl $dst, $src\t# l2i" %}
11996 ins_encode %{
11997 __ movl($dst$$Register, $src$$Register);
11998 %}
11999 ins_pipe(ialu_reg_reg);
12000 %}
12001
12002
12003 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
12004 match(Set dst (MoveF2I src));
12005 effect(DEF dst, USE src);
12006
12007 ins_cost(125);
12008 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
12009 ins_encode %{
12010 __ movl($dst$$Register, Address(rsp, $src$$disp));
12011 %}
12012 ins_pipe(ialu_reg_mem);
12013 %}
12014
12015 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
12016 match(Set dst (MoveI2F src));
12017 effect(DEF dst, USE src);
12018
12019 ins_cost(125);
12020 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
12021 ins_encode %{
12022 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
12023 %}
12024 ins_pipe(pipe_slow);
12025 %}
12026
12027 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
12028 match(Set dst (MoveD2L src));
12029 effect(DEF dst, USE src);
12030
12031 ins_cost(125);
12032 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
12033 ins_encode %{
12034 __ movq($dst$$Register, Address(rsp, $src$$disp));
12035 %}
12036 ins_pipe(ialu_reg_mem);
12037 %}
12038
12039 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
12040 predicate(!UseXmmLoadAndClearUpper);
12041 match(Set dst (MoveL2D src));
12042 effect(DEF dst, USE src);
12043
12044 ins_cost(125);
12045 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
12046 ins_encode %{
12047 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
12048 %}
12049 ins_pipe(pipe_slow);
12050 %}
12051
12052 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
12053 predicate(UseXmmLoadAndClearUpper);
12054 match(Set dst (MoveL2D src));
12055 effect(DEF dst, USE src);
12056
12057 ins_cost(125);
12058 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
12059 ins_encode %{
12060 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
12061 %}
12062 ins_pipe(pipe_slow);
12063 %}
12064
12065
12066 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
12067 match(Set dst (MoveF2I src));
12068 effect(DEF dst, USE src);
12069
12070 ins_cost(95); // XXX
12071 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
12072 ins_encode %{
12073 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
12074 %}
12075 ins_pipe(pipe_slow);
12076 %}
12077
12078 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
12079 match(Set dst (MoveI2F src));
12080 effect(DEF dst, USE src);
12081
12082 ins_cost(100);
12083 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
12084 ins_encode %{
12085 __ movl(Address(rsp, $dst$$disp), $src$$Register);
12086 %}
12087 ins_pipe( ialu_mem_reg );
12088 %}
12089
12090 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
12091 match(Set dst (MoveD2L src));
12092 effect(DEF dst, USE src);
12093
12094 ins_cost(95); // XXX
12095 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
12096 ins_encode %{
12097 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
12098 %}
12099 ins_pipe(pipe_slow);
12100 %}
12101
12102 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
12103 match(Set dst (MoveL2D src));
12104 effect(DEF dst, USE src);
12105
12106 ins_cost(100);
12107 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
12108 ins_encode %{
12109 __ movq(Address(rsp, $dst$$disp), $src$$Register);
12110 %}
12111 ins_pipe(ialu_mem_reg);
12112 %}
12113
12114 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
12115 match(Set dst (MoveF2I src));
12116 effect(DEF dst, USE src);
12117 ins_cost(85);
12118 format %{ "movd $dst,$src\t# MoveF2I" %}
12119 ins_encode %{
12120 __ movdl($dst$$Register, $src$$XMMRegister);
12121 %}
12122 ins_pipe( pipe_slow );
12123 %}
12124
12125 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
12126 match(Set dst (MoveD2L src));
12127 effect(DEF dst, USE src);
12128 ins_cost(85);
12129 format %{ "movd $dst,$src\t# MoveD2L" %}
12130 ins_encode %{
12131 __ movdq($dst$$Register, $src$$XMMRegister);
12132 %}
12133 ins_pipe( pipe_slow );
12134 %}
12135
12136 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
12137 match(Set dst (MoveI2F src));
12138 effect(DEF dst, USE src);
12139 ins_cost(100);
12140 format %{ "movd $dst,$src\t# MoveI2F" %}
12141 ins_encode %{
12142 __ movdl($dst$$XMMRegister, $src$$Register);
12143 %}
12144 ins_pipe( pipe_slow );
12145 %}
12146
12147 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
12148 match(Set dst (MoveL2D src));
12149 effect(DEF dst, USE src);
12150 ins_cost(100);
12151 format %{ "movd $dst,$src\t# MoveL2D" %}
12152 ins_encode %{
12153 __ movdq($dst$$XMMRegister, $src$$Register);
12154 %}
12155 ins_pipe( pipe_slow );
12156 %}
12157
12158 // Fast clearing of an array
12159 // Small non-constant lenght ClearArray for non-AVX512 targets.
12160 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
12161 Universe dummy, rFlagsReg cr)
12162 %{
12163 predicate(!((ClearArrayNode*)n)->is_large() && (UseAVX <= 2));
12164 match(Set dummy (ClearArray cnt base));
12165 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
12166
12167 format %{ $$template
12168 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
12169 $$emit$$"cmp InitArrayShortSize,rcx\n\t"
12170 $$emit$$"jg LARGE\n\t"
12171 $$emit$$"dec rcx\n\t"
12172 $$emit$$"js DONE\t# Zero length\n\t"
12173 $$emit$$"mov rax,(rdi,rcx,8)\t# LOOP\n\t"
12174 $$emit$$"dec rcx\n\t"
12175 $$emit$$"jge LOOP\n\t"
12176 $$emit$$"jmp DONE\n\t"
12177 $$emit$$"# LARGE:\n\t"
12178 if (UseFastStosb) {
12179 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
12180 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--\n\t"
12181 } else if (UseXMMForObjInit) {
12182 $$emit$$"mov rdi,rax\n\t"
12183 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
12184 $$emit$$"jmpq L_zero_64_bytes\n\t"
12185 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
12186 $$emit$$"vmovdqu ymm0,(rax)\n\t"
12187 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
12188 $$emit$$"add 0x40,rax\n\t"
12189 $$emit$$"# L_zero_64_bytes:\n\t"
12190 $$emit$$"sub 0x8,rcx\n\t"
12191 $$emit$$"jge L_loop\n\t"
12192 $$emit$$"add 0x4,rcx\n\t"
12193 $$emit$$"jl L_tail\n\t"
12194 $$emit$$"vmovdqu ymm0,(rax)\n\t"
12195 $$emit$$"add 0x20,rax\n\t"
12196 $$emit$$"sub 0x4,rcx\n\t"
12197 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
12198 $$emit$$"add 0x4,rcx\n\t"
12199 $$emit$$"jle L_end\n\t"
12200 $$emit$$"dec rcx\n\t"
12201 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
12202 $$emit$$"vmovq xmm0,(rax)\n\t"
12203 $$emit$$"add 0x8,rax\n\t"
12204 $$emit$$"dec rcx\n\t"
12205 $$emit$$"jge L_sloop\n\t"
12206 $$emit$$"# L_end:\n\t"
12207 } else {
12208 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--\n\t"
12209 }
12210 $$emit$$"# DONE"
12211 %}
12212 ins_encode %{
12213 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
12214 $tmp$$XMMRegister, false, knoreg);
12215 %}
12216 ins_pipe(pipe_slow);
12217 %}
12218
12219 // Small non-constant length ClearArray for AVX512 targets.
12220 instruct rep_stos_evex(rcx_RegL cnt, rdi_RegP base, legRegD tmp, kReg ktmp, rax_RegI zero,
12221 Universe dummy, rFlagsReg cr)
12222 %{
12223 predicate(!((ClearArrayNode*)n)->is_large() && (UseAVX > 2));
12224 match(Set dummy (ClearArray cnt base));
12225 ins_cost(125);
12226 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, TEMP ktmp, KILL zero, KILL cr);
12227
12228 format %{ $$template
12229 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
12230 $$emit$$"cmp InitArrayShortSize,rcx\n\t"
12231 $$emit$$"jg LARGE\n\t"
12232 $$emit$$"dec rcx\n\t"
12233 $$emit$$"js DONE\t# Zero length\n\t"
12234 $$emit$$"mov rax,(rdi,rcx,8)\t# LOOP\n\t"
12235 $$emit$$"dec rcx\n\t"
12236 $$emit$$"jge LOOP\n\t"
12237 $$emit$$"jmp DONE\n\t"
12238 $$emit$$"# LARGE:\n\t"
12239 if (UseFastStosb) {
12240 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
12241 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--\n\t"
12242 } else if (UseXMMForObjInit) {
12243 $$emit$$"mov rdi,rax\n\t"
12244 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
12245 $$emit$$"jmpq L_zero_64_bytes\n\t"
12246 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
12247 $$emit$$"vmovdqu ymm0,(rax)\n\t"
12248 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
12249 $$emit$$"add 0x40,rax\n\t"
12250 $$emit$$"# L_zero_64_bytes:\n\t"
12251 $$emit$$"sub 0x8,rcx\n\t"
12252 $$emit$$"jge L_loop\n\t"
12253 $$emit$$"add 0x4,rcx\n\t"
12254 $$emit$$"jl L_tail\n\t"
12255 $$emit$$"vmovdqu ymm0,(rax)\n\t"
12256 $$emit$$"add 0x20,rax\n\t"
12257 $$emit$$"sub 0x4,rcx\n\t"
12258 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
12259 $$emit$$"add 0x4,rcx\n\t"
12260 $$emit$$"jle L_end\n\t"
12261 $$emit$$"dec rcx\n\t"
12262 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
12263 $$emit$$"vmovq xmm0,(rax)\n\t"
12264 $$emit$$"add 0x8,rax\n\t"
12265 $$emit$$"dec rcx\n\t"
12266 $$emit$$"jge L_sloop\n\t"
12267 $$emit$$"# L_end:\n\t"
12268 } else {
12269 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--\n\t"
12270 }
12271 $$emit$$"# DONE"
12272 %}
12273 ins_encode %{
12274 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
12275 $tmp$$XMMRegister, false, $ktmp$$KRegister);
12276 %}
12277 ins_pipe(pipe_slow);
12278 %}
12279
12280 // Large non-constant length ClearArray for non-AVX512 targets.
12281 instruct rep_stos_large(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
12282 Universe dummy, rFlagsReg cr)
12283 %{
12284 predicate((UseAVX <=2) && ((ClearArrayNode*)n)->is_large());
12285 match(Set dummy (ClearArray cnt base));
12286 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
12287
12288 format %{ $$template
12289 if (UseFastStosb) {
12290 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
12291 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
12292 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--"
12293 } else if (UseXMMForObjInit) {
12294 $$emit$$"mov rdi,rax\t# ClearArray:\n\t"
12295 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
12296 $$emit$$"jmpq L_zero_64_bytes\n\t"
12297 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
12298 $$emit$$"vmovdqu ymm0,(rax)\n\t"
12299 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
12300 $$emit$$"add 0x40,rax\n\t"
12301 $$emit$$"# L_zero_64_bytes:\n\t"
12302 $$emit$$"sub 0x8,rcx\n\t"
12303 $$emit$$"jge L_loop\n\t"
12304 $$emit$$"add 0x4,rcx\n\t"
12305 $$emit$$"jl L_tail\n\t"
12306 $$emit$$"vmovdqu ymm0,(rax)\n\t"
12307 $$emit$$"add 0x20,rax\n\t"
12308 $$emit$$"sub 0x4,rcx\n\t"
12309 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
12310 $$emit$$"add 0x4,rcx\n\t"
12311 $$emit$$"jle L_end\n\t"
12312 $$emit$$"dec rcx\n\t"
12313 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
12314 $$emit$$"vmovq xmm0,(rax)\n\t"
12315 $$emit$$"add 0x8,rax\n\t"
12316 $$emit$$"dec rcx\n\t"
12317 $$emit$$"jge L_sloop\n\t"
12318 $$emit$$"# L_end:\n\t"
12319 } else {
12320 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
12321 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--"
12322 }
12323 %}
12324 ins_encode %{
12325 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
12326 $tmp$$XMMRegister, true, knoreg);
12327 %}
12328 ins_pipe(pipe_slow);
12329 %}
12330
12331 // Large non-constant length ClearArray for AVX512 targets.
12332 instruct rep_stos_large_evex(rcx_RegL cnt, rdi_RegP base, legRegD tmp, kReg ktmp, rax_RegI zero,
12333 Universe dummy, rFlagsReg cr)
12334 %{
12335 predicate((UseAVX > 2) && ((ClearArrayNode*)n)->is_large());
12336 match(Set dummy (ClearArray cnt base));
12337 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, TEMP ktmp, KILL zero, KILL cr);
12338
12339 format %{ $$template
12340 if (UseFastStosb) {
12341 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
12342 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
12343 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--"
12344 } else if (UseXMMForObjInit) {
12345 $$emit$$"mov rdi,rax\t# ClearArray:\n\t"
12346 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
12347 $$emit$$"jmpq L_zero_64_bytes\n\t"
12348 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
12349 $$emit$$"vmovdqu ymm0,(rax)\n\t"
12350 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
12351 $$emit$$"add 0x40,rax\n\t"
12352 $$emit$$"# L_zero_64_bytes:\n\t"
12353 $$emit$$"sub 0x8,rcx\n\t"
12354 $$emit$$"jge L_loop\n\t"
12355 $$emit$$"add 0x4,rcx\n\t"
12356 $$emit$$"jl L_tail\n\t"
12357 $$emit$$"vmovdqu ymm0,(rax)\n\t"
12358 $$emit$$"add 0x20,rax\n\t"
12359 $$emit$$"sub 0x4,rcx\n\t"
12360 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
12361 $$emit$$"add 0x4,rcx\n\t"
12362 $$emit$$"jle L_end\n\t"
12363 $$emit$$"dec rcx\n\t"
12364 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
12365 $$emit$$"vmovq xmm0,(rax)\n\t"
12366 $$emit$$"add 0x8,rax\n\t"
12367 $$emit$$"dec rcx\n\t"
12368 $$emit$$"jge L_sloop\n\t"
12369 $$emit$$"# L_end:\n\t"
12370 } else {
12371 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
12372 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--"
12373 }
12374 %}
12375 ins_encode %{
12376 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
12377 $tmp$$XMMRegister, true, $ktmp$$KRegister);
12378 %}
12379 ins_pipe(pipe_slow);
12380 %}
12381
12382 // Small constant length ClearArray for AVX512 targets.
12383 instruct rep_stos_im(immL cnt, rRegP base, regD tmp, rRegI zero, kReg ktmp, Universe dummy, rFlagsReg cr)
12384 %{
12385 predicate(!((ClearArrayNode*)n)->is_large() && (MaxVectorSize >= 32) && VM_Version::supports_avx512vl());
12386 match(Set dummy (ClearArray cnt base));
12387 ins_cost(100);
12388 effect(TEMP tmp, TEMP zero, TEMP ktmp, KILL cr);
12389 format %{ "clear_mem_imm $base , $cnt \n\t" %}
12390 ins_encode %{
12391 __ clear_mem($base$$Register, $cnt$$constant, $zero$$Register, $tmp$$XMMRegister, $ktmp$$KRegister);
12392 %}
12393 ins_pipe(pipe_slow);
12394 %}
12395
12396 instruct string_compareL(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
12397 rax_RegI result, legRegD tmp1, rFlagsReg cr)
12398 %{
12399 predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
12400 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12401 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12402
12403 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
12404 ins_encode %{
12405 __ string_compare($str1$$Register, $str2$$Register,
12406 $cnt1$$Register, $cnt2$$Register, $result$$Register,
12407 $tmp1$$XMMRegister, StrIntrinsicNode::LL, knoreg);
12408 %}
12409 ins_pipe( pipe_slow );
12410 %}
12411
12412 instruct string_compareL_evex(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
12413 rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
12414 %{
12415 predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
12416 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12417 effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12418
12419 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
12420 ins_encode %{
12421 __ string_compare($str1$$Register, $str2$$Register,
12422 $cnt1$$Register, $cnt2$$Register, $result$$Register,
12423 $tmp1$$XMMRegister, StrIntrinsicNode::LL, $ktmp$$KRegister);
12424 %}
12425 ins_pipe( pipe_slow );
12426 %}
12427
12428 instruct string_compareU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
12429 rax_RegI result, legRegD tmp1, rFlagsReg cr)
12430 %{
12431 predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
12432 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12433 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12434
12435 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
12436 ins_encode %{
12437 __ string_compare($str1$$Register, $str2$$Register,
12438 $cnt1$$Register, $cnt2$$Register, $result$$Register,
12439 $tmp1$$XMMRegister, StrIntrinsicNode::UU, knoreg);
12440 %}
12441 ins_pipe( pipe_slow );
12442 %}
12443
12444 instruct string_compareU_evex(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
12445 rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
12446 %{
12447 predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
12448 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12449 effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12450
12451 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
12452 ins_encode %{
12453 __ string_compare($str1$$Register, $str2$$Register,
12454 $cnt1$$Register, $cnt2$$Register, $result$$Register,
12455 $tmp1$$XMMRegister, StrIntrinsicNode::UU, $ktmp$$KRegister);
12456 %}
12457 ins_pipe( pipe_slow );
12458 %}
12459
12460 instruct string_compareLU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
12461 rax_RegI result, legRegD tmp1, rFlagsReg cr)
12462 %{
12463 predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
12464 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12465 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12466
12467 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
12468 ins_encode %{
12469 __ string_compare($str1$$Register, $str2$$Register,
12470 $cnt1$$Register, $cnt2$$Register, $result$$Register,
12471 $tmp1$$XMMRegister, StrIntrinsicNode::LU, knoreg);
12472 %}
12473 ins_pipe( pipe_slow );
12474 %}
12475
12476 instruct string_compareLU_evex(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
12477 rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
12478 %{
12479 predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
12480 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12481 effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12482
12483 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
12484 ins_encode %{
12485 __ string_compare($str1$$Register, $str2$$Register,
12486 $cnt1$$Register, $cnt2$$Register, $result$$Register,
12487 $tmp1$$XMMRegister, StrIntrinsicNode::LU, $ktmp$$KRegister);
12488 %}
12489 ins_pipe( pipe_slow );
12490 %}
12491
12492 instruct string_compareUL(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
12493 rax_RegI result, legRegD tmp1, rFlagsReg cr)
12494 %{
12495 predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
12496 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12497 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12498
12499 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
12500 ins_encode %{
12501 __ string_compare($str2$$Register, $str1$$Register,
12502 $cnt2$$Register, $cnt1$$Register, $result$$Register,
12503 $tmp1$$XMMRegister, StrIntrinsicNode::UL, knoreg);
12504 %}
12505 ins_pipe( pipe_slow );
12506 %}
12507
12508 instruct string_compareUL_evex(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
12509 rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
12510 %{
12511 predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
12512 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12513 effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12514
12515 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
12516 ins_encode %{
12517 __ string_compare($str2$$Register, $str1$$Register,
12518 $cnt2$$Register, $cnt1$$Register, $result$$Register,
12519 $tmp1$$XMMRegister, StrIntrinsicNode::UL, $ktmp$$KRegister);
12520 %}
12521 ins_pipe( pipe_slow );
12522 %}
12523
12524 // fast search of substring with known size.
12525 instruct string_indexof_conL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
12526 rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
12527 %{
12528 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
12529 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
12530 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
12531
12532 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
12533 ins_encode %{
12534 int icnt2 = (int)$int_cnt2$$constant;
12535 if (icnt2 >= 16) {
12536 // IndexOf for constant substrings with size >= 16 elements
12537 // which don't need to be loaded through stack.
12538 __ string_indexofC8($str1$$Register, $str2$$Register,
12539 $cnt1$$Register, $cnt2$$Register,
12540 icnt2, $result$$Register,
12541 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
12542 } else {
12543 // Small strings are loaded through stack if they cross page boundary.
12544 __ string_indexof($str1$$Register, $str2$$Register,
12545 $cnt1$$Register, $cnt2$$Register,
12546 icnt2, $result$$Register,
12547 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
12548 }
12549 %}
12550 ins_pipe( pipe_slow );
12551 %}
12552
12553 // fast search of substring with known size.
12554 instruct string_indexof_conU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
12555 rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
12556 %{
12557 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
12558 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
12559 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
12560
12561 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
12562 ins_encode %{
12563 int icnt2 = (int)$int_cnt2$$constant;
12564 if (icnt2 >= 8) {
12565 // IndexOf for constant substrings with size >= 8 elements
12566 // which don't need to be loaded through stack.
12567 __ string_indexofC8($str1$$Register, $str2$$Register,
12568 $cnt1$$Register, $cnt2$$Register,
12569 icnt2, $result$$Register,
12570 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
12571 } else {
12572 // Small strings are loaded through stack if they cross page boundary.
12573 __ string_indexof($str1$$Register, $str2$$Register,
12574 $cnt1$$Register, $cnt2$$Register,
12575 icnt2, $result$$Register,
12576 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
12577 }
12578 %}
12579 ins_pipe( pipe_slow );
12580 %}
12581
12582 // fast search of substring with known size.
12583 instruct string_indexof_conUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
12584 rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
12585 %{
12586 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
12587 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
12588 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
12589
12590 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
12591 ins_encode %{
12592 int icnt2 = (int)$int_cnt2$$constant;
12593 if (icnt2 >= 8) {
12594 // IndexOf for constant substrings with size >= 8 elements
12595 // which don't need to be loaded through stack.
12596 __ string_indexofC8($str1$$Register, $str2$$Register,
12597 $cnt1$$Register, $cnt2$$Register,
12598 icnt2, $result$$Register,
12599 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
12600 } else {
12601 // Small strings are loaded through stack if they cross page boundary.
12602 __ string_indexof($str1$$Register, $str2$$Register,
12603 $cnt1$$Register, $cnt2$$Register,
12604 icnt2, $result$$Register,
12605 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
12606 }
12607 %}
12608 ins_pipe( pipe_slow );
12609 %}
12610
12611 instruct string_indexofL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
12612 rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
12613 %{
12614 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
12615 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
12616 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
12617
12618 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
12619 ins_encode %{
12620 __ string_indexof($str1$$Register, $str2$$Register,
12621 $cnt1$$Register, $cnt2$$Register,
12622 (-1), $result$$Register,
12623 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
12624 %}
12625 ins_pipe( pipe_slow );
12626 %}
12627
12628 instruct string_indexofU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
12629 rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
12630 %{
12631 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
12632 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
12633 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
12634
12635 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
12636 ins_encode %{
12637 __ string_indexof($str1$$Register, $str2$$Register,
12638 $cnt1$$Register, $cnt2$$Register,
12639 (-1), $result$$Register,
12640 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
12641 %}
12642 ins_pipe( pipe_slow );
12643 %}
12644
12645 instruct string_indexofUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
12646 rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
12647 %{
12648 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
12649 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
12650 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
12651
12652 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
12653 ins_encode %{
12654 __ string_indexof($str1$$Register, $str2$$Register,
12655 $cnt1$$Register, $cnt2$$Register,
12656 (-1), $result$$Register,
12657 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
12658 %}
12659 ins_pipe( pipe_slow );
12660 %}
12661
12662 instruct string_indexof_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
12663 rbx_RegI result, legRegD tmp_vec1, legRegD tmp_vec2, legRegD tmp_vec3, rcx_RegI tmp, rFlagsReg cr)
12664 %{
12665 predicate(UseSSE42Intrinsics && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U));
12666 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
12667 effect(TEMP tmp_vec1, TEMP tmp_vec2, TEMP tmp_vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
12668 format %{ "StringUTF16 IndexOf char[] $str1,$cnt1,$ch -> $result // KILL all" %}
12669 ins_encode %{
12670 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
12671 $tmp_vec1$$XMMRegister, $tmp_vec2$$XMMRegister, $tmp_vec3$$XMMRegister, $tmp$$Register);
12672 %}
12673 ins_pipe( pipe_slow );
12674 %}
12675
12676 instruct stringL_indexof_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
12677 rbx_RegI result, legRegD tmp_vec1, legRegD tmp_vec2, legRegD tmp_vec3, rcx_RegI tmp, rFlagsReg cr)
12678 %{
12679 predicate(UseSSE42Intrinsics && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L));
12680 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
12681 effect(TEMP tmp_vec1, TEMP tmp_vec2, TEMP tmp_vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
12682 format %{ "StringLatin1 IndexOf char[] $str1,$cnt1,$ch -> $result // KILL all" %}
12683 ins_encode %{
12684 __ stringL_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
12685 $tmp_vec1$$XMMRegister, $tmp_vec2$$XMMRegister, $tmp_vec3$$XMMRegister, $tmp$$Register);
12686 %}
12687 ins_pipe( pipe_slow );
12688 %}
12689
12690 // fast string equals
12691 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
12692 legRegD tmp1, legRegD tmp2, rbx_RegI tmp3, rFlagsReg cr)
12693 %{
12694 predicate(!VM_Version::supports_avx512vlbw());
12695 match(Set result (StrEquals (Binary str1 str2) cnt));
12696 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
12697
12698 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
12699 ins_encode %{
12700 __ arrays_equals(false, $str1$$Register, $str2$$Register,
12701 $cnt$$Register, $result$$Register, $tmp3$$Register,
12702 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, knoreg);
12703 %}
12704 ins_pipe( pipe_slow );
12705 %}
12706
12707 instruct string_equals_evex(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
12708 legRegD tmp1, legRegD tmp2, kReg ktmp, rbx_RegI tmp3, rFlagsReg cr)
12709 %{
12710 predicate(VM_Version::supports_avx512vlbw());
12711 match(Set result (StrEquals (Binary str1 str2) cnt));
12712 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
12713
12714 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
12715 ins_encode %{
12716 __ arrays_equals(false, $str1$$Register, $str2$$Register,
12717 $cnt$$Register, $result$$Register, $tmp3$$Register,
12718 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, $ktmp$$KRegister);
12719 %}
12720 ins_pipe( pipe_slow );
12721 %}
12722
12723 // fast array equals
12724 instruct array_equalsB(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
12725 legRegD tmp1, legRegD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
12726 %{
12727 predicate(!VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
12728 match(Set result (AryEq ary1 ary2));
12729 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
12730
12731 format %{ "Array Equals byte[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
12732 ins_encode %{
12733 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
12734 $tmp3$$Register, $result$$Register, $tmp4$$Register,
12735 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, knoreg);
12736 %}
12737 ins_pipe( pipe_slow );
12738 %}
12739
12740 instruct array_equalsB_evex(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
12741 legRegD tmp1, legRegD tmp2, kReg ktmp, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
12742 %{
12743 predicate(VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
12744 match(Set result (AryEq ary1 ary2));
12745 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
12746
12747 format %{ "Array Equals byte[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
12748 ins_encode %{
12749 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
12750 $tmp3$$Register, $result$$Register, $tmp4$$Register,
12751 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, $ktmp$$KRegister);
12752 %}
12753 ins_pipe( pipe_slow );
12754 %}
12755
12756 instruct array_equalsC(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
12757 legRegD tmp1, legRegD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
12758 %{
12759 predicate(!VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
12760 match(Set result (AryEq ary1 ary2));
12761 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
12762
12763 format %{ "Array Equals char[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
12764 ins_encode %{
12765 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
12766 $tmp3$$Register, $result$$Register, $tmp4$$Register,
12767 $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */, knoreg);
12768 %}
12769 ins_pipe( pipe_slow );
12770 %}
12771
12772 instruct array_equalsC_evex(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
12773 legRegD tmp1, legRegD tmp2, kReg ktmp, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
12774 %{
12775 predicate(VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
12776 match(Set result (AryEq ary1 ary2));
12777 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
12778
12779 format %{ "Array Equals char[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
12780 ins_encode %{
12781 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
12782 $tmp3$$Register, $result$$Register, $tmp4$$Register,
12783 $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */, $ktmp$$KRegister);
12784 %}
12785 ins_pipe( pipe_slow );
12786 %}
12787
12788 instruct arrays_hashcode(rdi_RegP ary1, rdx_RegI cnt1, rbx_RegI result, immU8 basic_type,
12789 legRegD tmp_vec1, legRegD tmp_vec2, legRegD tmp_vec3, legRegD tmp_vec4,
12790 legRegD tmp_vec5, legRegD tmp_vec6, legRegD tmp_vec7, legRegD tmp_vec8,
12791 legRegD tmp_vec9, legRegD tmp_vec10, legRegD tmp_vec11, legRegD tmp_vec12,
12792 legRegD tmp_vec13, rRegI tmp1, rRegI tmp2, rRegI tmp3, rFlagsReg cr)
12793 %{
12794 predicate(UseAVX >= 2);
12795 match(Set result (VectorizedHashCode (Binary ary1 cnt1) (Binary result basic_type)));
12796 effect(TEMP tmp_vec1, TEMP tmp_vec2, TEMP tmp_vec3, TEMP tmp_vec4, TEMP tmp_vec5, TEMP tmp_vec6,
12797 TEMP tmp_vec7, TEMP tmp_vec8, TEMP tmp_vec9, TEMP tmp_vec10, TEMP tmp_vec11, TEMP tmp_vec12,
12798 TEMP tmp_vec13, TEMP tmp1, TEMP tmp2, TEMP tmp3, USE_KILL ary1, USE_KILL cnt1,
12799 USE basic_type, KILL cr);
12800
12801 format %{ "Array HashCode array[] $ary1,$cnt1,$result,$basic_type -> $result // KILL all" %}
12802 ins_encode %{
12803 __ arrays_hashcode($ary1$$Register, $cnt1$$Register, $result$$Register,
12804 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
12805 $tmp_vec1$$XMMRegister, $tmp_vec2$$XMMRegister, $tmp_vec3$$XMMRegister,
12806 $tmp_vec4$$XMMRegister, $tmp_vec5$$XMMRegister, $tmp_vec6$$XMMRegister,
12807 $tmp_vec7$$XMMRegister, $tmp_vec8$$XMMRegister, $tmp_vec9$$XMMRegister,
12808 $tmp_vec10$$XMMRegister, $tmp_vec11$$XMMRegister, $tmp_vec12$$XMMRegister,
12809 $tmp_vec13$$XMMRegister, (BasicType)$basic_type$$constant);
12810 %}
12811 ins_pipe( pipe_slow );
12812 %}
12813
12814 instruct count_positives(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
12815 legRegD tmp1, legRegD tmp2, rbx_RegI tmp3, rFlagsReg cr,)
12816 %{
12817 predicate(!VM_Version::supports_avx512vlbw() || !VM_Version::supports_bmi2());
12818 match(Set result (CountPositives ary1 len));
12819 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
12820
12821 format %{ "countPositives byte[] $ary1,$len -> $result // KILL $tmp1, $tmp2, $tmp3" %}
12822 ins_encode %{
12823 __ count_positives($ary1$$Register, $len$$Register,
12824 $result$$Register, $tmp3$$Register,
12825 $tmp1$$XMMRegister, $tmp2$$XMMRegister, knoreg, knoreg);
12826 %}
12827 ins_pipe( pipe_slow );
12828 %}
12829
12830 instruct count_positives_evex(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
12831 legRegD tmp1, legRegD tmp2, kReg ktmp1, kReg ktmp2, rbx_RegI tmp3, rFlagsReg cr,)
12832 %{
12833 predicate(VM_Version::supports_avx512vlbw() && VM_Version::supports_bmi2());
12834 match(Set result (CountPositives ary1 len));
12835 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp1, TEMP ktmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
12836
12837 format %{ "countPositives byte[] $ary1,$len -> $result // KILL $tmp1, $tmp2, $tmp3" %}
12838 ins_encode %{
12839 __ count_positives($ary1$$Register, $len$$Register,
12840 $result$$Register, $tmp3$$Register,
12841 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $ktmp1$$KRegister, $ktmp2$$KRegister);
12842 %}
12843 ins_pipe( pipe_slow );
12844 %}
12845
12846 // fast char[] to byte[] compression
12847 instruct string_compress(rsi_RegP src, rdi_RegP dst, rdx_RegI len, legRegD tmp1, legRegD tmp2, legRegD tmp3,
12848 legRegD tmp4, rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
12849 predicate(!VM_Version::supports_avx512vlbw() || !VM_Version::supports_bmi2());
12850 match(Set result (StrCompressedCopy src (Binary dst len)));
12851 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst,
12852 USE_KILL len, KILL tmp5, KILL cr);
12853
12854 format %{ "String Compress $src,$dst -> $result // KILL RAX, RCX, RDX" %}
12855 ins_encode %{
12856 __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
12857 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
12858 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register,
12859 knoreg, knoreg);
12860 %}
12861 ins_pipe( pipe_slow );
12862 %}
12863
12864 instruct string_compress_evex(rsi_RegP src, rdi_RegP dst, rdx_RegI len, legRegD tmp1, legRegD tmp2, legRegD tmp3,
12865 legRegD tmp4, kReg ktmp1, kReg ktmp2, rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
12866 predicate(VM_Version::supports_avx512vlbw() && VM_Version::supports_bmi2());
12867 match(Set result (StrCompressedCopy src (Binary dst len)));
12868 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP ktmp1, TEMP ktmp2, USE_KILL src, USE_KILL dst,
12869 USE_KILL len, KILL tmp5, KILL cr);
12870
12871 format %{ "String Compress $src,$dst -> $result // KILL RAX, RCX, RDX" %}
12872 ins_encode %{
12873 __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
12874 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
12875 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register,
12876 $ktmp1$$KRegister, $ktmp2$$KRegister);
12877 %}
12878 ins_pipe( pipe_slow );
12879 %}
12880 // fast byte[] to char[] inflation
12881 instruct string_inflate(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
12882 legRegD tmp1, rcx_RegI tmp2, rFlagsReg cr) %{
12883 predicate(!VM_Version::supports_avx512vlbw() || !VM_Version::supports_bmi2());
12884 match(Set dummy (StrInflatedCopy src (Binary dst len)));
12885 effect(TEMP tmp1, TEMP tmp2, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
12886
12887 format %{ "String Inflate $src,$dst // KILL $tmp1, $tmp2" %}
12888 ins_encode %{
12889 __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
12890 $tmp1$$XMMRegister, $tmp2$$Register, knoreg);
12891 %}
12892 ins_pipe( pipe_slow );
12893 %}
12894
12895 instruct string_inflate_evex(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
12896 legRegD tmp1, kReg ktmp, rcx_RegI tmp2, rFlagsReg cr) %{
12897 predicate(VM_Version::supports_avx512vlbw() && VM_Version::supports_bmi2());
12898 match(Set dummy (StrInflatedCopy src (Binary dst len)));
12899 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
12900
12901 format %{ "String Inflate $src,$dst // KILL $tmp1, $tmp2" %}
12902 ins_encode %{
12903 __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
12904 $tmp1$$XMMRegister, $tmp2$$Register, $ktmp$$KRegister);
12905 %}
12906 ins_pipe( pipe_slow );
12907 %}
12908
12909 // encode char[] to byte[] in ISO_8859_1
12910 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
12911 legRegD tmp1, legRegD tmp2, legRegD tmp3, legRegD tmp4,
12912 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
12913 predicate(!((EncodeISOArrayNode*)n)->is_ascii());
12914 match(Set result (EncodeISOArray src (Binary dst len)));
12915 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
12916
12917 format %{ "Encode iso array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
12918 ins_encode %{
12919 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
12920 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
12921 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register, false);
12922 %}
12923 ins_pipe( pipe_slow );
12924 %}
12925
12926 // encode char[] to byte[] in ASCII
12927 instruct encode_ascii_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
12928 legRegD tmp1, legRegD tmp2, legRegD tmp3, legRegD tmp4,
12929 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
12930 predicate(((EncodeISOArrayNode*)n)->is_ascii());
12931 match(Set result (EncodeISOArray src (Binary dst len)));
12932 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
12933
12934 format %{ "Encode ascii array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
12935 ins_encode %{
12936 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
12937 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
12938 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register, true);
12939 %}
12940 ins_pipe( pipe_slow );
12941 %}
12942
12943 //----------Overflow Math Instructions-----------------------------------------
12944
12945 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
12946 %{
12947 match(Set cr (OverflowAddI op1 op2));
12948 effect(DEF cr, USE_KILL op1, USE op2);
12949
12950 format %{ "addl $op1, $op2\t# overflow check int" %}
12951
12952 ins_encode %{
12953 __ addl($op1$$Register, $op2$$Register);
12954 %}
12955 ins_pipe(ialu_reg_reg);
12956 %}
12957
12958 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
12959 %{
12960 match(Set cr (OverflowAddI op1 op2));
12961 effect(DEF cr, USE_KILL op1, USE op2);
12962
12963 format %{ "addl $op1, $op2\t# overflow check int" %}
12964
12965 ins_encode %{
12966 __ addl($op1$$Register, $op2$$constant);
12967 %}
12968 ins_pipe(ialu_reg_reg);
12969 %}
12970
12971 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
12972 %{
12973 match(Set cr (OverflowAddL op1 op2));
12974 effect(DEF cr, USE_KILL op1, USE op2);
12975
12976 format %{ "addq $op1, $op2\t# overflow check long" %}
12977 ins_encode %{
12978 __ addq($op1$$Register, $op2$$Register);
12979 %}
12980 ins_pipe(ialu_reg_reg);
12981 %}
12982
12983 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
12984 %{
12985 match(Set cr (OverflowAddL op1 op2));
12986 effect(DEF cr, USE_KILL op1, USE op2);
12987
12988 format %{ "addq $op1, $op2\t# overflow check long" %}
12989 ins_encode %{
12990 __ addq($op1$$Register, $op2$$constant);
12991 %}
12992 ins_pipe(ialu_reg_reg);
12993 %}
12994
12995 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
12996 %{
12997 match(Set cr (OverflowSubI op1 op2));
12998
12999 format %{ "cmpl $op1, $op2\t# overflow check int" %}
13000 ins_encode %{
13001 __ cmpl($op1$$Register, $op2$$Register);
13002 %}
13003 ins_pipe(ialu_reg_reg);
13004 %}
13005
13006 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
13007 %{
13008 match(Set cr (OverflowSubI op1 op2));
13009
13010 format %{ "cmpl $op1, $op2\t# overflow check int" %}
13011 ins_encode %{
13012 __ cmpl($op1$$Register, $op2$$constant);
13013 %}
13014 ins_pipe(ialu_reg_reg);
13015 %}
13016
13017 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
13018 %{
13019 match(Set cr (OverflowSubL op1 op2));
13020
13021 format %{ "cmpq $op1, $op2\t# overflow check long" %}
13022 ins_encode %{
13023 __ cmpq($op1$$Register, $op2$$Register);
13024 %}
13025 ins_pipe(ialu_reg_reg);
13026 %}
13027
13028 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
13029 %{
13030 match(Set cr (OverflowSubL op1 op2));
13031
13032 format %{ "cmpq $op1, $op2\t# overflow check long" %}
13033 ins_encode %{
13034 __ cmpq($op1$$Register, $op2$$constant);
13035 %}
13036 ins_pipe(ialu_reg_reg);
13037 %}
13038
13039 instruct overflowNegI_rReg(rFlagsReg cr, immI_0 zero, rax_RegI op2)
13040 %{
13041 match(Set cr (OverflowSubI zero op2));
13042 effect(DEF cr, USE_KILL op2);
13043
13044 format %{ "negl $op2\t# overflow check int" %}
13045 ins_encode %{
13046 __ negl($op2$$Register);
13047 %}
13048 ins_pipe(ialu_reg_reg);
13049 %}
13050
13051 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
13052 %{
13053 match(Set cr (OverflowSubL zero op2));
13054 effect(DEF cr, USE_KILL op2);
13055
13056 format %{ "negq $op2\t# overflow check long" %}
13057 ins_encode %{
13058 __ negq($op2$$Register);
13059 %}
13060 ins_pipe(ialu_reg_reg);
13061 %}
13062
13063 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
13064 %{
13065 match(Set cr (OverflowMulI op1 op2));
13066 effect(DEF cr, USE_KILL op1, USE op2);
13067
13068 format %{ "imull $op1, $op2\t# overflow check int" %}
13069 ins_encode %{
13070 __ imull($op1$$Register, $op2$$Register);
13071 %}
13072 ins_pipe(ialu_reg_reg_alu0);
13073 %}
13074
13075 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
13076 %{
13077 match(Set cr (OverflowMulI op1 op2));
13078 effect(DEF cr, TEMP tmp, USE op1, USE op2);
13079
13080 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %}
13081 ins_encode %{
13082 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
13083 %}
13084 ins_pipe(ialu_reg_reg_alu0);
13085 %}
13086
13087 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
13088 %{
13089 match(Set cr (OverflowMulL op1 op2));
13090 effect(DEF cr, USE_KILL op1, USE op2);
13091
13092 format %{ "imulq $op1, $op2\t# overflow check long" %}
13093 ins_encode %{
13094 __ imulq($op1$$Register, $op2$$Register);
13095 %}
13096 ins_pipe(ialu_reg_reg_alu0);
13097 %}
13098
13099 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
13100 %{
13101 match(Set cr (OverflowMulL op1 op2));
13102 effect(DEF cr, TEMP tmp, USE op1, USE op2);
13103
13104 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %}
13105 ins_encode %{
13106 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
13107 %}
13108 ins_pipe(ialu_reg_reg_alu0);
13109 %}
13110
13111
13112 //----------Control Flow Instructions------------------------------------------
13113 // Signed compare Instructions
13114
13115 // XXX more variants!!
13116 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
13117 %{
13118 match(Set cr (CmpI op1 op2));
13119 effect(DEF cr, USE op1, USE op2);
13120
13121 format %{ "cmpl $op1, $op2" %}
13122 ins_encode %{
13123 __ cmpl($op1$$Register, $op2$$Register);
13124 %}
13125 ins_pipe(ialu_cr_reg_reg);
13126 %}
13127
13128 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
13129 %{
13130 match(Set cr (CmpI op1 op2));
13131
13132 format %{ "cmpl $op1, $op2" %}
13133 ins_encode %{
13134 __ cmpl($op1$$Register, $op2$$constant);
13135 %}
13136 ins_pipe(ialu_cr_reg_imm);
13137 %}
13138
13139 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
13140 %{
13141 match(Set cr (CmpI op1 (LoadI op2)));
13142
13143 ins_cost(500); // XXX
13144 format %{ "cmpl $op1, $op2" %}
13145 ins_encode %{
13146 __ cmpl($op1$$Register, $op2$$Address);
13147 %}
13148 ins_pipe(ialu_cr_reg_mem);
13149 %}
13150
13151 instruct testI_reg(rFlagsReg cr, rRegI src, immI_0 zero)
13152 %{
13153 match(Set cr (CmpI src zero));
13154
13155 format %{ "testl $src, $src" %}
13156 ins_encode %{
13157 __ testl($src$$Register, $src$$Register);
13158 %}
13159 ins_pipe(ialu_cr_reg_imm);
13160 %}
13161
13162 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI_0 zero)
13163 %{
13164 match(Set cr (CmpI (AndI src con) zero));
13165
13166 format %{ "testl $src, $con" %}
13167 ins_encode %{
13168 __ testl($src$$Register, $con$$constant);
13169 %}
13170 ins_pipe(ialu_cr_reg_imm);
13171 %}
13172
13173 instruct testI_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2, immI_0 zero)
13174 %{
13175 match(Set cr (CmpI (AndI src1 src2) zero));
13176
13177 format %{ "testl $src1, $src2" %}
13178 ins_encode %{
13179 __ testl($src1$$Register, $src2$$Register);
13180 %}
13181 ins_pipe(ialu_cr_reg_imm);
13182 %}
13183
13184 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI_0 zero)
13185 %{
13186 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
13187
13188 format %{ "testl $src, $mem" %}
13189 ins_encode %{
13190 __ testl($src$$Register, $mem$$Address);
13191 %}
13192 ins_pipe(ialu_cr_reg_mem);
13193 %}
13194
13195 // Unsigned compare Instructions; really, same as signed except they
13196 // produce an rFlagsRegU instead of rFlagsReg.
13197 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
13198 %{
13199 match(Set cr (CmpU op1 op2));
13200
13201 format %{ "cmpl $op1, $op2\t# unsigned" %}
13202 ins_encode %{
13203 __ cmpl($op1$$Register, $op2$$Register);
13204 %}
13205 ins_pipe(ialu_cr_reg_reg);
13206 %}
13207
13208 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
13209 %{
13210 match(Set cr (CmpU op1 op2));
13211
13212 format %{ "cmpl $op1, $op2\t# unsigned" %}
13213 ins_encode %{
13214 __ cmpl($op1$$Register, $op2$$constant);
13215 %}
13216 ins_pipe(ialu_cr_reg_imm);
13217 %}
13218
13219 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
13220 %{
13221 match(Set cr (CmpU op1 (LoadI op2)));
13222
13223 ins_cost(500); // XXX
13224 format %{ "cmpl $op1, $op2\t# unsigned" %}
13225 ins_encode %{
13226 __ cmpl($op1$$Register, $op2$$Address);
13227 %}
13228 ins_pipe(ialu_cr_reg_mem);
13229 %}
13230
13231 instruct testU_reg(rFlagsRegU cr, rRegI src, immI_0 zero)
13232 %{
13233 match(Set cr (CmpU src zero));
13234
13235 format %{ "testl $src, $src\t# unsigned" %}
13236 ins_encode %{
13237 __ testl($src$$Register, $src$$Register);
13238 %}
13239 ins_pipe(ialu_cr_reg_imm);
13240 %}
13241
13242 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
13243 %{
13244 match(Set cr (CmpP op1 op2));
13245
13246 format %{ "cmpq $op1, $op2\t# ptr" %}
13247 ins_encode %{
13248 __ cmpq($op1$$Register, $op2$$Register);
13249 %}
13250 ins_pipe(ialu_cr_reg_reg);
13251 %}
13252
13253 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
13254 %{
13255 match(Set cr (CmpP op1 (LoadP op2)));
13256 predicate(n->in(2)->as_Load()->barrier_data() == 0);
13257
13258 ins_cost(500); // XXX
13259 format %{ "cmpq $op1, $op2\t# ptr" %}
13260 ins_encode %{
13261 __ cmpq($op1$$Register, $op2$$Address);
13262 %}
13263 ins_pipe(ialu_cr_reg_mem);
13264 %}
13265
13266 // XXX this is generalized by compP_rReg_mem???
13267 // Compare raw pointer (used in out-of-heap check).
13268 // Only works because non-oop pointers must be raw pointers
13269 // and raw pointers have no anti-dependencies.
13270 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
13271 %{
13272 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none &&
13273 n->in(2)->as_Load()->barrier_data() == 0);
13274 match(Set cr (CmpP op1 (LoadP op2)));
13275
13276 format %{ "cmpq $op1, $op2\t# raw ptr" %}
13277 ins_encode %{
13278 __ cmpq($op1$$Register, $op2$$Address);
13279 %}
13280 ins_pipe(ialu_cr_reg_mem);
13281 %}
13282
13283 // This will generate a signed flags result. This should be OK since
13284 // any compare to a zero should be eq/neq.
13285 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
13286 %{
13287 match(Set cr (CmpP src zero));
13288
13289 format %{ "testq $src, $src\t# ptr" %}
13290 ins_encode %{
13291 __ testq($src$$Register, $src$$Register);
13292 %}
13293 ins_pipe(ialu_cr_reg_imm);
13294 %}
13295
13296 // This will generate a signed flags result. This should be OK since
13297 // any compare to a zero should be eq/neq.
13298 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
13299 %{
13300 predicate((!UseCompressedOops || (CompressedOops::base() != nullptr)) &&
13301 n->in(1)->as_Load()->barrier_data() == 0);
13302 match(Set cr (CmpP (LoadP op) zero));
13303
13304 ins_cost(500); // XXX
13305 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
13306 ins_encode %{
13307 __ testq($op$$Address, 0xFFFFFFFF);
13308 %}
13309 ins_pipe(ialu_cr_reg_imm);
13310 %}
13311
13312 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
13313 %{
13314 predicate(UseCompressedOops && (CompressedOops::base() == nullptr) &&
13315 n->in(1)->as_Load()->barrier_data() == 0);
13316 match(Set cr (CmpP (LoadP mem) zero));
13317
13318 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
13319 ins_encode %{
13320 __ cmpq(r12, $mem$$Address);
13321 %}
13322 ins_pipe(ialu_cr_reg_mem);
13323 %}
13324
13325 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
13326 %{
13327 match(Set cr (CmpN op1 op2));
13328
13329 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
13330 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
13331 ins_pipe(ialu_cr_reg_reg);
13332 %}
13333
13334 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
13335 %{
13336 predicate(n->in(2)->as_Load()->barrier_data() == 0);
13337 match(Set cr (CmpN src (LoadN mem)));
13338
13339 format %{ "cmpl $src, $mem\t# compressed ptr" %}
13340 ins_encode %{
13341 __ cmpl($src$$Register, $mem$$Address);
13342 %}
13343 ins_pipe(ialu_cr_reg_mem);
13344 %}
13345
13346 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
13347 match(Set cr (CmpN op1 op2));
13348
13349 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
13350 ins_encode %{
13351 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
13352 %}
13353 ins_pipe(ialu_cr_reg_imm);
13354 %}
13355
13356 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
13357 %{
13358 predicate(n->in(2)->as_Load()->barrier_data() == 0);
13359 match(Set cr (CmpN src (LoadN mem)));
13360
13361 format %{ "cmpl $mem, $src\t# compressed ptr" %}
13362 ins_encode %{
13363 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
13364 %}
13365 ins_pipe(ialu_cr_reg_mem);
13366 %}
13367
13368 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
13369 match(Set cr (CmpN op1 op2));
13370
13371 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %}
13372 ins_encode %{
13373 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
13374 %}
13375 ins_pipe(ialu_cr_reg_imm);
13376 %}
13377
13378 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
13379 %{
13380 predicate(!UseCompactObjectHeaders);
13381 match(Set cr (CmpN src (LoadNKlass mem)));
13382
13383 format %{ "cmpl $mem, $src\t# compressed klass ptr" %}
13384 ins_encode %{
13385 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
13386 %}
13387 ins_pipe(ialu_cr_reg_mem);
13388 %}
13389
13390 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
13391 match(Set cr (CmpN src zero));
13392
13393 format %{ "testl $src, $src\t# compressed ptr" %}
13394 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
13395 ins_pipe(ialu_cr_reg_imm);
13396 %}
13397
13398 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
13399 %{
13400 predicate(CompressedOops::base() != nullptr &&
13401 n->in(1)->as_Load()->barrier_data() == 0);
13402 match(Set cr (CmpN (LoadN mem) zero));
13403
13404 ins_cost(500); // XXX
13405 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
13406 ins_encode %{
13407 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
13408 %}
13409 ins_pipe(ialu_cr_reg_mem);
13410 %}
13411
13412 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
13413 %{
13414 predicate(CompressedOops::base() == nullptr &&
13415 n->in(1)->as_Load()->barrier_data() == 0);
13416 match(Set cr (CmpN (LoadN mem) zero));
13417
13418 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
13419 ins_encode %{
13420 __ cmpl(r12, $mem$$Address);
13421 %}
13422 ins_pipe(ialu_cr_reg_mem);
13423 %}
13424
13425 // Yanked all unsigned pointer compare operations.
13426 // Pointer compares are done with CmpP which is already unsigned.
13427
13428 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
13429 %{
13430 match(Set cr (CmpL op1 op2));
13431
13432 format %{ "cmpq $op1, $op2" %}
13433 ins_encode %{
13434 __ cmpq($op1$$Register, $op2$$Register);
13435 %}
13436 ins_pipe(ialu_cr_reg_reg);
13437 %}
13438
13439 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
13440 %{
13441 match(Set cr (CmpL op1 op2));
13442
13443 format %{ "cmpq $op1, $op2" %}
13444 ins_encode %{
13445 __ cmpq($op1$$Register, $op2$$constant);
13446 %}
13447 ins_pipe(ialu_cr_reg_imm);
13448 %}
13449
13450 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
13451 %{
13452 match(Set cr (CmpL op1 (LoadL op2)));
13453
13454 format %{ "cmpq $op1, $op2" %}
13455 ins_encode %{
13456 __ cmpq($op1$$Register, $op2$$Address);
13457 %}
13458 ins_pipe(ialu_cr_reg_mem);
13459 %}
13460
13461 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
13462 %{
13463 match(Set cr (CmpL src zero));
13464
13465 format %{ "testq $src, $src" %}
13466 ins_encode %{
13467 __ testq($src$$Register, $src$$Register);
13468 %}
13469 ins_pipe(ialu_cr_reg_imm);
13470 %}
13471
13472 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
13473 %{
13474 match(Set cr (CmpL (AndL src con) zero));
13475
13476 format %{ "testq $src, $con\t# long" %}
13477 ins_encode %{
13478 __ testq($src$$Register, $con$$constant);
13479 %}
13480 ins_pipe(ialu_cr_reg_imm);
13481 %}
13482
13483 instruct testL_reg_reg(rFlagsReg cr, rRegL src1, rRegL src2, immL0 zero)
13484 %{
13485 match(Set cr (CmpL (AndL src1 src2) zero));
13486
13487 format %{ "testq $src1, $src2\t# long" %}
13488 ins_encode %{
13489 __ testq($src1$$Register, $src2$$Register);
13490 %}
13491 ins_pipe(ialu_cr_reg_imm);
13492 %}
13493
13494 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
13495 %{
13496 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
13497
13498 format %{ "testq $src, $mem" %}
13499 ins_encode %{
13500 __ testq($src$$Register, $mem$$Address);
13501 %}
13502 ins_pipe(ialu_cr_reg_mem);
13503 %}
13504
13505 instruct testL_reg_mem2(rFlagsReg cr, rRegP src, memory mem, immL0 zero)
13506 %{
13507 match(Set cr (CmpL (AndL (CastP2X src) (LoadL mem)) zero));
13508
13509 format %{ "testq $src, $mem" %}
13510 ins_encode %{
13511 __ testq($src$$Register, $mem$$Address);
13512 %}
13513 ins_pipe(ialu_cr_reg_mem);
13514 %}
13515
13516 // Manifest a CmpU result in an integer register. Very painful.
13517 // This is the test to avoid.
13518 instruct cmpU3_reg_reg(rRegI dst, rRegI src1, rRegI src2, rFlagsReg flags)
13519 %{
13520 match(Set dst (CmpU3 src1 src2));
13521 effect(KILL flags);
13522
13523 ins_cost(275); // XXX
13524 format %{ "cmpl $src1, $src2\t# CmpL3\n\t"
13525 "movl $dst, -1\n\t"
13526 "jb,u done\n\t"
13527 "setcc $dst \t# emits setne + movzbl or setzune for APX"
13528 "done:" %}
13529 ins_encode %{
13530 Label done;
13531 __ cmpl($src1$$Register, $src2$$Register);
13532 __ movl($dst$$Register, -1);
13533 __ jccb(Assembler::below, done);
13534 __ setcc(Assembler::notZero, $dst$$Register);
13535 __ bind(done);
13536 %}
13537 ins_pipe(pipe_slow);
13538 %}
13539
13540 // Manifest a CmpL result in an integer register. Very painful.
13541 // This is the test to avoid.
13542 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
13543 %{
13544 match(Set dst (CmpL3 src1 src2));
13545 effect(KILL flags);
13546
13547 ins_cost(275); // XXX
13548 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
13549 "movl $dst, -1\n\t"
13550 "jl,s done\n\t"
13551 "setcc $dst \t# emits setne + movzbl or setzune for APX"
13552 "done:" %}
13553 ins_encode %{
13554 Label done;
13555 __ cmpq($src1$$Register, $src2$$Register);
13556 __ movl($dst$$Register, -1);
13557 __ jccb(Assembler::less, done);
13558 __ setcc(Assembler::notZero, $dst$$Register);
13559 __ bind(done);
13560 %}
13561 ins_pipe(pipe_slow);
13562 %}
13563
13564 // Manifest a CmpUL result in an integer register. Very painful.
13565 // This is the test to avoid.
13566 instruct cmpUL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
13567 %{
13568 match(Set dst (CmpUL3 src1 src2));
13569 effect(KILL flags);
13570
13571 ins_cost(275); // XXX
13572 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
13573 "movl $dst, -1\n\t"
13574 "jb,u done\n\t"
13575 "setcc $dst \t# emits setne + movzbl or setzune for APX"
13576 "done:" %}
13577 ins_encode %{
13578 Label done;
13579 __ cmpq($src1$$Register, $src2$$Register);
13580 __ movl($dst$$Register, -1);
13581 __ jccb(Assembler::below, done);
13582 __ setcc(Assembler::notZero, $dst$$Register);
13583 __ bind(done);
13584 %}
13585 ins_pipe(pipe_slow);
13586 %}
13587
13588 // Unsigned long compare Instructions; really, same as signed long except they
13589 // produce an rFlagsRegU instead of rFlagsReg.
13590 instruct compUL_rReg(rFlagsRegU cr, rRegL op1, rRegL op2)
13591 %{
13592 match(Set cr (CmpUL op1 op2));
13593
13594 format %{ "cmpq $op1, $op2\t# unsigned" %}
13595 ins_encode %{
13596 __ cmpq($op1$$Register, $op2$$Register);
13597 %}
13598 ins_pipe(ialu_cr_reg_reg);
13599 %}
13600
13601 instruct compUL_rReg_imm(rFlagsRegU cr, rRegL op1, immL32 op2)
13602 %{
13603 match(Set cr (CmpUL op1 op2));
13604
13605 format %{ "cmpq $op1, $op2\t# unsigned" %}
13606 ins_encode %{
13607 __ cmpq($op1$$Register, $op2$$constant);
13608 %}
13609 ins_pipe(ialu_cr_reg_imm);
13610 %}
13611
13612 instruct compUL_rReg_mem(rFlagsRegU cr, rRegL op1, memory op2)
13613 %{
13614 match(Set cr (CmpUL op1 (LoadL op2)));
13615
13616 format %{ "cmpq $op1, $op2\t# unsigned" %}
13617 ins_encode %{
13618 __ cmpq($op1$$Register, $op2$$Address);
13619 %}
13620 ins_pipe(ialu_cr_reg_mem);
13621 %}
13622
13623 instruct testUL_reg(rFlagsRegU cr, rRegL src, immL0 zero)
13624 %{
13625 match(Set cr (CmpUL src zero));
13626
13627 format %{ "testq $src, $src\t# unsigned" %}
13628 ins_encode %{
13629 __ testq($src$$Register, $src$$Register);
13630 %}
13631 ins_pipe(ialu_cr_reg_imm);
13632 %}
13633
13634 instruct compB_mem_imm(rFlagsReg cr, memory mem, immI8 imm)
13635 %{
13636 match(Set cr (CmpI (LoadB mem) imm));
13637
13638 ins_cost(125);
13639 format %{ "cmpb $mem, $imm" %}
13640 ins_encode %{ __ cmpb($mem$$Address, $imm$$constant); %}
13641 ins_pipe(ialu_cr_reg_mem);
13642 %}
13643
13644 instruct testUB_mem_imm(rFlagsReg cr, memory mem, immU7 imm, immI_0 zero)
13645 %{
13646 match(Set cr (CmpI (AndI (LoadUB mem) imm) zero));
13647
13648 ins_cost(125);
13649 format %{ "testb $mem, $imm\t# ubyte" %}
13650 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
13651 ins_pipe(ialu_cr_reg_mem);
13652 %}
13653
13654 instruct testB_mem_imm(rFlagsReg cr, memory mem, immI8 imm, immI_0 zero)
13655 %{
13656 match(Set cr (CmpI (AndI (LoadB mem) imm) zero));
13657
13658 ins_cost(125);
13659 format %{ "testb $mem, $imm\t# byte" %}
13660 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
13661 ins_pipe(ialu_cr_reg_mem);
13662 %}
13663
13664 //----------Max and Min--------------------------------------------------------
13665 // Min Instructions
13666
13667 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
13668 %{
13669 predicate(!UseAPX);
13670 effect(USE_DEF dst, USE src, USE cr);
13671
13672 format %{ "cmovlgt $dst, $src\t# min" %}
13673 ins_encode %{
13674 __ cmovl(Assembler::greater, $dst$$Register, $src$$Register);
13675 %}
13676 ins_pipe(pipe_cmov_reg);
13677 %}
13678
13679 instruct cmovI_reg_g_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
13680 %{
13681 predicate(UseAPX);
13682 effect(DEF dst, USE src1, USE src2, USE cr);
13683
13684 format %{ "ecmovlgt $dst, $src1, $src2\t# min ndd" %}
13685 ins_encode %{
13686 __ ecmovl(Assembler::greater, $dst$$Register, $src1$$Register, $src2$$Register);
13687 %}
13688 ins_pipe(pipe_cmov_reg);
13689 %}
13690
13691 instruct minI_rReg(rRegI dst, rRegI src)
13692 %{
13693 predicate(!UseAPX);
13694 match(Set dst (MinI dst src));
13695
13696 ins_cost(200);
13697 expand %{
13698 rFlagsReg cr;
13699 compI_rReg(cr, dst, src);
13700 cmovI_reg_g(dst, src, cr);
13701 %}
13702 %}
13703
13704 instruct minI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2)
13705 %{
13706 predicate(UseAPX);
13707 match(Set dst (MinI src1 src2));
13708 effect(DEF dst, USE src1, USE src2);
13709
13710 ins_cost(200);
13711 expand %{
13712 rFlagsReg cr;
13713 compI_rReg(cr, src1, src2);
13714 cmovI_reg_g_ndd(dst, src1, src2, cr);
13715 %}
13716 %}
13717
13718 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
13719 %{
13720 predicate(!UseAPX);
13721 effect(USE_DEF dst, USE src, USE cr);
13722
13723 format %{ "cmovllt $dst, $src\t# max" %}
13724 ins_encode %{
13725 __ cmovl(Assembler::less, $dst$$Register, $src$$Register);
13726 %}
13727 ins_pipe(pipe_cmov_reg);
13728 %}
13729
13730 instruct cmovI_reg_l_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
13731 %{
13732 predicate(UseAPX);
13733 effect(DEF dst, USE src1, USE src2, USE cr);
13734
13735 format %{ "ecmovllt $dst, $src1, $src2\t# max ndd" %}
13736 ins_encode %{
13737 __ ecmovl(Assembler::less, $dst$$Register, $src1$$Register, $src2$$Register);
13738 %}
13739 ins_pipe(pipe_cmov_reg);
13740 %}
13741
13742 instruct maxI_rReg(rRegI dst, rRegI src)
13743 %{
13744 predicate(!UseAPX);
13745 match(Set dst (MaxI dst src));
13746
13747 ins_cost(200);
13748 expand %{
13749 rFlagsReg cr;
13750 compI_rReg(cr, dst, src);
13751 cmovI_reg_l(dst, src, cr);
13752 %}
13753 %}
13754
13755 instruct maxI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2)
13756 %{
13757 predicate(UseAPX);
13758 match(Set dst (MaxI src1 src2));
13759 effect(DEF dst, USE src1, USE src2);
13760
13761 ins_cost(200);
13762 expand %{
13763 rFlagsReg cr;
13764 compI_rReg(cr, src1, src2);
13765 cmovI_reg_l_ndd(dst, src1, src2, cr);
13766 %}
13767 %}
13768
13769 // ============================================================================
13770 // Branch Instructions
13771
13772 // Jump Direct - Label defines a relative address from JMP+1
13773 instruct jmpDir(label labl)
13774 %{
13775 match(Goto);
13776 effect(USE labl);
13777
13778 ins_cost(300);
13779 format %{ "jmp $labl" %}
13780 size(5);
13781 ins_encode %{
13782 Label* L = $labl$$label;
13783 __ jmp(*L, false); // Always long jump
13784 %}
13785 ins_pipe(pipe_jmp);
13786 %}
13787
13788 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13789 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
13790 %{
13791 match(If cop cr);
13792 effect(USE labl);
13793
13794 ins_cost(300);
13795 format %{ "j$cop $labl" %}
13796 size(6);
13797 ins_encode %{
13798 Label* L = $labl$$label;
13799 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
13800 %}
13801 ins_pipe(pipe_jcc);
13802 %}
13803
13804 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13805 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
13806 %{
13807 match(CountedLoopEnd cop cr);
13808 effect(USE labl);
13809
13810 ins_cost(300);
13811 format %{ "j$cop $labl\t# loop end" %}
13812 size(6);
13813 ins_encode %{
13814 Label* L = $labl$$label;
13815 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
13816 %}
13817 ins_pipe(pipe_jcc);
13818 %}
13819
13820 // Jump Direct Conditional - using unsigned comparison
13821 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
13822 match(If cop cmp);
13823 effect(USE labl);
13824
13825 ins_cost(300);
13826 format %{ "j$cop,u $labl" %}
13827 size(6);
13828 ins_encode %{
13829 Label* L = $labl$$label;
13830 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
13831 %}
13832 ins_pipe(pipe_jcc);
13833 %}
13834
13835 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
13836 match(If cop cmp);
13837 effect(USE labl);
13838
13839 ins_cost(200);
13840 format %{ "j$cop,u $labl" %}
13841 size(6);
13842 ins_encode %{
13843 Label* L = $labl$$label;
13844 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
13845 %}
13846 ins_pipe(pipe_jcc);
13847 %}
13848
13849 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
13850 match(If cop cmp);
13851 effect(USE labl);
13852
13853 ins_cost(200);
13854 format %{ $$template
13855 if ($cop$$cmpcode == Assembler::notEqual) {
13856 $$emit$$"jp,u $labl\n\t"
13857 $$emit$$"j$cop,u $labl"
13858 } else {
13859 $$emit$$"jp,u done\n\t"
13860 $$emit$$"j$cop,u $labl\n\t"
13861 $$emit$$"done:"
13862 }
13863 %}
13864 ins_encode %{
13865 Label* l = $labl$$label;
13866 if ($cop$$cmpcode == Assembler::notEqual) {
13867 __ jcc(Assembler::parity, *l, false);
13868 __ jcc(Assembler::notEqual, *l, false);
13869 } else if ($cop$$cmpcode == Assembler::equal) {
13870 Label done;
13871 __ jccb(Assembler::parity, done);
13872 __ jcc(Assembler::equal, *l, false);
13873 __ bind(done);
13874 } else {
13875 ShouldNotReachHere();
13876 }
13877 %}
13878 ins_pipe(pipe_jcc);
13879 %}
13880
13881 // ============================================================================
13882 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
13883 // superklass array for an instance of the superklass. Set a hidden
13884 // internal cache on a hit (cache is checked with exposed code in
13885 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
13886 // encoding ALSO sets flags.
13887
13888 instruct partialSubtypeCheck(rdi_RegP result,
13889 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
13890 rFlagsReg cr)
13891 %{
13892 match(Set result (PartialSubtypeCheck sub super));
13893 predicate(!UseSecondarySupersTable);
13894 effect(KILL rcx, KILL cr);
13895
13896 ins_cost(1100); // slightly larger than the next version
13897 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
13898 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
13899 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
13900 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
13901 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
13902 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
13903 "xorq $result, $result\t\t Hit: rdi zero\n\t"
13904 "miss:\t" %}
13905
13906 ins_encode %{
13907 Label miss;
13908 // NB: Callers may assume that, when $result is a valid register,
13909 // check_klass_subtype_slow_path_linear sets it to a nonzero
13910 // value.
13911 __ check_klass_subtype_slow_path_linear($sub$$Register, $super$$Register,
13912 $rcx$$Register, $result$$Register,
13913 nullptr, &miss,
13914 /*set_cond_codes:*/ true);
13915 __ xorptr($result$$Register, $result$$Register);
13916 __ bind(miss);
13917 %}
13918
13919 ins_pipe(pipe_slow);
13920 %}
13921
13922 // ============================================================================
13923 // Two versions of hashtable-based partialSubtypeCheck, both used when
13924 // we need to search for a super class in the secondary supers array.
13925 // The first is used when we don't know _a priori_ the class being
13926 // searched for. The second, far more common, is used when we do know:
13927 // this is used for instanceof, checkcast, and any case where C2 can
13928 // determine it by constant propagation.
13929
13930 instruct partialSubtypeCheckVarSuper(rsi_RegP sub, rax_RegP super, rdi_RegP result,
13931 rdx_RegL temp1, rcx_RegL temp2, rbx_RegP temp3, r11_RegL temp4,
13932 rFlagsReg cr)
13933 %{
13934 match(Set result (PartialSubtypeCheck sub super));
13935 predicate(UseSecondarySupersTable);
13936 effect(KILL cr, TEMP temp1, TEMP temp2, TEMP temp3, TEMP temp4);
13937
13938 ins_cost(1000);
13939 format %{ "partialSubtypeCheck $result, $sub, $super" %}
13940
13941 ins_encode %{
13942 __ lookup_secondary_supers_table_var($sub$$Register, $super$$Register, $temp1$$Register, $temp2$$Register,
13943 $temp3$$Register, $temp4$$Register, $result$$Register);
13944 %}
13945
13946 ins_pipe(pipe_slow);
13947 %}
13948
13949 instruct partialSubtypeCheckConstSuper(rsi_RegP sub, rax_RegP super_reg, immP super_con, rdi_RegP result,
13950 rdx_RegL temp1, rcx_RegL temp2, rbx_RegP temp3, r11_RegL temp4,
13951 rFlagsReg cr)
13952 %{
13953 match(Set result (PartialSubtypeCheck sub (Binary super_reg super_con)));
13954 predicate(UseSecondarySupersTable);
13955 effect(KILL cr, TEMP temp1, TEMP temp2, TEMP temp3, TEMP temp4);
13956
13957 ins_cost(700); // smaller than the next version
13958 format %{ "partialSubtypeCheck $result, $sub, $super_reg, $super_con" %}
13959
13960 ins_encode %{
13961 u1 super_klass_slot = ((Klass*)$super_con$$constant)->hash_slot();
13962 if (InlineSecondarySupersTest) {
13963 __ lookup_secondary_supers_table_const($sub$$Register, $super_reg$$Register, $temp1$$Register, $temp2$$Register,
13964 $temp3$$Register, $temp4$$Register, $result$$Register,
13965 super_klass_slot);
13966 } else {
13967 __ call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_stub(super_klass_slot)));
13968 }
13969 %}
13970
13971 ins_pipe(pipe_slow);
13972 %}
13973
13974 // ============================================================================
13975 // Branch Instructions -- short offset versions
13976 //
13977 // These instructions are used to replace jumps of a long offset (the default
13978 // match) with jumps of a shorter offset. These instructions are all tagged
13979 // with the ins_short_branch attribute, which causes the ADLC to suppress the
13980 // match rules in general matching. Instead, the ADLC generates a conversion
13981 // method in the MachNode which can be used to do in-place replacement of the
13982 // long variant with the shorter variant. The compiler will determine if a
13983 // branch can be taken by the is_short_branch_offset() predicate in the machine
13984 // specific code section of the file.
13985
13986 // Jump Direct - Label defines a relative address from JMP+1
13987 instruct jmpDir_short(label labl) %{
13988 match(Goto);
13989 effect(USE labl);
13990
13991 ins_cost(300);
13992 format %{ "jmp,s $labl" %}
13993 size(2);
13994 ins_encode %{
13995 Label* L = $labl$$label;
13996 __ jmpb(*L);
13997 %}
13998 ins_pipe(pipe_jmp);
13999 ins_short_branch(1);
14000 %}
14001
14002 // Jump Direct Conditional - Label defines a relative address from Jcc+1
14003 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
14004 match(If cop cr);
14005 effect(USE labl);
14006
14007 ins_cost(300);
14008 format %{ "j$cop,s $labl" %}
14009 size(2);
14010 ins_encode %{
14011 Label* L = $labl$$label;
14012 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
14013 %}
14014 ins_pipe(pipe_jcc);
14015 ins_short_branch(1);
14016 %}
14017
14018 // Jump Direct Conditional - Label defines a relative address from Jcc+1
14019 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
14020 match(CountedLoopEnd cop cr);
14021 effect(USE labl);
14022
14023 ins_cost(300);
14024 format %{ "j$cop,s $labl\t# loop end" %}
14025 size(2);
14026 ins_encode %{
14027 Label* L = $labl$$label;
14028 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
14029 %}
14030 ins_pipe(pipe_jcc);
14031 ins_short_branch(1);
14032 %}
14033
14034 // Jump Direct Conditional - using unsigned comparison
14035 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
14036 match(If cop cmp);
14037 effect(USE labl);
14038
14039 ins_cost(300);
14040 format %{ "j$cop,us $labl" %}
14041 size(2);
14042 ins_encode %{
14043 Label* L = $labl$$label;
14044 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
14045 %}
14046 ins_pipe(pipe_jcc);
14047 ins_short_branch(1);
14048 %}
14049
14050 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
14051 match(If cop cmp);
14052 effect(USE labl);
14053
14054 ins_cost(300);
14055 format %{ "j$cop,us $labl" %}
14056 size(2);
14057 ins_encode %{
14058 Label* L = $labl$$label;
14059 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
14060 %}
14061 ins_pipe(pipe_jcc);
14062 ins_short_branch(1);
14063 %}
14064
14065 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
14066 match(If cop cmp);
14067 effect(USE labl);
14068
14069 ins_cost(300);
14070 format %{ $$template
14071 if ($cop$$cmpcode == Assembler::notEqual) {
14072 $$emit$$"jp,u,s $labl\n\t"
14073 $$emit$$"j$cop,u,s $labl"
14074 } else {
14075 $$emit$$"jp,u,s done\n\t"
14076 $$emit$$"j$cop,u,s $labl\n\t"
14077 $$emit$$"done:"
14078 }
14079 %}
14080 size(4);
14081 ins_encode %{
14082 Label* l = $labl$$label;
14083 if ($cop$$cmpcode == Assembler::notEqual) {
14084 __ jccb(Assembler::parity, *l);
14085 __ jccb(Assembler::notEqual, *l);
14086 } else if ($cop$$cmpcode == Assembler::equal) {
14087 Label done;
14088 __ jccb(Assembler::parity, done);
14089 __ jccb(Assembler::equal, *l);
14090 __ bind(done);
14091 } else {
14092 ShouldNotReachHere();
14093 }
14094 %}
14095 ins_pipe(pipe_jcc);
14096 ins_short_branch(1);
14097 %}
14098
14099 // ============================================================================
14100 // inlined locking and unlocking
14101
14102 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{
14103 predicate(LockingMode != LM_LIGHTWEIGHT);
14104 match(Set cr (FastLock object box));
14105 effect(TEMP tmp, TEMP scr, USE_KILL box);
14106 ins_cost(300);
14107 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
14108 ins_encode %{
14109 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
14110 $scr$$Register, noreg, noreg, r15_thread, nullptr);
14111 %}
14112 ins_pipe(pipe_slow);
14113 %}
14114
14115 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
14116 predicate(LockingMode != LM_LIGHTWEIGHT);
14117 match(Set cr (FastUnlock object box));
14118 effect(TEMP tmp, USE_KILL box);
14119 ins_cost(300);
14120 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
14121 ins_encode %{
14122 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register);
14123 %}
14124 ins_pipe(pipe_slow);
14125 %}
14126
14127 instruct cmpFastLockLightweight(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI rax_reg, rRegP tmp) %{
14128 predicate(LockingMode == LM_LIGHTWEIGHT);
14129 match(Set cr (FastLock object box));
14130 effect(TEMP rax_reg, TEMP tmp, USE_KILL box);
14131 ins_cost(300);
14132 format %{ "fastlock $object,$box\t! kills $box,$rax_reg,$tmp" %}
14133 ins_encode %{
14134 __ fast_lock_lightweight($object$$Register, $box$$Register, $rax_reg$$Register, $tmp$$Register, r15_thread);
14135 %}
14136 ins_pipe(pipe_slow);
14137 %}
14138
14139 instruct cmpFastUnlockLightweight(rFlagsReg cr, rRegP object, rax_RegP rax_reg, rRegP tmp) %{
14140 predicate(LockingMode == LM_LIGHTWEIGHT);
14141 match(Set cr (FastUnlock object rax_reg));
14142 effect(TEMP tmp, USE_KILL rax_reg);
14143 ins_cost(300);
14144 format %{ "fastunlock $object,$rax_reg\t! kills $rax_reg,$tmp" %}
14145 ins_encode %{
14146 __ fast_unlock_lightweight($object$$Register, $rax_reg$$Register, $tmp$$Register, r15_thread);
14147 %}
14148 ins_pipe(pipe_slow);
14149 %}
14150
14151
14152 // ============================================================================
14153 // Safepoint Instructions
14154 instruct safePoint_poll_tls(rFlagsReg cr, rRegP poll)
14155 %{
14156 match(SafePoint poll);
14157 effect(KILL cr, USE poll);
14158
14159 format %{ "testl rax, [$poll]\t"
14160 "# Safepoint: poll for GC" %}
14161 ins_cost(125);
14162 ins_encode %{
14163 __ relocate(relocInfo::poll_type);
14164 address pre_pc = __ pc();
14165 __ testl(rax, Address($poll$$Register, 0));
14166 assert(nativeInstruction_at(pre_pc)->is_safepoint_poll(), "must emit test %%eax [reg]");
14167 %}
14168 ins_pipe(ialu_reg_mem);
14169 %}
14170
14171 instruct mask_all_evexL(kReg dst, rRegL src) %{
14172 match(Set dst (MaskAll src));
14173 format %{ "mask_all_evexL $dst, $src \t! mask all operation" %}
14174 ins_encode %{
14175 int mask_len = Matcher::vector_length(this);
14176 __ vector_maskall_operation($dst$$KRegister, $src$$Register, mask_len);
14177 %}
14178 ins_pipe( pipe_slow );
14179 %}
14180
14181 instruct mask_all_evexI_GT32(kReg dst, rRegI src, rRegL tmp) %{
14182 predicate(Matcher::vector_length(n) > 32);
14183 match(Set dst (MaskAll src));
14184 effect(TEMP tmp);
14185 format %{ "mask_all_evexI_GT32 $dst, $src \t! using $tmp as TEMP" %}
14186 ins_encode %{
14187 int mask_len = Matcher::vector_length(this);
14188 __ movslq($tmp$$Register, $src$$Register);
14189 __ vector_maskall_operation($dst$$KRegister, $tmp$$Register, mask_len);
14190 %}
14191 ins_pipe( pipe_slow );
14192 %}
14193
14194 // ============================================================================
14195 // Procedure Call/Return Instructions
14196 // Call Java Static Instruction
14197 // Note: If this code changes, the corresponding ret_addr_offset() and
14198 // compute_padding() functions will have to be adjusted.
14199 instruct CallStaticJavaDirect(method meth) %{
14200 match(CallStaticJava);
14201 effect(USE meth);
14202
14203 ins_cost(300);
14204 format %{ "call,static " %}
14205 opcode(0xE8); /* E8 cd */
14206 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
14207 ins_pipe(pipe_slow);
14208 ins_alignment(4);
14209 %}
14210
14211 // Call Java Dynamic Instruction
14212 // Note: If this code changes, the corresponding ret_addr_offset() and
14213 // compute_padding() functions will have to be adjusted.
14214 instruct CallDynamicJavaDirect(method meth)
14215 %{
14216 match(CallDynamicJava);
14217 effect(USE meth);
14218
14219 ins_cost(300);
14220 format %{ "movq rax, #Universe::non_oop_word()\n\t"
14221 "call,dynamic " %}
14222 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
14223 ins_pipe(pipe_slow);
14224 ins_alignment(4);
14225 %}
14226
14227 // Call Runtime Instruction
14228 instruct CallRuntimeDirect(method meth)
14229 %{
14230 match(CallRuntime);
14231 effect(USE meth);
14232
14233 ins_cost(300);
14234 format %{ "call,runtime " %}
14235 ins_encode(clear_avx, Java_To_Runtime(meth));
14236 ins_pipe(pipe_slow);
14237 %}
14238
14239 // Call runtime without safepoint
14240 instruct CallLeafDirect(method meth)
14241 %{
14242 match(CallLeaf);
14243 effect(USE meth);
14244
14245 ins_cost(300);
14246 format %{ "call_leaf,runtime " %}
14247 ins_encode(clear_avx, Java_To_Runtime(meth));
14248 ins_pipe(pipe_slow);
14249 %}
14250
14251 // Call runtime without safepoint and with vector arguments
14252 instruct CallLeafDirectVector(method meth)
14253 %{
14254 match(CallLeafVector);
14255 effect(USE meth);
14256
14257 ins_cost(300);
14258 format %{ "call_leaf,vector " %}
14259 ins_encode(Java_To_Runtime(meth));
14260 ins_pipe(pipe_slow);
14261 %}
14262
14263 // Call runtime without safepoint
14264 instruct CallLeafNoFPDirect(method meth)
14265 %{
14266 match(CallLeafNoFP);
14267 effect(USE meth);
14268
14269 ins_cost(300);
14270 format %{ "call_leaf_nofp,runtime " %}
14271 ins_encode(clear_avx, Java_To_Runtime(meth));
14272 ins_pipe(pipe_slow);
14273 %}
14274
14275 // Return Instruction
14276 // Remove the return address & jump to it.
14277 // Notice: We always emit a nop after a ret to make sure there is room
14278 // for safepoint patching
14279 instruct Ret()
14280 %{
14281 match(Return);
14282
14283 format %{ "ret" %}
14284 ins_encode %{
14285 __ ret(0);
14286 %}
14287 ins_pipe(pipe_jmp);
14288 %}
14289
14290 // Tail Call; Jump from runtime stub to Java code.
14291 // Also known as an 'interprocedural jump'.
14292 // Target of jump will eventually return to caller.
14293 // TailJump below removes the return address.
14294 // Don't use rbp for 'jump_target' because a MachEpilogNode has already been
14295 // emitted just above the TailCall which has reset rbp to the caller state.
14296 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_ptr)
14297 %{
14298 match(TailCall jump_target method_ptr);
14299
14300 ins_cost(300);
14301 format %{ "jmp $jump_target\t# rbx holds method" %}
14302 ins_encode %{
14303 __ jmp($jump_target$$Register);
14304 %}
14305 ins_pipe(pipe_jmp);
14306 %}
14307
14308 // Tail Jump; remove the return address; jump to target.
14309 // TailCall above leaves the return address around.
14310 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
14311 %{
14312 match(TailJump jump_target ex_oop);
14313
14314 ins_cost(300);
14315 format %{ "popq rdx\t# pop return address\n\t"
14316 "jmp $jump_target" %}
14317 ins_encode %{
14318 __ popq(as_Register(RDX_enc));
14319 __ jmp($jump_target$$Register);
14320 %}
14321 ins_pipe(pipe_jmp);
14322 %}
14323
14324 // Forward exception.
14325 instruct ForwardExceptionjmp()
14326 %{
14327 match(ForwardException);
14328
14329 format %{ "jmp forward_exception_stub" %}
14330 ins_encode %{
14331 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()), noreg);
14332 %}
14333 ins_pipe(pipe_jmp);
14334 %}
14335
14336 // Create exception oop: created by stack-crawling runtime code.
14337 // Created exception is now available to this handler, and is setup
14338 // just prior to jumping to this handler. No code emitted.
14339 instruct CreateException(rax_RegP ex_oop)
14340 %{
14341 match(Set ex_oop (CreateEx));
14342
14343 size(0);
14344 // use the following format syntax
14345 format %{ "# exception oop is in rax; no code emitted" %}
14346 ins_encode();
14347 ins_pipe(empty);
14348 %}
14349
14350 // Rethrow exception:
14351 // The exception oop will come in the first argument position.
14352 // Then JUMP (not call) to the rethrow stub code.
14353 instruct RethrowException()
14354 %{
14355 match(Rethrow);
14356
14357 // use the following format syntax
14358 format %{ "jmp rethrow_stub" %}
14359 ins_encode %{
14360 __ jump(RuntimeAddress(OptoRuntime::rethrow_stub()), noreg);
14361 %}
14362 ins_pipe(pipe_jmp);
14363 %}
14364
14365 // ============================================================================
14366 // This name is KNOWN by the ADLC and cannot be changed.
14367 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
14368 // for this guy.
14369 instruct tlsLoadP(r15_RegP dst) %{
14370 match(Set dst (ThreadLocal));
14371 effect(DEF dst);
14372
14373 size(0);
14374 format %{ "# TLS is in R15" %}
14375 ins_encode( /*empty encoding*/ );
14376 ins_pipe(ialu_reg_reg);
14377 %}
14378
14379
14380 //----------PEEPHOLE RULES-----------------------------------------------------
14381 // These must follow all instruction definitions as they use the names
14382 // defined in the instructions definitions.
14383 //
14384 // peeppredicate ( rule_predicate );
14385 // // the predicate unless which the peephole rule will be ignored
14386 //
14387 // peepmatch ( root_instr_name [preceding_instruction]* );
14388 //
14389 // peepprocedure ( procedure_name );
14390 // // provide a procedure name to perform the optimization, the procedure should
14391 // // reside in the architecture dependent peephole file, the method has the
14392 // // signature of MachNode* (Block*, int, PhaseRegAlloc*, (MachNode*)(*)(), int...)
14393 // // with the arguments being the basic block, the current node index inside the
14394 // // block, the register allocator, the functions upon invoked return a new node
14395 // // defined in peepreplace, and the rules of the nodes appearing in the
14396 // // corresponding peepmatch, the function return true if successful, else
14397 // // return false
14398 //
14399 // peepconstraint %{
14400 // (instruction_number.operand_name relational_op instruction_number.operand_name
14401 // [, ...] );
14402 // // instruction numbers are zero-based using left to right order in peepmatch
14403 //
14404 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
14405 // // provide an instruction_number.operand_name for each operand that appears
14406 // // in the replacement instruction's match rule
14407 //
14408 // ---------VM FLAGS---------------------------------------------------------
14409 //
14410 // All peephole optimizations can be turned off using -XX:-OptoPeephole
14411 //
14412 // Each peephole rule is given an identifying number starting with zero and
14413 // increasing by one in the order seen by the parser. An individual peephole
14414 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
14415 // on the command-line.
14416 //
14417 // ---------CURRENT LIMITATIONS----------------------------------------------
14418 //
14419 // Only transformations inside a basic block (do we need more for peephole)
14420 //
14421 // ---------EXAMPLE----------------------------------------------------------
14422 //
14423 // // pertinent parts of existing instructions in architecture description
14424 // instruct movI(rRegI dst, rRegI src)
14425 // %{
14426 // match(Set dst (CopyI src));
14427 // %}
14428 //
14429 // instruct incI_rReg(rRegI dst, immI_1 src, rFlagsReg cr)
14430 // %{
14431 // match(Set dst (AddI dst src));
14432 // effect(KILL cr);
14433 // %}
14434 //
14435 // instruct leaI_rReg_immI(rRegI dst, immI_1 src)
14436 // %{
14437 // match(Set dst (AddI dst src));
14438 // %}
14439 //
14440 // 1. Simple replacement
14441 // - Only match adjacent instructions in same basic block
14442 // - Only equality constraints
14443 // - Only constraints between operands, not (0.dest_reg == RAX_enc)
14444 // - Only one replacement instruction
14445 //
14446 // // Change (inc mov) to lea
14447 // peephole %{
14448 // // lea should only be emitted when beneficial
14449 // peeppredicate( VM_Version::supports_fast_2op_lea() );
14450 // // increment preceded by register-register move
14451 // peepmatch ( incI_rReg movI );
14452 // // require that the destination register of the increment
14453 // // match the destination register of the move
14454 // peepconstraint ( 0.dst == 1.dst );
14455 // // construct a replacement instruction that sets
14456 // // the destination to ( move's source register + one )
14457 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
14458 // %}
14459 //
14460 // 2. Procedural replacement
14461 // - More flexible finding relevent nodes
14462 // - More flexible constraints
14463 // - More flexible transformations
14464 // - May utilise architecture-dependent API more effectively
14465 // - Currently only one replacement instruction due to adlc parsing capabilities
14466 //
14467 // // Change (inc mov) to lea
14468 // peephole %{
14469 // // lea should only be emitted when beneficial
14470 // peeppredicate( VM_Version::supports_fast_2op_lea() );
14471 // // the rule numbers of these nodes inside are passed into the function below
14472 // peepmatch ( incI_rReg movI );
14473 // // the method that takes the responsibility of transformation
14474 // peepprocedure ( inc_mov_to_lea );
14475 // // the replacement is a leaI_rReg_immI, a lambda upon invoked creating this
14476 // // node is passed into the function above
14477 // peepreplace ( leaI_rReg_immI() );
14478 // %}
14479
14480 // These instructions is not matched by the matcher but used by the peephole
14481 instruct leaI_rReg_rReg_peep(rRegI dst, rRegI src1, rRegI src2)
14482 %{
14483 predicate(false);
14484 match(Set dst (AddI src1 src2));
14485 format %{ "leal $dst, [$src1 + $src2]" %}
14486 ins_encode %{
14487 Register dst = $dst$$Register;
14488 Register src1 = $src1$$Register;
14489 Register src2 = $src2$$Register;
14490 if (src1 != rbp && src1 != r13) {
14491 __ leal(dst, Address(src1, src2, Address::times_1));
14492 } else {
14493 assert(src2 != rbp && src2 != r13, "");
14494 __ leal(dst, Address(src2, src1, Address::times_1));
14495 }
14496 %}
14497 ins_pipe(ialu_reg_reg);
14498 %}
14499
14500 instruct leaI_rReg_immI_peep(rRegI dst, rRegI src1, immI src2)
14501 %{
14502 predicate(false);
14503 match(Set dst (AddI src1 src2));
14504 format %{ "leal $dst, [$src1 + $src2]" %}
14505 ins_encode %{
14506 __ leal($dst$$Register, Address($src1$$Register, $src2$$constant));
14507 %}
14508 ins_pipe(ialu_reg_reg);
14509 %}
14510
14511 instruct leaI_rReg_immI2_peep(rRegI dst, rRegI src, immI2 shift)
14512 %{
14513 predicate(false);
14514 match(Set dst (LShiftI src shift));
14515 format %{ "leal $dst, [$src << $shift]" %}
14516 ins_encode %{
14517 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($shift$$constant);
14518 Register src = $src$$Register;
14519 if (scale == Address::times_2 && src != rbp && src != r13) {
14520 __ leal($dst$$Register, Address(src, src, Address::times_1));
14521 } else {
14522 __ leal($dst$$Register, Address(noreg, src, scale));
14523 }
14524 %}
14525 ins_pipe(ialu_reg_reg);
14526 %}
14527
14528 instruct leaL_rReg_rReg_peep(rRegL dst, rRegL src1, rRegL src2)
14529 %{
14530 predicate(false);
14531 match(Set dst (AddL src1 src2));
14532 format %{ "leaq $dst, [$src1 + $src2]" %}
14533 ins_encode %{
14534 Register dst = $dst$$Register;
14535 Register src1 = $src1$$Register;
14536 Register src2 = $src2$$Register;
14537 if (src1 != rbp && src1 != r13) {
14538 __ leaq(dst, Address(src1, src2, Address::times_1));
14539 } else {
14540 assert(src2 != rbp && src2 != r13, "");
14541 __ leaq(dst, Address(src2, src1, Address::times_1));
14542 }
14543 %}
14544 ins_pipe(ialu_reg_reg);
14545 %}
14546
14547 instruct leaL_rReg_immL32_peep(rRegL dst, rRegL src1, immL32 src2)
14548 %{
14549 predicate(false);
14550 match(Set dst (AddL src1 src2));
14551 format %{ "leaq $dst, [$src1 + $src2]" %}
14552 ins_encode %{
14553 __ leaq($dst$$Register, Address($src1$$Register, $src2$$constant));
14554 %}
14555 ins_pipe(ialu_reg_reg);
14556 %}
14557
14558 instruct leaL_rReg_immI2_peep(rRegL dst, rRegL src, immI2 shift)
14559 %{
14560 predicate(false);
14561 match(Set dst (LShiftL src shift));
14562 format %{ "leaq $dst, [$src << $shift]" %}
14563 ins_encode %{
14564 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($shift$$constant);
14565 Register src = $src$$Register;
14566 if (scale == Address::times_2 && src != rbp && src != r13) {
14567 __ leaq($dst$$Register, Address(src, src, Address::times_1));
14568 } else {
14569 __ leaq($dst$$Register, Address(noreg, src, scale));
14570 }
14571 %}
14572 ins_pipe(ialu_reg_reg);
14573 %}
14574
14575 // These peephole rules replace mov + I pairs (where I is one of {add, inc, dec,
14576 // sal}) with lea instructions. The {add, sal} rules are beneficial in
14577 // processors with at least partial ALU support for lea
14578 // (supports_fast_2op_lea()), whereas the {inc, dec} rules are only generally
14579 // beneficial for processors with full ALU support
14580 // (VM_Version::supports_fast_3op_lea()) and Intel Cascade Lake.
14581
14582 peephole
14583 %{
14584 peeppredicate(VM_Version::supports_fast_2op_lea());
14585 peepmatch (addI_rReg);
14586 peepprocedure (lea_coalesce_reg);
14587 peepreplace (leaI_rReg_rReg_peep());
14588 %}
14589
14590 peephole
14591 %{
14592 peeppredicate(VM_Version::supports_fast_2op_lea());
14593 peepmatch (addI_rReg_imm);
14594 peepprocedure (lea_coalesce_imm);
14595 peepreplace (leaI_rReg_immI_peep());
14596 %}
14597
14598 peephole
14599 %{
14600 peeppredicate(VM_Version::supports_fast_3op_lea() ||
14601 VM_Version::is_intel_cascade_lake());
14602 peepmatch (incI_rReg);
14603 peepprocedure (lea_coalesce_imm);
14604 peepreplace (leaI_rReg_immI_peep());
14605 %}
14606
14607 peephole
14608 %{
14609 peeppredicate(VM_Version::supports_fast_3op_lea() ||
14610 VM_Version::is_intel_cascade_lake());
14611 peepmatch (decI_rReg);
14612 peepprocedure (lea_coalesce_imm);
14613 peepreplace (leaI_rReg_immI_peep());
14614 %}
14615
14616 peephole
14617 %{
14618 peeppredicate(VM_Version::supports_fast_2op_lea());
14619 peepmatch (salI_rReg_immI2);
14620 peepprocedure (lea_coalesce_imm);
14621 peepreplace (leaI_rReg_immI2_peep());
14622 %}
14623
14624 peephole
14625 %{
14626 peeppredicate(VM_Version::supports_fast_2op_lea());
14627 peepmatch (addL_rReg);
14628 peepprocedure (lea_coalesce_reg);
14629 peepreplace (leaL_rReg_rReg_peep());
14630 %}
14631
14632 peephole
14633 %{
14634 peeppredicate(VM_Version::supports_fast_2op_lea());
14635 peepmatch (addL_rReg_imm);
14636 peepprocedure (lea_coalesce_imm);
14637 peepreplace (leaL_rReg_immL32_peep());
14638 %}
14639
14640 peephole
14641 %{
14642 peeppredicate(VM_Version::supports_fast_3op_lea() ||
14643 VM_Version::is_intel_cascade_lake());
14644 peepmatch (incL_rReg);
14645 peepprocedure (lea_coalesce_imm);
14646 peepreplace (leaL_rReg_immL32_peep());
14647 %}
14648
14649 peephole
14650 %{
14651 peeppredicate(VM_Version::supports_fast_3op_lea() ||
14652 VM_Version::is_intel_cascade_lake());
14653 peepmatch (decL_rReg);
14654 peepprocedure (lea_coalesce_imm);
14655 peepreplace (leaL_rReg_immL32_peep());
14656 %}
14657
14658 peephole
14659 %{
14660 peeppredicate(VM_Version::supports_fast_2op_lea());
14661 peepmatch (salL_rReg_immI2);
14662 peepprocedure (lea_coalesce_imm);
14663 peepreplace (leaL_rReg_immI2_peep());
14664 %}
14665
14666 // These peephole rules matches instructions which set flags and are followed by a testI/L_reg
14667 // The test instruction is redudanent in case the downstream instuctions (like JCC or CMOV) only use flags that are already set by the previous instruction
14668
14669 //int variant
14670 peephole
14671 %{
14672 peepmatch (testI_reg);
14673 peepprocedure (test_may_remove);
14674 %}
14675
14676 //long variant
14677 peephole
14678 %{
14679 peepmatch (testL_reg);
14680 peepprocedure (test_may_remove);
14681 %}
14682
14683
14684 //----------SMARTSPILL RULES---------------------------------------------------
14685 // These must follow all instruction definitions as they use the names
14686 // defined in the instructions definitions.