1 /*
2 * Copyright (c) 2020, 2024, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
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23 */
24
25 #ifndef CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP
26 #define CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP
27
28 // C2_MacroAssembler contains high-level macros for C2
29
30 private:
31 // Return true if the phase output is in the scratch emit size mode.
32 virtual bool in_scratch_emit_size() override;
33
34 void neon_reduce_logical_helper(int opc, bool sf, Register Rd, Register Rn, Register Rm,
35 enum shift_kind kind = Assembler::LSL, unsigned shift = 0);
36
37 public:
38 // jdk.internal.util.ArraysSupport.vectorizedHashCode
39 address arrays_hashcode(Register ary, Register cnt, Register result, FloatRegister vdata0,
40 FloatRegister vdata1, FloatRegister vdata2, FloatRegister vdata3,
41 FloatRegister vmul0, FloatRegister vmul1, FloatRegister vmul2,
42 FloatRegister vmul3, FloatRegister vpow, FloatRegister vpowm,
43 BasicType eltype);
44
45 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
46 void fast_lock(Register object, Register box, Register tmp, Register tmp2, Register tmp3);
47 void fast_unlock(Register object, Register box, Register tmp, Register tmp2);
48 // Code used by cmpFastLockLightweight and cmpFastUnlockLightweight mach instructions in .ad file.
49 void fast_lock_lightweight(Register object, Register box, Register t1, Register t2, Register t3);
50 void fast_unlock_lightweight(Register object, Register box, Register t1, Register t2, Register t3);
51
52 void string_compare(Register str1, Register str2,
53 Register cnt1, Register cnt2, Register result,
54 Register tmp1, Register tmp2, FloatRegister vtmp1,
55 FloatRegister vtmp2, FloatRegister vtmp3,
56 PRegister pgtmp1, PRegister pgtmp2, int ae);
57
58 void string_indexof(Register str1, Register str2,
59 Register cnt1, Register cnt2,
60 Register tmp1, Register tmp2,
61 Register tmp3, Register tmp4,
62 Register tmp5, Register tmp6,
63 int int_cnt1, Register result, int ae);
64
65 void string_indexof_char(Register str1, Register cnt1,
66 Register ch, Register result,
67 Register tmp1, Register tmp2, Register tmp3);
68
69 void stringL_indexof_char(Register str1, Register cnt1,
70 Register ch, Register result,
71 Register tmp1, Register tmp2, Register tmp3);
72
73 void string_indexof_char_sve(Register str1, Register cnt1,
74 Register ch, Register result,
75 FloatRegister ztmp1, FloatRegister ztmp2,
76 PRegister pgtmp, PRegister ptmp, bool isL);
77
78 // Compress the least significant bit of each byte to the rightmost and clear
79 // the higher garbage bits.
80 void bytemask_compress(Register dst);
81
82 // Pack the lowest-numbered bit of each mask element in src into a long value
83 // in dst, at most the first 64 lane elements.
84 void sve_vmask_tolong(Register dst, PRegister src, BasicType bt, int lane_cnt,
85 FloatRegister vtmp1, FloatRegister vtmp2);
86
87 // Unpack the mask, a long value in src, into predicate register dst based on the
88 // corresponding data type. Note that dst can support at most 64 lanes.
89 void sve_vmask_fromlong(PRegister dst, Register src, BasicType bt, int lane_cnt,
90 FloatRegister vtmp1, FloatRegister vtmp2);
91
92 // SIMD&FP comparison
93 void neon_compare(FloatRegister dst, BasicType bt, FloatRegister src1,
94 FloatRegister src2, Condition cond, bool isQ);
95
96 void neon_compare_zero(FloatRegister dst, BasicType bt, FloatRegister src,
97 Condition cond, bool isQ);
98
99 void sve_compare(PRegister pd, BasicType bt, PRegister pg,
100 FloatRegister zn, FloatRegister zm, Condition cond);
101
102 void sve_vmask_lasttrue(Register dst, BasicType bt, PRegister src, PRegister ptmp);
103
104 // Vector cast
105 void neon_vector_extend(FloatRegister dst, BasicType dst_bt, unsigned dst_vlen_in_bytes,
106 FloatRegister src, BasicType src_bt, bool is_unsigned = false);
107
108 void neon_vector_narrow(FloatRegister dst, BasicType dst_bt,
109 FloatRegister src, BasicType src_bt, unsigned src_vlen_in_bytes);
110
111 void sve_vector_extend(FloatRegister dst, SIMD_RegVariant dst_size,
112 FloatRegister src, SIMD_RegVariant src_size, bool is_unsigned = false);
113
114 void sve_vector_narrow(FloatRegister dst, SIMD_RegVariant dst_size,
115 FloatRegister src, SIMD_RegVariant src_size, FloatRegister tmp);
116
117 void sve_vmaskcast_extend(PRegister dst, PRegister src,
118 uint dst_element_length_in_bytes, uint src_element_lenght_in_bytes);
119
120 void sve_vmaskcast_narrow(PRegister dst, PRegister src, PRegister ptmp,
121 uint dst_element_length_in_bytes, uint src_element_lenght_in_bytes);
122
123 // Vector reduction
124 void neon_reduce_add_integral(Register dst, BasicType bt,
125 Register isrc, FloatRegister vsrc,
126 unsigned vector_length_in_bytes, FloatRegister vtmp);
127
128 void neon_reduce_mul_integral(Register dst, BasicType bt,
129 Register isrc, FloatRegister vsrc,
130 unsigned vector_length_in_bytes,
131 FloatRegister vtmp1, FloatRegister vtmp2);
132
133 void neon_reduce_mul_fp(FloatRegister dst, BasicType bt,
134 FloatRegister fsrc, FloatRegister vsrc,
135 unsigned vector_length_in_bytes, FloatRegister vtmp);
136
137 void neon_reduce_logical(int opc, Register dst, BasicType bt, Register isrc,
138 FloatRegister vsrc, unsigned vector_length_in_bytes);
139
140 void neon_reduce_minmax_integral(int opc, Register dst, BasicType bt,
141 Register isrc, FloatRegister vsrc,
142 unsigned vector_length_in_bytes, FloatRegister vtmp);
143
144 void sve_reduce_integral(int opc, Register dst, BasicType bt, Register src1,
145 FloatRegister src2, PRegister pg, FloatRegister tmp);
146
147 // Set elements of the dst predicate to true for lanes in the range of
148 // [0, lane_cnt), or to false otherwise. The input "lane_cnt" should be
149 // smaller than or equal to the supported max vector length of the basic
150 // type. Clobbers: rscratch1 and the rFlagsReg.
151 void sve_gen_mask_imm(PRegister dst, BasicType bt, uint32_t lane_cnt);
152
153 // Extract a scalar element from an sve vector at position 'idx'.
154 // The input elements in src are expected to be of integral type.
155 void sve_extract_integral(Register dst, BasicType bt, FloatRegister src,
156 int idx, FloatRegister vtmp);
157
158 // java.lang.Math::round intrinsics
159 void vector_round_neon(FloatRegister dst, FloatRegister src, FloatRegister tmp1,
160 FloatRegister tmp2, FloatRegister tmp3,
161 SIMD_Arrangement T);
162 void vector_round_sve(FloatRegister dst, FloatRegister src, FloatRegister tmp1,
163 FloatRegister tmp2, PRegister pgtmp,
164 SIMD_RegVariant T);
165
166 // Pack active elements of src, under the control of mask, into the
167 // lowest-numbered elements of dst. Any remaining elements of dst will
168 // be filled with zero.
169 void sve_compress_byte(FloatRegister dst, FloatRegister src, PRegister mask,
170 FloatRegister vtmp1, FloatRegister vtmp2,
171 FloatRegister vtmp3, FloatRegister vtmp4,
172 PRegister ptmp, PRegister pgtmp);
173
174 void sve_compress_short(FloatRegister dst, FloatRegister src, PRegister mask,
175 FloatRegister vtmp1, FloatRegister vtmp2,
176 PRegister pgtmp);
177
178 void neon_reverse_bits(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ);
179
180 void neon_reverse_bytes(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ);
181
182 // java.lang.Math::signum intrinsics
183 void vector_signum_neon(FloatRegister dst, FloatRegister src, FloatRegister zero,
184 FloatRegister one, SIMD_Arrangement T);
185
186 void vector_signum_sve(FloatRegister dst, FloatRegister src, FloatRegister zero,
187 FloatRegister one, FloatRegister vtmp, PRegister pgtmp, SIMD_RegVariant T);
188
189 #endif // CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP