18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP
26 #define CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP
27
28 // C2_MacroAssembler contains high-level macros for C2
29
30 private:
31 // Return true if the phase output is in the scratch emit size mode.
32 virtual bool in_scratch_emit_size() override;
33
34 void neon_reduce_logical_helper(int opc, bool sf, Register Rd, Register Rn, Register Rm,
35 enum shift_kind kind = Assembler::LSL, unsigned shift = 0);
36
37 public:
38 // jdk.internal.util.ArraysSupport.vectorizedHashCode
39 address arrays_hashcode(Register ary, Register cnt, Register result, FloatRegister vdata0,
40 FloatRegister vdata1, FloatRegister vdata2, FloatRegister vdata3,
41 FloatRegister vmul0, FloatRegister vmul1, FloatRegister vmul2,
42 FloatRegister vmul3, FloatRegister vpow, FloatRegister vpowm,
43 BasicType eltype);
44
45 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
46 void fast_lock(Register object, Register box, Register tmp, Register tmp2, Register tmp3);
47 void fast_unlock(Register object, Register box, Register tmp, Register tmp2);
48 // Code used by cmpFastLockLightweight and cmpFastUnlockLightweight mach instructions in .ad file.
49 void fast_lock_lightweight(Register object, Register box, Register t1, Register t2, Register t3);
50 void fast_unlock_lightweight(Register object, Register box, Register t1, Register t2, Register t3);
51
52 void string_compare(Register str1, Register str2,
53 Register cnt1, Register cnt2, Register result,
54 Register tmp1, Register tmp2, FloatRegister vtmp1,
55 FloatRegister vtmp2, FloatRegister vtmp3,
56 PRegister pgtmp1, PRegister pgtmp2, int ae);
57
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18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP
26 #define CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP
27
28 // C2_MacroAssembler contains high-level macros for C2
29
30 private:
31 // Return true if the phase output is in the scratch emit size mode.
32 virtual bool in_scratch_emit_size() override;
33
34 void neon_reduce_logical_helper(int opc, bool sf, Register Rd, Register Rn, Register Rm,
35 enum shift_kind kind = Assembler::LSL, unsigned shift = 0);
36
37 public:
38 void entry_barrier();
39
40 // jdk.internal.util.ArraysSupport.vectorizedHashCode
41 address arrays_hashcode(Register ary, Register cnt, Register result, FloatRegister vdata0,
42 FloatRegister vdata1, FloatRegister vdata2, FloatRegister vdata3,
43 FloatRegister vmul0, FloatRegister vmul1, FloatRegister vmul2,
44 FloatRegister vmul3, FloatRegister vpow, FloatRegister vpowm,
45 BasicType eltype);
46
47 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
48 void fast_lock(Register object, Register box, Register tmp, Register tmp2, Register tmp3);
49 void fast_unlock(Register object, Register box, Register tmp, Register tmp2);
50 // Code used by cmpFastLockLightweight and cmpFastUnlockLightweight mach instructions in .ad file.
51 void fast_lock_lightweight(Register object, Register box, Register t1, Register t2, Register t3);
52 void fast_unlock_lightweight(Register object, Register box, Register t1, Register t2, Register t3);
53
54 void string_compare(Register str1, Register str2,
55 Register cnt1, Register cnt2, Register result,
56 Register tmp1, Register tmp2, FloatRegister vtmp1,
57 FloatRegister vtmp2, FloatRegister vtmp3,
58 PRegister pgtmp1, PRegister pgtmp2, int ae);
59
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