1 /*
2 * Copyright (c) 1997, 2024, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "code/compiledIC.hpp"
29 #include "compiler/compiler_globals.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "crc32c.h"
32 #include "gc/shared/barrierSet.hpp"
33 #include "gc/shared/barrierSetAssembler.hpp"
34 #include "gc/shared/collectedHeap.inline.hpp"
35 #include "gc/shared/tlab_globals.hpp"
36 #include "interpreter/bytecodeHistogram.hpp"
37 #include "interpreter/interpreter.hpp"
38 #include "jvm.h"
39 #include "memory/resourceArea.hpp"
40 #include "memory/universe.hpp"
41 #include "oops/accessDecorators.hpp"
42 #include "oops/compressedKlass.inline.hpp"
43 #include "oops/compressedOops.inline.hpp"
44 #include "oops/klass.inline.hpp"
45 #include "prims/methodHandles.hpp"
46 #include "runtime/continuation.hpp"
47 #include "runtime/interfaceSupport.inline.hpp"
48 #include "runtime/javaThread.hpp"
49 #include "runtime/jniHandles.hpp"
50 #include "runtime/objectMonitor.hpp"
51 #include "runtime/os.hpp"
52 #include "runtime/safepoint.hpp"
53 #include "runtime/safepointMechanism.hpp"
54 #include "runtime/sharedRuntime.hpp"
55 #include "runtime/stubRoutines.hpp"
56 #include "utilities/checkedCast.hpp"
57 #include "utilities/macros.hpp"
58
59 #ifdef PRODUCT
60 #define BLOCK_COMMENT(str) /* nothing */
61 #define STOP(error) stop(error)
62 #else
63 #define BLOCK_COMMENT(str) block_comment(str)
64 #define STOP(error) block_comment(error); stop(error)
65 #endif
66
67 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
68
69 #ifdef ASSERT
70 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
71 #endif
72
73 static const Assembler::Condition reverse[] = {
74 Assembler::noOverflow /* overflow = 0x0 */ ,
75 Assembler::overflow /* noOverflow = 0x1 */ ,
76 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
77 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
78 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
79 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
80 Assembler::above /* belowEqual = 0x6 */ ,
81 Assembler::belowEqual /* above = 0x7 */ ,
82 Assembler::positive /* negative = 0x8 */ ,
83 Assembler::negative /* positive = 0x9 */ ,
84 Assembler::noParity /* parity = 0xa */ ,
85 Assembler::parity /* noParity = 0xb */ ,
86 Assembler::greaterEqual /* less = 0xc */ ,
87 Assembler::less /* greaterEqual = 0xd */ ,
88 Assembler::greater /* lessEqual = 0xe */ ,
89 Assembler::lessEqual /* greater = 0xf, */
90
91 };
92
93
94 // Implementation of MacroAssembler
95
96 // First all the versions that have distinct versions depending on 32/64 bit
97 // Unless the difference is trivial (1 line or so).
98
99 #ifndef _LP64
100
101 // 32bit versions
102
103 Address MacroAssembler::as_Address(AddressLiteral adr) {
104 return Address(adr.target(), adr.rspec());
105 }
106
107 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
108 assert(rscratch == noreg, "");
109 return Address::make_array(adr);
110 }
111
112 void MacroAssembler::call_VM_leaf_base(address entry_point,
113 int number_of_arguments) {
114 call(RuntimeAddress(entry_point));
115 increment(rsp, number_of_arguments * wordSize);
116 }
117
118 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
119 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
120 }
121
122
123 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
124 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
125 }
126
127 void MacroAssembler::cmpoop(Address src1, jobject obj) {
128 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
129 }
130
131 void MacroAssembler::cmpoop(Register src1, jobject obj, Register rscratch) {
132 assert(rscratch == noreg, "redundant");
133 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
134 }
135
136 void MacroAssembler::extend_sign(Register hi, Register lo) {
137 // According to Intel Doc. AP-526, "Integer Divide", p.18.
138 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
139 cdql();
140 } else {
141 movl(hi, lo);
142 sarl(hi, 31);
143 }
144 }
145
146 void MacroAssembler::jC2(Register tmp, Label& L) {
147 // set parity bit if FPU flag C2 is set (via rax)
148 save_rax(tmp);
149 fwait(); fnstsw_ax();
150 sahf();
151 restore_rax(tmp);
152 // branch
153 jcc(Assembler::parity, L);
154 }
155
156 void MacroAssembler::jnC2(Register tmp, Label& L) {
157 // set parity bit if FPU flag C2 is set (via rax)
158 save_rax(tmp);
159 fwait(); fnstsw_ax();
160 sahf();
161 restore_rax(tmp);
162 // branch
163 jcc(Assembler::noParity, L);
164 }
165
166 // 32bit can do a case table jump in one instruction but we no longer allow the base
167 // to be installed in the Address class
168 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
169 assert(rscratch == noreg, "not needed");
170 jmp(as_Address(entry, noreg));
171 }
172
173 // Note: y_lo will be destroyed
174 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
175 // Long compare for Java (semantics as described in JVM spec.)
176 Label high, low, done;
177
178 cmpl(x_hi, y_hi);
179 jcc(Assembler::less, low);
180 jcc(Assembler::greater, high);
181 // x_hi is the return register
182 xorl(x_hi, x_hi);
183 cmpl(x_lo, y_lo);
184 jcc(Assembler::below, low);
185 jcc(Assembler::equal, done);
186
187 bind(high);
188 xorl(x_hi, x_hi);
189 increment(x_hi);
190 jmp(done);
191
192 bind(low);
193 xorl(x_hi, x_hi);
194 decrementl(x_hi);
195
196 bind(done);
197 }
198
199 void MacroAssembler::lea(Register dst, AddressLiteral src) {
200 mov_literal32(dst, (int32_t)src.target(), src.rspec());
201 }
202
203 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
204 assert(rscratch == noreg, "not needed");
205
206 // leal(dst, as_Address(adr));
207 // see note in movl as to why we must use a move
208 mov_literal32(dst, (int32_t)adr.target(), adr.rspec());
209 }
210
211 void MacroAssembler::leave() {
212 mov(rsp, rbp);
213 pop(rbp);
214 }
215
216 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
217 // Multiplication of two Java long values stored on the stack
218 // as illustrated below. Result is in rdx:rax.
219 //
220 // rsp ---> [ ?? ] \ \
221 // .... | y_rsp_offset |
222 // [ y_lo ] / (in bytes) | x_rsp_offset
223 // [ y_hi ] | (in bytes)
224 // .... |
225 // [ x_lo ] /
226 // [ x_hi ]
227 // ....
228 //
229 // Basic idea: lo(result) = lo(x_lo * y_lo)
230 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
231 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
232 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
233 Label quick;
234 // load x_hi, y_hi and check if quick
235 // multiplication is possible
236 movl(rbx, x_hi);
237 movl(rcx, y_hi);
238 movl(rax, rbx);
239 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
240 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
241 // do full multiplication
242 // 1st step
243 mull(y_lo); // x_hi * y_lo
244 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
245 // 2nd step
246 movl(rax, x_lo);
247 mull(rcx); // x_lo * y_hi
248 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
249 // 3rd step
250 bind(quick); // note: rbx, = 0 if quick multiply!
251 movl(rax, x_lo);
252 mull(y_lo); // x_lo * y_lo
253 addl(rdx, rbx); // correct hi(x_lo * y_lo)
254 }
255
256 void MacroAssembler::lneg(Register hi, Register lo) {
257 negl(lo);
258 adcl(hi, 0);
259 negl(hi);
260 }
261
262 void MacroAssembler::lshl(Register hi, Register lo) {
263 // Java shift left long support (semantics as described in JVM spec., p.305)
264 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
265 // shift value is in rcx !
266 assert(hi != rcx, "must not use rcx");
267 assert(lo != rcx, "must not use rcx");
268 const Register s = rcx; // shift count
269 const int n = BitsPerWord;
270 Label L;
271 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
272 cmpl(s, n); // if (s < n)
273 jcc(Assembler::less, L); // else (s >= n)
274 movl(hi, lo); // x := x << n
275 xorl(lo, lo);
276 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
277 bind(L); // s (mod n) < n
278 shldl(hi, lo); // x := x << s
279 shll(lo);
280 }
281
282
283 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
284 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
285 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
286 assert(hi != rcx, "must not use rcx");
287 assert(lo != rcx, "must not use rcx");
288 const Register s = rcx; // shift count
289 const int n = BitsPerWord;
290 Label L;
291 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
292 cmpl(s, n); // if (s < n)
293 jcc(Assembler::less, L); // else (s >= n)
294 movl(lo, hi); // x := x >> n
295 if (sign_extension) sarl(hi, 31);
296 else xorl(hi, hi);
297 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
298 bind(L); // s (mod n) < n
299 shrdl(lo, hi); // x := x >> s
300 if (sign_extension) sarl(hi);
301 else shrl(hi);
302 }
303
304 void MacroAssembler::movoop(Register dst, jobject obj) {
305 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
306 }
307
308 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
309 assert(rscratch == noreg, "redundant");
310 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
311 }
312
313 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
314 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
315 }
316
317 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
318 assert(rscratch == noreg, "redundant");
319 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
320 }
321
322 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
323 if (src.is_lval()) {
324 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
325 } else {
326 movl(dst, as_Address(src));
327 }
328 }
329
330 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
331 assert(rscratch == noreg, "redundant");
332 movl(as_Address(dst, noreg), src);
333 }
334
335 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
336 movl(dst, as_Address(src, noreg));
337 }
338
339 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
340 assert(rscratch == noreg, "redundant");
341 movl(dst, src);
342 }
343
344 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
345 assert(rscratch == noreg, "redundant");
346 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
347 }
348
349 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
350 assert(rscratch == noreg, "redundant");
351 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
352 }
353
354 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
355 assert(rscratch == noreg, "redundant");
356 if (src.is_lval()) {
357 push_literal32((int32_t)src.target(), src.rspec());
358 } else {
359 pushl(as_Address(src));
360 }
361 }
362
363 static void pass_arg0(MacroAssembler* masm, Register arg) {
364 masm->push(arg);
365 }
366
367 static void pass_arg1(MacroAssembler* masm, Register arg) {
368 masm->push(arg);
369 }
370
371 static void pass_arg2(MacroAssembler* masm, Register arg) {
372 masm->push(arg);
373 }
374
375 static void pass_arg3(MacroAssembler* masm, Register arg) {
376 masm->push(arg);
377 }
378
379 #ifndef PRODUCT
380 extern "C" void findpc(intptr_t x);
381 #endif
382
383 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
384 // In order to get locks to work, we need to fake a in_VM state
385 JavaThread* thread = JavaThread::current();
386 JavaThreadState saved_state = thread->thread_state();
387 thread->set_thread_state(_thread_in_vm);
388 if (ShowMessageBoxOnError) {
389 JavaThread* thread = JavaThread::current();
390 JavaThreadState saved_state = thread->thread_state();
391 thread->set_thread_state(_thread_in_vm);
392 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
393 ttyLocker ttyl;
394 BytecodeCounter::print();
395 }
396 // To see where a verify_oop failed, get $ebx+40/X for this frame.
397 // This is the value of eip which points to where verify_oop will return.
398 if (os::message_box(msg, "Execution stopped, print registers?")) {
399 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
400 BREAKPOINT;
401 }
402 }
403 fatal("DEBUG MESSAGE: %s", msg);
404 }
405
406 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
407 ttyLocker ttyl;
408 DebuggingContext debugging{};
409 tty->print_cr("eip = 0x%08x", eip);
410 #ifndef PRODUCT
411 if ((WizardMode || Verbose) && PrintMiscellaneous) {
412 tty->cr();
413 findpc(eip);
414 tty->cr();
415 }
416 #endif
417 #define PRINT_REG(rax) \
418 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
419 PRINT_REG(rax);
420 PRINT_REG(rbx);
421 PRINT_REG(rcx);
422 PRINT_REG(rdx);
423 PRINT_REG(rdi);
424 PRINT_REG(rsi);
425 PRINT_REG(rbp);
426 PRINT_REG(rsp);
427 #undef PRINT_REG
428 // Print some words near top of staack.
429 int* dump_sp = (int*) rsp;
430 for (int col1 = 0; col1 < 8; col1++) {
431 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
432 os::print_location(tty, *dump_sp++);
433 }
434 for (int row = 0; row < 16; row++) {
435 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
436 for (int col = 0; col < 8; col++) {
437 tty->print(" 0x%08x", *dump_sp++);
438 }
439 tty->cr();
440 }
441 // Print some instructions around pc:
442 Disassembler::decode((address)eip-64, (address)eip);
443 tty->print_cr("--------");
444 Disassembler::decode((address)eip, (address)eip+32);
445 }
446
447 void MacroAssembler::stop(const char* msg) {
448 // push address of message
449 ExternalAddress message((address)msg);
450 pushptr(message.addr(), noreg);
451 { Label L; call(L, relocInfo::none); bind(L); } // push eip
452 pusha(); // push registers
453 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
454 hlt();
455 }
456
457 void MacroAssembler::warn(const char* msg) {
458 push_CPU_state();
459
460 // push address of message
461 ExternalAddress message((address)msg);
462 pushptr(message.addr(), noreg);
463
464 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
465 addl(rsp, wordSize); // discard argument
466 pop_CPU_state();
467 }
468
469 void MacroAssembler::print_state() {
470 { Label L; call(L, relocInfo::none); bind(L); } // push eip
471 pusha(); // push registers
472
473 push_CPU_state();
474 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
475 pop_CPU_state();
476
477 popa();
478 addl(rsp, wordSize);
479 }
480
481 #else // _LP64
482
483 // 64 bit versions
484
485 Address MacroAssembler::as_Address(AddressLiteral adr) {
486 // amd64 always does this as a pc-rel
487 // we can be absolute or disp based on the instruction type
488 // jmp/call are displacements others are absolute
489 assert(!adr.is_lval(), "must be rval");
490 assert(reachable(adr), "must be");
491 return Address(checked_cast<int32_t>(adr.target() - pc()), adr.target(), adr.reloc());
492
493 }
494
495 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
496 AddressLiteral base = adr.base();
497 lea(rscratch, base);
498 Address index = adr.index();
499 assert(index._disp == 0, "must not have disp"); // maybe it can?
500 Address array(rscratch, index._index, index._scale, index._disp);
501 return array;
502 }
503
504 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
505 Label L, E;
506
507 #ifdef _WIN64
508 // Windows always allocates space for it's register args
509 assert(num_args <= 4, "only register arguments supported");
510 subq(rsp, frame::arg_reg_save_area_bytes);
511 #endif
512
513 // Align stack if necessary
514 testl(rsp, 15);
515 jcc(Assembler::zero, L);
516
517 subq(rsp, 8);
518 call(RuntimeAddress(entry_point));
519 addq(rsp, 8);
520 jmp(E);
521
522 bind(L);
523 call(RuntimeAddress(entry_point));
524
525 bind(E);
526
527 #ifdef _WIN64
528 // restore stack pointer
529 addq(rsp, frame::arg_reg_save_area_bytes);
530 #endif
531
532 }
533
534 void MacroAssembler::cmp64(Register src1, AddressLiteral src2, Register rscratch) {
535 assert(!src2.is_lval(), "should use cmpptr");
536 assert(rscratch != noreg || always_reachable(src2), "missing");
537
538 if (reachable(src2)) {
539 cmpq(src1, as_Address(src2));
540 } else {
541 lea(rscratch, src2);
542 Assembler::cmpq(src1, Address(rscratch, 0));
543 }
544 }
545
546 int MacroAssembler::corrected_idivq(Register reg) {
547 // Full implementation of Java ldiv and lrem; checks for special
548 // case as described in JVM spec., p.243 & p.271. The function
549 // returns the (pc) offset of the idivl instruction - may be needed
550 // for implicit exceptions.
551 //
552 // normal case special case
553 //
554 // input : rax: dividend min_long
555 // reg: divisor (may not be eax/edx) -1
556 //
557 // output: rax: quotient (= rax idiv reg) min_long
558 // rdx: remainder (= rax irem reg) 0
559 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
560 static const int64_t min_long = 0x8000000000000000;
561 Label normal_case, special_case;
562
563 // check for special case
564 cmp64(rax, ExternalAddress((address) &min_long), rdx /*rscratch*/);
565 jcc(Assembler::notEqual, normal_case);
566 xorl(rdx, rdx); // prepare rdx for possible special case (where
567 // remainder = 0)
568 cmpq(reg, -1);
569 jcc(Assembler::equal, special_case);
570
571 // handle normal case
572 bind(normal_case);
573 cdqq();
574 int idivq_offset = offset();
575 idivq(reg);
576
577 // normal and special case exit
578 bind(special_case);
579
580 return idivq_offset;
581 }
582
583 void MacroAssembler::decrementq(Register reg, int value) {
584 if (value == min_jint) { subq(reg, value); return; }
585 if (value < 0) { incrementq(reg, -value); return; }
586 if (value == 0) { ; return; }
587 if (value == 1 && UseIncDec) { decq(reg) ; return; }
588 /* else */ { subq(reg, value) ; return; }
589 }
590
591 void MacroAssembler::decrementq(Address dst, int value) {
592 if (value == min_jint) { subq(dst, value); return; }
593 if (value < 0) { incrementq(dst, -value); return; }
594 if (value == 0) { ; return; }
595 if (value == 1 && UseIncDec) { decq(dst) ; return; }
596 /* else */ { subq(dst, value) ; return; }
597 }
598
599 void MacroAssembler::incrementq(AddressLiteral dst, Register rscratch) {
600 assert(rscratch != noreg || always_reachable(dst), "missing");
601
602 if (reachable(dst)) {
603 incrementq(as_Address(dst));
604 } else {
605 lea(rscratch, dst);
606 incrementq(Address(rscratch, 0));
607 }
608 }
609
610 void MacroAssembler::incrementq(Register reg, int value) {
611 if (value == min_jint) { addq(reg, value); return; }
612 if (value < 0) { decrementq(reg, -value); return; }
613 if (value == 0) { ; return; }
614 if (value == 1 && UseIncDec) { incq(reg) ; return; }
615 /* else */ { addq(reg, value) ; return; }
616 }
617
618 void MacroAssembler::incrementq(Address dst, int value) {
619 if (value == min_jint) { addq(dst, value); return; }
620 if (value < 0) { decrementq(dst, -value); return; }
621 if (value == 0) { ; return; }
622 if (value == 1 && UseIncDec) { incq(dst) ; return; }
623 /* else */ { addq(dst, value) ; return; }
624 }
625
626 // 32bit can do a case table jump in one instruction but we no longer allow the base
627 // to be installed in the Address class
628 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
629 lea(rscratch, entry.base());
630 Address dispatch = entry.index();
631 assert(dispatch._base == noreg, "must be");
632 dispatch._base = rscratch;
633 jmp(dispatch);
634 }
635
636 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
637 ShouldNotReachHere(); // 64bit doesn't use two regs
638 cmpq(x_lo, y_lo);
639 }
640
641 void MacroAssembler::lea(Register dst, AddressLiteral src) {
642 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
643 }
644
645 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
646 lea(rscratch, adr);
647 movptr(dst, rscratch);
648 }
649
650 void MacroAssembler::leave() {
651 // %%% is this really better? Why not on 32bit too?
652 emit_int8((unsigned char)0xC9); // LEAVE
653 }
654
655 void MacroAssembler::lneg(Register hi, Register lo) {
656 ShouldNotReachHere(); // 64bit doesn't use two regs
657 negq(lo);
658 }
659
660 void MacroAssembler::movoop(Register dst, jobject obj) {
661 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
662 }
663
664 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
665 mov_literal64(rscratch, (intptr_t)obj, oop_Relocation::spec_for_immediate());
666 movq(dst, rscratch);
667 }
668
669 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
670 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
671 }
672
673 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
674 mov_literal64(rscratch, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
675 movq(dst, rscratch);
676 }
677
678 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
679 if (src.is_lval()) {
680 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
681 } else {
682 if (reachable(src)) {
683 movq(dst, as_Address(src));
684 } else {
685 lea(dst, src);
686 movq(dst, Address(dst, 0));
687 }
688 }
689 }
690
691 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
692 movq(as_Address(dst, rscratch), src);
693 }
694
695 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
696 movq(dst, as_Address(src, dst /*rscratch*/));
697 }
698
699 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
700 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
701 if (is_simm32(src)) {
702 movptr(dst, checked_cast<int32_t>(src));
703 } else {
704 mov64(rscratch, src);
705 movq(dst, rscratch);
706 }
707 }
708
709 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
710 movoop(rscratch, obj);
711 push(rscratch);
712 }
713
714 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
715 mov_metadata(rscratch, obj);
716 push(rscratch);
717 }
718
719 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
720 lea(rscratch, src);
721 if (src.is_lval()) {
722 push(rscratch);
723 } else {
724 pushq(Address(rscratch, 0));
725 }
726 }
727
728 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
729 reset_last_Java_frame(r15_thread, clear_fp);
730 }
731
732 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
733 Register last_java_fp,
734 address last_java_pc,
735 Register rscratch) {
736 set_last_Java_frame(r15_thread, last_java_sp, last_java_fp, last_java_pc, rscratch);
737 }
738
739 static void pass_arg0(MacroAssembler* masm, Register arg) {
740 if (c_rarg0 != arg ) {
741 masm->mov(c_rarg0, arg);
742 }
743 }
744
745 static void pass_arg1(MacroAssembler* masm, Register arg) {
746 if (c_rarg1 != arg ) {
747 masm->mov(c_rarg1, arg);
748 }
749 }
750
751 static void pass_arg2(MacroAssembler* masm, Register arg) {
752 if (c_rarg2 != arg ) {
753 masm->mov(c_rarg2, arg);
754 }
755 }
756
757 static void pass_arg3(MacroAssembler* masm, Register arg) {
758 if (c_rarg3 != arg ) {
759 masm->mov(c_rarg3, arg);
760 }
761 }
762
763 void MacroAssembler::stop(const char* msg) {
764 if (ShowMessageBoxOnError) {
765 address rip = pc();
766 pusha(); // get regs on stack
767 lea(c_rarg1, InternalAddress(rip));
768 movq(c_rarg2, rsp); // pass pointer to regs array
769 }
770 lea(c_rarg0, ExternalAddress((address) msg));
771 andq(rsp, -16); // align stack as required by ABI
772 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
773 hlt();
774 }
775
776 void MacroAssembler::warn(const char* msg) {
777 push(rbp);
778 movq(rbp, rsp);
779 andq(rsp, -16); // align stack as required by push_CPU_state and call
780 push_CPU_state(); // keeps alignment at 16 bytes
781
782 lea(c_rarg0, ExternalAddress((address) msg));
783 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
784
785 pop_CPU_state();
786 mov(rsp, rbp);
787 pop(rbp);
788 }
789
790 void MacroAssembler::print_state() {
791 address rip = pc();
792 pusha(); // get regs on stack
793 push(rbp);
794 movq(rbp, rsp);
795 andq(rsp, -16); // align stack as required by push_CPU_state and call
796 push_CPU_state(); // keeps alignment at 16 bytes
797
798 lea(c_rarg0, InternalAddress(rip));
799 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
800 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
801
802 pop_CPU_state();
803 mov(rsp, rbp);
804 pop(rbp);
805 popa();
806 }
807
808 #ifndef PRODUCT
809 extern "C" void findpc(intptr_t x);
810 #endif
811
812 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
813 // In order to get locks to work, we need to fake a in_VM state
814 if (ShowMessageBoxOnError) {
815 JavaThread* thread = JavaThread::current();
816 JavaThreadState saved_state = thread->thread_state();
817 thread->set_thread_state(_thread_in_vm);
818 #ifndef PRODUCT
819 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
820 ttyLocker ttyl;
821 BytecodeCounter::print();
822 }
823 #endif
824 // To see where a verify_oop failed, get $ebx+40/X for this frame.
825 // XXX correct this offset for amd64
826 // This is the value of eip which points to where verify_oop will return.
827 if (os::message_box(msg, "Execution stopped, print registers?")) {
828 print_state64(pc, regs);
829 BREAKPOINT;
830 }
831 }
832 fatal("DEBUG MESSAGE: %s", msg);
833 }
834
835 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
836 ttyLocker ttyl;
837 DebuggingContext debugging{};
838 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
839 #ifndef PRODUCT
840 tty->cr();
841 findpc(pc);
842 tty->cr();
843 #endif
844 #define PRINT_REG(rax, value) \
845 { tty->print("%s = ", #rax); os::print_location(tty, value); }
846 PRINT_REG(rax, regs[15]);
847 PRINT_REG(rbx, regs[12]);
848 PRINT_REG(rcx, regs[14]);
849 PRINT_REG(rdx, regs[13]);
850 PRINT_REG(rdi, regs[8]);
851 PRINT_REG(rsi, regs[9]);
852 PRINT_REG(rbp, regs[10]);
853 // rsp is actually not stored by pusha(), compute the old rsp from regs (rsp after pusha): regs + 16 = old rsp
854 PRINT_REG(rsp, (intptr_t)(®s[16]));
855 PRINT_REG(r8 , regs[7]);
856 PRINT_REG(r9 , regs[6]);
857 PRINT_REG(r10, regs[5]);
858 PRINT_REG(r11, regs[4]);
859 PRINT_REG(r12, regs[3]);
860 PRINT_REG(r13, regs[2]);
861 PRINT_REG(r14, regs[1]);
862 PRINT_REG(r15, regs[0]);
863 #undef PRINT_REG
864 // Print some words near the top of the stack.
865 int64_t* rsp = ®s[16];
866 int64_t* dump_sp = rsp;
867 for (int col1 = 0; col1 < 8; col1++) {
868 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
869 os::print_location(tty, *dump_sp++);
870 }
871 for (int row = 0; row < 25; row++) {
872 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
873 for (int col = 0; col < 4; col++) {
874 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
875 }
876 tty->cr();
877 }
878 // Print some instructions around pc:
879 Disassembler::decode((address)pc-64, (address)pc);
880 tty->print_cr("--------");
881 Disassembler::decode((address)pc, (address)pc+32);
882 }
883
884 // The java_calling_convention describes stack locations as ideal slots on
885 // a frame with no abi restrictions. Since we must observe abi restrictions
886 // (like the placement of the register window) the slots must be biased by
887 // the following value.
888 static int reg2offset_in(VMReg r) {
889 // Account for saved rbp and return address
890 // This should really be in_preserve_stack_slots
891 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
892 }
893
894 static int reg2offset_out(VMReg r) {
895 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
896 }
897
898 // A long move
899 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
900
901 // The calling conventions assures us that each VMregpair is either
902 // all really one physical register or adjacent stack slots.
903
904 if (src.is_single_phys_reg() ) {
905 if (dst.is_single_phys_reg()) {
906 if (dst.first() != src.first()) {
907 mov(dst.first()->as_Register(), src.first()->as_Register());
908 }
909 } else {
910 assert(dst.is_single_reg(), "not a stack pair: (%s, %s), (%s, %s)",
911 src.first()->name(), src.second()->name(), dst.first()->name(), dst.second()->name());
912 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
913 }
914 } else if (dst.is_single_phys_reg()) {
915 assert(src.is_single_reg(), "not a stack pair");
916 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
917 } else {
918 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
919 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
920 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
921 }
922 }
923
924 // A double move
925 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
926
927 // The calling conventions assures us that each VMregpair is either
928 // all really one physical register or adjacent stack slots.
929
930 if (src.is_single_phys_reg() ) {
931 if (dst.is_single_phys_reg()) {
932 // In theory these overlap but the ordering is such that this is likely a nop
933 if ( src.first() != dst.first()) {
934 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
935 }
936 } else {
937 assert(dst.is_single_reg(), "not a stack pair");
938 movdbl(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
939 }
940 } else if (dst.is_single_phys_reg()) {
941 assert(src.is_single_reg(), "not a stack pair");
942 movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
943 } else {
944 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
945 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
946 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
947 }
948 }
949
950
951 // A float arg may have to do float reg int reg conversion
952 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
953 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
954
955 // The calling conventions assures us that each VMregpair is either
956 // all really one physical register or adjacent stack slots.
957
958 if (src.first()->is_stack()) {
959 if (dst.first()->is_stack()) {
960 movl(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
961 movptr(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
962 } else {
963 // stack to reg
964 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
965 movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
966 }
967 } else if (dst.first()->is_stack()) {
968 // reg to stack
969 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
970 movflt(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
971 } else {
972 // reg to reg
973 // In theory these overlap but the ordering is such that this is likely a nop
974 if ( src.first() != dst.first()) {
975 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
976 }
977 }
978 }
979
980 // On 64 bit we will store integer like items to the stack as
981 // 64 bits items (x86_32/64 abi) even though java would only store
982 // 32bits for a parameter. On 32bit it will simply be 32 bits
983 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
984 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
985 if (src.first()->is_stack()) {
986 if (dst.first()->is_stack()) {
987 // stack to stack
988 movslq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
989 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
990 } else {
991 // stack to reg
992 movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
993 }
994 } else if (dst.first()->is_stack()) {
995 // reg to stack
996 // Do we really have to sign extend???
997 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
998 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
999 } else {
1000 // Do we really have to sign extend???
1001 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
1002 if (dst.first() != src.first()) {
1003 movq(dst.first()->as_Register(), src.first()->as_Register());
1004 }
1005 }
1006 }
1007
1008 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) {
1009 if (src.first()->is_stack()) {
1010 if (dst.first()->is_stack()) {
1011 // stack to stack
1012 movq(rax, Address(rbp, reg2offset_in(src.first())));
1013 movq(Address(rsp, reg2offset_out(dst.first())), rax);
1014 } else {
1015 // stack to reg
1016 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1017 }
1018 } else if (dst.first()->is_stack()) {
1019 // reg to stack
1020 movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1021 } else {
1022 if (dst.first() != src.first()) {
1023 movq(dst.first()->as_Register(), src.first()->as_Register());
1024 }
1025 }
1026 }
1027
1028 // An oop arg. Must pass a handle not the oop itself
1029 void MacroAssembler::object_move(OopMap* map,
1030 int oop_handle_offset,
1031 int framesize_in_slots,
1032 VMRegPair src,
1033 VMRegPair dst,
1034 bool is_receiver,
1035 int* receiver_offset) {
1036
1037 // must pass a handle. First figure out the location we use as a handle
1038
1039 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
1040
1041 // See if oop is null if it is we need no handle
1042
1043 if (src.first()->is_stack()) {
1044
1045 // Oop is already on the stack as an argument
1046 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1047 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
1048 if (is_receiver) {
1049 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
1050 }
1051
1052 cmpptr(Address(rbp, reg2offset_in(src.first())), NULL_WORD);
1053 lea(rHandle, Address(rbp, reg2offset_in(src.first())));
1054 // conditionally move a null
1055 cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
1056 } else {
1057
1058 // Oop is in a register we must store it to the space we reserve
1059 // on the stack for oop_handles and pass a handle if oop is non-null
1060
1061 const Register rOop = src.first()->as_Register();
1062 int oop_slot;
1063 if (rOop == j_rarg0)
1064 oop_slot = 0;
1065 else if (rOop == j_rarg1)
1066 oop_slot = 1;
1067 else if (rOop == j_rarg2)
1068 oop_slot = 2;
1069 else if (rOop == j_rarg3)
1070 oop_slot = 3;
1071 else if (rOop == j_rarg4)
1072 oop_slot = 4;
1073 else {
1074 assert(rOop == j_rarg5, "wrong register");
1075 oop_slot = 5;
1076 }
1077
1078 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
1079 int offset = oop_slot*VMRegImpl::stack_slot_size;
1080
1081 map->set_oop(VMRegImpl::stack2reg(oop_slot));
1082 // Store oop in handle area, may be null
1083 movptr(Address(rsp, offset), rOop);
1084 if (is_receiver) {
1085 *receiver_offset = offset;
1086 }
1087
1088 cmpptr(rOop, NULL_WORD);
1089 lea(rHandle, Address(rsp, offset));
1090 // conditionally move a null from the handle area where it was just stored
1091 cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
1092 }
1093
1094 // If arg is on the stack then place it otherwise it is already in correct reg.
1095 if (dst.first()->is_stack()) {
1096 movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
1097 }
1098 }
1099
1100 #endif // _LP64
1101
1102 // Now versions that are common to 32/64 bit
1103
1104 void MacroAssembler::addptr(Register dst, int32_t imm32) {
1105 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
1106 }
1107
1108 void MacroAssembler::addptr(Register dst, Register src) {
1109 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1110 }
1111
1112 void MacroAssembler::addptr(Address dst, Register src) {
1113 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1114 }
1115
1116 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1117 assert(rscratch != noreg || always_reachable(src), "missing");
1118
1119 if (reachable(src)) {
1120 Assembler::addsd(dst, as_Address(src));
1121 } else {
1122 lea(rscratch, src);
1123 Assembler::addsd(dst, Address(rscratch, 0));
1124 }
1125 }
1126
1127 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1128 assert(rscratch != noreg || always_reachable(src), "missing");
1129
1130 if (reachable(src)) {
1131 addss(dst, as_Address(src));
1132 } else {
1133 lea(rscratch, src);
1134 addss(dst, Address(rscratch, 0));
1135 }
1136 }
1137
1138 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1139 assert(rscratch != noreg || always_reachable(src), "missing");
1140
1141 if (reachable(src)) {
1142 Assembler::addpd(dst, as_Address(src));
1143 } else {
1144 lea(rscratch, src);
1145 Assembler::addpd(dst, Address(rscratch, 0));
1146 }
1147 }
1148
1149 // See 8273459. Function for ensuring 64-byte alignment, intended for stubs only.
1150 // Stub code is generated once and never copied.
1151 // NMethods can't use this because they get copied and we can't force alignment > 32 bytes.
1152 void MacroAssembler::align64() {
1153 align(64, (uint)(uintptr_t)pc());
1154 }
1155
1156 void MacroAssembler::align32() {
1157 align(32, (uint)(uintptr_t)pc());
1158 }
1159
1160 void MacroAssembler::align(uint modulus) {
1161 // 8273459: Ensure alignment is possible with current segment alignment
1162 assert(modulus <= (uintx)CodeEntryAlignment, "Alignment must be <= CodeEntryAlignment");
1163 align(modulus, offset());
1164 }
1165
1166 void MacroAssembler::align(uint modulus, uint target) {
1167 if (target % modulus != 0) {
1168 nop(modulus - (target % modulus));
1169 }
1170 }
1171
1172 void MacroAssembler::push_f(XMMRegister r) {
1173 subptr(rsp, wordSize);
1174 movflt(Address(rsp, 0), r);
1175 }
1176
1177 void MacroAssembler::pop_f(XMMRegister r) {
1178 movflt(r, Address(rsp, 0));
1179 addptr(rsp, wordSize);
1180 }
1181
1182 void MacroAssembler::push_d(XMMRegister r) {
1183 subptr(rsp, 2 * wordSize);
1184 movdbl(Address(rsp, 0), r);
1185 }
1186
1187 void MacroAssembler::pop_d(XMMRegister r) {
1188 movdbl(r, Address(rsp, 0));
1189 addptr(rsp, 2 * Interpreter::stackElementSize);
1190 }
1191
1192 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1193 // Used in sign-masking with aligned address.
1194 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1195 assert(rscratch != noreg || always_reachable(src), "missing");
1196
1197 if (reachable(src)) {
1198 Assembler::andpd(dst, as_Address(src));
1199 } else {
1200 lea(rscratch, src);
1201 Assembler::andpd(dst, Address(rscratch, 0));
1202 }
1203 }
1204
1205 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register rscratch) {
1206 // Used in sign-masking with aligned address.
1207 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1208 assert(rscratch != noreg || always_reachable(src), "missing");
1209
1210 if (reachable(src)) {
1211 Assembler::andps(dst, as_Address(src));
1212 } else {
1213 lea(rscratch, src);
1214 Assembler::andps(dst, Address(rscratch, 0));
1215 }
1216 }
1217
1218 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1219 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1220 }
1221
1222 #ifdef _LP64
1223 void MacroAssembler::andq(Register dst, AddressLiteral src, Register rscratch) {
1224 assert(rscratch != noreg || always_reachable(src), "missing");
1225
1226 if (reachable(src)) {
1227 andq(dst, as_Address(src));
1228 } else {
1229 lea(rscratch, src);
1230 andq(dst, Address(rscratch, 0));
1231 }
1232 }
1233 #endif
1234
1235 void MacroAssembler::atomic_incl(Address counter_addr) {
1236 lock();
1237 incrementl(counter_addr);
1238 }
1239
1240 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register rscratch) {
1241 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1242
1243 if (reachable(counter_addr)) {
1244 atomic_incl(as_Address(counter_addr));
1245 } else {
1246 lea(rscratch, counter_addr);
1247 atomic_incl(Address(rscratch, 0));
1248 }
1249 }
1250
1251 #ifdef _LP64
1252 void MacroAssembler::atomic_incq(Address counter_addr) {
1253 lock();
1254 incrementq(counter_addr);
1255 }
1256
1257 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register rscratch) {
1258 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1259
1260 if (reachable(counter_addr)) {
1261 atomic_incq(as_Address(counter_addr));
1262 } else {
1263 lea(rscratch, counter_addr);
1264 atomic_incq(Address(rscratch, 0));
1265 }
1266 }
1267 #endif
1268
1269 // Writes to stack successive pages until offset reached to check for
1270 // stack overflow + shadow pages. This clobbers tmp.
1271 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1272 movptr(tmp, rsp);
1273 // Bang stack for total size given plus shadow page size.
1274 // Bang one page at a time because large size can bang beyond yellow and
1275 // red zones.
1276 Label loop;
1277 bind(loop);
1278 movl(Address(tmp, (-(int)os::vm_page_size())), size );
1279 subptr(tmp, (int)os::vm_page_size());
1280 subl(size, (int)os::vm_page_size());
1281 jcc(Assembler::greater, loop);
1282
1283 // Bang down shadow pages too.
1284 // At this point, (tmp-0) is the last address touched, so don't
1285 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1286 // was post-decremented.) Skip this address by starting at i=1, and
1287 // touch a few more pages below. N.B. It is important to touch all
1288 // the way down including all pages in the shadow zone.
1289 for (int i = 1; i < ((int)StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()); i++) {
1290 // this could be any sized move but this is can be a debugging crumb
1291 // so the bigger the better.
1292 movptr(Address(tmp, (-i*(int)os::vm_page_size())), size );
1293 }
1294 }
1295
1296 void MacroAssembler::reserved_stack_check() {
1297 // testing if reserved zone needs to be enabled
1298 Label no_reserved_zone_enabling;
1299 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1300 NOT_LP64(get_thread(rsi);)
1301
1302 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1303 jcc(Assembler::below, no_reserved_zone_enabling);
1304
1305 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1306 jump(RuntimeAddress(SharedRuntime::throw_delayed_StackOverflowError_entry()));
1307 should_not_reach_here();
1308
1309 bind(no_reserved_zone_enabling);
1310 }
1311
1312 void MacroAssembler::c2bool(Register x) {
1313 // implements x == 0 ? 0 : 1
1314 // note: must only look at least-significant byte of x
1315 // since C-style booleans are stored in one byte
1316 // only! (was bug)
1317 andl(x, 0xFF);
1318 setb(Assembler::notZero, x);
1319 }
1320
1321 // Wouldn't need if AddressLiteral version had new name
1322 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
1323 Assembler::call(L, rtype);
1324 }
1325
1326 void MacroAssembler::call(Register entry) {
1327 Assembler::call(entry);
1328 }
1329
1330 void MacroAssembler::call(AddressLiteral entry, Register rscratch) {
1331 assert(rscratch != noreg || always_reachable(entry), "missing");
1332
1333 if (reachable(entry)) {
1334 Assembler::call_literal(entry.target(), entry.rspec());
1335 } else {
1336 lea(rscratch, entry);
1337 Assembler::call(rscratch);
1338 }
1339 }
1340
1341 void MacroAssembler::ic_call(address entry, jint method_index) {
1342 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
1343 #ifdef _LP64
1344 // Needs full 64-bit immediate for later patching.
1345 mov64(rax, (int64_t)Universe::non_oop_word());
1346 #else
1347 movptr(rax, (intptr_t)Universe::non_oop_word());
1348 #endif
1349 call(AddressLiteral(entry, rh));
1350 }
1351
1352 int MacroAssembler::ic_check_size() {
1353 return LP64_ONLY(14) NOT_LP64(12);
1354 }
1355
1356 int MacroAssembler::ic_check(int end_alignment) {
1357 Register receiver = LP64_ONLY(j_rarg0) NOT_LP64(rcx);
1358 Register data = rax;
1359 Register temp = LP64_ONLY(rscratch1) NOT_LP64(rbx);
1360
1361 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
1362 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
1363 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
1364 // before the inline cache check here, and not after
1365 align(end_alignment, offset() + ic_check_size());
1366
1367 int uep_offset = offset();
1368
1369 if (UseCompressedClassPointers) {
1370 movl(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
1371 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
1372 } else {
1373 movptr(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
1374 cmpptr(temp, Address(data, CompiledICData::speculated_klass_offset()));
1375 }
1376
1377 // if inline cache check fails, then jump to runtime routine
1378 jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1379 assert((offset() % end_alignment) == 0, "Misaligned verified entry point");
1380
1381 return uep_offset;
1382 }
1383
1384 void MacroAssembler::emit_static_call_stub() {
1385 // Static stub relocation also tags the Method* in the code-stream.
1386 mov_metadata(rbx, (Metadata*) nullptr); // Method is zapped till fixup time.
1387 // This is recognized as unresolved by relocs/nativeinst/ic code.
1388 jump(RuntimeAddress(pc()));
1389 }
1390
1391 // Implementation of call_VM versions
1392
1393 void MacroAssembler::call_VM(Register oop_result,
1394 address entry_point,
1395 bool check_exceptions) {
1396 Label C, E;
1397 call(C, relocInfo::none);
1398 jmp(E);
1399
1400 bind(C);
1401 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1402 ret(0);
1403
1404 bind(E);
1405 }
1406
1407 void MacroAssembler::call_VM(Register oop_result,
1408 address entry_point,
1409 Register arg_1,
1410 bool check_exceptions) {
1411 Label C, E;
1412 call(C, relocInfo::none);
1413 jmp(E);
1414
1415 bind(C);
1416 pass_arg1(this, arg_1);
1417 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1418 ret(0);
1419
1420 bind(E);
1421 }
1422
1423 void MacroAssembler::call_VM(Register oop_result,
1424 address entry_point,
1425 Register arg_1,
1426 Register arg_2,
1427 bool check_exceptions) {
1428 Label C, E;
1429 call(C, relocInfo::none);
1430 jmp(E);
1431
1432 bind(C);
1433
1434 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1435
1436 pass_arg2(this, arg_2);
1437 pass_arg1(this, arg_1);
1438 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1439 ret(0);
1440
1441 bind(E);
1442 }
1443
1444 void MacroAssembler::call_VM(Register oop_result,
1445 address entry_point,
1446 Register arg_1,
1447 Register arg_2,
1448 Register arg_3,
1449 bool check_exceptions) {
1450 Label C, E;
1451 call(C, relocInfo::none);
1452 jmp(E);
1453
1454 bind(C);
1455
1456 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1457 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1458 pass_arg3(this, arg_3);
1459 pass_arg2(this, arg_2);
1460 pass_arg1(this, arg_1);
1461 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1462 ret(0);
1463
1464 bind(E);
1465 }
1466
1467 void MacroAssembler::call_VM(Register oop_result,
1468 Register last_java_sp,
1469 address entry_point,
1470 int number_of_arguments,
1471 bool check_exceptions) {
1472 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1473 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1474 }
1475
1476 void MacroAssembler::call_VM(Register oop_result,
1477 Register last_java_sp,
1478 address entry_point,
1479 Register arg_1,
1480 bool check_exceptions) {
1481 pass_arg1(this, arg_1);
1482 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1483 }
1484
1485 void MacroAssembler::call_VM(Register oop_result,
1486 Register last_java_sp,
1487 address entry_point,
1488 Register arg_1,
1489 Register arg_2,
1490 bool check_exceptions) {
1491
1492 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1493 pass_arg2(this, arg_2);
1494 pass_arg1(this, arg_1);
1495 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1496 }
1497
1498 void MacroAssembler::call_VM(Register oop_result,
1499 Register last_java_sp,
1500 address entry_point,
1501 Register arg_1,
1502 Register arg_2,
1503 Register arg_3,
1504 bool check_exceptions) {
1505 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1506 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1507 pass_arg3(this, arg_3);
1508 pass_arg2(this, arg_2);
1509 pass_arg1(this, arg_1);
1510 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1511 }
1512
1513 void MacroAssembler::super_call_VM(Register oop_result,
1514 Register last_java_sp,
1515 address entry_point,
1516 int number_of_arguments,
1517 bool check_exceptions) {
1518 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1519 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1520 }
1521
1522 void MacroAssembler::super_call_VM(Register oop_result,
1523 Register last_java_sp,
1524 address entry_point,
1525 Register arg_1,
1526 bool check_exceptions) {
1527 pass_arg1(this, arg_1);
1528 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1529 }
1530
1531 void MacroAssembler::super_call_VM(Register oop_result,
1532 Register last_java_sp,
1533 address entry_point,
1534 Register arg_1,
1535 Register arg_2,
1536 bool check_exceptions) {
1537
1538 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1539 pass_arg2(this, arg_2);
1540 pass_arg1(this, arg_1);
1541 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1542 }
1543
1544 void MacroAssembler::super_call_VM(Register oop_result,
1545 Register last_java_sp,
1546 address entry_point,
1547 Register arg_1,
1548 Register arg_2,
1549 Register arg_3,
1550 bool check_exceptions) {
1551 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1552 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1553 pass_arg3(this, arg_3);
1554 pass_arg2(this, arg_2);
1555 pass_arg1(this, arg_1);
1556 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1557 }
1558
1559 void MacroAssembler::call_VM_base(Register oop_result,
1560 Register java_thread,
1561 Register last_java_sp,
1562 address entry_point,
1563 int number_of_arguments,
1564 bool check_exceptions) {
1565 // determine java_thread register
1566 if (!java_thread->is_valid()) {
1567 #ifdef _LP64
1568 java_thread = r15_thread;
1569 #else
1570 java_thread = rdi;
1571 get_thread(java_thread);
1572 #endif // LP64
1573 }
1574 // determine last_java_sp register
1575 if (!last_java_sp->is_valid()) {
1576 last_java_sp = rsp;
1577 }
1578 // debugging support
1579 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
1580 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
1581 #ifdef ASSERT
1582 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
1583 // r12 is the heapbase.
1584 LP64_ONLY(if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
1585 #endif // ASSERT
1586
1587 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
1588 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
1589
1590 // push java thread (becomes first argument of C function)
1591
1592 NOT_LP64(push(java_thread); number_of_arguments++);
1593 LP64_ONLY(mov(c_rarg0, r15_thread));
1594
1595 // set last Java frame before call
1596 assert(last_java_sp != rbp, "can't use ebp/rbp");
1597
1598 // Only interpreter should have to set fp
1599 set_last_Java_frame(java_thread, last_java_sp, rbp, nullptr, rscratch1);
1600
1601 // do the call, remove parameters
1602 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
1603
1604 // restore the thread (cannot use the pushed argument since arguments
1605 // may be overwritten by C code generated by an optimizing compiler);
1606 // however can use the register value directly if it is callee saved.
1607 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
1608 // rdi & rsi (also r15) are callee saved -> nothing to do
1609 #ifdef ASSERT
1610 guarantee(java_thread != rax, "change this code");
1611 push(rax);
1612 { Label L;
1613 get_thread(rax);
1614 cmpptr(java_thread, rax);
1615 jcc(Assembler::equal, L);
1616 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
1617 bind(L);
1618 }
1619 pop(rax);
1620 #endif
1621 } else {
1622 get_thread(java_thread);
1623 }
1624 // reset last Java frame
1625 // Only interpreter should have to clear fp
1626 reset_last_Java_frame(java_thread, true);
1627
1628 // C++ interp handles this in the interpreter
1629 check_and_handle_popframe(java_thread);
1630 check_and_handle_earlyret(java_thread);
1631
1632 if (check_exceptions) {
1633 // check for pending exceptions (java_thread is set upon return)
1634 cmpptr(Address(java_thread, Thread::pending_exception_offset()), NULL_WORD);
1635 #ifndef _LP64
1636 jump_cc(Assembler::notEqual,
1637 RuntimeAddress(StubRoutines::forward_exception_entry()));
1638 #else
1639 // This used to conditionally jump to forward_exception however it is
1640 // possible if we relocate that the branch will not reach. So we must jump
1641 // around so we can always reach
1642
1643 Label ok;
1644 jcc(Assembler::equal, ok);
1645 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
1646 bind(ok);
1647 #endif // LP64
1648 }
1649
1650 // get oop result if there is one and reset the value in the thread
1651 if (oop_result->is_valid()) {
1652 get_vm_result(oop_result, java_thread);
1653 }
1654 }
1655
1656 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1657
1658 // Calculate the value for last_Java_sp
1659 // somewhat subtle. call_VM does an intermediate call
1660 // which places a return address on the stack just under the
1661 // stack pointer as the user finished with it. This allows
1662 // use to retrieve last_Java_pc from last_Java_sp[-1].
1663 // On 32bit we then have to push additional args on the stack to accomplish
1664 // the actual requested call. On 64bit call_VM only can use register args
1665 // so the only extra space is the return address that call_VM created.
1666 // This hopefully explains the calculations here.
1667
1668 #ifdef _LP64
1669 // We've pushed one address, correct last_Java_sp
1670 lea(rax, Address(rsp, wordSize));
1671 #else
1672 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
1673 #endif // LP64
1674
1675 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
1676
1677 }
1678
1679 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
1680 void MacroAssembler::call_VM_leaf0(address entry_point) {
1681 MacroAssembler::call_VM_leaf_base(entry_point, 0);
1682 }
1683
1684 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1685 call_VM_leaf_base(entry_point, number_of_arguments);
1686 }
1687
1688 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1689 pass_arg0(this, arg_0);
1690 call_VM_leaf(entry_point, 1);
1691 }
1692
1693 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1694
1695 LP64_ONLY(assert_different_registers(arg_0, c_rarg1));
1696 pass_arg1(this, arg_1);
1697 pass_arg0(this, arg_0);
1698 call_VM_leaf(entry_point, 2);
1699 }
1700
1701 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1702 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2));
1703 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1704 pass_arg2(this, arg_2);
1705 pass_arg1(this, arg_1);
1706 pass_arg0(this, arg_0);
1707 call_VM_leaf(entry_point, 3);
1708 }
1709
1710 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1711 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3));
1712 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1713 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1714 pass_arg3(this, arg_3);
1715 pass_arg2(this, arg_2);
1716 pass_arg1(this, arg_1);
1717 pass_arg0(this, arg_0);
1718 call_VM_leaf(entry_point, 3);
1719 }
1720
1721 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1722 pass_arg0(this, arg_0);
1723 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1724 }
1725
1726 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1727 LP64_ONLY(assert_different_registers(arg_0, c_rarg1));
1728 pass_arg1(this, arg_1);
1729 pass_arg0(this, arg_0);
1730 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1731 }
1732
1733 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1734 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2));
1735 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1736 pass_arg2(this, arg_2);
1737 pass_arg1(this, arg_1);
1738 pass_arg0(this, arg_0);
1739 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1740 }
1741
1742 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1743 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3));
1744 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1745 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1746 pass_arg3(this, arg_3);
1747 pass_arg2(this, arg_2);
1748 pass_arg1(this, arg_1);
1749 pass_arg0(this, arg_0);
1750 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1751 }
1752
1753 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
1754 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
1755 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
1756 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1757 }
1758
1759 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
1760 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
1761 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
1762 }
1763
1764 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
1765 }
1766
1767 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
1768 }
1769
1770 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm, Register rscratch) {
1771 assert(rscratch != noreg || always_reachable(src1), "missing");
1772
1773 if (reachable(src1)) {
1774 cmpl(as_Address(src1), imm);
1775 } else {
1776 lea(rscratch, src1);
1777 cmpl(Address(rscratch, 0), imm);
1778 }
1779 }
1780
1781 void MacroAssembler::cmp32(Register src1, AddressLiteral src2, Register rscratch) {
1782 assert(!src2.is_lval(), "use cmpptr");
1783 assert(rscratch != noreg || always_reachable(src2), "missing");
1784
1785 if (reachable(src2)) {
1786 cmpl(src1, as_Address(src2));
1787 } else {
1788 lea(rscratch, src2);
1789 cmpl(src1, Address(rscratch, 0));
1790 }
1791 }
1792
1793 void MacroAssembler::cmp32(Register src1, int32_t imm) {
1794 Assembler::cmpl(src1, imm);
1795 }
1796
1797 void MacroAssembler::cmp32(Register src1, Address src2) {
1798 Assembler::cmpl(src1, src2);
1799 }
1800
1801 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1802 ucomisd(opr1, opr2);
1803
1804 Label L;
1805 if (unordered_is_less) {
1806 movl(dst, -1);
1807 jcc(Assembler::parity, L);
1808 jcc(Assembler::below , L);
1809 movl(dst, 0);
1810 jcc(Assembler::equal , L);
1811 increment(dst);
1812 } else { // unordered is greater
1813 movl(dst, 1);
1814 jcc(Assembler::parity, L);
1815 jcc(Assembler::above , L);
1816 movl(dst, 0);
1817 jcc(Assembler::equal , L);
1818 decrementl(dst);
1819 }
1820 bind(L);
1821 }
1822
1823 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1824 ucomiss(opr1, opr2);
1825
1826 Label L;
1827 if (unordered_is_less) {
1828 movl(dst, -1);
1829 jcc(Assembler::parity, L);
1830 jcc(Assembler::below , L);
1831 movl(dst, 0);
1832 jcc(Assembler::equal , L);
1833 increment(dst);
1834 } else { // unordered is greater
1835 movl(dst, 1);
1836 jcc(Assembler::parity, L);
1837 jcc(Assembler::above , L);
1838 movl(dst, 0);
1839 jcc(Assembler::equal , L);
1840 decrementl(dst);
1841 }
1842 bind(L);
1843 }
1844
1845
1846 void MacroAssembler::cmp8(AddressLiteral src1, int imm, Register rscratch) {
1847 assert(rscratch != noreg || always_reachable(src1), "missing");
1848
1849 if (reachable(src1)) {
1850 cmpb(as_Address(src1), imm);
1851 } else {
1852 lea(rscratch, src1);
1853 cmpb(Address(rscratch, 0), imm);
1854 }
1855 }
1856
1857 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2, Register rscratch) {
1858 #ifdef _LP64
1859 assert(rscratch != noreg || always_reachable(src2), "missing");
1860
1861 if (src2.is_lval()) {
1862 movptr(rscratch, src2);
1863 Assembler::cmpq(src1, rscratch);
1864 } else if (reachable(src2)) {
1865 cmpq(src1, as_Address(src2));
1866 } else {
1867 lea(rscratch, src2);
1868 Assembler::cmpq(src1, Address(rscratch, 0));
1869 }
1870 #else
1871 assert(rscratch == noreg, "not needed");
1872 if (src2.is_lval()) {
1873 cmp_literal32(src1, (int32_t)src2.target(), src2.rspec());
1874 } else {
1875 cmpl(src1, as_Address(src2));
1876 }
1877 #endif // _LP64
1878 }
1879
1880 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2, Register rscratch) {
1881 assert(src2.is_lval(), "not a mem-mem compare");
1882 #ifdef _LP64
1883 // moves src2's literal address
1884 movptr(rscratch, src2);
1885 Assembler::cmpq(src1, rscratch);
1886 #else
1887 assert(rscratch == noreg, "not needed");
1888 cmp_literal32(src1, (int32_t)src2.target(), src2.rspec());
1889 #endif // _LP64
1890 }
1891
1892 void MacroAssembler::cmpoop(Register src1, Register src2) {
1893 cmpptr(src1, src2);
1894 }
1895
1896 void MacroAssembler::cmpoop(Register src1, Address src2) {
1897 cmpptr(src1, src2);
1898 }
1899
1900 #ifdef _LP64
1901 void MacroAssembler::cmpoop(Register src1, jobject src2, Register rscratch) {
1902 movoop(rscratch, src2);
1903 cmpptr(src1, rscratch);
1904 }
1905 #endif
1906
1907 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch) {
1908 assert(rscratch != noreg || always_reachable(adr), "missing");
1909
1910 if (reachable(adr)) {
1911 lock();
1912 cmpxchgptr(reg, as_Address(adr));
1913 } else {
1914 lea(rscratch, adr);
1915 lock();
1916 cmpxchgptr(reg, Address(rscratch, 0));
1917 }
1918 }
1919
1920 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
1921 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
1922 }
1923
1924 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1925 assert(rscratch != noreg || always_reachable(src), "missing");
1926
1927 if (reachable(src)) {
1928 Assembler::comisd(dst, as_Address(src));
1929 } else {
1930 lea(rscratch, src);
1931 Assembler::comisd(dst, Address(rscratch, 0));
1932 }
1933 }
1934
1935 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1936 assert(rscratch != noreg || always_reachable(src), "missing");
1937
1938 if (reachable(src)) {
1939 Assembler::comiss(dst, as_Address(src));
1940 } else {
1941 lea(rscratch, src);
1942 Assembler::comiss(dst, Address(rscratch, 0));
1943 }
1944 }
1945
1946
1947 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr, Register rscratch) {
1948 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1949
1950 Condition negated_cond = negate_condition(cond);
1951 Label L;
1952 jcc(negated_cond, L);
1953 pushf(); // Preserve flags
1954 atomic_incl(counter_addr, rscratch);
1955 popf();
1956 bind(L);
1957 }
1958
1959 int MacroAssembler::corrected_idivl(Register reg) {
1960 // Full implementation of Java idiv and irem; checks for
1961 // special case as described in JVM spec., p.243 & p.271.
1962 // The function returns the (pc) offset of the idivl
1963 // instruction - may be needed for implicit exceptions.
1964 //
1965 // normal case special case
1966 //
1967 // input : rax,: dividend min_int
1968 // reg: divisor (may not be rax,/rdx) -1
1969 //
1970 // output: rax,: quotient (= rax, idiv reg) min_int
1971 // rdx: remainder (= rax, irem reg) 0
1972 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
1973 const int min_int = 0x80000000;
1974 Label normal_case, special_case;
1975
1976 // check for special case
1977 cmpl(rax, min_int);
1978 jcc(Assembler::notEqual, normal_case);
1979 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
1980 cmpl(reg, -1);
1981 jcc(Assembler::equal, special_case);
1982
1983 // handle normal case
1984 bind(normal_case);
1985 cdql();
1986 int idivl_offset = offset();
1987 idivl(reg);
1988
1989 // normal and special case exit
1990 bind(special_case);
1991
1992 return idivl_offset;
1993 }
1994
1995
1996
1997 void MacroAssembler::decrementl(Register reg, int value) {
1998 if (value == min_jint) {subl(reg, value) ; return; }
1999 if (value < 0) { incrementl(reg, -value); return; }
2000 if (value == 0) { ; return; }
2001 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2002 /* else */ { subl(reg, value) ; return; }
2003 }
2004
2005 void MacroAssembler::decrementl(Address dst, int value) {
2006 if (value == min_jint) {subl(dst, value) ; return; }
2007 if (value < 0) { incrementl(dst, -value); return; }
2008 if (value == 0) { ; return; }
2009 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2010 /* else */ { subl(dst, value) ; return; }
2011 }
2012
2013 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2014 assert(shift_value > 0, "illegal shift value");
2015 Label _is_positive;
2016 testl (reg, reg);
2017 jcc (Assembler::positive, _is_positive);
2018 int offset = (1 << shift_value) - 1 ;
2019
2020 if (offset == 1) {
2021 incrementl(reg);
2022 } else {
2023 addl(reg, offset);
2024 }
2025
2026 bind (_is_positive);
2027 sarl(reg, shift_value);
2028 }
2029
2030 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2031 assert(rscratch != noreg || always_reachable(src), "missing");
2032
2033 if (reachable(src)) {
2034 Assembler::divsd(dst, as_Address(src));
2035 } else {
2036 lea(rscratch, src);
2037 Assembler::divsd(dst, Address(rscratch, 0));
2038 }
2039 }
2040
2041 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2042 assert(rscratch != noreg || always_reachable(src), "missing");
2043
2044 if (reachable(src)) {
2045 Assembler::divss(dst, as_Address(src));
2046 } else {
2047 lea(rscratch, src);
2048 Assembler::divss(dst, Address(rscratch, 0));
2049 }
2050 }
2051
2052 void MacroAssembler::enter() {
2053 push(rbp);
2054 mov(rbp, rsp);
2055 }
2056
2057 void MacroAssembler::post_call_nop() {
2058 if (!Continuations::enabled()) {
2059 return;
2060 }
2061 InstructionMark im(this);
2062 relocate(post_call_nop_Relocation::spec());
2063 InlineSkippedInstructionsCounter skipCounter(this);
2064 emit_int8((uint8_t)0x0f);
2065 emit_int8((uint8_t)0x1f);
2066 emit_int8((uint8_t)0x84);
2067 emit_int8((uint8_t)0x00);
2068 emit_int32(0x00);
2069 }
2070
2071 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2072 void MacroAssembler::fat_nop() {
2073 if (UseAddressNop) {
2074 addr_nop_5();
2075 } else {
2076 emit_int8((uint8_t)0x26); // es:
2077 emit_int8((uint8_t)0x2e); // cs:
2078 emit_int8((uint8_t)0x64); // fs:
2079 emit_int8((uint8_t)0x65); // gs:
2080 emit_int8((uint8_t)0x90);
2081 }
2082 }
2083
2084 #ifndef _LP64
2085 void MacroAssembler::fcmp(Register tmp) {
2086 fcmp(tmp, 1, true, true);
2087 }
2088
2089 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2090 assert(!pop_right || pop_left, "usage error");
2091 if (VM_Version::supports_cmov()) {
2092 assert(tmp == noreg, "unneeded temp");
2093 if (pop_left) {
2094 fucomip(index);
2095 } else {
2096 fucomi(index);
2097 }
2098 if (pop_right) {
2099 fpop();
2100 }
2101 } else {
2102 assert(tmp != noreg, "need temp");
2103 if (pop_left) {
2104 if (pop_right) {
2105 fcompp();
2106 } else {
2107 fcomp(index);
2108 }
2109 } else {
2110 fcom(index);
2111 }
2112 // convert FPU condition into eflags condition via rax,
2113 save_rax(tmp);
2114 fwait(); fnstsw_ax();
2115 sahf();
2116 restore_rax(tmp);
2117 }
2118 // condition codes set as follows:
2119 //
2120 // CF (corresponds to C0) if x < y
2121 // PF (corresponds to C2) if unordered
2122 // ZF (corresponds to C3) if x = y
2123 }
2124
2125 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
2126 fcmp2int(dst, unordered_is_less, 1, true, true);
2127 }
2128
2129 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
2130 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
2131 Label L;
2132 if (unordered_is_less) {
2133 movl(dst, -1);
2134 jcc(Assembler::parity, L);
2135 jcc(Assembler::below , L);
2136 movl(dst, 0);
2137 jcc(Assembler::equal , L);
2138 increment(dst);
2139 } else { // unordered is greater
2140 movl(dst, 1);
2141 jcc(Assembler::parity, L);
2142 jcc(Assembler::above , L);
2143 movl(dst, 0);
2144 jcc(Assembler::equal , L);
2145 decrementl(dst);
2146 }
2147 bind(L);
2148 }
2149
2150 void MacroAssembler::fld_d(AddressLiteral src) {
2151 fld_d(as_Address(src));
2152 }
2153
2154 void MacroAssembler::fld_s(AddressLiteral src) {
2155 fld_s(as_Address(src));
2156 }
2157
2158 void MacroAssembler::fldcw(AddressLiteral src) {
2159 fldcw(as_Address(src));
2160 }
2161
2162 void MacroAssembler::fpop() {
2163 ffree();
2164 fincstp();
2165 }
2166
2167 void MacroAssembler::fremr(Register tmp) {
2168 save_rax(tmp);
2169 { Label L;
2170 bind(L);
2171 fprem();
2172 fwait(); fnstsw_ax();
2173 sahf();
2174 jcc(Assembler::parity, L);
2175 }
2176 restore_rax(tmp);
2177 // Result is in ST0.
2178 // Note: fxch & fpop to get rid of ST1
2179 // (otherwise FPU stack could overflow eventually)
2180 fxch(1);
2181 fpop();
2182 }
2183
2184 void MacroAssembler::empty_FPU_stack() {
2185 if (VM_Version::supports_mmx()) {
2186 emms();
2187 } else {
2188 for (int i = 8; i-- > 0; ) ffree(i);
2189 }
2190 }
2191 #endif // !LP64
2192
2193 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2194 assert(rscratch != noreg || always_reachable(src), "missing");
2195 if (reachable(src)) {
2196 Assembler::mulpd(dst, as_Address(src));
2197 } else {
2198 lea(rscratch, src);
2199 Assembler::mulpd(dst, Address(rscratch, 0));
2200 }
2201 }
2202
2203 void MacroAssembler::load_float(Address src) {
2204 #ifdef _LP64
2205 movflt(xmm0, src);
2206 #else
2207 if (UseSSE >= 1) {
2208 movflt(xmm0, src);
2209 } else {
2210 fld_s(src);
2211 }
2212 #endif // LP64
2213 }
2214
2215 void MacroAssembler::store_float(Address dst) {
2216 #ifdef _LP64
2217 movflt(dst, xmm0);
2218 #else
2219 if (UseSSE >= 1) {
2220 movflt(dst, xmm0);
2221 } else {
2222 fstp_s(dst);
2223 }
2224 #endif // LP64
2225 }
2226
2227 void MacroAssembler::load_double(Address src) {
2228 #ifdef _LP64
2229 movdbl(xmm0, src);
2230 #else
2231 if (UseSSE >= 2) {
2232 movdbl(xmm0, src);
2233 } else {
2234 fld_d(src);
2235 }
2236 #endif // LP64
2237 }
2238
2239 void MacroAssembler::store_double(Address dst) {
2240 #ifdef _LP64
2241 movdbl(dst, xmm0);
2242 #else
2243 if (UseSSE >= 2) {
2244 movdbl(dst, xmm0);
2245 } else {
2246 fstp_d(dst);
2247 }
2248 #endif // LP64
2249 }
2250
2251 // dst = c = a * b + c
2252 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2253 Assembler::vfmadd231sd(c, a, b);
2254 if (dst != c) {
2255 movdbl(dst, c);
2256 }
2257 }
2258
2259 // dst = c = a * b + c
2260 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2261 Assembler::vfmadd231ss(c, a, b);
2262 if (dst != c) {
2263 movflt(dst, c);
2264 }
2265 }
2266
2267 // dst = c = a * b + c
2268 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2269 Assembler::vfmadd231pd(c, a, b, vector_len);
2270 if (dst != c) {
2271 vmovdqu(dst, c);
2272 }
2273 }
2274
2275 // dst = c = a * b + c
2276 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2277 Assembler::vfmadd231ps(c, a, b, vector_len);
2278 if (dst != c) {
2279 vmovdqu(dst, c);
2280 }
2281 }
2282
2283 // dst = c = a * b + c
2284 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2285 Assembler::vfmadd231pd(c, a, b, vector_len);
2286 if (dst != c) {
2287 vmovdqu(dst, c);
2288 }
2289 }
2290
2291 // dst = c = a * b + c
2292 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2293 Assembler::vfmadd231ps(c, a, b, vector_len);
2294 if (dst != c) {
2295 vmovdqu(dst, c);
2296 }
2297 }
2298
2299 void MacroAssembler::incrementl(AddressLiteral dst, Register rscratch) {
2300 assert(rscratch != noreg || always_reachable(dst), "missing");
2301
2302 if (reachable(dst)) {
2303 incrementl(as_Address(dst));
2304 } else {
2305 lea(rscratch, dst);
2306 incrementl(Address(rscratch, 0));
2307 }
2308 }
2309
2310 void MacroAssembler::incrementl(ArrayAddress dst, Register rscratch) {
2311 incrementl(as_Address(dst, rscratch));
2312 }
2313
2314 void MacroAssembler::incrementl(Register reg, int value) {
2315 if (value == min_jint) {addl(reg, value) ; return; }
2316 if (value < 0) { decrementl(reg, -value); return; }
2317 if (value == 0) { ; return; }
2318 if (value == 1 && UseIncDec) { incl(reg) ; return; }
2319 /* else */ { addl(reg, value) ; return; }
2320 }
2321
2322 void MacroAssembler::incrementl(Address dst, int value) {
2323 if (value == min_jint) {addl(dst, value) ; return; }
2324 if (value < 0) { decrementl(dst, -value); return; }
2325 if (value == 0) { ; return; }
2326 if (value == 1 && UseIncDec) { incl(dst) ; return; }
2327 /* else */ { addl(dst, value) ; return; }
2328 }
2329
2330 void MacroAssembler::jump(AddressLiteral dst, Register rscratch) {
2331 assert(rscratch != noreg || always_reachable(dst), "missing");
2332 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump");
2333 if (reachable(dst)) {
2334 jmp_literal(dst.target(), dst.rspec());
2335 } else {
2336 lea(rscratch, dst);
2337 jmp(rscratch);
2338 }
2339 }
2340
2341 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst, Register rscratch) {
2342 assert(rscratch != noreg || always_reachable(dst), "missing");
2343 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump_cc");
2344 if (reachable(dst)) {
2345 InstructionMark im(this);
2346 relocate(dst.reloc());
2347 const int short_size = 2;
2348 const int long_size = 6;
2349 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
2350 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
2351 // 0111 tttn #8-bit disp
2352 emit_int8(0x70 | cc);
2353 emit_int8((offs - short_size) & 0xFF);
2354 } else {
2355 // 0000 1111 1000 tttn #32-bit disp
2356 emit_int8(0x0F);
2357 emit_int8((unsigned char)(0x80 | cc));
2358 emit_int32(offs - long_size);
2359 }
2360 } else {
2361 #ifdef ASSERT
2362 warning("reversing conditional branch");
2363 #endif /* ASSERT */
2364 Label skip;
2365 jccb(reverse[cc], skip);
2366 lea(rscratch, dst);
2367 Assembler::jmp(rscratch);
2368 bind(skip);
2369 }
2370 }
2371
2372 void MacroAssembler::ldmxcsr(AddressLiteral src, Register rscratch) {
2373 assert(rscratch != noreg || always_reachable(src), "missing");
2374
2375 if (reachable(src)) {
2376 Assembler::ldmxcsr(as_Address(src));
2377 } else {
2378 lea(rscratch, src);
2379 Assembler::ldmxcsr(Address(rscratch, 0));
2380 }
2381 }
2382
2383 int MacroAssembler::load_signed_byte(Register dst, Address src) {
2384 int off;
2385 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2386 off = offset();
2387 movsbl(dst, src); // movsxb
2388 } else {
2389 off = load_unsigned_byte(dst, src);
2390 shll(dst, 24);
2391 sarl(dst, 24);
2392 }
2393 return off;
2394 }
2395
2396 // Note: load_signed_short used to be called load_signed_word.
2397 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
2398 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
2399 // The term "word" in HotSpot means a 32- or 64-bit machine word.
2400 int MacroAssembler::load_signed_short(Register dst, Address src) {
2401 int off;
2402 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2403 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
2404 // version but this is what 64bit has always done. This seems to imply
2405 // that users are only using 32bits worth.
2406 off = offset();
2407 movswl(dst, src); // movsxw
2408 } else {
2409 off = load_unsigned_short(dst, src);
2410 shll(dst, 16);
2411 sarl(dst, 16);
2412 }
2413 return off;
2414 }
2415
2416 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
2417 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2418 // and "3.9 Partial Register Penalties", p. 22).
2419 int off;
2420 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
2421 off = offset();
2422 movzbl(dst, src); // movzxb
2423 } else {
2424 xorl(dst, dst);
2425 off = offset();
2426 movb(dst, src);
2427 }
2428 return off;
2429 }
2430
2431 // Note: load_unsigned_short used to be called load_unsigned_word.
2432 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
2433 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2434 // and "3.9 Partial Register Penalties", p. 22).
2435 int off;
2436 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
2437 off = offset();
2438 movzwl(dst, src); // movzxw
2439 } else {
2440 xorl(dst, dst);
2441 off = offset();
2442 movw(dst, src);
2443 }
2444 return off;
2445 }
2446
2447 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
2448 switch (size_in_bytes) {
2449 #ifndef _LP64
2450 case 8:
2451 assert(dst2 != noreg, "second dest register required");
2452 movl(dst, src);
2453 movl(dst2, src.plus_disp(BytesPerInt));
2454 break;
2455 #else
2456 case 8: movq(dst, src); break;
2457 #endif
2458 case 4: movl(dst, src); break;
2459 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
2460 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
2461 default: ShouldNotReachHere();
2462 }
2463 }
2464
2465 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
2466 switch (size_in_bytes) {
2467 #ifndef _LP64
2468 case 8:
2469 assert(src2 != noreg, "second source register required");
2470 movl(dst, src);
2471 movl(dst.plus_disp(BytesPerInt), src2);
2472 break;
2473 #else
2474 case 8: movq(dst, src); break;
2475 #endif
2476 case 4: movl(dst, src); break;
2477 case 2: movw(dst, src); break;
2478 case 1: movb(dst, src); break;
2479 default: ShouldNotReachHere();
2480 }
2481 }
2482
2483 void MacroAssembler::mov32(AddressLiteral dst, Register src, Register rscratch) {
2484 assert(rscratch != noreg || always_reachable(dst), "missing");
2485
2486 if (reachable(dst)) {
2487 movl(as_Address(dst), src);
2488 } else {
2489 lea(rscratch, dst);
2490 movl(Address(rscratch, 0), src);
2491 }
2492 }
2493
2494 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
2495 if (reachable(src)) {
2496 movl(dst, as_Address(src));
2497 } else {
2498 lea(dst, src);
2499 movl(dst, Address(dst, 0));
2500 }
2501 }
2502
2503 // C++ bool manipulation
2504
2505 void MacroAssembler::movbool(Register dst, Address src) {
2506 if(sizeof(bool) == 1)
2507 movb(dst, src);
2508 else if(sizeof(bool) == 2)
2509 movw(dst, src);
2510 else if(sizeof(bool) == 4)
2511 movl(dst, src);
2512 else
2513 // unsupported
2514 ShouldNotReachHere();
2515 }
2516
2517 void MacroAssembler::movbool(Address dst, bool boolconst) {
2518 if(sizeof(bool) == 1)
2519 movb(dst, (int) boolconst);
2520 else if(sizeof(bool) == 2)
2521 movw(dst, (int) boolconst);
2522 else if(sizeof(bool) == 4)
2523 movl(dst, (int) boolconst);
2524 else
2525 // unsupported
2526 ShouldNotReachHere();
2527 }
2528
2529 void MacroAssembler::movbool(Address dst, Register src) {
2530 if(sizeof(bool) == 1)
2531 movb(dst, src);
2532 else if(sizeof(bool) == 2)
2533 movw(dst, src);
2534 else if(sizeof(bool) == 4)
2535 movl(dst, src);
2536 else
2537 // unsupported
2538 ShouldNotReachHere();
2539 }
2540
2541 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src, Register rscratch) {
2542 assert(rscratch != noreg || always_reachable(src), "missing");
2543
2544 if (reachable(src)) {
2545 movdl(dst, as_Address(src));
2546 } else {
2547 lea(rscratch, src);
2548 movdl(dst, Address(rscratch, 0));
2549 }
2550 }
2551
2552 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src, Register rscratch) {
2553 assert(rscratch != noreg || always_reachable(src), "missing");
2554
2555 if (reachable(src)) {
2556 movq(dst, as_Address(src));
2557 } else {
2558 lea(rscratch, src);
2559 movq(dst, Address(rscratch, 0));
2560 }
2561 }
2562
2563 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src, Register rscratch) {
2564 assert(rscratch != noreg || always_reachable(src), "missing");
2565
2566 if (reachable(src)) {
2567 if (UseXmmLoadAndClearUpper) {
2568 movsd (dst, as_Address(src));
2569 } else {
2570 movlpd(dst, as_Address(src));
2571 }
2572 } else {
2573 lea(rscratch, src);
2574 if (UseXmmLoadAndClearUpper) {
2575 movsd (dst, Address(rscratch, 0));
2576 } else {
2577 movlpd(dst, Address(rscratch, 0));
2578 }
2579 }
2580 }
2581
2582 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src, Register rscratch) {
2583 assert(rscratch != noreg || always_reachable(src), "missing");
2584
2585 if (reachable(src)) {
2586 movss(dst, as_Address(src));
2587 } else {
2588 lea(rscratch, src);
2589 movss(dst, Address(rscratch, 0));
2590 }
2591 }
2592
2593 void MacroAssembler::movptr(Register dst, Register src) {
2594 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2595 }
2596
2597 void MacroAssembler::movptr(Register dst, Address src) {
2598 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2599 }
2600
2601 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
2602 void MacroAssembler::movptr(Register dst, intptr_t src) {
2603 #ifdef _LP64
2604 if (is_uimm32(src)) {
2605 movl(dst, checked_cast<uint32_t>(src));
2606 } else if (is_simm32(src)) {
2607 movq(dst, checked_cast<int32_t>(src));
2608 } else {
2609 mov64(dst, src);
2610 }
2611 #else
2612 movl(dst, src);
2613 #endif
2614 }
2615
2616 void MacroAssembler::movptr(Address dst, Register src) {
2617 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2618 }
2619
2620 void MacroAssembler::movptr(Address dst, int32_t src) {
2621 LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src));
2622 }
2623
2624 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
2625 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2626 Assembler::movdqu(dst, src);
2627 }
2628
2629 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
2630 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2631 Assembler::movdqu(dst, src);
2632 }
2633
2634 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
2635 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2636 Assembler::movdqu(dst, src);
2637 }
2638
2639 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2640 assert(rscratch != noreg || always_reachable(src), "missing");
2641
2642 if (reachable(src)) {
2643 movdqu(dst, as_Address(src));
2644 } else {
2645 lea(rscratch, src);
2646 movdqu(dst, Address(rscratch, 0));
2647 }
2648 }
2649
2650 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
2651 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2652 Assembler::vmovdqu(dst, src);
2653 }
2654
2655 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
2656 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2657 Assembler::vmovdqu(dst, src);
2658 }
2659
2660 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2661 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2662 Assembler::vmovdqu(dst, src);
2663 }
2664
2665 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2666 assert(rscratch != noreg || always_reachable(src), "missing");
2667
2668 if (reachable(src)) {
2669 vmovdqu(dst, as_Address(src));
2670 }
2671 else {
2672 lea(rscratch, src);
2673 vmovdqu(dst, Address(rscratch, 0));
2674 }
2675 }
2676
2677 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2678 assert(rscratch != noreg || always_reachable(src), "missing");
2679
2680 if (vector_len == AVX_512bit) {
2681 evmovdquq(dst, src, AVX_512bit, rscratch);
2682 } else if (vector_len == AVX_256bit) {
2683 vmovdqu(dst, src, rscratch);
2684 } else {
2685 movdqu(dst, src, rscratch);
2686 }
2687 }
2688
2689 void MacroAssembler::kmov(KRegister dst, Address src) {
2690 if (VM_Version::supports_avx512bw()) {
2691 kmovql(dst, src);
2692 } else {
2693 assert(VM_Version::supports_evex(), "");
2694 kmovwl(dst, src);
2695 }
2696 }
2697
2698 void MacroAssembler::kmov(Address dst, KRegister src) {
2699 if (VM_Version::supports_avx512bw()) {
2700 kmovql(dst, src);
2701 } else {
2702 assert(VM_Version::supports_evex(), "");
2703 kmovwl(dst, src);
2704 }
2705 }
2706
2707 void MacroAssembler::kmov(KRegister dst, KRegister src) {
2708 if (VM_Version::supports_avx512bw()) {
2709 kmovql(dst, src);
2710 } else {
2711 assert(VM_Version::supports_evex(), "");
2712 kmovwl(dst, src);
2713 }
2714 }
2715
2716 void MacroAssembler::kmov(Register dst, KRegister src) {
2717 if (VM_Version::supports_avx512bw()) {
2718 kmovql(dst, src);
2719 } else {
2720 assert(VM_Version::supports_evex(), "");
2721 kmovwl(dst, src);
2722 }
2723 }
2724
2725 void MacroAssembler::kmov(KRegister dst, Register src) {
2726 if (VM_Version::supports_avx512bw()) {
2727 kmovql(dst, src);
2728 } else {
2729 assert(VM_Version::supports_evex(), "");
2730 kmovwl(dst, src);
2731 }
2732 }
2733
2734 void MacroAssembler::kmovql(KRegister dst, AddressLiteral src, Register rscratch) {
2735 assert(rscratch != noreg || always_reachable(src), "missing");
2736
2737 if (reachable(src)) {
2738 kmovql(dst, as_Address(src));
2739 } else {
2740 lea(rscratch, src);
2741 kmovql(dst, Address(rscratch, 0));
2742 }
2743 }
2744
2745 void MacroAssembler::kmovwl(KRegister dst, AddressLiteral src, Register rscratch) {
2746 assert(rscratch != noreg || always_reachable(src), "missing");
2747
2748 if (reachable(src)) {
2749 kmovwl(dst, as_Address(src));
2750 } else {
2751 lea(rscratch, src);
2752 kmovwl(dst, Address(rscratch, 0));
2753 }
2754 }
2755
2756 void MacroAssembler::evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2757 int vector_len, Register rscratch) {
2758 assert(rscratch != noreg || always_reachable(src), "missing");
2759
2760 if (reachable(src)) {
2761 Assembler::evmovdqub(dst, mask, as_Address(src), merge, vector_len);
2762 } else {
2763 lea(rscratch, src);
2764 Assembler::evmovdqub(dst, mask, Address(rscratch, 0), merge, vector_len);
2765 }
2766 }
2767
2768 void MacroAssembler::evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2769 int vector_len, Register rscratch) {
2770 assert(rscratch != noreg || always_reachable(src), "missing");
2771
2772 if (reachable(src)) {
2773 Assembler::evmovdquw(dst, mask, as_Address(src), merge, vector_len);
2774 } else {
2775 lea(rscratch, src);
2776 Assembler::evmovdquw(dst, mask, Address(rscratch, 0), merge, vector_len);
2777 }
2778 }
2779
2780 void MacroAssembler::evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2781 assert(rscratch != noreg || always_reachable(src), "missing");
2782
2783 if (reachable(src)) {
2784 Assembler::evmovdqul(dst, mask, as_Address(src), merge, vector_len);
2785 } else {
2786 lea(rscratch, src);
2787 Assembler::evmovdqul(dst, mask, Address(rscratch, 0), merge, vector_len);
2788 }
2789 }
2790
2791 void MacroAssembler::evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2792 assert(rscratch != noreg || always_reachable(src), "missing");
2793
2794 if (reachable(src)) {
2795 Assembler::evmovdquq(dst, mask, as_Address(src), merge, vector_len);
2796 } else {
2797 lea(rscratch, src);
2798 Assembler::evmovdquq(dst, mask, Address(rscratch, 0), merge, vector_len);
2799 }
2800 }
2801
2802 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2803 assert(rscratch != noreg || always_reachable(src), "missing");
2804
2805 if (reachable(src)) {
2806 Assembler::evmovdquq(dst, as_Address(src), vector_len);
2807 } else {
2808 lea(rscratch, src);
2809 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
2810 }
2811 }
2812
2813 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2814 assert(rscratch != noreg || always_reachable(src), "missing");
2815
2816 if (reachable(src)) {
2817 Assembler::movdqa(dst, as_Address(src));
2818 } else {
2819 lea(rscratch, src);
2820 Assembler::movdqa(dst, Address(rscratch, 0));
2821 }
2822 }
2823
2824 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2825 assert(rscratch != noreg || always_reachable(src), "missing");
2826
2827 if (reachable(src)) {
2828 Assembler::movsd(dst, as_Address(src));
2829 } else {
2830 lea(rscratch, src);
2831 Assembler::movsd(dst, Address(rscratch, 0));
2832 }
2833 }
2834
2835 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2836 assert(rscratch != noreg || always_reachable(src), "missing");
2837
2838 if (reachable(src)) {
2839 Assembler::movss(dst, as_Address(src));
2840 } else {
2841 lea(rscratch, src);
2842 Assembler::movss(dst, Address(rscratch, 0));
2843 }
2844 }
2845
2846 void MacroAssembler::movddup(XMMRegister dst, AddressLiteral src, Register rscratch) {
2847 assert(rscratch != noreg || always_reachable(src), "missing");
2848
2849 if (reachable(src)) {
2850 Assembler::movddup(dst, as_Address(src));
2851 } else {
2852 lea(rscratch, src);
2853 Assembler::movddup(dst, Address(rscratch, 0));
2854 }
2855 }
2856
2857 void MacroAssembler::vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2858 assert(rscratch != noreg || always_reachable(src), "missing");
2859
2860 if (reachable(src)) {
2861 Assembler::vmovddup(dst, as_Address(src), vector_len);
2862 } else {
2863 lea(rscratch, src);
2864 Assembler::vmovddup(dst, Address(rscratch, 0), vector_len);
2865 }
2866 }
2867
2868 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2869 assert(rscratch != noreg || always_reachable(src), "missing");
2870
2871 if (reachable(src)) {
2872 Assembler::mulsd(dst, as_Address(src));
2873 } else {
2874 lea(rscratch, src);
2875 Assembler::mulsd(dst, Address(rscratch, 0));
2876 }
2877 }
2878
2879 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2880 assert(rscratch != noreg || always_reachable(src), "missing");
2881
2882 if (reachable(src)) {
2883 Assembler::mulss(dst, as_Address(src));
2884 } else {
2885 lea(rscratch, src);
2886 Assembler::mulss(dst, Address(rscratch, 0));
2887 }
2888 }
2889
2890 void MacroAssembler::null_check(Register reg, int offset) {
2891 if (needs_explicit_null_check(offset)) {
2892 // provoke OS null exception if reg is null by
2893 // accessing M[reg] w/o changing any (non-CC) registers
2894 // NOTE: cmpl is plenty here to provoke a segv
2895 cmpptr(rax, Address(reg, 0));
2896 // Note: should probably use testl(rax, Address(reg, 0));
2897 // may be shorter code (however, this version of
2898 // testl needs to be implemented first)
2899 } else {
2900 // nothing to do, (later) access of M[reg + offset]
2901 // will provoke OS null exception if reg is null
2902 }
2903 }
2904
2905 void MacroAssembler::os_breakpoint() {
2906 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
2907 // (e.g., MSVC can't call ps() otherwise)
2908 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
2909 }
2910
2911 void MacroAssembler::unimplemented(const char* what) {
2912 const char* buf = nullptr;
2913 {
2914 ResourceMark rm;
2915 stringStream ss;
2916 ss.print("unimplemented: %s", what);
2917 buf = code_string(ss.as_string());
2918 }
2919 stop(buf);
2920 }
2921
2922 #ifdef _LP64
2923 #define XSTATE_BV 0x200
2924 #endif
2925
2926 void MacroAssembler::pop_CPU_state() {
2927 pop_FPU_state();
2928 pop_IU_state();
2929 }
2930
2931 void MacroAssembler::pop_FPU_state() {
2932 #ifndef _LP64
2933 frstor(Address(rsp, 0));
2934 #else
2935 fxrstor(Address(rsp, 0));
2936 #endif
2937 addptr(rsp, FPUStateSizeInWords * wordSize);
2938 }
2939
2940 void MacroAssembler::pop_IU_state() {
2941 popa();
2942 LP64_ONLY(addq(rsp, 8));
2943 popf();
2944 }
2945
2946 // Save Integer and Float state
2947 // Warning: Stack must be 16 byte aligned (64bit)
2948 void MacroAssembler::push_CPU_state() {
2949 push_IU_state();
2950 push_FPU_state();
2951 }
2952
2953 void MacroAssembler::push_FPU_state() {
2954 subptr(rsp, FPUStateSizeInWords * wordSize);
2955 #ifndef _LP64
2956 fnsave(Address(rsp, 0));
2957 fwait();
2958 #else
2959 fxsave(Address(rsp, 0));
2960 #endif // LP64
2961 }
2962
2963 void MacroAssembler::push_IU_state() {
2964 // Push flags first because pusha kills them
2965 pushf();
2966 // Make sure rsp stays 16-byte aligned
2967 LP64_ONLY(subq(rsp, 8));
2968 pusha();
2969 }
2970
2971 void MacroAssembler::push_cont_fastpath() {
2972 if (!Continuations::enabled()) return;
2973
2974 #ifndef _LP64
2975 Register rthread = rax;
2976 Register rrealsp = rbx;
2977 push(rthread);
2978 push(rrealsp);
2979
2980 get_thread(rthread);
2981
2982 // The code below wants the original RSP.
2983 // Move it back after the pushes above.
2984 movptr(rrealsp, rsp);
2985 addptr(rrealsp, 2*wordSize);
2986 #else
2987 Register rthread = r15_thread;
2988 Register rrealsp = rsp;
2989 #endif
2990
2991 Label done;
2992 cmpptr(rrealsp, Address(rthread, JavaThread::cont_fastpath_offset()));
2993 jccb(Assembler::belowEqual, done);
2994 movptr(Address(rthread, JavaThread::cont_fastpath_offset()), rrealsp);
2995 bind(done);
2996
2997 #ifndef _LP64
2998 pop(rrealsp);
2999 pop(rthread);
3000 #endif
3001 }
3002
3003 void MacroAssembler::pop_cont_fastpath() {
3004 if (!Continuations::enabled()) return;
3005
3006 #ifndef _LP64
3007 Register rthread = rax;
3008 Register rrealsp = rbx;
3009 push(rthread);
3010 push(rrealsp);
3011
3012 get_thread(rthread);
3013
3014 // The code below wants the original RSP.
3015 // Move it back after the pushes above.
3016 movptr(rrealsp, rsp);
3017 addptr(rrealsp, 2*wordSize);
3018 #else
3019 Register rthread = r15_thread;
3020 Register rrealsp = rsp;
3021 #endif
3022
3023 Label done;
3024 cmpptr(rrealsp, Address(rthread, JavaThread::cont_fastpath_offset()));
3025 jccb(Assembler::below, done);
3026 movptr(Address(rthread, JavaThread::cont_fastpath_offset()), 0);
3027 bind(done);
3028
3029 #ifndef _LP64
3030 pop(rrealsp);
3031 pop(rthread);
3032 #endif
3033 }
3034
3035 void MacroAssembler::inc_held_monitor_count() {
3036 #ifndef _LP64
3037 Register thread = rax;
3038 push(thread);
3039 get_thread(thread);
3040 incrementl(Address(thread, JavaThread::held_monitor_count_offset()));
3041 pop(thread);
3042 #else // LP64
3043 incrementq(Address(r15_thread, JavaThread::held_monitor_count_offset()));
3044 #endif
3045 }
3046
3047 void MacroAssembler::dec_held_monitor_count() {
3048 #ifndef _LP64
3049 Register thread = rax;
3050 push(thread);
3051 get_thread(thread);
3052 decrementl(Address(thread, JavaThread::held_monitor_count_offset()));
3053 pop(thread);
3054 #else // LP64
3055 decrementq(Address(r15_thread, JavaThread::held_monitor_count_offset()));
3056 #endif
3057 }
3058
3059 #ifdef ASSERT
3060 void MacroAssembler::stop_if_in_cont(Register cont, const char* name) {
3061 #ifdef _LP64
3062 Label no_cont;
3063 movptr(cont, Address(r15_thread, JavaThread::cont_entry_offset()));
3064 testl(cont, cont);
3065 jcc(Assembler::zero, no_cont);
3066 stop(name);
3067 bind(no_cont);
3068 #else
3069 Unimplemented();
3070 #endif
3071 }
3072 #endif
3073
3074 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
3075 if (!java_thread->is_valid()) {
3076 java_thread = rdi;
3077 get_thread(java_thread);
3078 }
3079 // we must set sp to zero to clear frame
3080 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3081 // must clear fp, so that compiled frames are not confused; it is
3082 // possible that we need it only for debugging
3083 if (clear_fp) {
3084 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3085 }
3086 // Always clear the pc because it could have been set by make_walkable()
3087 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3088 vzeroupper();
3089 }
3090
3091 void MacroAssembler::restore_rax(Register tmp) {
3092 if (tmp == noreg) pop(rax);
3093 else if (tmp != rax) mov(rax, tmp);
3094 }
3095
3096 void MacroAssembler::round_to(Register reg, int modulus) {
3097 addptr(reg, modulus - 1);
3098 andptr(reg, -modulus);
3099 }
3100
3101 void MacroAssembler::save_rax(Register tmp) {
3102 if (tmp == noreg) push(rax);
3103 else if (tmp != rax) mov(tmp, rax);
3104 }
3105
3106 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, bool at_return, bool in_nmethod) {
3107 if (at_return) {
3108 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
3109 // we may safely use rsp instead to perform the stack watermark check.
3110 cmpptr(in_nmethod ? rsp : rbp, Address(thread_reg, JavaThread::polling_word_offset()));
3111 jcc(Assembler::above, slow_path);
3112 return;
3113 }
3114 testb(Address(thread_reg, JavaThread::polling_word_offset()), SafepointMechanism::poll_bit());
3115 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
3116 }
3117
3118 // Calls to C land
3119 //
3120 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3121 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3122 // has to be reset to 0. This is required to allow proper stack traversal.
3123 void MacroAssembler::set_last_Java_frame(Register java_thread,
3124 Register last_java_sp,
3125 Register last_java_fp,
3126 address last_java_pc,
3127 Register rscratch) {
3128 vzeroupper();
3129 // determine java_thread register
3130 if (!java_thread->is_valid()) {
3131 java_thread = rdi;
3132 get_thread(java_thread);
3133 }
3134 // determine last_java_sp register
3135 if (!last_java_sp->is_valid()) {
3136 last_java_sp = rsp;
3137 }
3138 // last_java_fp is optional
3139 if (last_java_fp->is_valid()) {
3140 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3141 }
3142 // last_java_pc is optional
3143 if (last_java_pc != nullptr) {
3144 Address java_pc(java_thread,
3145 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
3146 lea(java_pc, InternalAddress(last_java_pc), rscratch);
3147 }
3148 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3149 }
3150
3151 void MacroAssembler::shlptr(Register dst, int imm8) {
3152 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3153 }
3154
3155 void MacroAssembler::shrptr(Register dst, int imm8) {
3156 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3157 }
3158
3159 void MacroAssembler::sign_extend_byte(Register reg) {
3160 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3161 movsbl(reg, reg); // movsxb
3162 } else {
3163 shll(reg, 24);
3164 sarl(reg, 24);
3165 }
3166 }
3167
3168 void MacroAssembler::sign_extend_short(Register reg) {
3169 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3170 movswl(reg, reg); // movsxw
3171 } else {
3172 shll(reg, 16);
3173 sarl(reg, 16);
3174 }
3175 }
3176
3177 void MacroAssembler::testl(Address dst, int32_t imm32) {
3178 if (imm32 >= 0 && is8bit(imm32)) {
3179 testb(dst, imm32);
3180 } else {
3181 Assembler::testl(dst, imm32);
3182 }
3183 }
3184
3185 void MacroAssembler::testl(Register dst, int32_t imm32) {
3186 if (imm32 >= 0 && is8bit(imm32) && dst->has_byte_register()) {
3187 testb(dst, imm32);
3188 } else {
3189 Assembler::testl(dst, imm32);
3190 }
3191 }
3192
3193 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3194 assert(always_reachable(src), "Address should be reachable");
3195 testl(dst, as_Address(src));
3196 }
3197
3198 #ifdef _LP64
3199
3200 void MacroAssembler::testq(Address dst, int32_t imm32) {
3201 if (imm32 >= 0) {
3202 testl(dst, imm32);
3203 } else {
3204 Assembler::testq(dst, imm32);
3205 }
3206 }
3207
3208 void MacroAssembler::testq(Register dst, int32_t imm32) {
3209 if (imm32 >= 0) {
3210 testl(dst, imm32);
3211 } else {
3212 Assembler::testq(dst, imm32);
3213 }
3214 }
3215
3216 #endif
3217
3218 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3219 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3220 Assembler::pcmpeqb(dst, src);
3221 }
3222
3223 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3224 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3225 Assembler::pcmpeqw(dst, src);
3226 }
3227
3228 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3229 assert((dst->encoding() < 16),"XMM register should be 0-15");
3230 Assembler::pcmpestri(dst, src, imm8);
3231 }
3232
3233 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3234 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3235 Assembler::pcmpestri(dst, src, imm8);
3236 }
3237
3238 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3239 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3240 Assembler::pmovzxbw(dst, src);
3241 }
3242
3243 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
3244 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3245 Assembler::pmovzxbw(dst, src);
3246 }
3247
3248 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
3249 assert((src->encoding() < 16),"XMM register should be 0-15");
3250 Assembler::pmovmskb(dst, src);
3251 }
3252
3253 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
3254 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3255 Assembler::ptest(dst, src);
3256 }
3257
3258 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src, Register rscratch) {
3259 assert(rscratch != noreg || always_reachable(src), "missing");
3260
3261 if (reachable(src)) {
3262 Assembler::sqrtss(dst, as_Address(src));
3263 } else {
3264 lea(rscratch, src);
3265 Assembler::sqrtss(dst, Address(rscratch, 0));
3266 }
3267 }
3268
3269 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
3270 assert(rscratch != noreg || always_reachable(src), "missing");
3271
3272 if (reachable(src)) {
3273 Assembler::subsd(dst, as_Address(src));
3274 } else {
3275 lea(rscratch, src);
3276 Assembler::subsd(dst, Address(rscratch, 0));
3277 }
3278 }
3279
3280 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register rscratch) {
3281 assert(rscratch != noreg || always_reachable(src), "missing");
3282
3283 if (reachable(src)) {
3284 Assembler::roundsd(dst, as_Address(src), rmode);
3285 } else {
3286 lea(rscratch, src);
3287 Assembler::roundsd(dst, Address(rscratch, 0), rmode);
3288 }
3289 }
3290
3291 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src, Register rscratch) {
3292 assert(rscratch != noreg || always_reachable(src), "missing");
3293
3294 if (reachable(src)) {
3295 Assembler::subss(dst, as_Address(src));
3296 } else {
3297 lea(rscratch, src);
3298 Assembler::subss(dst, Address(rscratch, 0));
3299 }
3300 }
3301
3302 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
3303 assert(rscratch != noreg || always_reachable(src), "missing");
3304
3305 if (reachable(src)) {
3306 Assembler::ucomisd(dst, as_Address(src));
3307 } else {
3308 lea(rscratch, src);
3309 Assembler::ucomisd(dst, Address(rscratch, 0));
3310 }
3311 }
3312
3313 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
3314 assert(rscratch != noreg || always_reachable(src), "missing");
3315
3316 if (reachable(src)) {
3317 Assembler::ucomiss(dst, as_Address(src));
3318 } else {
3319 lea(rscratch, src);
3320 Assembler::ucomiss(dst, Address(rscratch, 0));
3321 }
3322 }
3323
3324 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
3325 assert(rscratch != noreg || always_reachable(src), "missing");
3326
3327 // Used in sign-bit flipping with aligned address.
3328 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3329 if (reachable(src)) {
3330 Assembler::xorpd(dst, as_Address(src));
3331 } else {
3332 lea(rscratch, src);
3333 Assembler::xorpd(dst, Address(rscratch, 0));
3334 }
3335 }
3336
3337 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
3338 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3339 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3340 }
3341 else {
3342 Assembler::xorpd(dst, src);
3343 }
3344 }
3345
3346 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
3347 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3348 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3349 } else {
3350 Assembler::xorps(dst, src);
3351 }
3352 }
3353
3354 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register rscratch) {
3355 assert(rscratch != noreg || always_reachable(src), "missing");
3356
3357 // Used in sign-bit flipping with aligned address.
3358 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3359 if (reachable(src)) {
3360 Assembler::xorps(dst, as_Address(src));
3361 } else {
3362 lea(rscratch, src);
3363 Assembler::xorps(dst, Address(rscratch, 0));
3364 }
3365 }
3366
3367 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src, Register rscratch) {
3368 assert(rscratch != noreg || always_reachable(src), "missing");
3369
3370 // Used in sign-bit flipping with aligned address.
3371 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
3372 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
3373 if (reachable(src)) {
3374 Assembler::pshufb(dst, as_Address(src));
3375 } else {
3376 lea(rscratch, src);
3377 Assembler::pshufb(dst, Address(rscratch, 0));
3378 }
3379 }
3380
3381 // AVX 3-operands instructions
3382
3383 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3384 assert(rscratch != noreg || always_reachable(src), "missing");
3385
3386 if (reachable(src)) {
3387 vaddsd(dst, nds, as_Address(src));
3388 } else {
3389 lea(rscratch, src);
3390 vaddsd(dst, nds, Address(rscratch, 0));
3391 }
3392 }
3393
3394 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3395 assert(rscratch != noreg || always_reachable(src), "missing");
3396
3397 if (reachable(src)) {
3398 vaddss(dst, nds, as_Address(src));
3399 } else {
3400 lea(rscratch, src);
3401 vaddss(dst, nds, Address(rscratch, 0));
3402 }
3403 }
3404
3405 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3406 assert(UseAVX > 0, "requires some form of AVX");
3407 assert(rscratch != noreg || always_reachable(src), "missing");
3408
3409 if (reachable(src)) {
3410 Assembler::vpaddb(dst, nds, as_Address(src), vector_len);
3411 } else {
3412 lea(rscratch, src);
3413 Assembler::vpaddb(dst, nds, Address(rscratch, 0), vector_len);
3414 }
3415 }
3416
3417 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3418 assert(UseAVX > 0, "requires some form of AVX");
3419 assert(rscratch != noreg || always_reachable(src), "missing");
3420
3421 if (reachable(src)) {
3422 Assembler::vpaddd(dst, nds, as_Address(src), vector_len);
3423 } else {
3424 lea(rscratch, src);
3425 Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len);
3426 }
3427 }
3428
3429 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
3430 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3431 assert(rscratch != noreg || always_reachable(negate_field), "missing");
3432
3433 vandps(dst, nds, negate_field, vector_len, rscratch);
3434 }
3435
3436 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
3437 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3438 assert(rscratch != noreg || always_reachable(negate_field), "missing");
3439
3440 vandpd(dst, nds, negate_field, vector_len, rscratch);
3441 }
3442
3443 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3444 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3445 Assembler::vpaddb(dst, nds, src, vector_len);
3446 }
3447
3448 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3449 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3450 Assembler::vpaddb(dst, nds, src, vector_len);
3451 }
3452
3453 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3454 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3455 Assembler::vpaddw(dst, nds, src, vector_len);
3456 }
3457
3458 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3459 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3460 Assembler::vpaddw(dst, nds, src, vector_len);
3461 }
3462
3463 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3464 assert(rscratch != noreg || always_reachable(src), "missing");
3465
3466 if (reachable(src)) {
3467 Assembler::vpand(dst, nds, as_Address(src), vector_len);
3468 } else {
3469 lea(rscratch, src);
3470 Assembler::vpand(dst, nds, Address(rscratch, 0), vector_len);
3471 }
3472 }
3473
3474 void MacroAssembler::vpbroadcastd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3475 assert(rscratch != noreg || always_reachable(src), "missing");
3476
3477 if (reachable(src)) {
3478 Assembler::vpbroadcastd(dst, as_Address(src), vector_len);
3479 } else {
3480 lea(rscratch, src);
3481 Assembler::vpbroadcastd(dst, Address(rscratch, 0), vector_len);
3482 }
3483 }
3484
3485 void MacroAssembler::vbroadcasti128(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3486 assert(rscratch != noreg || always_reachable(src), "missing");
3487
3488 if (reachable(src)) {
3489 Assembler::vbroadcasti128(dst, as_Address(src), vector_len);
3490 } else {
3491 lea(rscratch, src);
3492 Assembler::vbroadcasti128(dst, Address(rscratch, 0), vector_len);
3493 }
3494 }
3495
3496 void MacroAssembler::vpbroadcastq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3497 assert(rscratch != noreg || always_reachable(src), "missing");
3498
3499 if (reachable(src)) {
3500 Assembler::vpbroadcastq(dst, as_Address(src), vector_len);
3501 } else {
3502 lea(rscratch, src);
3503 Assembler::vpbroadcastq(dst, Address(rscratch, 0), vector_len);
3504 }
3505 }
3506
3507 void MacroAssembler::vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3508 assert(rscratch != noreg || always_reachable(src), "missing");
3509
3510 if (reachable(src)) {
3511 Assembler::vbroadcastsd(dst, as_Address(src), vector_len);
3512 } else {
3513 lea(rscratch, src);
3514 Assembler::vbroadcastsd(dst, Address(rscratch, 0), vector_len);
3515 }
3516 }
3517
3518 void MacroAssembler::vbroadcastss(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3519 assert(rscratch != noreg || always_reachable(src), "missing");
3520
3521 if (reachable(src)) {
3522 Assembler::vbroadcastss(dst, as_Address(src), vector_len);
3523 } else {
3524 lea(rscratch, src);
3525 Assembler::vbroadcastss(dst, Address(rscratch, 0), vector_len);
3526 }
3527 }
3528
3529 // Vector float blend
3530 // vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3531 void MacroAssembler::vblendvps(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3532 // WARN: Allow dst == (src1|src2), mask == scratch
3533 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1;
3534 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst;
3535 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3536 if (blend_emulation && scratch_available && dst_available) {
3537 if (compute_mask) {
3538 vpsrad(scratch, mask, 32, vector_len);
3539 mask = scratch;
3540 }
3541 if (dst == src1) {
3542 vpandn(dst, mask, src1, vector_len); // if mask == 0, src1
3543 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3544 } else {
3545 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3546 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src1
3547 }
3548 vpor(dst, dst, scratch, vector_len);
3549 } else {
3550 Assembler::vblendvps(dst, src1, src2, mask, vector_len);
3551 }
3552 }
3553
3554 // vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3555 void MacroAssembler::vblendvpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3556 // WARN: Allow dst == (src1|src2), mask == scratch
3557 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1;
3558 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst && (!compute_mask || scratch != mask);
3559 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3560 if (blend_emulation && scratch_available && dst_available) {
3561 if (compute_mask) {
3562 vpxor(scratch, scratch, scratch, vector_len);
3563 vpcmpgtq(scratch, scratch, mask, vector_len);
3564 mask = scratch;
3565 }
3566 if (dst == src1) {
3567 vpandn(dst, mask, src1, vector_len); // if mask == 0, src
3568 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3569 } else {
3570 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3571 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src
3572 }
3573 vpor(dst, dst, scratch, vector_len);
3574 } else {
3575 Assembler::vblendvpd(dst, src1, src2, mask, vector_len);
3576 }
3577 }
3578
3579 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3580 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3581 Assembler::vpcmpeqb(dst, nds, src, vector_len);
3582 }
3583
3584 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
3585 assert(((dst->encoding() < 16 && src1->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3586 Assembler::vpcmpeqb(dst, src1, src2, vector_len);
3587 }
3588
3589 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3590 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3591 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3592 }
3593
3594 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3595 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3596 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3597 }
3598
3599 void MacroAssembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3600 assert(rscratch != noreg || always_reachable(src), "missing");
3601
3602 if (reachable(src)) {
3603 Assembler::evpcmpeqd(kdst, mask, nds, as_Address(src), vector_len);
3604 } else {
3605 lea(rscratch, src);
3606 Assembler::evpcmpeqd(kdst, mask, nds, Address(rscratch, 0), vector_len);
3607 }
3608 }
3609
3610 void MacroAssembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3611 int comparison, bool is_signed, int vector_len, Register rscratch) {
3612 assert(rscratch != noreg || always_reachable(src), "missing");
3613
3614 if (reachable(src)) {
3615 Assembler::evpcmpd(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3616 } else {
3617 lea(rscratch, src);
3618 Assembler::evpcmpd(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3619 }
3620 }
3621
3622 void MacroAssembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3623 int comparison, bool is_signed, int vector_len, Register rscratch) {
3624 assert(rscratch != noreg || always_reachable(src), "missing");
3625
3626 if (reachable(src)) {
3627 Assembler::evpcmpq(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3628 } else {
3629 lea(rscratch, src);
3630 Assembler::evpcmpq(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3631 }
3632 }
3633
3634 void MacroAssembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3635 int comparison, bool is_signed, int vector_len, Register rscratch) {
3636 assert(rscratch != noreg || always_reachable(src), "missing");
3637
3638 if (reachable(src)) {
3639 Assembler::evpcmpb(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3640 } else {
3641 lea(rscratch, src);
3642 Assembler::evpcmpb(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3643 }
3644 }
3645
3646 void MacroAssembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3647 int comparison, bool is_signed, int vector_len, Register rscratch) {
3648 assert(rscratch != noreg || always_reachable(src), "missing");
3649
3650 if (reachable(src)) {
3651 Assembler::evpcmpw(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3652 } else {
3653 lea(rscratch, src);
3654 Assembler::evpcmpw(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3655 }
3656 }
3657
3658 void MacroAssembler::vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len) {
3659 if (width == Assembler::Q) {
3660 Assembler::vpcmpCCq(dst, nds, src, cond_encoding, vector_len);
3661 } else {
3662 Assembler::vpcmpCCbwd(dst, nds, src, cond_encoding, vector_len);
3663 }
3664 }
3665
3666 void MacroAssembler::vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len) {
3667 int eq_cond_enc = 0x29;
3668 int gt_cond_enc = 0x37;
3669 if (width != Assembler::Q) {
3670 eq_cond_enc = 0x74 + width;
3671 gt_cond_enc = 0x64 + width;
3672 }
3673 switch (cond) {
3674 case eq:
3675 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3676 break;
3677 case neq:
3678 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3679 vallones(xtmp, vector_len);
3680 vpxor(dst, xtmp, dst, vector_len);
3681 break;
3682 case le:
3683 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3684 vallones(xtmp, vector_len);
3685 vpxor(dst, xtmp, dst, vector_len);
3686 break;
3687 case nlt:
3688 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3689 vallones(xtmp, vector_len);
3690 vpxor(dst, xtmp, dst, vector_len);
3691 break;
3692 case lt:
3693 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3694 break;
3695 case nle:
3696 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3697 break;
3698 default:
3699 assert(false, "Should not reach here");
3700 }
3701 }
3702
3703 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3704 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3705 Assembler::vpmovzxbw(dst, src, vector_len);
3706 }
3707
3708 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src, int vector_len) {
3709 assert((src->encoding() < 16),"XMM register should be 0-15");
3710 Assembler::vpmovmskb(dst, src, vector_len);
3711 }
3712
3713 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3714 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3715 Assembler::vpmullw(dst, nds, src, vector_len);
3716 }
3717
3718 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3719 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3720 Assembler::vpmullw(dst, nds, src, vector_len);
3721 }
3722
3723 void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3724 assert((UseAVX > 0), "AVX support is needed");
3725 assert(rscratch != noreg || always_reachable(src), "missing");
3726
3727 if (reachable(src)) {
3728 Assembler::vpmulld(dst, nds, as_Address(src), vector_len);
3729 } else {
3730 lea(rscratch, src);
3731 Assembler::vpmulld(dst, nds, Address(rscratch, 0), vector_len);
3732 }
3733 }
3734
3735 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3736 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3737 Assembler::vpsubb(dst, nds, src, vector_len);
3738 }
3739
3740 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3741 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3742 Assembler::vpsubb(dst, nds, src, vector_len);
3743 }
3744
3745 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3746 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3747 Assembler::vpsubw(dst, nds, src, vector_len);
3748 }
3749
3750 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3751 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3752 Assembler::vpsubw(dst, nds, src, vector_len);
3753 }
3754
3755 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3756 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3757 Assembler::vpsraw(dst, nds, shift, vector_len);
3758 }
3759
3760 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3761 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3762 Assembler::vpsraw(dst, nds, shift, vector_len);
3763 }
3764
3765 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3766 assert(UseAVX > 2,"");
3767 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3768 vector_len = 2;
3769 }
3770 Assembler::evpsraq(dst, nds, shift, vector_len);
3771 }
3772
3773 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3774 assert(UseAVX > 2,"");
3775 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3776 vector_len = 2;
3777 }
3778 Assembler::evpsraq(dst, nds, shift, vector_len);
3779 }
3780
3781 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3782 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3783 Assembler::vpsrlw(dst, nds, shift, vector_len);
3784 }
3785
3786 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3787 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3788 Assembler::vpsrlw(dst, nds, shift, vector_len);
3789 }
3790
3791 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3792 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3793 Assembler::vpsllw(dst, nds, shift, vector_len);
3794 }
3795
3796 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3797 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3798 Assembler::vpsllw(dst, nds, shift, vector_len);
3799 }
3800
3801 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3802 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3803 Assembler::vptest(dst, src);
3804 }
3805
3806 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3807 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3808 Assembler::punpcklbw(dst, src);
3809 }
3810
3811 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3812 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3813 Assembler::pshufd(dst, src, mode);
3814 }
3815
3816 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3817 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3818 Assembler::pshuflw(dst, src, mode);
3819 }
3820
3821 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3822 assert(rscratch != noreg || always_reachable(src), "missing");
3823
3824 if (reachable(src)) {
3825 vandpd(dst, nds, as_Address(src), vector_len);
3826 } else {
3827 lea(rscratch, src);
3828 vandpd(dst, nds, Address(rscratch, 0), vector_len);
3829 }
3830 }
3831
3832 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3833 assert(rscratch != noreg || always_reachable(src), "missing");
3834
3835 if (reachable(src)) {
3836 vandps(dst, nds, as_Address(src), vector_len);
3837 } else {
3838 lea(rscratch, src);
3839 vandps(dst, nds, Address(rscratch, 0), vector_len);
3840 }
3841 }
3842
3843 void MacroAssembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src,
3844 bool merge, int vector_len, Register rscratch) {
3845 assert(rscratch != noreg || always_reachable(src), "missing");
3846
3847 if (reachable(src)) {
3848 Assembler::evpord(dst, mask, nds, as_Address(src), merge, vector_len);
3849 } else {
3850 lea(rscratch, src);
3851 Assembler::evpord(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
3852 }
3853 }
3854
3855 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3856 assert(rscratch != noreg || always_reachable(src), "missing");
3857
3858 if (reachable(src)) {
3859 vdivsd(dst, nds, as_Address(src));
3860 } else {
3861 lea(rscratch, src);
3862 vdivsd(dst, nds, Address(rscratch, 0));
3863 }
3864 }
3865
3866 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3867 assert(rscratch != noreg || always_reachable(src), "missing");
3868
3869 if (reachable(src)) {
3870 vdivss(dst, nds, as_Address(src));
3871 } else {
3872 lea(rscratch, src);
3873 vdivss(dst, nds, Address(rscratch, 0));
3874 }
3875 }
3876
3877 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3878 assert(rscratch != noreg || always_reachable(src), "missing");
3879
3880 if (reachable(src)) {
3881 vmulsd(dst, nds, as_Address(src));
3882 } else {
3883 lea(rscratch, src);
3884 vmulsd(dst, nds, Address(rscratch, 0));
3885 }
3886 }
3887
3888 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3889 assert(rscratch != noreg || always_reachable(src), "missing");
3890
3891 if (reachable(src)) {
3892 vmulss(dst, nds, as_Address(src));
3893 } else {
3894 lea(rscratch, src);
3895 vmulss(dst, nds, Address(rscratch, 0));
3896 }
3897 }
3898
3899 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3900 assert(rscratch != noreg || always_reachable(src), "missing");
3901
3902 if (reachable(src)) {
3903 vsubsd(dst, nds, as_Address(src));
3904 } else {
3905 lea(rscratch, src);
3906 vsubsd(dst, nds, Address(rscratch, 0));
3907 }
3908 }
3909
3910 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3911 assert(rscratch != noreg || always_reachable(src), "missing");
3912
3913 if (reachable(src)) {
3914 vsubss(dst, nds, as_Address(src));
3915 } else {
3916 lea(rscratch, src);
3917 vsubss(dst, nds, Address(rscratch, 0));
3918 }
3919 }
3920
3921 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3922 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3923 assert(rscratch != noreg || always_reachable(src), "missing");
3924
3925 vxorps(dst, nds, src, Assembler::AVX_128bit, rscratch);
3926 }
3927
3928 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3929 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3930 assert(rscratch != noreg || always_reachable(src), "missing");
3931
3932 vxorpd(dst, nds, src, Assembler::AVX_128bit, rscratch);
3933 }
3934
3935 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3936 assert(rscratch != noreg || always_reachable(src), "missing");
3937
3938 if (reachable(src)) {
3939 vxorpd(dst, nds, as_Address(src), vector_len);
3940 } else {
3941 lea(rscratch, src);
3942 vxorpd(dst, nds, Address(rscratch, 0), vector_len);
3943 }
3944 }
3945
3946 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3947 assert(rscratch != noreg || always_reachable(src), "missing");
3948
3949 if (reachable(src)) {
3950 vxorps(dst, nds, as_Address(src), vector_len);
3951 } else {
3952 lea(rscratch, src);
3953 vxorps(dst, nds, Address(rscratch, 0), vector_len);
3954 }
3955 }
3956
3957 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3958 assert(rscratch != noreg || always_reachable(src), "missing");
3959
3960 if (UseAVX > 1 || (vector_len < 1)) {
3961 if (reachable(src)) {
3962 Assembler::vpxor(dst, nds, as_Address(src), vector_len);
3963 } else {
3964 lea(rscratch, src);
3965 Assembler::vpxor(dst, nds, Address(rscratch, 0), vector_len);
3966 }
3967 } else {
3968 MacroAssembler::vxorpd(dst, nds, src, vector_len, rscratch);
3969 }
3970 }
3971
3972 void MacroAssembler::vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3973 assert(rscratch != noreg || always_reachable(src), "missing");
3974
3975 if (reachable(src)) {
3976 Assembler::vpermd(dst, nds, as_Address(src), vector_len);
3977 } else {
3978 lea(rscratch, src);
3979 Assembler::vpermd(dst, nds, Address(rscratch, 0), vector_len);
3980 }
3981 }
3982
3983 void MacroAssembler::clear_jobject_tag(Register possibly_non_local) {
3984 const int32_t inverted_mask = ~static_cast<int32_t>(JNIHandles::tag_mask);
3985 STATIC_ASSERT(inverted_mask == -4); // otherwise check this code
3986 // The inverted mask is sign-extended
3987 andptr(possibly_non_local, inverted_mask);
3988 }
3989
3990 void MacroAssembler::resolve_jobject(Register value,
3991 Register thread,
3992 Register tmp) {
3993 assert_different_registers(value, thread, tmp);
3994 Label done, tagged, weak_tagged;
3995 testptr(value, value);
3996 jcc(Assembler::zero, done); // Use null as-is.
3997 testptr(value, JNIHandles::tag_mask); // Test for tag.
3998 jcc(Assembler::notZero, tagged);
3999
4000 // Resolve local handle
4001 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp, thread);
4002 verify_oop(value);
4003 jmp(done);
4004
4005 bind(tagged);
4006 testptr(value, JNIHandles::TypeTag::weak_global); // Test for weak tag.
4007 jcc(Assembler::notZero, weak_tagged);
4008
4009 // Resolve global handle
4010 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp, thread);
4011 verify_oop(value);
4012 jmp(done);
4013
4014 bind(weak_tagged);
4015 // Resolve jweak.
4016 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
4017 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp, thread);
4018 verify_oop(value);
4019
4020 bind(done);
4021 }
4022
4023 void MacroAssembler::resolve_global_jobject(Register value,
4024 Register thread,
4025 Register tmp) {
4026 assert_different_registers(value, thread, tmp);
4027 Label done;
4028
4029 testptr(value, value);
4030 jcc(Assembler::zero, done); // Use null as-is.
4031
4032 #ifdef ASSERT
4033 {
4034 Label valid_global_tag;
4035 testptr(value, JNIHandles::TypeTag::global); // Test for global tag.
4036 jcc(Assembler::notZero, valid_global_tag);
4037 stop("non global jobject using resolve_global_jobject");
4038 bind(valid_global_tag);
4039 }
4040 #endif
4041
4042 // Resolve global handle
4043 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp, thread);
4044 verify_oop(value);
4045
4046 bind(done);
4047 }
4048
4049 void MacroAssembler::subptr(Register dst, int32_t imm32) {
4050 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
4051 }
4052
4053 // Force generation of a 4 byte immediate value even if it fits into 8bit
4054 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
4055 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
4056 }
4057
4058 void MacroAssembler::subptr(Register dst, Register src) {
4059 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
4060 }
4061
4062 // C++ bool manipulation
4063 void MacroAssembler::testbool(Register dst) {
4064 if(sizeof(bool) == 1)
4065 testb(dst, 0xff);
4066 else if(sizeof(bool) == 2) {
4067 // testw implementation needed for two byte bools
4068 ShouldNotReachHere();
4069 } else if(sizeof(bool) == 4)
4070 testl(dst, dst);
4071 else
4072 // unsupported
4073 ShouldNotReachHere();
4074 }
4075
4076 void MacroAssembler::testptr(Register dst, Register src) {
4077 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4078 }
4079
4080 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4081 void MacroAssembler::tlab_allocate(Register thread, Register obj,
4082 Register var_size_in_bytes,
4083 int con_size_in_bytes,
4084 Register t1,
4085 Register t2,
4086 Label& slow_case) {
4087 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4088 bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
4089 }
4090
4091 RegSet MacroAssembler::call_clobbered_gp_registers() {
4092 RegSet regs;
4093 #ifdef _LP64
4094 regs += RegSet::of(rax, rcx, rdx);
4095 #ifndef WINDOWS
4096 regs += RegSet::of(rsi, rdi);
4097 #endif
4098 regs += RegSet::range(r8, r11);
4099 #else
4100 regs += RegSet::of(rax, rcx, rdx);
4101 #endif
4102 #ifdef _LP64
4103 if (UseAPX) {
4104 regs += RegSet::range(r16, as_Register(Register::number_of_registers - 1));
4105 }
4106 #endif
4107 return regs;
4108 }
4109
4110 XMMRegSet MacroAssembler::call_clobbered_xmm_registers() {
4111 int num_xmm_registers = XMMRegister::available_xmm_registers();
4112 #if defined(WINDOWS) && defined(_LP64)
4113 XMMRegSet result = XMMRegSet::range(xmm0, xmm5);
4114 if (num_xmm_registers > 16) {
4115 result += XMMRegSet::range(xmm16, as_XMMRegister(num_xmm_registers - 1));
4116 }
4117 return result;
4118 #else
4119 return XMMRegSet::range(xmm0, as_XMMRegister(num_xmm_registers - 1));
4120 #endif
4121 }
4122
4123 static int FPUSaveAreaSize = align_up(108, StackAlignmentInBytes); // 108 bytes needed for FPU state by fsave/frstor
4124
4125 #ifndef _LP64
4126 static bool use_x87_registers() { return UseSSE < 2; }
4127 #endif
4128 static bool use_xmm_registers() { return UseSSE >= 1; }
4129
4130 // C1 only ever uses the first double/float of the XMM register.
4131 static int xmm_save_size() { return UseSSE >= 2 ? sizeof(double) : sizeof(float); }
4132
4133 static void save_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
4134 if (UseSSE == 1) {
4135 masm->movflt(Address(rsp, offset), reg);
4136 } else {
4137 masm->movdbl(Address(rsp, offset), reg);
4138 }
4139 }
4140
4141 static void restore_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
4142 if (UseSSE == 1) {
4143 masm->movflt(reg, Address(rsp, offset));
4144 } else {
4145 masm->movdbl(reg, Address(rsp, offset));
4146 }
4147 }
4148
4149 static int register_section_sizes(RegSet gp_registers, XMMRegSet xmm_registers,
4150 bool save_fpu, int& gp_area_size,
4151 int& fp_area_size, int& xmm_area_size) {
4152
4153 gp_area_size = align_up(gp_registers.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size,
4154 StackAlignmentInBytes);
4155 #ifdef _LP64
4156 fp_area_size = 0;
4157 #else
4158 fp_area_size = (save_fpu && use_x87_registers()) ? FPUSaveAreaSize : 0;
4159 #endif
4160 xmm_area_size = (save_fpu && use_xmm_registers()) ? xmm_registers.size() * xmm_save_size() : 0;
4161
4162 return gp_area_size + fp_area_size + xmm_area_size;
4163 }
4164
4165 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude, bool save_fpu) {
4166 block_comment("push_call_clobbered_registers start");
4167 // Regular registers
4168 RegSet gp_registers_to_push = call_clobbered_gp_registers() - exclude;
4169
4170 int gp_area_size;
4171 int fp_area_size;
4172 int xmm_area_size;
4173 int total_save_size = register_section_sizes(gp_registers_to_push, call_clobbered_xmm_registers(), save_fpu,
4174 gp_area_size, fp_area_size, xmm_area_size);
4175 subptr(rsp, total_save_size);
4176
4177 push_set(gp_registers_to_push, 0);
4178
4179 #ifndef _LP64
4180 if (save_fpu && use_x87_registers()) {
4181 fnsave(Address(rsp, gp_area_size));
4182 fwait();
4183 }
4184 #endif
4185 if (save_fpu && use_xmm_registers()) {
4186 push_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size);
4187 }
4188
4189 block_comment("push_call_clobbered_registers end");
4190 }
4191
4192 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu) {
4193 block_comment("pop_call_clobbered_registers start");
4194
4195 RegSet gp_registers_to_pop = call_clobbered_gp_registers() - exclude;
4196
4197 int gp_area_size;
4198 int fp_area_size;
4199 int xmm_area_size;
4200 int total_save_size = register_section_sizes(gp_registers_to_pop, call_clobbered_xmm_registers(), restore_fpu,
4201 gp_area_size, fp_area_size, xmm_area_size);
4202
4203 if (restore_fpu && use_xmm_registers()) {
4204 pop_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size);
4205 }
4206 #ifndef _LP64
4207 if (restore_fpu && use_x87_registers()) {
4208 frstor(Address(rsp, gp_area_size));
4209 }
4210 #endif
4211
4212 pop_set(gp_registers_to_pop, 0);
4213
4214 addptr(rsp, total_save_size);
4215
4216 vzeroupper();
4217
4218 block_comment("pop_call_clobbered_registers end");
4219 }
4220
4221 void MacroAssembler::push_set(XMMRegSet set, int offset) {
4222 assert(is_aligned(set.size() * xmm_save_size(), StackAlignmentInBytes), "must be");
4223 int spill_offset = offset;
4224
4225 for (RegSetIterator<XMMRegister> it = set.begin(); *it != xnoreg; ++it) {
4226 save_xmm_register(this, spill_offset, *it);
4227 spill_offset += xmm_save_size();
4228 }
4229 }
4230
4231 void MacroAssembler::pop_set(XMMRegSet set, int offset) {
4232 int restore_size = set.size() * xmm_save_size();
4233 assert(is_aligned(restore_size, StackAlignmentInBytes), "must be");
4234
4235 int restore_offset = offset + restore_size - xmm_save_size();
4236
4237 for (ReverseRegSetIterator<XMMRegister> it = set.rbegin(); *it != xnoreg; ++it) {
4238 restore_xmm_register(this, restore_offset, *it);
4239 restore_offset -= xmm_save_size();
4240 }
4241 }
4242
4243 void MacroAssembler::push_set(RegSet set, int offset) {
4244 int spill_offset;
4245 if (offset == -1) {
4246 int register_push_size = set.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4247 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
4248 subptr(rsp, aligned_size);
4249 spill_offset = 0;
4250 } else {
4251 spill_offset = offset;
4252 }
4253
4254 for (RegSetIterator<Register> it = set.begin(); *it != noreg; ++it) {
4255 movptr(Address(rsp, spill_offset), *it);
4256 spill_offset += Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4257 }
4258 }
4259
4260 void MacroAssembler::pop_set(RegSet set, int offset) {
4261
4262 int gp_reg_size = Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4263 int restore_size = set.size() * gp_reg_size;
4264 int aligned_size = align_up(restore_size, StackAlignmentInBytes);
4265
4266 int restore_offset;
4267 if (offset == -1) {
4268 restore_offset = restore_size - gp_reg_size;
4269 } else {
4270 restore_offset = offset + restore_size - gp_reg_size;
4271 }
4272 for (ReverseRegSetIterator<Register> it = set.rbegin(); *it != noreg; ++it) {
4273 movptr(*it, Address(rsp, restore_offset));
4274 restore_offset -= gp_reg_size;
4275 }
4276
4277 if (offset == -1) {
4278 addptr(rsp, aligned_size);
4279 }
4280 }
4281
4282 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
4283 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
4284 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
4285 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
4286 Label done;
4287
4288 testptr(length_in_bytes, length_in_bytes);
4289 jcc(Assembler::zero, done);
4290
4291 // initialize topmost word, divide index by 2, check if odd and test if zero
4292 // note: for the remaining code to work, index must be a multiple of BytesPerWord
4293 #ifdef ASSERT
4294 {
4295 Label L;
4296 testptr(length_in_bytes, BytesPerWord - 1);
4297 jcc(Assembler::zero, L);
4298 stop("length must be a multiple of BytesPerWord");
4299 bind(L);
4300 }
4301 #endif
4302 Register index = length_in_bytes;
4303 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
4304 if (UseIncDec) {
4305 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
4306 } else {
4307 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
4308 shrptr(index, 1);
4309 }
4310 #ifndef _LP64
4311 // index could have not been a multiple of 8 (i.e., bit 2 was set)
4312 {
4313 Label even;
4314 // note: if index was a multiple of 8, then it cannot
4315 // be 0 now otherwise it must have been 0 before
4316 // => if it is even, we don't need to check for 0 again
4317 jcc(Assembler::carryClear, even);
4318 // clear topmost word (no jump would be needed if conditional assignment worked here)
4319 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
4320 // index could be 0 now, must check again
4321 jcc(Assembler::zero, done);
4322 bind(even);
4323 }
4324 #endif // !_LP64
4325 // initialize remaining object fields: index is a multiple of 2 now
4326 {
4327 Label loop;
4328 bind(loop);
4329 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
4330 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
4331 decrement(index);
4332 jcc(Assembler::notZero, loop);
4333 }
4334
4335 bind(done);
4336 }
4337
4338 // Look up the method for a megamorphic invokeinterface call.
4339 // The target method is determined by <intf_klass, itable_index>.
4340 // The receiver klass is in recv_klass.
4341 // On success, the result will be in method_result, and execution falls through.
4342 // On failure, execution transfers to the given label.
4343 void MacroAssembler::lookup_interface_method(Register recv_klass,
4344 Register intf_klass,
4345 RegisterOrConstant itable_index,
4346 Register method_result,
4347 Register scan_temp,
4348 Label& L_no_such_interface,
4349 bool return_method) {
4350 assert_different_registers(recv_klass, intf_klass, scan_temp);
4351 assert_different_registers(method_result, intf_klass, scan_temp);
4352 assert(recv_klass != method_result || !return_method,
4353 "recv_klass can be destroyed when method isn't needed");
4354
4355 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4356 "caller must use same register for non-constant itable index as for method");
4357
4358 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
4359 int vtable_base = in_bytes(Klass::vtable_start_offset());
4360 int itentry_off = in_bytes(itableMethodEntry::method_offset());
4361 int scan_step = itableOffsetEntry::size() * wordSize;
4362 int vte_size = vtableEntry::size_in_bytes();
4363 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4364 assert(vte_size == wordSize, "else adjust times_vte_scale");
4365
4366 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4367
4368 // Could store the aligned, prescaled offset in the klass.
4369 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
4370
4371 if (return_method) {
4372 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
4373 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4374 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
4375 }
4376
4377 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
4378 // if (scan->interface() == intf) {
4379 // result = (klass + scan->offset() + itable_index);
4380 // }
4381 // }
4382 Label search, found_method;
4383
4384 for (int peel = 1; peel >= 0; peel--) {
4385 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
4386 cmpptr(intf_klass, method_result);
4387
4388 if (peel) {
4389 jccb(Assembler::equal, found_method);
4390 } else {
4391 jccb(Assembler::notEqual, search);
4392 // (invert the test to fall through to found_method...)
4393 }
4394
4395 if (!peel) break;
4396
4397 bind(search);
4398
4399 // Check that the previous entry is non-null. A null entry means that
4400 // the receiver class doesn't implement the interface, and wasn't the
4401 // same as when the caller was compiled.
4402 testptr(method_result, method_result);
4403 jcc(Assembler::zero, L_no_such_interface);
4404 addptr(scan_temp, scan_step);
4405 }
4406
4407 bind(found_method);
4408
4409 if (return_method) {
4410 // Got a hit.
4411 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
4412 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
4413 }
4414 }
4415
4416 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
4417 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
4418 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
4419 // The target method is determined by <holder_klass, itable_index>.
4420 // The receiver klass is in recv_klass.
4421 // On success, the result will be in method_result, and execution falls through.
4422 // On failure, execution transfers to the given label.
4423 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
4424 Register holder_klass,
4425 Register resolved_klass,
4426 Register method_result,
4427 Register scan_temp,
4428 Register temp_reg2,
4429 Register receiver,
4430 int itable_index,
4431 Label& L_no_such_interface) {
4432 assert_different_registers(recv_klass, method_result, holder_klass, resolved_klass, scan_temp, temp_reg2, receiver);
4433 Register temp_itbl_klass = method_result;
4434 Register temp_reg = (temp_reg2 == noreg ? recv_klass : temp_reg2); // reuse recv_klass register on 32-bit x86 impl
4435
4436 int vtable_base = in_bytes(Klass::vtable_start_offset());
4437 int itentry_off = in_bytes(itableMethodEntry::method_offset());
4438 int scan_step = itableOffsetEntry::size() * wordSize;
4439 int vte_size = vtableEntry::size_in_bytes();
4440 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
4441 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
4442 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4443 assert(vte_size == wordSize, "adjust times_vte_scale");
4444
4445 Label L_loop_scan_resolved_entry, L_resolved_found, L_holder_found;
4446
4447 // temp_itbl_klass = recv_klass.itable[0]
4448 // scan_temp = &recv_klass.itable[0] + step
4449 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4450 movptr(temp_itbl_klass, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset));
4451 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset + scan_step));
4452 xorptr(temp_reg, temp_reg);
4453
4454 // Initial checks:
4455 // - if (holder_klass != resolved_klass), go to "scan for resolved"
4456 // - if (itable[0] == 0), no such interface
4457 // - if (itable[0] == holder_klass), shortcut to "holder found"
4458 cmpptr(holder_klass, resolved_klass);
4459 jccb(Assembler::notEqual, L_loop_scan_resolved_entry);
4460 testptr(temp_itbl_klass, temp_itbl_klass);
4461 jccb(Assembler::zero, L_no_such_interface);
4462 cmpptr(holder_klass, temp_itbl_klass);
4463 jccb(Assembler::equal, L_holder_found);
4464
4465 // Loop: Look for holder_klass record in itable
4466 // do {
4467 // tmp = itable[index];
4468 // index += step;
4469 // if (tmp == holder_klass) {
4470 // goto L_holder_found; // Found!
4471 // }
4472 // } while (tmp != 0);
4473 // goto L_no_such_interface // Not found.
4474 Label L_scan_holder;
4475 bind(L_scan_holder);
4476 movptr(temp_itbl_klass, Address(scan_temp, 0));
4477 addptr(scan_temp, scan_step);
4478 cmpptr(holder_klass, temp_itbl_klass);
4479 jccb(Assembler::equal, L_holder_found);
4480 testptr(temp_itbl_klass, temp_itbl_klass);
4481 jccb(Assembler::notZero, L_scan_holder);
4482
4483 jmpb(L_no_such_interface);
4484
4485 // Loop: Look for resolved_class record in itable
4486 // do {
4487 // tmp = itable[index];
4488 // index += step;
4489 // if (tmp == holder_klass) {
4490 // // Also check if we have met a holder klass
4491 // holder_tmp = itable[index-step-ioffset];
4492 // }
4493 // if (tmp == resolved_klass) {
4494 // goto L_resolved_found; // Found!
4495 // }
4496 // } while (tmp != 0);
4497 // goto L_no_such_interface // Not found.
4498 //
4499 Label L_loop_scan_resolved;
4500 bind(L_loop_scan_resolved);
4501 movptr(temp_itbl_klass, Address(scan_temp, 0));
4502 addptr(scan_temp, scan_step);
4503 bind(L_loop_scan_resolved_entry);
4504 cmpptr(holder_klass, temp_itbl_klass);
4505 cmovl(Assembler::equal, temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4506 cmpptr(resolved_klass, temp_itbl_klass);
4507 jccb(Assembler::equal, L_resolved_found);
4508 testptr(temp_itbl_klass, temp_itbl_klass);
4509 jccb(Assembler::notZero, L_loop_scan_resolved);
4510
4511 jmpb(L_no_such_interface);
4512
4513 Label L_ready;
4514
4515 // See if we already have a holder klass. If not, go and scan for it.
4516 bind(L_resolved_found);
4517 testptr(temp_reg, temp_reg);
4518 jccb(Assembler::zero, L_scan_holder);
4519 jmpb(L_ready);
4520
4521 bind(L_holder_found);
4522 movl(temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4523
4524 // Finally, temp_reg contains holder_klass vtable offset
4525 bind(L_ready);
4526 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4527 if (temp_reg2 == noreg) { // recv_klass register is clobbered for 32-bit x86 impl
4528 load_klass(scan_temp, receiver, noreg);
4529 movptr(method_result, Address(scan_temp, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4530 } else {
4531 movptr(method_result, Address(recv_klass, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4532 }
4533 }
4534
4535
4536 // virtual method calling
4537 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4538 RegisterOrConstant vtable_index,
4539 Register method_result) {
4540 const ByteSize base = Klass::vtable_start_offset();
4541 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4542 Address vtable_entry_addr(recv_klass,
4543 vtable_index, Address::times_ptr,
4544 base + vtableEntry::method_offset());
4545 movptr(method_result, vtable_entry_addr);
4546 }
4547
4548
4549 void MacroAssembler::check_klass_subtype(Register sub_klass,
4550 Register super_klass,
4551 Register temp_reg,
4552 Label& L_success) {
4553 Label L_failure;
4554 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
4555 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
4556 bind(L_failure);
4557 }
4558
4559
4560 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4561 Register super_klass,
4562 Register temp_reg,
4563 Label* L_success,
4564 Label* L_failure,
4565 Label* L_slow_path,
4566 RegisterOrConstant super_check_offset) {
4567 assert_different_registers(sub_klass, super_klass, temp_reg);
4568 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4569 if (super_check_offset.is_register()) {
4570 assert_different_registers(sub_klass, super_klass,
4571 super_check_offset.as_register());
4572 } else if (must_load_sco) {
4573 assert(temp_reg != noreg, "supply either a temp or a register offset");
4574 }
4575
4576 Label L_fallthrough;
4577 int label_nulls = 0;
4578 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4579 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4580 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
4581 assert(label_nulls <= 1, "at most one null in the batch");
4582
4583 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4584 int sco_offset = in_bytes(Klass::super_check_offset_offset());
4585 Address super_check_offset_addr(super_klass, sco_offset);
4586
4587 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4588 // range of a jccb. If this routine grows larger, reconsider at
4589 // least some of these.
4590 #define local_jcc(assembler_cond, label) \
4591 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
4592 else jcc( assembler_cond, label) /*omit semi*/
4593
4594 // Hacked jmp, which may only be used just before L_fallthrough.
4595 #define final_jmp(label) \
4596 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
4597 else jmp(label) /*omit semi*/
4598
4599 // If the pointers are equal, we are done (e.g., String[] elements).
4600 // This self-check enables sharing of secondary supertype arrays among
4601 // non-primary types such as array-of-interface. Otherwise, each such
4602 // type would need its own customized SSA.
4603 // We move this check to the front of the fast path because many
4604 // type checks are in fact trivially successful in this manner,
4605 // so we get a nicely predicted branch right at the start of the check.
4606 cmpptr(sub_klass, super_klass);
4607 local_jcc(Assembler::equal, *L_success);
4608
4609 // Check the supertype display:
4610 if (must_load_sco) {
4611 // Positive movl does right thing on LP64.
4612 movl(temp_reg, super_check_offset_addr);
4613 super_check_offset = RegisterOrConstant(temp_reg);
4614 }
4615 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4616 cmpptr(super_klass, super_check_addr); // load displayed supertype
4617
4618 // This check has worked decisively for primary supers.
4619 // Secondary supers are sought in the super_cache ('super_cache_addr').
4620 // (Secondary supers are interfaces and very deeply nested subtypes.)
4621 // This works in the same check above because of a tricky aliasing
4622 // between the super_cache and the primary super display elements.
4623 // (The 'super_check_addr' can address either, as the case requires.)
4624 // Note that the cache is updated below if it does not help us find
4625 // what we need immediately.
4626 // So if it was a primary super, we can just fail immediately.
4627 // Otherwise, it's the slow path for us (no success at this point).
4628
4629 if (super_check_offset.is_register()) {
4630 local_jcc(Assembler::equal, *L_success);
4631 cmpl(super_check_offset.as_register(), sc_offset);
4632 if (L_failure == &L_fallthrough) {
4633 local_jcc(Assembler::equal, *L_slow_path);
4634 } else {
4635 local_jcc(Assembler::notEqual, *L_failure);
4636 final_jmp(*L_slow_path);
4637 }
4638 } else if (super_check_offset.as_constant() == sc_offset) {
4639 // Need a slow path; fast failure is impossible.
4640 if (L_slow_path == &L_fallthrough) {
4641 local_jcc(Assembler::equal, *L_success);
4642 } else {
4643 local_jcc(Assembler::notEqual, *L_slow_path);
4644 final_jmp(*L_success);
4645 }
4646 } else {
4647 // No slow path; it's a fast decision.
4648 if (L_failure == &L_fallthrough) {
4649 local_jcc(Assembler::equal, *L_success);
4650 } else {
4651 local_jcc(Assembler::notEqual, *L_failure);
4652 final_jmp(*L_success);
4653 }
4654 }
4655
4656 bind(L_fallthrough);
4657
4658 #undef local_jcc
4659 #undef final_jmp
4660 }
4661
4662
4663 void MacroAssembler::check_klass_subtype_slow_path_linear(Register sub_klass,
4664 Register super_klass,
4665 Register temp_reg,
4666 Register temp2_reg,
4667 Label* L_success,
4668 Label* L_failure,
4669 bool set_cond_codes) {
4670 assert_different_registers(sub_klass, super_klass, temp_reg);
4671 if (temp2_reg != noreg)
4672 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4673 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4674
4675 Label L_fallthrough;
4676 int label_nulls = 0;
4677 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4678 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4679 assert(label_nulls <= 1, "at most one null in the batch");
4680
4681 // a couple of useful fields in sub_klass:
4682 int ss_offset = in_bytes(Klass::secondary_supers_offset());
4683 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4684 Address secondary_supers_addr(sub_klass, ss_offset);
4685 Address super_cache_addr( sub_klass, sc_offset);
4686
4687 // Do a linear scan of the secondary super-klass chain.
4688 // This code is rarely used, so simplicity is a virtue here.
4689 // The repne_scan instruction uses fixed registers, which we must spill.
4690 // Don't worry too much about pre-existing connections with the input regs.
4691
4692 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4693 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4694
4695 // Get super_klass value into rax (even if it was in rdi or rcx).
4696 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4697 if (super_klass != rax) {
4698 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4699 mov(rax, super_klass);
4700 }
4701 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4702 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4703
4704 #ifndef PRODUCT
4705 uint* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4706 ExternalAddress pst_counter_addr((address) pst_counter);
4707 NOT_LP64( incrementl(pst_counter_addr) );
4708 LP64_ONLY( lea(rcx, pst_counter_addr) );
4709 LP64_ONLY( incrementl(Address(rcx, 0)) );
4710 #endif //PRODUCT
4711
4712 // We will consult the secondary-super array.
4713 movptr(rdi, secondary_supers_addr);
4714 // Load the array length. (Positive movl does right thing on LP64.)
4715 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4716 // Skip to start of data.
4717 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4718
4719 // Scan RCX words at [RDI] for an occurrence of RAX.
4720 // Set NZ/Z based on last compare.
4721 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4722 // not change flags (only scas instruction which is repeated sets flags).
4723 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4724
4725 testptr(rax,rax); // Set Z = 0
4726 repne_scan();
4727
4728 // Unspill the temp. registers:
4729 if (pushed_rdi) pop(rdi);
4730 if (pushed_rcx) pop(rcx);
4731 if (pushed_rax) pop(rax);
4732
4733 if (set_cond_codes) {
4734 // Special hack for the AD files: rdi is guaranteed non-zero.
4735 assert(!pushed_rdi, "rdi must be left non-null");
4736 // Also, the condition codes are properly set Z/NZ on succeed/failure.
4737 }
4738
4739 if (L_failure == &L_fallthrough)
4740 jccb(Assembler::notEqual, *L_failure);
4741 else jcc(Assembler::notEqual, *L_failure);
4742
4743 // Success. Cache the super we found and proceed in triumph.
4744 movptr(super_cache_addr, super_klass);
4745
4746 if (L_success != &L_fallthrough) {
4747 jmp(*L_success);
4748 }
4749
4750 #undef IS_A_TEMP
4751
4752 bind(L_fallthrough);
4753 }
4754
4755 #ifndef _LP64
4756
4757 // 32-bit x86 only: always use the linear search.
4758 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4759 Register super_klass,
4760 Register temp_reg,
4761 Register temp2_reg,
4762 Label* L_success,
4763 Label* L_failure,
4764 bool set_cond_codes) {
4765 check_klass_subtype_slow_path_linear
4766 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, set_cond_codes);
4767 }
4768
4769 #else // _LP64
4770
4771 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4772 Register super_klass,
4773 Register temp_reg,
4774 Register temp2_reg,
4775 Label* L_success,
4776 Label* L_failure,
4777 bool set_cond_codes) {
4778 assert(set_cond_codes == false, "must be false on 64-bit x86");
4779 check_klass_subtype_slow_path
4780 (sub_klass, super_klass, temp_reg, temp2_reg, noreg, noreg,
4781 L_success, L_failure);
4782 }
4783
4784 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4785 Register super_klass,
4786 Register temp_reg,
4787 Register temp2_reg,
4788 Register temp3_reg,
4789 Register temp4_reg,
4790 Label* L_success,
4791 Label* L_failure) {
4792 if (UseSecondarySupersTable) {
4793 check_klass_subtype_slow_path_table
4794 (sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, temp4_reg,
4795 L_success, L_failure);
4796 } else {
4797 check_klass_subtype_slow_path_linear
4798 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, /*set_cond_codes*/false);
4799 }
4800 }
4801
4802 Register MacroAssembler::allocate_if_noreg(Register r,
4803 RegSetIterator<Register> &available_regs,
4804 RegSet ®s_to_push) {
4805 if (!r->is_valid()) {
4806 r = *available_regs++;
4807 regs_to_push += r;
4808 }
4809 return r;
4810 }
4811
4812 void MacroAssembler::check_klass_subtype_slow_path_table(Register sub_klass,
4813 Register super_klass,
4814 Register temp_reg,
4815 Register temp2_reg,
4816 Register temp3_reg,
4817 Register result_reg,
4818 Label* L_success,
4819 Label* L_failure) {
4820 // NB! Callers may assume that, when temp2_reg is a valid register,
4821 // this code sets it to a nonzero value.
4822 bool temp2_reg_was_valid = temp2_reg->is_valid();
4823
4824 RegSet temps = RegSet::of(temp_reg, temp2_reg, temp3_reg);
4825
4826 Label L_fallthrough;
4827 int label_nulls = 0;
4828 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4829 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4830 assert(label_nulls <= 1, "at most one null in the batch");
4831
4832 BLOCK_COMMENT("check_klass_subtype_slow_path_table");
4833
4834 RegSetIterator<Register> available_regs
4835 = (RegSet::of(rax, rcx, rdx, r8) + r9 + r10 + r11 + r12 - temps - sub_klass - super_klass).begin();
4836
4837 RegSet pushed_regs;
4838
4839 temp_reg = allocate_if_noreg(temp_reg, available_regs, pushed_regs);
4840 temp2_reg = allocate_if_noreg(temp2_reg, available_regs, pushed_regs);
4841 temp3_reg = allocate_if_noreg(temp3_reg, available_regs, pushed_regs);
4842 result_reg = allocate_if_noreg(result_reg, available_regs, pushed_regs);
4843 Register temp4_reg = allocate_if_noreg(noreg, available_regs, pushed_regs);
4844
4845 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, result_reg);
4846
4847 {
4848
4849 int register_push_size = pushed_regs.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4850 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
4851 subptr(rsp, aligned_size);
4852 push_set(pushed_regs, 0);
4853
4854 lookup_secondary_supers_table_var(sub_klass,
4855 super_klass,
4856 temp_reg, temp2_reg, temp3_reg, temp4_reg, result_reg);
4857 cmpq(result_reg, 0);
4858
4859 // Unspill the temp. registers:
4860 pop_set(pushed_regs, 0);
4861 // Increment SP but do not clobber flags.
4862 lea(rsp, Address(rsp, aligned_size));
4863 }
4864
4865 if (temp2_reg_was_valid) {
4866 movq(temp2_reg, 1);
4867 }
4868
4869 jcc(Assembler::notEqual, *L_failure);
4870
4871 if (L_success != &L_fallthrough) {
4872 jmp(*L_success);
4873 }
4874
4875 bind(L_fallthrough);
4876 }
4877
4878 // population_count variant for running without the POPCNT
4879 // instruction, which was introduced with SSE4.2 in 2008.
4880 void MacroAssembler::population_count(Register dst, Register src,
4881 Register scratch1, Register scratch2) {
4882 assert_different_registers(src, scratch1, scratch2);
4883 if (UsePopCountInstruction) {
4884 Assembler::popcntq(dst, src);
4885 } else {
4886 assert_different_registers(src, scratch1, scratch2);
4887 assert_different_registers(dst, scratch1, scratch2);
4888 Label loop, done;
4889
4890 mov(scratch1, src);
4891 // dst = 0;
4892 // while(scratch1 != 0) {
4893 // dst++;
4894 // scratch1 &= (scratch1 - 1);
4895 // }
4896 xorl(dst, dst);
4897 testq(scratch1, scratch1);
4898 jccb(Assembler::equal, done);
4899 {
4900 bind(loop);
4901 incq(dst);
4902 movq(scratch2, scratch1);
4903 decq(scratch2);
4904 andq(scratch1, scratch2);
4905 jccb(Assembler::notEqual, loop);
4906 }
4907 bind(done);
4908 }
4909 }
4910
4911 // Ensure that the inline code and the stub are using the same registers.
4912 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
4913 do { \
4914 assert(r_super_klass == rax, "mismatch"); \
4915 assert(r_array_base == rbx, "mismatch"); \
4916 assert(r_array_length == rcx, "mismatch"); \
4917 assert(r_array_index == rdx, "mismatch"); \
4918 assert(r_sub_klass == rsi || r_sub_klass == noreg, "mismatch"); \
4919 assert(r_bitmap == r11 || r_bitmap == noreg, "mismatch"); \
4920 assert(result == rdi || result == noreg, "mismatch"); \
4921 } while(0)
4922
4923 // Versions of salq and rorq that don't need count to be in rcx
4924
4925 void MacroAssembler::salq(Register dest, Register count) {
4926 if (count == rcx) {
4927 Assembler::salq(dest);
4928 } else {
4929 assert_different_registers(rcx, dest);
4930 xchgq(rcx, count);
4931 Assembler::salq(dest);
4932 xchgq(rcx, count);
4933 }
4934 }
4935
4936 void MacroAssembler::rorq(Register dest, Register count) {
4937 if (count == rcx) {
4938 Assembler::rorq(dest);
4939 } else {
4940 assert_different_registers(rcx, dest);
4941 xchgq(rcx, count);
4942 Assembler::rorq(dest);
4943 xchgq(rcx, count);
4944 }
4945 }
4946
4947 // Return true: we succeeded in generating this code
4948 //
4949 // At runtime, return 0 in result if r_super_klass is a superclass of
4950 // r_sub_klass, otherwise return nonzero. Use this if you know the
4951 // super_klass_slot of the class you're looking for. This is always
4952 // the case for instanceof and checkcast.
4953 void MacroAssembler::lookup_secondary_supers_table_const(Register r_sub_klass,
4954 Register r_super_klass,
4955 Register temp1,
4956 Register temp2,
4957 Register temp3,
4958 Register temp4,
4959 Register result,
4960 u1 super_klass_slot) {
4961 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
4962
4963 Label L_fallthrough, L_success, L_failure;
4964
4965 BLOCK_COMMENT("lookup_secondary_supers_table {");
4966
4967 const Register
4968 r_array_index = temp1,
4969 r_array_length = temp2,
4970 r_array_base = temp3,
4971 r_bitmap = temp4;
4972
4973 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
4974
4975 xorq(result, result); // = 0
4976
4977 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
4978 movq(r_array_index, r_bitmap);
4979
4980 // First check the bitmap to see if super_klass might be present. If
4981 // the bit is zero, we are certain that super_klass is not one of
4982 // the secondary supers.
4983 u1 bit = super_klass_slot;
4984 {
4985 // NB: If the count in a x86 shift instruction is 0, the flags are
4986 // not affected, so we do a testq instead.
4987 int shift_count = Klass::SECONDARY_SUPERS_TABLE_MASK - bit;
4988 if (shift_count != 0) {
4989 salq(r_array_index, shift_count);
4990 } else {
4991 testq(r_array_index, r_array_index);
4992 }
4993 }
4994 // We test the MSB of r_array_index, i.e. its sign bit
4995 jcc(Assembler::positive, L_failure);
4996
4997 // Get the first array index that can contain super_klass into r_array_index.
4998 if (bit != 0) {
4999 population_count(r_array_index, r_array_index, temp2, temp3);
5000 } else {
5001 movl(r_array_index, 1);
5002 }
5003 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
5004
5005 // We will consult the secondary-super array.
5006 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
5007
5008 // We're asserting that the first word in an Array<Klass*> is the
5009 // length, and the second word is the first word of the data. If
5010 // that ever changes, r_array_base will have to be adjusted here.
5011 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
5012 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
5013
5014 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
5015 jccb(Assembler::equal, L_success);
5016
5017 // Is there another entry to check? Consult the bitmap.
5018 btq(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK);
5019 jccb(Assembler::carryClear, L_failure);
5020
5021 // Linear probe. Rotate the bitmap so that the next bit to test is
5022 // in Bit 1.
5023 if (bit != 0) {
5024 rorq(r_bitmap, bit);
5025 }
5026
5027 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
5028 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
5029 // Kills: r_array_length.
5030 // Returns: result.
5031 call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub()));
5032 // Result (0/1) is in rdi
5033 jmpb(L_fallthrough);
5034
5035 bind(L_failure);
5036 incq(result); // 0 => 1
5037
5038 bind(L_success);
5039 // result = 0;
5040
5041 bind(L_fallthrough);
5042 BLOCK_COMMENT("} lookup_secondary_supers_table");
5043
5044 if (VerifySecondarySupers) {
5045 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
5046 temp1, temp2, temp3);
5047 }
5048 }
5049
5050 // At runtime, return 0 in result if r_super_klass is a superclass of
5051 // r_sub_klass, otherwise return nonzero. Use this version of
5052 // lookup_secondary_supers_table() if you don't know ahead of time
5053 // which superclass will be searched for. Used by interpreter and
5054 // runtime stubs. It is larger and has somewhat greater latency than
5055 // the version above, which takes a constant super_klass_slot.
5056 void MacroAssembler::lookup_secondary_supers_table_var(Register r_sub_klass,
5057 Register r_super_klass,
5058 Register temp1,
5059 Register temp2,
5060 Register temp3,
5061 Register temp4,
5062 Register result) {
5063 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
5064 assert_different_registers(r_sub_klass, r_super_klass, rcx);
5065 RegSet temps = RegSet::of(temp1, temp2, temp3, temp4);
5066
5067 Label L_fallthrough, L_success, L_failure;
5068
5069 BLOCK_COMMENT("lookup_secondary_supers_table {");
5070
5071 RegSetIterator<Register> available_regs = (temps - rcx).begin();
5072
5073 // FIXME. Once we are sure that all paths reaching this point really
5074 // do pass rcx as one of our temps we can get rid of the following
5075 // workaround.
5076 assert(temps.contains(rcx), "fix this code");
5077
5078 // We prefer to have our shift count in rcx. If rcx is one of our
5079 // temps, use it for slot. If not, pick any of our temps.
5080 Register slot;
5081 if (!temps.contains(rcx)) {
5082 slot = *available_regs++;
5083 } else {
5084 slot = rcx;
5085 }
5086
5087 const Register r_array_index = *available_regs++;
5088 const Register r_bitmap = *available_regs++;
5089
5090 // The logic above guarantees this property, but we state it here.
5091 assert_different_registers(r_array_index, r_bitmap, rcx);
5092
5093 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
5094 movq(r_array_index, r_bitmap);
5095
5096 // First check the bitmap to see if super_klass might be present. If
5097 // the bit is zero, we are certain that super_klass is not one of
5098 // the secondary supers.
5099 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
5100 xorl(slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1)); // slot ^ 63 === 63 - slot (mod 64)
5101 salq(r_array_index, slot);
5102
5103 testq(r_array_index, r_array_index);
5104 // We test the MSB of r_array_index, i.e. its sign bit
5105 jcc(Assembler::positive, L_failure);
5106
5107 const Register r_array_base = *available_regs++;
5108
5109 // Get the first array index that can contain super_klass into r_array_index.
5110 population_count(r_array_index, r_array_index, /*temp2*/r_array_base, /*temp3*/slot);
5111
5112 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
5113
5114 // We will consult the secondary-super array.
5115 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
5116
5117 // We're asserting that the first word in an Array<Klass*> is the
5118 // length, and the second word is the first word of the data. If
5119 // that ever changes, r_array_base will have to be adjusted here.
5120 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
5121 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
5122
5123 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
5124 jccb(Assembler::equal, L_success);
5125
5126 // Restore slot to its true value
5127 xorl(slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1)); // slot ^ 63 === 63 - slot (mod 64)
5128
5129 // Linear probe. Rotate the bitmap so that the next bit to test is
5130 // in Bit 1.
5131 rorq(r_bitmap, slot);
5132
5133 // Is there another entry to check? Consult the bitmap.
5134 btq(r_bitmap, 1);
5135 jccb(Assembler::carryClear, L_failure);
5136
5137 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
5138 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
5139 // Kills: r_array_length.
5140 // Returns: result.
5141 lookup_secondary_supers_table_slow_path(r_super_klass,
5142 r_array_base,
5143 r_array_index,
5144 r_bitmap,
5145 /*temp1*/result,
5146 /*temp2*/slot,
5147 &L_success,
5148 nullptr);
5149
5150 bind(L_failure);
5151 movq(result, 1);
5152 jmpb(L_fallthrough);
5153
5154 bind(L_success);
5155 xorq(result, result); // = 0
5156
5157 bind(L_fallthrough);
5158 BLOCK_COMMENT("} lookup_secondary_supers_table");
5159
5160 if (VerifySecondarySupers) {
5161 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
5162 temp1, temp2, temp3);
5163 }
5164 }
5165
5166 void MacroAssembler::repne_scanq(Register addr, Register value, Register count, Register limit,
5167 Label* L_success, Label* L_failure) {
5168 Label L_loop, L_fallthrough;
5169 {
5170 int label_nulls = 0;
5171 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
5172 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
5173 assert(label_nulls <= 1, "at most one null in the batch");
5174 }
5175 bind(L_loop);
5176 cmpq(value, Address(addr, count, Address::times_8));
5177 jcc(Assembler::equal, *L_success);
5178 addl(count, 1);
5179 cmpl(count, limit);
5180 jcc(Assembler::less, L_loop);
5181
5182 if (&L_fallthrough != L_failure) {
5183 jmp(*L_failure);
5184 }
5185 bind(L_fallthrough);
5186 }
5187
5188 // Called by code generated by check_klass_subtype_slow_path
5189 // above. This is called when there is a collision in the hashed
5190 // lookup in the secondary supers array.
5191 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
5192 Register r_array_base,
5193 Register r_array_index,
5194 Register r_bitmap,
5195 Register temp1,
5196 Register temp2,
5197 Label* L_success,
5198 Label* L_failure) {
5199 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, temp2);
5200
5201 const Register
5202 r_array_length = temp1,
5203 r_sub_klass = noreg,
5204 result = noreg;
5205
5206 Label L_fallthrough;
5207 int label_nulls = 0;
5208 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
5209 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
5210 assert(label_nulls <= 1, "at most one null in the batch");
5211
5212 // Load the array length.
5213 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
5214 // And adjust the array base to point to the data.
5215 // NB! Effectively increments current slot index by 1.
5216 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
5217 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
5218
5219 // Linear probe
5220 Label L_huge;
5221
5222 // The bitmap is full to bursting.
5223 // Implicit invariant: BITMAP_FULL implies (length > 0)
5224 cmpl(r_array_length, (int32_t)Klass::SECONDARY_SUPERS_TABLE_SIZE - 2);
5225 jcc(Assembler::greater, L_huge);
5226
5227 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
5228 // current slot (at secondary_supers[r_array_index]) has not yet
5229 // been inspected, and r_array_index may be out of bounds if we
5230 // wrapped around the end of the array.
5231
5232 { // This is conventional linear probing, but instead of terminating
5233 // when a null entry is found in the table, we maintain a bitmap
5234 // in which a 0 indicates missing entries.
5235 // The check above guarantees there are 0s in the bitmap, so the loop
5236 // eventually terminates.
5237
5238 xorl(temp2, temp2); // = 0;
5239
5240 Label L_again;
5241 bind(L_again);
5242
5243 // Check for array wraparound.
5244 cmpl(r_array_index, r_array_length);
5245 cmovl(Assembler::greaterEqual, r_array_index, temp2);
5246
5247 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
5248 jcc(Assembler::equal, *L_success);
5249
5250 // If the next bit in bitmap is zero, we're done.
5251 btq(r_bitmap, 2); // look-ahead check (Bit 2); Bits 0 and 1 are tested by now
5252 jcc(Assembler::carryClear, *L_failure);
5253
5254 rorq(r_bitmap, 1); // Bits 1/2 => 0/1
5255 addl(r_array_index, 1);
5256
5257 jmp(L_again);
5258 }
5259
5260 { // Degenerate case: more than 64 secondary supers.
5261 // FIXME: We could do something smarter here, maybe a vectorized
5262 // comparison or a binary search, but is that worth any added
5263 // complexity?
5264 bind(L_huge);
5265 xorl(r_array_index, r_array_index); // = 0
5266 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length,
5267 L_success,
5268 (&L_fallthrough != L_failure ? L_failure : nullptr));
5269
5270 bind(L_fallthrough);
5271 }
5272 }
5273
5274 struct VerifyHelperArguments {
5275 Klass* _super;
5276 Klass* _sub;
5277 intptr_t _linear_result;
5278 intptr_t _table_result;
5279 };
5280
5281 static void verify_secondary_supers_table_helper(const char* msg, VerifyHelperArguments* args) {
5282 Klass::on_secondary_supers_verification_failure(args->_super,
5283 args->_sub,
5284 args->_linear_result,
5285 args->_table_result,
5286 msg);
5287 }
5288
5289 // Make sure that the hashed lookup and a linear scan agree.
5290 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
5291 Register r_super_klass,
5292 Register result,
5293 Register temp1,
5294 Register temp2,
5295 Register temp3) {
5296 const Register
5297 r_array_index = temp1,
5298 r_array_length = temp2,
5299 r_array_base = temp3,
5300 r_bitmap = noreg;
5301
5302 BLOCK_COMMENT("verify_secondary_supers_table {");
5303
5304 Label L_success, L_failure, L_check, L_done;
5305
5306 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
5307 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
5308 // And adjust the array base to point to the data.
5309 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
5310
5311 testl(r_array_length, r_array_length); // array_length == 0?
5312 jcc(Assembler::zero, L_failure);
5313
5314 movl(r_array_index, 0);
5315 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length, &L_success);
5316 // fall through to L_failure
5317
5318 const Register linear_result = r_array_index; // reuse temp1
5319
5320 bind(L_failure); // not present
5321 movl(linear_result, 1);
5322 jmp(L_check);
5323
5324 bind(L_success); // present
5325 movl(linear_result, 0);
5326
5327 bind(L_check);
5328 cmpl(linear_result, result);
5329 jcc(Assembler::equal, L_done);
5330
5331 { // To avoid calling convention issues, build a record on the stack
5332 // and pass the pointer to that instead.
5333 push(result);
5334 push(linear_result);
5335 push(r_sub_klass);
5336 push(r_super_klass);
5337 movptr(c_rarg1, rsp);
5338 movptr(c_rarg0, (uintptr_t) "mismatch");
5339 call(RuntimeAddress(CAST_FROM_FN_PTR(address, verify_secondary_supers_table_helper)));
5340 should_not_reach_here();
5341 }
5342 bind(L_done);
5343
5344 BLOCK_COMMENT("} verify_secondary_supers_table");
5345 }
5346
5347 #undef LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS
5348
5349 #endif // LP64
5350
5351 void MacroAssembler::clinit_barrier(Register klass, Register thread, Label* L_fast_path, Label* L_slow_path) {
5352 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
5353
5354 Label L_fallthrough;
5355 if (L_fast_path == nullptr) {
5356 L_fast_path = &L_fallthrough;
5357 } else if (L_slow_path == nullptr) {
5358 L_slow_path = &L_fallthrough;
5359 }
5360
5361 // Fast path check: class is fully initialized.
5362 // init_state needs acquire, but x86 is TSO, and so we are already good.
5363 cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
5364 jcc(Assembler::equal, *L_fast_path);
5365
5366 // Fast path check: current thread is initializer thread
5367 cmpptr(thread, Address(klass, InstanceKlass::init_thread_offset()));
5368 if (L_slow_path == &L_fallthrough) {
5369 jcc(Assembler::equal, *L_fast_path);
5370 bind(*L_slow_path);
5371 } else if (L_fast_path == &L_fallthrough) {
5372 jcc(Assembler::notEqual, *L_slow_path);
5373 bind(*L_fast_path);
5374 } else {
5375 Unimplemented();
5376 }
5377 }
5378
5379 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
5380 if (VM_Version::supports_cmov()) {
5381 cmovl(cc, dst, src);
5382 } else {
5383 Label L;
5384 jccb(negate_condition(cc), L);
5385 movl(dst, src);
5386 bind(L);
5387 }
5388 }
5389
5390 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
5391 if (VM_Version::supports_cmov()) {
5392 cmovl(cc, dst, src);
5393 } else {
5394 Label L;
5395 jccb(negate_condition(cc), L);
5396 movl(dst, src);
5397 bind(L);
5398 }
5399 }
5400
5401 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
5402 if (!VerifyOops) return;
5403
5404 BLOCK_COMMENT("verify_oop {");
5405 #ifdef _LP64
5406 push(rscratch1);
5407 #endif
5408 push(rax); // save rax
5409 push(reg); // pass register argument
5410
5411 // Pass register number to verify_oop_subroutine
5412 const char* b = nullptr;
5413 {
5414 ResourceMark rm;
5415 stringStream ss;
5416 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
5417 b = code_string(ss.as_string());
5418 }
5419 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5420 pushptr(buffer.addr(), rscratch1);
5421
5422 // call indirectly to solve generation ordering problem
5423 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5424 call(rax);
5425 // Caller pops the arguments (oop, message) and restores rax, r10
5426 BLOCK_COMMENT("} verify_oop");
5427 }
5428
5429 void MacroAssembler::vallones(XMMRegister dst, int vector_len) {
5430 if (UseAVX > 2 && (vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl())) {
5431 // Only pcmpeq has dependency breaking treatment (i.e the execution can begin without
5432 // waiting for the previous result on dst), not vpcmpeqd, so just use vpternlog
5433 vpternlogd(dst, 0xFF, dst, dst, vector_len);
5434 } else if (VM_Version::supports_avx()) {
5435 vpcmpeqd(dst, dst, dst, vector_len);
5436 } else {
5437 assert(VM_Version::supports_sse2(), "");
5438 pcmpeqd(dst, dst);
5439 }
5440 }
5441
5442 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
5443 int extra_slot_offset) {
5444 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5445 int stackElementSize = Interpreter::stackElementSize;
5446 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5447 #ifdef ASSERT
5448 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5449 assert(offset1 - offset == stackElementSize, "correct arithmetic");
5450 #endif
5451 Register scale_reg = noreg;
5452 Address::ScaleFactor scale_factor = Address::no_scale;
5453 if (arg_slot.is_constant()) {
5454 offset += arg_slot.as_constant() * stackElementSize;
5455 } else {
5456 scale_reg = arg_slot.as_register();
5457 scale_factor = Address::times(stackElementSize);
5458 }
5459 offset += wordSize; // return PC is on stack
5460 return Address(rsp, scale_reg, scale_factor, offset);
5461 }
5462
5463 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
5464 if (!VerifyOops) return;
5465
5466 #ifdef _LP64
5467 push(rscratch1);
5468 #endif
5469 push(rax); // save rax,
5470 // addr may contain rsp so we will have to adjust it based on the push
5471 // we just did (and on 64 bit we do two pushes)
5472 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5473 // stores rax into addr which is backwards of what was intended.
5474 if (addr.uses(rsp)) {
5475 lea(rax, addr);
5476 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
5477 } else {
5478 pushptr(addr);
5479 }
5480
5481 // Pass register number to verify_oop_subroutine
5482 const char* b = nullptr;
5483 {
5484 ResourceMark rm;
5485 stringStream ss;
5486 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
5487 b = code_string(ss.as_string());
5488 }
5489 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5490 pushptr(buffer.addr(), rscratch1);
5491
5492 // call indirectly to solve generation ordering problem
5493 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5494 call(rax);
5495 // Caller pops the arguments (addr, message) and restores rax, r10.
5496 }
5497
5498 void MacroAssembler::verify_tlab() {
5499 #ifdef ASSERT
5500 if (UseTLAB && VerifyOops) {
5501 Label next, ok;
5502 Register t1 = rsi;
5503 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
5504
5505 push(t1);
5506 NOT_LP64(push(thread_reg));
5507 NOT_LP64(get_thread(thread_reg));
5508
5509 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5510 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5511 jcc(Assembler::aboveEqual, next);
5512 STOP("assert(top >= start)");
5513 should_not_reach_here();
5514
5515 bind(next);
5516 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5517 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5518 jcc(Assembler::aboveEqual, ok);
5519 STOP("assert(top <= end)");
5520 should_not_reach_here();
5521
5522 bind(ok);
5523 NOT_LP64(pop(thread_reg));
5524 pop(t1);
5525 }
5526 #endif
5527 }
5528
5529 class ControlWord {
5530 public:
5531 int32_t _value;
5532
5533 int rounding_control() const { return (_value >> 10) & 3 ; }
5534 int precision_control() const { return (_value >> 8) & 3 ; }
5535 bool precision() const { return ((_value >> 5) & 1) != 0; }
5536 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5537 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5538 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5539 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5540 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5541
5542 void print() const {
5543 // rounding control
5544 const char* rc;
5545 switch (rounding_control()) {
5546 case 0: rc = "round near"; break;
5547 case 1: rc = "round down"; break;
5548 case 2: rc = "round up "; break;
5549 case 3: rc = "chop "; break;
5550 default:
5551 rc = nullptr; // silence compiler warnings
5552 fatal("Unknown rounding control: %d", rounding_control());
5553 };
5554 // precision control
5555 const char* pc;
5556 switch (precision_control()) {
5557 case 0: pc = "24 bits "; break;
5558 case 1: pc = "reserved"; break;
5559 case 2: pc = "53 bits "; break;
5560 case 3: pc = "64 bits "; break;
5561 default:
5562 pc = nullptr; // silence compiler warnings
5563 fatal("Unknown precision control: %d", precision_control());
5564 };
5565 // flags
5566 char f[9];
5567 f[0] = ' ';
5568 f[1] = ' ';
5569 f[2] = (precision ()) ? 'P' : 'p';
5570 f[3] = (underflow ()) ? 'U' : 'u';
5571 f[4] = (overflow ()) ? 'O' : 'o';
5572 f[5] = (zero_divide ()) ? 'Z' : 'z';
5573 f[6] = (denormalized()) ? 'D' : 'd';
5574 f[7] = (invalid ()) ? 'I' : 'i';
5575 f[8] = '\x0';
5576 // output
5577 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5578 }
5579
5580 };
5581
5582 class StatusWord {
5583 public:
5584 int32_t _value;
5585
5586 bool busy() const { return ((_value >> 15) & 1) != 0; }
5587 bool C3() const { return ((_value >> 14) & 1) != 0; }
5588 bool C2() const { return ((_value >> 10) & 1) != 0; }
5589 bool C1() const { return ((_value >> 9) & 1) != 0; }
5590 bool C0() const { return ((_value >> 8) & 1) != 0; }
5591 int top() const { return (_value >> 11) & 7 ; }
5592 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5593 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5594 bool precision() const { return ((_value >> 5) & 1) != 0; }
5595 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5596 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5597 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5598 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5599 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5600
5601 void print() const {
5602 // condition codes
5603 char c[5];
5604 c[0] = (C3()) ? '3' : '-';
5605 c[1] = (C2()) ? '2' : '-';
5606 c[2] = (C1()) ? '1' : '-';
5607 c[3] = (C0()) ? '0' : '-';
5608 c[4] = '\x0';
5609 // flags
5610 char f[9];
5611 f[0] = (error_status()) ? 'E' : '-';
5612 f[1] = (stack_fault ()) ? 'S' : '-';
5613 f[2] = (precision ()) ? 'P' : '-';
5614 f[3] = (underflow ()) ? 'U' : '-';
5615 f[4] = (overflow ()) ? 'O' : '-';
5616 f[5] = (zero_divide ()) ? 'Z' : '-';
5617 f[6] = (denormalized()) ? 'D' : '-';
5618 f[7] = (invalid ()) ? 'I' : '-';
5619 f[8] = '\x0';
5620 // output
5621 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5622 }
5623
5624 };
5625
5626 class TagWord {
5627 public:
5628 int32_t _value;
5629
5630 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5631
5632 void print() const {
5633 printf("%04x", _value & 0xFFFF);
5634 }
5635
5636 };
5637
5638 class FPU_Register {
5639 public:
5640 int32_t _m0;
5641 int32_t _m1;
5642 int16_t _ex;
5643
5644 bool is_indefinite() const {
5645 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5646 }
5647
5648 void print() const {
5649 char sign = (_ex < 0) ? '-' : '+';
5650 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5651 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5652 };
5653
5654 };
5655
5656 class FPU_State {
5657 public:
5658 enum {
5659 register_size = 10,
5660 number_of_registers = 8,
5661 register_mask = 7
5662 };
5663
5664 ControlWord _control_word;
5665 StatusWord _status_word;
5666 TagWord _tag_word;
5667 int32_t _error_offset;
5668 int32_t _error_selector;
5669 int32_t _data_offset;
5670 int32_t _data_selector;
5671 int8_t _register[register_size * number_of_registers];
5672
5673 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5674 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5675
5676 const char* tag_as_string(int tag) const {
5677 switch (tag) {
5678 case 0: return "valid";
5679 case 1: return "zero";
5680 case 2: return "special";
5681 case 3: return "empty";
5682 }
5683 ShouldNotReachHere();
5684 return nullptr;
5685 }
5686
5687 void print() const {
5688 // print computation registers
5689 { int t = _status_word.top();
5690 for (int i = 0; i < number_of_registers; i++) {
5691 int j = (i - t) & register_mask;
5692 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5693 st(j)->print();
5694 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5695 }
5696 }
5697 printf("\n");
5698 // print control registers
5699 printf("ctrl = "); _control_word.print(); printf("\n");
5700 printf("stat = "); _status_word .print(); printf("\n");
5701 printf("tags = "); _tag_word .print(); printf("\n");
5702 }
5703
5704 };
5705
5706 class Flag_Register {
5707 public:
5708 int32_t _value;
5709
5710 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5711 bool direction() const { return ((_value >> 10) & 1) != 0; }
5712 bool sign() const { return ((_value >> 7) & 1) != 0; }
5713 bool zero() const { return ((_value >> 6) & 1) != 0; }
5714 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5715 bool parity() const { return ((_value >> 2) & 1) != 0; }
5716 bool carry() const { return ((_value >> 0) & 1) != 0; }
5717
5718 void print() const {
5719 // flags
5720 char f[8];
5721 f[0] = (overflow ()) ? 'O' : '-';
5722 f[1] = (direction ()) ? 'D' : '-';
5723 f[2] = (sign ()) ? 'S' : '-';
5724 f[3] = (zero ()) ? 'Z' : '-';
5725 f[4] = (auxiliary_carry()) ? 'A' : '-';
5726 f[5] = (parity ()) ? 'P' : '-';
5727 f[6] = (carry ()) ? 'C' : '-';
5728 f[7] = '\x0';
5729 // output
5730 printf("%08x flags = %s", _value, f);
5731 }
5732
5733 };
5734
5735 class IU_Register {
5736 public:
5737 int32_t _value;
5738
5739 void print() const {
5740 printf("%08x %11d", _value, _value);
5741 }
5742
5743 };
5744
5745 class IU_State {
5746 public:
5747 Flag_Register _eflags;
5748 IU_Register _rdi;
5749 IU_Register _rsi;
5750 IU_Register _rbp;
5751 IU_Register _rsp;
5752 IU_Register _rbx;
5753 IU_Register _rdx;
5754 IU_Register _rcx;
5755 IU_Register _rax;
5756
5757 void print() const {
5758 // computation registers
5759 printf("rax, = "); _rax.print(); printf("\n");
5760 printf("rbx, = "); _rbx.print(); printf("\n");
5761 printf("rcx = "); _rcx.print(); printf("\n");
5762 printf("rdx = "); _rdx.print(); printf("\n");
5763 printf("rdi = "); _rdi.print(); printf("\n");
5764 printf("rsi = "); _rsi.print(); printf("\n");
5765 printf("rbp, = "); _rbp.print(); printf("\n");
5766 printf("rsp = "); _rsp.print(); printf("\n");
5767 printf("\n");
5768 // control registers
5769 printf("flgs = "); _eflags.print(); printf("\n");
5770 }
5771 };
5772
5773
5774 class CPU_State {
5775 public:
5776 FPU_State _fpu_state;
5777 IU_State _iu_state;
5778
5779 void print() const {
5780 printf("--------------------------------------------------\n");
5781 _iu_state .print();
5782 printf("\n");
5783 _fpu_state.print();
5784 printf("--------------------------------------------------\n");
5785 }
5786
5787 };
5788
5789
5790 static void _print_CPU_state(CPU_State* state) {
5791 state->print();
5792 };
5793
5794
5795 void MacroAssembler::print_CPU_state() {
5796 push_CPU_state();
5797 push(rsp); // pass CPU state
5798 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5799 addptr(rsp, wordSize); // discard argument
5800 pop_CPU_state();
5801 }
5802
5803
5804 #ifndef _LP64
5805 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
5806 static int counter = 0;
5807 FPU_State* fs = &state->_fpu_state;
5808 counter++;
5809 // For leaf calls, only verify that the top few elements remain empty.
5810 // We only need 1 empty at the top for C2 code.
5811 if( stack_depth < 0 ) {
5812 if( fs->tag_for_st(7) != 3 ) {
5813 printf("FPR7 not empty\n");
5814 state->print();
5815 assert(false, "error");
5816 return false;
5817 }
5818 return true; // All other stack states do not matter
5819 }
5820
5821 assert((fs->_control_word._value & 0xffff) == StubRoutines::x86::fpu_cntrl_wrd_std(),
5822 "bad FPU control word");
5823
5824 // compute stack depth
5825 int i = 0;
5826 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
5827 int d = i;
5828 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
5829 // verify findings
5830 if (i != FPU_State::number_of_registers) {
5831 // stack not contiguous
5832 printf("%s: stack not contiguous at ST%d\n", s, i);
5833 state->print();
5834 assert(false, "error");
5835 return false;
5836 }
5837 // check if computed stack depth corresponds to expected stack depth
5838 if (stack_depth < 0) {
5839 // expected stack depth is -stack_depth or less
5840 if (d > -stack_depth) {
5841 // too many elements on the stack
5842 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
5843 state->print();
5844 assert(false, "error");
5845 return false;
5846 }
5847 } else {
5848 // expected stack depth is stack_depth
5849 if (d != stack_depth) {
5850 // wrong stack depth
5851 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
5852 state->print();
5853 assert(false, "error");
5854 return false;
5855 }
5856 }
5857 // everything is cool
5858 return true;
5859 }
5860
5861 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
5862 if (!VerifyFPU) return;
5863 push_CPU_state();
5864 push(rsp); // pass CPU state
5865 ExternalAddress msg((address) s);
5866 // pass message string s
5867 pushptr(msg.addr(), noreg);
5868 push(stack_depth); // pass stack depth
5869 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
5870 addptr(rsp, 3 * wordSize); // discard arguments
5871 // check for error
5872 { Label L;
5873 testl(rax, rax);
5874 jcc(Assembler::notZero, L);
5875 int3(); // break if error condition
5876 bind(L);
5877 }
5878 pop_CPU_state();
5879 }
5880 #endif // _LP64
5881
5882 void MacroAssembler::restore_cpu_control_state_after_jni(Register rscratch) {
5883 // Either restore the MXCSR register after returning from the JNI Call
5884 // or verify that it wasn't changed (with -Xcheck:jni flag).
5885 if (VM_Version::supports_sse()) {
5886 if (RestoreMXCSROnJNICalls) {
5887 ldmxcsr(ExternalAddress(StubRoutines::x86::addr_mxcsr_std()), rscratch);
5888 } else if (CheckJNICalls) {
5889 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5890 }
5891 }
5892 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5893 vzeroupper();
5894
5895 #ifndef _LP64
5896 // Either restore the x87 floating pointer control word after returning
5897 // from the JNI call or verify that it wasn't changed.
5898 if (CheckJNICalls) {
5899 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
5900 }
5901 #endif // _LP64
5902 }
5903
5904 // ((OopHandle)result).resolve();
5905 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
5906 assert_different_registers(result, tmp);
5907
5908 // Only 64 bit platforms support GCs that require a tmp register
5909 // Only IN_HEAP loads require a thread_tmp register
5910 // OopHandle::resolve is an indirection like jobject.
5911 access_load_at(T_OBJECT, IN_NATIVE,
5912 result, Address(result, 0), tmp, /*tmp_thread*/noreg);
5913 }
5914
5915 // ((WeakHandle)result).resolve();
5916 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
5917 assert_different_registers(rresult, rtmp);
5918 Label resolved;
5919
5920 // A null weak handle resolves to null.
5921 cmpptr(rresult, 0);
5922 jcc(Assembler::equal, resolved);
5923
5924 // Only 64 bit platforms support GCs that require a tmp register
5925 // Only IN_HEAP loads require a thread_tmp register
5926 // WeakHandle::resolve is an indirection like jweak.
5927 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5928 rresult, Address(rresult, 0), rtmp, /*tmp_thread*/noreg);
5929 bind(resolved);
5930 }
5931
5932 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
5933 // get mirror
5934 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5935 load_method_holder(mirror, method);
5936 movptr(mirror, Address(mirror, mirror_offset));
5937 resolve_oop_handle(mirror, tmp);
5938 }
5939
5940 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5941 load_method_holder(rresult, rmethod);
5942 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5943 }
5944
5945 void MacroAssembler::load_method_holder(Register holder, Register method) {
5946 movptr(holder, Address(method, Method::const_offset())); // ConstMethod*
5947 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5948 movptr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5949 }
5950
5951 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
5952 assert_different_registers(src, tmp);
5953 assert_different_registers(dst, tmp);
5954 #ifdef _LP64
5955 if (UseCompressedClassPointers) {
5956 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5957 decode_klass_not_null(dst, tmp);
5958 } else
5959 #endif
5960 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5961 }
5962
5963 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
5964 assert_different_registers(src, tmp);
5965 assert_different_registers(dst, tmp);
5966 #ifdef _LP64
5967 if (UseCompressedClassPointers) {
5968 encode_klass_not_null(src, tmp);
5969 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5970 } else
5971 #endif
5972 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5973 }
5974
5975 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
5976 Register tmp1, Register thread_tmp) {
5977 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5978 decorators = AccessInternal::decorator_fixup(decorators, type);
5979 bool as_raw = (decorators & AS_RAW) != 0;
5980 if (as_raw) {
5981 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
5982 } else {
5983 bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
5984 }
5985 }
5986
5987 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
5988 Register tmp1, Register tmp2, Register tmp3) {
5989 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5990 decorators = AccessInternal::decorator_fixup(decorators, type);
5991 bool as_raw = (decorators & AS_RAW) != 0;
5992 if (as_raw) {
5993 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5994 } else {
5995 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5996 }
5997 }
5998
5999 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
6000 Register thread_tmp, DecoratorSet decorators) {
6001 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
6002 }
6003
6004 // Doesn't do verification, generates fixed size code
6005 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
6006 Register thread_tmp, DecoratorSet decorators) {
6007 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
6008 }
6009
6010 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
6011 Register tmp2, Register tmp3, DecoratorSet decorators) {
6012 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
6013 }
6014
6015 // Used for storing nulls.
6016 void MacroAssembler::store_heap_oop_null(Address dst) {
6017 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
6018 }
6019
6020 #ifdef _LP64
6021 void MacroAssembler::store_klass_gap(Register dst, Register src) {
6022 if (UseCompressedClassPointers) {
6023 // Store to klass gap in destination
6024 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
6025 }
6026 }
6027
6028 #ifdef ASSERT
6029 void MacroAssembler::verify_heapbase(const char* msg) {
6030 assert (UseCompressedOops, "should be compressed");
6031 assert (Universe::heap() != nullptr, "java heap should be initialized");
6032 if (CheckCompressedOops) {
6033 Label ok;
6034 ExternalAddress src2(CompressedOops::base_addr());
6035 const bool is_src2_reachable = reachable(src2);
6036 if (!is_src2_reachable) {
6037 push(rscratch1); // cmpptr trashes rscratch1
6038 }
6039 cmpptr(r12_heapbase, src2, rscratch1);
6040 jcc(Assembler::equal, ok);
6041 STOP(msg);
6042 bind(ok);
6043 if (!is_src2_reachable) {
6044 pop(rscratch1);
6045 }
6046 }
6047 }
6048 #endif
6049
6050 // Algorithm must match oop.inline.hpp encode_heap_oop.
6051 void MacroAssembler::encode_heap_oop(Register r) {
6052 #ifdef ASSERT
6053 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
6054 #endif
6055 verify_oop_msg(r, "broken oop in encode_heap_oop");
6056 if (CompressedOops::base() == nullptr) {
6057 if (CompressedOops::shift() != 0) {
6058 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6059 shrq(r, LogMinObjAlignmentInBytes);
6060 }
6061 return;
6062 }
6063 testq(r, r);
6064 cmovq(Assembler::equal, r, r12_heapbase);
6065 subq(r, r12_heapbase);
6066 shrq(r, LogMinObjAlignmentInBytes);
6067 }
6068
6069 void MacroAssembler::encode_heap_oop_not_null(Register r) {
6070 #ifdef ASSERT
6071 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
6072 if (CheckCompressedOops) {
6073 Label ok;
6074 testq(r, r);
6075 jcc(Assembler::notEqual, ok);
6076 STOP("null oop passed to encode_heap_oop_not_null");
6077 bind(ok);
6078 }
6079 #endif
6080 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
6081 if (CompressedOops::base() != nullptr) {
6082 subq(r, r12_heapbase);
6083 }
6084 if (CompressedOops::shift() != 0) {
6085 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6086 shrq(r, LogMinObjAlignmentInBytes);
6087 }
6088 }
6089
6090 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
6091 #ifdef ASSERT
6092 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
6093 if (CheckCompressedOops) {
6094 Label ok;
6095 testq(src, src);
6096 jcc(Assembler::notEqual, ok);
6097 STOP("null oop passed to encode_heap_oop_not_null2");
6098 bind(ok);
6099 }
6100 #endif
6101 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
6102 if (dst != src) {
6103 movq(dst, src);
6104 }
6105 if (CompressedOops::base() != nullptr) {
6106 subq(dst, r12_heapbase);
6107 }
6108 if (CompressedOops::shift() != 0) {
6109 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6110 shrq(dst, LogMinObjAlignmentInBytes);
6111 }
6112 }
6113
6114 void MacroAssembler::decode_heap_oop(Register r) {
6115 #ifdef ASSERT
6116 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
6117 #endif
6118 if (CompressedOops::base() == nullptr) {
6119 if (CompressedOops::shift() != 0) {
6120 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6121 shlq(r, LogMinObjAlignmentInBytes);
6122 }
6123 } else {
6124 Label done;
6125 shlq(r, LogMinObjAlignmentInBytes);
6126 jccb(Assembler::equal, done);
6127 addq(r, r12_heapbase);
6128 bind(done);
6129 }
6130 verify_oop_msg(r, "broken oop in decode_heap_oop");
6131 }
6132
6133 void MacroAssembler::decode_heap_oop_not_null(Register r) {
6134 // Note: it will change flags
6135 assert (UseCompressedOops, "should only be used for compressed headers");
6136 assert (Universe::heap() != nullptr, "java heap should be initialized");
6137 // Cannot assert, unverified entry point counts instructions (see .ad file)
6138 // vtableStubs also counts instructions in pd_code_size_limit.
6139 // Also do not verify_oop as this is called by verify_oop.
6140 if (CompressedOops::shift() != 0) {
6141 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6142 shlq(r, LogMinObjAlignmentInBytes);
6143 if (CompressedOops::base() != nullptr) {
6144 addq(r, r12_heapbase);
6145 }
6146 } else {
6147 assert (CompressedOops::base() == nullptr, "sanity");
6148 }
6149 }
6150
6151 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
6152 // Note: it will change flags
6153 assert (UseCompressedOops, "should only be used for compressed headers");
6154 assert (Universe::heap() != nullptr, "java heap should be initialized");
6155 // Cannot assert, unverified entry point counts instructions (see .ad file)
6156 // vtableStubs also counts instructions in pd_code_size_limit.
6157 // Also do not verify_oop as this is called by verify_oop.
6158 if (CompressedOops::shift() != 0) {
6159 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6160 if (LogMinObjAlignmentInBytes == Address::times_8) {
6161 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
6162 } else {
6163 if (dst != src) {
6164 movq(dst, src);
6165 }
6166 shlq(dst, LogMinObjAlignmentInBytes);
6167 if (CompressedOops::base() != nullptr) {
6168 addq(dst, r12_heapbase);
6169 }
6170 }
6171 } else {
6172 assert (CompressedOops::base() == nullptr, "sanity");
6173 if (dst != src) {
6174 movq(dst, src);
6175 }
6176 }
6177 }
6178
6179 void MacroAssembler::encode_klass_not_null(Register r, Register tmp) {
6180 assert_different_registers(r, tmp);
6181 if (CompressedKlassPointers::base() != nullptr) {
6182 mov64(tmp, (int64_t)CompressedKlassPointers::base());
6183 subq(r, tmp);
6184 }
6185 if (CompressedKlassPointers::shift() != 0) {
6186 assert (LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
6187 shrq(r, LogKlassAlignmentInBytes);
6188 }
6189 }
6190
6191 void MacroAssembler::encode_and_move_klass_not_null(Register dst, Register src) {
6192 assert_different_registers(src, dst);
6193 if (CompressedKlassPointers::base() != nullptr) {
6194 mov64(dst, -(int64_t)CompressedKlassPointers::base());
6195 addq(dst, src);
6196 } else {
6197 movptr(dst, src);
6198 }
6199 if (CompressedKlassPointers::shift() != 0) {
6200 assert (LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
6201 shrq(dst, LogKlassAlignmentInBytes);
6202 }
6203 }
6204
6205 void MacroAssembler::decode_klass_not_null(Register r, Register tmp) {
6206 assert_different_registers(r, tmp);
6207 // Note: it will change flags
6208 assert(UseCompressedClassPointers, "should only be used for compressed headers");
6209 // Cannot assert, unverified entry point counts instructions (see .ad file)
6210 // vtableStubs also counts instructions in pd_code_size_limit.
6211 // Also do not verify_oop as this is called by verify_oop.
6212 if (CompressedKlassPointers::shift() != 0) {
6213 assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
6214 shlq(r, LogKlassAlignmentInBytes);
6215 }
6216 if (CompressedKlassPointers::base() != nullptr) {
6217 mov64(tmp, (int64_t)CompressedKlassPointers::base());
6218 addq(r, tmp);
6219 }
6220 }
6221
6222 void MacroAssembler::decode_and_move_klass_not_null(Register dst, Register src) {
6223 assert_different_registers(src, dst);
6224 // Note: it will change flags
6225 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6226 // Cannot assert, unverified entry point counts instructions (see .ad file)
6227 // vtableStubs also counts instructions in pd_code_size_limit.
6228 // Also do not verify_oop as this is called by verify_oop.
6229
6230 if (CompressedKlassPointers::base() == nullptr &&
6231 CompressedKlassPointers::shift() == 0) {
6232 // The best case scenario is that there is no base or shift. Then it is already
6233 // a pointer that needs nothing but a register rename.
6234 movl(dst, src);
6235 } else {
6236 if (CompressedKlassPointers::base() != nullptr) {
6237 mov64(dst, (int64_t)CompressedKlassPointers::base());
6238 } else {
6239 xorq(dst, dst);
6240 }
6241 if (CompressedKlassPointers::shift() != 0) {
6242 assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
6243 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
6244 leaq(dst, Address(dst, src, Address::times_8, 0));
6245 } else {
6246 addq(dst, src);
6247 }
6248 }
6249 }
6250
6251 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6252 assert (UseCompressedOops, "should only be used for compressed headers");
6253 assert (Universe::heap() != nullptr, "java heap should be initialized");
6254 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6255 int oop_index = oop_recorder()->find_index(obj);
6256 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6257 mov_narrow_oop(dst, oop_index, rspec);
6258 }
6259
6260 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
6261 assert (UseCompressedOops, "should only be used for compressed headers");
6262 assert (Universe::heap() != nullptr, "java heap should be initialized");
6263 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6264 int oop_index = oop_recorder()->find_index(obj);
6265 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6266 mov_narrow_oop(dst, oop_index, rspec);
6267 }
6268
6269 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6270 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6271 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6272 int klass_index = oop_recorder()->find_index(k);
6273 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6274 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6275 }
6276
6277 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6278 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6279 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6280 int klass_index = oop_recorder()->find_index(k);
6281 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6282 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6283 }
6284
6285 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6286 assert (UseCompressedOops, "should only be used for compressed headers");
6287 assert (Universe::heap() != nullptr, "java heap should be initialized");
6288 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6289 int oop_index = oop_recorder()->find_index(obj);
6290 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6291 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6292 }
6293
6294 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6295 assert (UseCompressedOops, "should only be used for compressed headers");
6296 assert (Universe::heap() != nullptr, "java heap should be initialized");
6297 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6298 int oop_index = oop_recorder()->find_index(obj);
6299 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6300 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6301 }
6302
6303 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6304 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6305 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6306 int klass_index = oop_recorder()->find_index(k);
6307 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6308 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6309 }
6310
6311 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6312 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6313 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6314 int klass_index = oop_recorder()->find_index(k);
6315 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6316 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6317 }
6318
6319 void MacroAssembler::reinit_heapbase() {
6320 if (UseCompressedOops) {
6321 if (Universe::heap() != nullptr) {
6322 if (CompressedOops::base() == nullptr) {
6323 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6324 } else {
6325 mov64(r12_heapbase, (int64_t)CompressedOops::base());
6326 }
6327 } else {
6328 movptr(r12_heapbase, ExternalAddress(CompressedOops::base_addr()));
6329 }
6330 }
6331 }
6332
6333 #endif // _LP64
6334
6335 #if COMPILER2_OR_JVMCI
6336
6337 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
6338 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6339 // cnt - number of qwords (8-byte words).
6340 // base - start address, qword aligned.
6341 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
6342 bool use64byteVector = (MaxVectorSize == 64) && (VM_Version::avx3_threshold() == 0);
6343 if (use64byteVector) {
6344 vpxor(xtmp, xtmp, xtmp, AVX_512bit);
6345 } else if (MaxVectorSize >= 32) {
6346 vpxor(xtmp, xtmp, xtmp, AVX_256bit);
6347 } else {
6348 pxor(xtmp, xtmp);
6349 }
6350 jmp(L_zero_64_bytes);
6351
6352 BIND(L_loop);
6353 if (MaxVectorSize >= 32) {
6354 fill64(base, 0, xtmp, use64byteVector);
6355 } else {
6356 movdqu(Address(base, 0), xtmp);
6357 movdqu(Address(base, 16), xtmp);
6358 movdqu(Address(base, 32), xtmp);
6359 movdqu(Address(base, 48), xtmp);
6360 }
6361 addptr(base, 64);
6362
6363 BIND(L_zero_64_bytes);
6364 subptr(cnt, 8);
6365 jccb(Assembler::greaterEqual, L_loop);
6366
6367 // Copy trailing 64 bytes
6368 if (use64byteVector) {
6369 addptr(cnt, 8);
6370 jccb(Assembler::equal, L_end);
6371 fill64_masked(3, base, 0, xtmp, mask, cnt, rtmp, true);
6372 jmp(L_end);
6373 } else {
6374 addptr(cnt, 4);
6375 jccb(Assembler::less, L_tail);
6376 if (MaxVectorSize >= 32) {
6377 vmovdqu(Address(base, 0), xtmp);
6378 } else {
6379 movdqu(Address(base, 0), xtmp);
6380 movdqu(Address(base, 16), xtmp);
6381 }
6382 }
6383 addptr(base, 32);
6384 subptr(cnt, 4);
6385
6386 BIND(L_tail);
6387 addptr(cnt, 4);
6388 jccb(Assembler::lessEqual, L_end);
6389 if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
6390 fill32_masked(3, base, 0, xtmp, mask, cnt, rtmp);
6391 } else {
6392 decrement(cnt);
6393
6394 BIND(L_sloop);
6395 movq(Address(base, 0), xtmp);
6396 addptr(base, 8);
6397 decrement(cnt);
6398 jccb(Assembler::greaterEqual, L_sloop);
6399 }
6400 BIND(L_end);
6401 }
6402
6403 // Clearing constant sized memory using YMM/ZMM registers.
6404 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6405 assert(UseAVX > 2 && VM_Version::supports_avx512vl(), "");
6406 bool use64byteVector = (MaxVectorSize > 32) && (VM_Version::avx3_threshold() == 0);
6407
6408 int vector64_count = (cnt & (~0x7)) >> 3;
6409 cnt = cnt & 0x7;
6410 const int fill64_per_loop = 4;
6411 const int max_unrolled_fill64 = 8;
6412
6413 // 64 byte initialization loop.
6414 vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
6415 int start64 = 0;
6416 if (vector64_count > max_unrolled_fill64) {
6417 Label LOOP;
6418 Register index = rtmp;
6419
6420 start64 = vector64_count - (vector64_count % fill64_per_loop);
6421
6422 movl(index, 0);
6423 BIND(LOOP);
6424 for (int i = 0; i < fill64_per_loop; i++) {
6425 fill64(Address(base, index, Address::times_1, i * 64), xtmp, use64byteVector);
6426 }
6427 addl(index, fill64_per_loop * 64);
6428 cmpl(index, start64 * 64);
6429 jccb(Assembler::less, LOOP);
6430 }
6431 for (int i = start64; i < vector64_count; i++) {
6432 fill64(base, i * 64, xtmp, use64byteVector);
6433 }
6434
6435 // Clear remaining 64 byte tail.
6436 int disp = vector64_count * 64;
6437 if (cnt) {
6438 switch (cnt) {
6439 case 1:
6440 movq(Address(base, disp), xtmp);
6441 break;
6442 case 2:
6443 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_128bit);
6444 break;
6445 case 3:
6446 movl(rtmp, 0x7);
6447 kmovwl(mask, rtmp);
6448 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_256bit);
6449 break;
6450 case 4:
6451 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6452 break;
6453 case 5:
6454 if (use64byteVector) {
6455 movl(rtmp, 0x1F);
6456 kmovwl(mask, rtmp);
6457 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6458 } else {
6459 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6460 movq(Address(base, disp + 32), xtmp);
6461 }
6462 break;
6463 case 6:
6464 if (use64byteVector) {
6465 movl(rtmp, 0x3F);
6466 kmovwl(mask, rtmp);
6467 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6468 } else {
6469 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6470 evmovdqu(T_LONG, k0, Address(base, disp + 32), xtmp, false, Assembler::AVX_128bit);
6471 }
6472 break;
6473 case 7:
6474 if (use64byteVector) {
6475 movl(rtmp, 0x7F);
6476 kmovwl(mask, rtmp);
6477 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6478 } else {
6479 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6480 movl(rtmp, 0x7);
6481 kmovwl(mask, rtmp);
6482 evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, true, Assembler::AVX_256bit);
6483 }
6484 break;
6485 default:
6486 fatal("Unexpected length : %d\n",cnt);
6487 break;
6488 }
6489 }
6490 }
6491
6492 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp,
6493 bool is_large, KRegister mask) {
6494 // cnt - number of qwords (8-byte words).
6495 // base - start address, qword aligned.
6496 // is_large - if optimizers know cnt is larger than InitArrayShortSize
6497 assert(base==rdi, "base register must be edi for rep stos");
6498 assert(tmp==rax, "tmp register must be eax for rep stos");
6499 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6500 assert(InitArrayShortSize % BytesPerLong == 0,
6501 "InitArrayShortSize should be the multiple of BytesPerLong");
6502
6503 Label DONE;
6504 if (!is_large || !UseXMMForObjInit) {
6505 xorptr(tmp, tmp);
6506 }
6507
6508 if (!is_large) {
6509 Label LOOP, LONG;
6510 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
6511 jccb(Assembler::greater, LONG);
6512
6513 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
6514
6515 decrement(cnt);
6516 jccb(Assembler::negative, DONE); // Zero length
6517
6518 // Use individual pointer-sized stores for small counts:
6519 BIND(LOOP);
6520 movptr(Address(base, cnt, Address::times_ptr), tmp);
6521 decrement(cnt);
6522 jccb(Assembler::greaterEqual, LOOP);
6523 jmpb(DONE);
6524
6525 BIND(LONG);
6526 }
6527
6528 // Use longer rep-prefixed ops for non-small counts:
6529 if (UseFastStosb) {
6530 shlptr(cnt, 3); // convert to number of bytes
6531 rep_stosb();
6532 } else if (UseXMMForObjInit) {
6533 xmm_clear_mem(base, cnt, tmp, xtmp, mask);
6534 } else {
6535 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
6536 rep_stos();
6537 }
6538
6539 BIND(DONE);
6540 }
6541
6542 #endif //COMPILER2_OR_JVMCI
6543
6544
6545 void MacroAssembler::generate_fill(BasicType t, bool aligned,
6546 Register to, Register value, Register count,
6547 Register rtmp, XMMRegister xtmp) {
6548 ShortBranchVerifier sbv(this);
6549 assert_different_registers(to, value, count, rtmp);
6550 Label L_exit;
6551 Label L_fill_2_bytes, L_fill_4_bytes;
6552
6553 #if defined(COMPILER2) && defined(_LP64)
6554 if(MaxVectorSize >=32 &&
6555 VM_Version::supports_avx512vlbw() &&
6556 VM_Version::supports_bmi2()) {
6557 generate_fill_avx3(t, to, value, count, rtmp, xtmp);
6558 return;
6559 }
6560 #endif
6561
6562 int shift = -1;
6563 switch (t) {
6564 case T_BYTE:
6565 shift = 2;
6566 break;
6567 case T_SHORT:
6568 shift = 1;
6569 break;
6570 case T_INT:
6571 shift = 0;
6572 break;
6573 default: ShouldNotReachHere();
6574 }
6575
6576 if (t == T_BYTE) {
6577 andl(value, 0xff);
6578 movl(rtmp, value);
6579 shll(rtmp, 8);
6580 orl(value, rtmp);
6581 }
6582 if (t == T_SHORT) {
6583 andl(value, 0xffff);
6584 }
6585 if (t == T_BYTE || t == T_SHORT) {
6586 movl(rtmp, value);
6587 shll(rtmp, 16);
6588 orl(value, rtmp);
6589 }
6590
6591 cmpptr(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
6592 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
6593 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
6594 Label L_skip_align2;
6595 // align source address at 4 bytes address boundary
6596 if (t == T_BYTE) {
6597 Label L_skip_align1;
6598 // One byte misalignment happens only for byte arrays
6599 testptr(to, 1);
6600 jccb(Assembler::zero, L_skip_align1);
6601 movb(Address(to, 0), value);
6602 increment(to);
6603 decrement(count);
6604 BIND(L_skip_align1);
6605 }
6606 // Two bytes misalignment happens only for byte and short (char) arrays
6607 testptr(to, 2);
6608 jccb(Assembler::zero, L_skip_align2);
6609 movw(Address(to, 0), value);
6610 addptr(to, 2);
6611 subptr(count, 1<<(shift-1));
6612 BIND(L_skip_align2);
6613 }
6614 if (UseSSE < 2) {
6615 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6616 // Fill 32-byte chunks
6617 subptr(count, 8 << shift);
6618 jcc(Assembler::less, L_check_fill_8_bytes);
6619 align(16);
6620
6621 BIND(L_fill_32_bytes_loop);
6622
6623 for (int i = 0; i < 32; i += 4) {
6624 movl(Address(to, i), value);
6625 }
6626
6627 addptr(to, 32);
6628 subptr(count, 8 << shift);
6629 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
6630 BIND(L_check_fill_8_bytes);
6631 addptr(count, 8 << shift);
6632 jccb(Assembler::zero, L_exit);
6633 jmpb(L_fill_8_bytes);
6634
6635 //
6636 // length is too short, just fill qwords
6637 //
6638 BIND(L_fill_8_bytes_loop);
6639 movl(Address(to, 0), value);
6640 movl(Address(to, 4), value);
6641 addptr(to, 8);
6642 BIND(L_fill_8_bytes);
6643 subptr(count, 1 << (shift + 1));
6644 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
6645 // fall through to fill 4 bytes
6646 } else {
6647 Label L_fill_32_bytes;
6648 if (!UseUnalignedLoadStores) {
6649 // align to 8 bytes, we know we are 4 byte aligned to start
6650 testptr(to, 4);
6651 jccb(Assembler::zero, L_fill_32_bytes);
6652 movl(Address(to, 0), value);
6653 addptr(to, 4);
6654 subptr(count, 1<<shift);
6655 }
6656 BIND(L_fill_32_bytes);
6657 {
6658 assert( UseSSE >= 2, "supported cpu only" );
6659 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6660 movdl(xtmp, value);
6661 if (UseAVX >= 2 && UseUnalignedLoadStores) {
6662 Label L_check_fill_32_bytes;
6663 if (UseAVX > 2) {
6664 // Fill 64-byte chunks
6665 Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
6666
6667 // If number of bytes to fill < VM_Version::avx3_threshold(), perform fill using AVX2
6668 cmpptr(count, VM_Version::avx3_threshold());
6669 jccb(Assembler::below, L_check_fill_64_bytes_avx2);
6670
6671 vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
6672
6673 subptr(count, 16 << shift);
6674 jccb(Assembler::less, L_check_fill_32_bytes);
6675 align(16);
6676
6677 BIND(L_fill_64_bytes_loop_avx3);
6678 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
6679 addptr(to, 64);
6680 subptr(count, 16 << shift);
6681 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
6682 jmpb(L_check_fill_32_bytes);
6683
6684 BIND(L_check_fill_64_bytes_avx2);
6685 }
6686 // Fill 64-byte chunks
6687 Label L_fill_64_bytes_loop;
6688 vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
6689
6690 subptr(count, 16 << shift);
6691 jcc(Assembler::less, L_check_fill_32_bytes);
6692 align(16);
6693
6694 BIND(L_fill_64_bytes_loop);
6695 vmovdqu(Address(to, 0), xtmp);
6696 vmovdqu(Address(to, 32), xtmp);
6697 addptr(to, 64);
6698 subptr(count, 16 << shift);
6699 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
6700
6701 BIND(L_check_fill_32_bytes);
6702 addptr(count, 8 << shift);
6703 jccb(Assembler::less, L_check_fill_8_bytes);
6704 vmovdqu(Address(to, 0), xtmp);
6705 addptr(to, 32);
6706 subptr(count, 8 << shift);
6707
6708 BIND(L_check_fill_8_bytes);
6709 // clean upper bits of YMM registers
6710 movdl(xtmp, value);
6711 pshufd(xtmp, xtmp, 0);
6712 } else {
6713 // Fill 32-byte chunks
6714 pshufd(xtmp, xtmp, 0);
6715
6716 subptr(count, 8 << shift);
6717 jcc(Assembler::less, L_check_fill_8_bytes);
6718 align(16);
6719
6720 BIND(L_fill_32_bytes_loop);
6721
6722 if (UseUnalignedLoadStores) {
6723 movdqu(Address(to, 0), xtmp);
6724 movdqu(Address(to, 16), xtmp);
6725 } else {
6726 movq(Address(to, 0), xtmp);
6727 movq(Address(to, 8), xtmp);
6728 movq(Address(to, 16), xtmp);
6729 movq(Address(to, 24), xtmp);
6730 }
6731
6732 addptr(to, 32);
6733 subptr(count, 8 << shift);
6734 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
6735
6736 BIND(L_check_fill_8_bytes);
6737 }
6738 addptr(count, 8 << shift);
6739 jccb(Assembler::zero, L_exit);
6740 jmpb(L_fill_8_bytes);
6741
6742 //
6743 // length is too short, just fill qwords
6744 //
6745 BIND(L_fill_8_bytes_loop);
6746 movq(Address(to, 0), xtmp);
6747 addptr(to, 8);
6748 BIND(L_fill_8_bytes);
6749 subptr(count, 1 << (shift + 1));
6750 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
6751 }
6752 }
6753 // fill trailing 4 bytes
6754 BIND(L_fill_4_bytes);
6755 testl(count, 1<<shift);
6756 jccb(Assembler::zero, L_fill_2_bytes);
6757 movl(Address(to, 0), value);
6758 if (t == T_BYTE || t == T_SHORT) {
6759 Label L_fill_byte;
6760 addptr(to, 4);
6761 BIND(L_fill_2_bytes);
6762 // fill trailing 2 bytes
6763 testl(count, 1<<(shift-1));
6764 jccb(Assembler::zero, L_fill_byte);
6765 movw(Address(to, 0), value);
6766 if (t == T_BYTE) {
6767 addptr(to, 2);
6768 BIND(L_fill_byte);
6769 // fill trailing byte
6770 testl(count, 1);
6771 jccb(Assembler::zero, L_exit);
6772 movb(Address(to, 0), value);
6773 } else {
6774 BIND(L_fill_byte);
6775 }
6776 } else {
6777 BIND(L_fill_2_bytes);
6778 }
6779 BIND(L_exit);
6780 }
6781
6782 void MacroAssembler::evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len) {
6783 switch(type) {
6784 case T_BYTE:
6785 case T_BOOLEAN:
6786 evpbroadcastb(dst, src, vector_len);
6787 break;
6788 case T_SHORT:
6789 case T_CHAR:
6790 evpbroadcastw(dst, src, vector_len);
6791 break;
6792 case T_INT:
6793 case T_FLOAT:
6794 evpbroadcastd(dst, src, vector_len);
6795 break;
6796 case T_LONG:
6797 case T_DOUBLE:
6798 evpbroadcastq(dst, src, vector_len);
6799 break;
6800 default:
6801 fatal("Unhandled type : %s", type2name(type));
6802 break;
6803 }
6804 }
6805
6806 // encode char[] to byte[] in ISO_8859_1 or ASCII
6807 //@IntrinsicCandidate
6808 //private static int implEncodeISOArray(byte[] sa, int sp,
6809 //byte[] da, int dp, int len) {
6810 // int i = 0;
6811 // for (; i < len; i++) {
6812 // char c = StringUTF16.getChar(sa, sp++);
6813 // if (c > '\u00FF')
6814 // break;
6815 // da[dp++] = (byte)c;
6816 // }
6817 // return i;
6818 //}
6819 //
6820 //@IntrinsicCandidate
6821 //private static int implEncodeAsciiArray(char[] sa, int sp,
6822 // byte[] da, int dp, int len) {
6823 // int i = 0;
6824 // for (; i < len; i++) {
6825 // char c = sa[sp++];
6826 // if (c >= '\u0080')
6827 // break;
6828 // da[dp++] = (byte)c;
6829 // }
6830 // return i;
6831 //}
6832 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
6833 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
6834 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
6835 Register tmp5, Register result, bool ascii) {
6836
6837 // rsi: src
6838 // rdi: dst
6839 // rdx: len
6840 // rcx: tmp5
6841 // rax: result
6842 ShortBranchVerifier sbv(this);
6843 assert_different_registers(src, dst, len, tmp5, result);
6844 Label L_done, L_copy_1_char, L_copy_1_char_exit;
6845
6846 int mask = ascii ? 0xff80ff80 : 0xff00ff00;
6847 int short_mask = ascii ? 0xff80 : 0xff00;
6848
6849 // set result
6850 xorl(result, result);
6851 // check for zero length
6852 testl(len, len);
6853 jcc(Assembler::zero, L_done);
6854
6855 movl(result, len);
6856
6857 // Setup pointers
6858 lea(src, Address(src, len, Address::times_2)); // char[]
6859 lea(dst, Address(dst, len, Address::times_1)); // byte[]
6860 negptr(len);
6861
6862 if (UseSSE42Intrinsics || UseAVX >= 2) {
6863 Label L_copy_8_chars, L_copy_8_chars_exit;
6864 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
6865
6866 if (UseAVX >= 2) {
6867 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
6868 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
6869 movdl(tmp1Reg, tmp5);
6870 vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
6871 jmp(L_chars_32_check);
6872
6873 bind(L_copy_32_chars);
6874 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
6875 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
6876 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
6877 vptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
6878 jccb(Assembler::notZero, L_copy_32_chars_exit);
6879 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
6880 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
6881 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
6882
6883 bind(L_chars_32_check);
6884 addptr(len, 32);
6885 jcc(Assembler::lessEqual, L_copy_32_chars);
6886
6887 bind(L_copy_32_chars_exit);
6888 subptr(len, 16);
6889 jccb(Assembler::greater, L_copy_16_chars_exit);
6890
6891 } else if (UseSSE42Intrinsics) {
6892 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
6893 movdl(tmp1Reg, tmp5);
6894 pshufd(tmp1Reg, tmp1Reg, 0);
6895 jmpb(L_chars_16_check);
6896 }
6897
6898 bind(L_copy_16_chars);
6899 if (UseAVX >= 2) {
6900 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
6901 vptest(tmp2Reg, tmp1Reg);
6902 jcc(Assembler::notZero, L_copy_16_chars_exit);
6903 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
6904 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
6905 } else {
6906 if (UseAVX > 0) {
6907 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
6908 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
6909 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
6910 } else {
6911 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
6912 por(tmp2Reg, tmp3Reg);
6913 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
6914 por(tmp2Reg, tmp4Reg);
6915 }
6916 ptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
6917 jccb(Assembler::notZero, L_copy_16_chars_exit);
6918 packuswb(tmp3Reg, tmp4Reg);
6919 }
6920 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
6921
6922 bind(L_chars_16_check);
6923 addptr(len, 16);
6924 jcc(Assembler::lessEqual, L_copy_16_chars);
6925
6926 bind(L_copy_16_chars_exit);
6927 if (UseAVX >= 2) {
6928 // clean upper bits of YMM registers
6929 vpxor(tmp2Reg, tmp2Reg);
6930 vpxor(tmp3Reg, tmp3Reg);
6931 vpxor(tmp4Reg, tmp4Reg);
6932 movdl(tmp1Reg, tmp5);
6933 pshufd(tmp1Reg, tmp1Reg, 0);
6934 }
6935 subptr(len, 8);
6936 jccb(Assembler::greater, L_copy_8_chars_exit);
6937
6938 bind(L_copy_8_chars);
6939 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
6940 ptest(tmp3Reg, tmp1Reg);
6941 jccb(Assembler::notZero, L_copy_8_chars_exit);
6942 packuswb(tmp3Reg, tmp1Reg);
6943 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
6944 addptr(len, 8);
6945 jccb(Assembler::lessEqual, L_copy_8_chars);
6946
6947 bind(L_copy_8_chars_exit);
6948 subptr(len, 8);
6949 jccb(Assembler::zero, L_done);
6950 }
6951
6952 bind(L_copy_1_char);
6953 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
6954 testl(tmp5, short_mask); // check if Unicode or non-ASCII char
6955 jccb(Assembler::notZero, L_copy_1_char_exit);
6956 movb(Address(dst, len, Address::times_1, 0), tmp5);
6957 addptr(len, 1);
6958 jccb(Assembler::less, L_copy_1_char);
6959
6960 bind(L_copy_1_char_exit);
6961 addptr(result, len); // len is negative count of not processed elements
6962
6963 bind(L_done);
6964 }
6965
6966 #ifdef _LP64
6967 /**
6968 * Helper for multiply_to_len().
6969 */
6970 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
6971 addq(dest_lo, src1);
6972 adcq(dest_hi, 0);
6973 addq(dest_lo, src2);
6974 adcq(dest_hi, 0);
6975 }
6976
6977 /**
6978 * Multiply 64 bit by 64 bit first loop.
6979 */
6980 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
6981 Register y, Register y_idx, Register z,
6982 Register carry, Register product,
6983 Register idx, Register kdx) {
6984 //
6985 // jlong carry, x[], y[], z[];
6986 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
6987 // huge_128 product = y[idx] * x[xstart] + carry;
6988 // z[kdx] = (jlong)product;
6989 // carry = (jlong)(product >>> 64);
6990 // }
6991 // z[xstart] = carry;
6992 //
6993
6994 Label L_first_loop, L_first_loop_exit;
6995 Label L_one_x, L_one_y, L_multiply;
6996
6997 decrementl(xstart);
6998 jcc(Assembler::negative, L_one_x);
6999
7000 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7001 rorq(x_xstart, 32); // convert big-endian to little-endian
7002
7003 bind(L_first_loop);
7004 decrementl(idx);
7005 jcc(Assembler::negative, L_first_loop_exit);
7006 decrementl(idx);
7007 jcc(Assembler::negative, L_one_y);
7008 movq(y_idx, Address(y, idx, Address::times_4, 0));
7009 rorq(y_idx, 32); // convert big-endian to little-endian
7010 bind(L_multiply);
7011 movq(product, x_xstart);
7012 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
7013 addq(product, carry);
7014 adcq(rdx, 0);
7015 subl(kdx, 2);
7016 movl(Address(z, kdx, Address::times_4, 4), product);
7017 shrq(product, 32);
7018 movl(Address(z, kdx, Address::times_4, 0), product);
7019 movq(carry, rdx);
7020 jmp(L_first_loop);
7021
7022 bind(L_one_y);
7023 movl(y_idx, Address(y, 0));
7024 jmp(L_multiply);
7025
7026 bind(L_one_x);
7027 movl(x_xstart, Address(x, 0));
7028 jmp(L_first_loop);
7029
7030 bind(L_first_loop_exit);
7031 }
7032
7033 /**
7034 * Multiply 64 bit by 64 bit and add 128 bit.
7035 */
7036 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7037 Register yz_idx, Register idx,
7038 Register carry, Register product, int offset) {
7039 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7040 // z[kdx] = (jlong)product;
7041
7042 movq(yz_idx, Address(y, idx, Address::times_4, offset));
7043 rorq(yz_idx, 32); // convert big-endian to little-endian
7044 movq(product, x_xstart);
7045 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7046 movq(yz_idx, Address(z, idx, Address::times_4, offset));
7047 rorq(yz_idx, 32); // convert big-endian to little-endian
7048
7049 add2_with_carry(rdx, product, carry, yz_idx);
7050
7051 movl(Address(z, idx, Address::times_4, offset+4), product);
7052 shrq(product, 32);
7053 movl(Address(z, idx, Address::times_4, offset), product);
7054
7055 }
7056
7057 /**
7058 * Multiply 128 bit by 128 bit. Unrolled inner loop.
7059 */
7060 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7061 Register yz_idx, Register idx, Register jdx,
7062 Register carry, Register product,
7063 Register carry2) {
7064 // jlong carry, x[], y[], z[];
7065 // int kdx = ystart+1;
7066 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7067 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7068 // z[kdx+idx+1] = (jlong)product;
7069 // jlong carry2 = (jlong)(product >>> 64);
7070 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7071 // z[kdx+idx] = (jlong)product;
7072 // carry = (jlong)(product >>> 64);
7073 // }
7074 // idx += 2;
7075 // if (idx > 0) {
7076 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7077 // z[kdx+idx] = (jlong)product;
7078 // carry = (jlong)(product >>> 64);
7079 // }
7080 //
7081
7082 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7083
7084 movl(jdx, idx);
7085 andl(jdx, 0xFFFFFFFC);
7086 shrl(jdx, 2);
7087
7088 bind(L_third_loop);
7089 subl(jdx, 1);
7090 jcc(Assembler::negative, L_third_loop_exit);
7091 subl(idx, 4);
7092
7093 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7094 movq(carry2, rdx);
7095
7096 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7097 movq(carry, rdx);
7098 jmp(L_third_loop);
7099
7100 bind (L_third_loop_exit);
7101
7102 andl (idx, 0x3);
7103 jcc(Assembler::zero, L_post_third_loop_done);
7104
7105 Label L_check_1;
7106 subl(idx, 2);
7107 jcc(Assembler::negative, L_check_1);
7108
7109 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7110 movq(carry, rdx);
7111
7112 bind (L_check_1);
7113 addl (idx, 0x2);
7114 andl (idx, 0x1);
7115 subl(idx, 1);
7116 jcc(Assembler::negative, L_post_third_loop_done);
7117
7118 movl(yz_idx, Address(y, idx, Address::times_4, 0));
7119 movq(product, x_xstart);
7120 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7121 movl(yz_idx, Address(z, idx, Address::times_4, 0));
7122
7123 add2_with_carry(rdx, product, yz_idx, carry);
7124
7125 movl(Address(z, idx, Address::times_4, 0), product);
7126 shrq(product, 32);
7127
7128 shlq(rdx, 32);
7129 orq(product, rdx);
7130 movq(carry, product);
7131
7132 bind(L_post_third_loop_done);
7133 }
7134
7135 /**
7136 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7137 *
7138 */
7139 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7140 Register carry, Register carry2,
7141 Register idx, Register jdx,
7142 Register yz_idx1, Register yz_idx2,
7143 Register tmp, Register tmp3, Register tmp4) {
7144 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7145
7146 // jlong carry, x[], y[], z[];
7147 // int kdx = ystart+1;
7148 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7149 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7150 // jlong carry2 = (jlong)(tmp3 >>> 64);
7151 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
7152 // carry = (jlong)(tmp4 >>> 64);
7153 // z[kdx+idx+1] = (jlong)tmp3;
7154 // z[kdx+idx] = (jlong)tmp4;
7155 // }
7156 // idx += 2;
7157 // if (idx > 0) {
7158 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7159 // z[kdx+idx] = (jlong)yz_idx1;
7160 // carry = (jlong)(yz_idx1 >>> 64);
7161 // }
7162 //
7163
7164 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7165
7166 movl(jdx, idx);
7167 andl(jdx, 0xFFFFFFFC);
7168 shrl(jdx, 2);
7169
7170 bind(L_third_loop);
7171 subl(jdx, 1);
7172 jcc(Assembler::negative, L_third_loop_exit);
7173 subl(idx, 4);
7174
7175 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
7176 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7177 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
7178 rorxq(yz_idx2, yz_idx2, 32);
7179
7180 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7181 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
7182
7183 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
7184 rorxq(yz_idx1, yz_idx1, 32);
7185 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7186 rorxq(yz_idx2, yz_idx2, 32);
7187
7188 if (VM_Version::supports_adx()) {
7189 adcxq(tmp3, carry);
7190 adoxq(tmp3, yz_idx1);
7191
7192 adcxq(tmp4, tmp);
7193 adoxq(tmp4, yz_idx2);
7194
7195 movl(carry, 0); // does not affect flags
7196 adcxq(carry2, carry);
7197 adoxq(carry2, carry);
7198 } else {
7199 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7200 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7201 }
7202 movq(carry, carry2);
7203
7204 movl(Address(z, idx, Address::times_4, 12), tmp3);
7205 shrq(tmp3, 32);
7206 movl(Address(z, idx, Address::times_4, 8), tmp3);
7207
7208 movl(Address(z, idx, Address::times_4, 4), tmp4);
7209 shrq(tmp4, 32);
7210 movl(Address(z, idx, Address::times_4, 0), tmp4);
7211
7212 jmp(L_third_loop);
7213
7214 bind (L_third_loop_exit);
7215
7216 andl (idx, 0x3);
7217 jcc(Assembler::zero, L_post_third_loop_done);
7218
7219 Label L_check_1;
7220 subl(idx, 2);
7221 jcc(Assembler::negative, L_check_1);
7222
7223 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
7224 rorxq(yz_idx1, yz_idx1, 32);
7225 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7226 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7227 rorxq(yz_idx2, yz_idx2, 32);
7228
7229 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7230
7231 movl(Address(z, idx, Address::times_4, 4), tmp3);
7232 shrq(tmp3, 32);
7233 movl(Address(z, idx, Address::times_4, 0), tmp3);
7234 movq(carry, tmp4);
7235
7236 bind (L_check_1);
7237 addl (idx, 0x2);
7238 andl (idx, 0x1);
7239 subl(idx, 1);
7240 jcc(Assembler::negative, L_post_third_loop_done);
7241 movl(tmp4, Address(y, idx, Address::times_4, 0));
7242 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
7243 movl(tmp4, Address(z, idx, Address::times_4, 0));
7244
7245 add2_with_carry(carry2, tmp3, tmp4, carry);
7246
7247 movl(Address(z, idx, Address::times_4, 0), tmp3);
7248 shrq(tmp3, 32);
7249
7250 shlq(carry2, 32);
7251 orq(tmp3, carry2);
7252 movq(carry, tmp3);
7253
7254 bind(L_post_third_loop_done);
7255 }
7256
7257 /**
7258 * Code for BigInteger::multiplyToLen() intrinsic.
7259 *
7260 * rdi: x
7261 * rax: xlen
7262 * rsi: y
7263 * rcx: ylen
7264 * r8: z
7265 * r11: tmp0
7266 * r12: tmp1
7267 * r13: tmp2
7268 * r14: tmp3
7269 * r15: tmp4
7270 * rbx: tmp5
7271 *
7272 */
7273 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register tmp0,
7274 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7275 ShortBranchVerifier sbv(this);
7276 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7277
7278 push(tmp0);
7279 push(tmp1);
7280 push(tmp2);
7281 push(tmp3);
7282 push(tmp4);
7283 push(tmp5);
7284
7285 push(xlen);
7286
7287 const Register idx = tmp1;
7288 const Register kdx = tmp2;
7289 const Register xstart = tmp3;
7290
7291 const Register y_idx = tmp4;
7292 const Register carry = tmp5;
7293 const Register product = xlen;
7294 const Register x_xstart = tmp0;
7295
7296 // First Loop.
7297 //
7298 // final static long LONG_MASK = 0xffffffffL;
7299 // int xstart = xlen - 1;
7300 // int ystart = ylen - 1;
7301 // long carry = 0;
7302 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7303 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7304 // z[kdx] = (int)product;
7305 // carry = product >>> 32;
7306 // }
7307 // z[xstart] = (int)carry;
7308 //
7309
7310 movl(idx, ylen); // idx = ylen;
7311 lea(kdx, Address(xlen, ylen)); // kdx = xlen+ylen;
7312 xorq(carry, carry); // carry = 0;
7313
7314 Label L_done;
7315
7316 movl(xstart, xlen);
7317 decrementl(xstart);
7318 jcc(Assembler::negative, L_done);
7319
7320 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
7321
7322 Label L_second_loop;
7323 testl(kdx, kdx);
7324 jcc(Assembler::zero, L_second_loop);
7325
7326 Label L_carry;
7327 subl(kdx, 1);
7328 jcc(Assembler::zero, L_carry);
7329
7330 movl(Address(z, kdx, Address::times_4, 0), carry);
7331 shrq(carry, 32);
7332 subl(kdx, 1);
7333
7334 bind(L_carry);
7335 movl(Address(z, kdx, Address::times_4, 0), carry);
7336
7337 // Second and third (nested) loops.
7338 //
7339 // for (int i = xstart-1; i >= 0; i--) { // Second loop
7340 // carry = 0;
7341 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
7342 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
7343 // (z[k] & LONG_MASK) + carry;
7344 // z[k] = (int)product;
7345 // carry = product >>> 32;
7346 // }
7347 // z[i] = (int)carry;
7348 // }
7349 //
7350 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
7351
7352 const Register jdx = tmp1;
7353
7354 bind(L_second_loop);
7355 xorl(carry, carry); // carry = 0;
7356 movl(jdx, ylen); // j = ystart+1
7357
7358 subl(xstart, 1); // i = xstart-1;
7359 jcc(Assembler::negative, L_done);
7360
7361 push (z);
7362
7363 Label L_last_x;
7364 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
7365 subl(xstart, 1); // i = xstart-1;
7366 jcc(Assembler::negative, L_last_x);
7367
7368 if (UseBMI2Instructions) {
7369 movq(rdx, Address(x, xstart, Address::times_4, 0));
7370 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
7371 } else {
7372 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7373 rorq(x_xstart, 32); // convert big-endian to little-endian
7374 }
7375
7376 Label L_third_loop_prologue;
7377 bind(L_third_loop_prologue);
7378
7379 push (x);
7380 push (xstart);
7381 push (ylen);
7382
7383
7384 if (UseBMI2Instructions) {
7385 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
7386 } else { // !UseBMI2Instructions
7387 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
7388 }
7389
7390 pop(ylen);
7391 pop(xlen);
7392 pop(x);
7393 pop(z);
7394
7395 movl(tmp3, xlen);
7396 addl(tmp3, 1);
7397 movl(Address(z, tmp3, Address::times_4, 0), carry);
7398 subl(tmp3, 1);
7399 jccb(Assembler::negative, L_done);
7400
7401 shrq(carry, 32);
7402 movl(Address(z, tmp3, Address::times_4, 0), carry);
7403 jmp(L_second_loop);
7404
7405 // Next infrequent code is moved outside loops.
7406 bind(L_last_x);
7407 if (UseBMI2Instructions) {
7408 movl(rdx, Address(x, 0));
7409 } else {
7410 movl(x_xstart, Address(x, 0));
7411 }
7412 jmp(L_third_loop_prologue);
7413
7414 bind(L_done);
7415
7416 pop(xlen);
7417
7418 pop(tmp5);
7419 pop(tmp4);
7420 pop(tmp3);
7421 pop(tmp2);
7422 pop(tmp1);
7423 pop(tmp0);
7424 }
7425
7426 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
7427 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
7428 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
7429 Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
7430 Label VECTOR8_TAIL, VECTOR4_TAIL;
7431 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
7432 Label SAME_TILL_END, DONE;
7433 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
7434
7435 //scale is in rcx in both Win64 and Unix
7436 ShortBranchVerifier sbv(this);
7437
7438 shlq(length);
7439 xorq(result, result);
7440
7441 if ((AVX3Threshold == 0) && (UseAVX > 2) &&
7442 VM_Version::supports_avx512vlbw()) {
7443 Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
7444
7445 cmpq(length, 64);
7446 jcc(Assembler::less, VECTOR32_TAIL);
7447
7448 movq(tmp1, length);
7449 andq(tmp1, 0x3F); // tail count
7450 andq(length, ~(0x3F)); //vector count
7451
7452 bind(VECTOR64_LOOP);
7453 // AVX512 code to compare 64 byte vectors.
7454 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
7455 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
7456 kortestql(k7, k7);
7457 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
7458 addq(result, 64);
7459 subq(length, 64);
7460 jccb(Assembler::notZero, VECTOR64_LOOP);
7461
7462 //bind(VECTOR64_TAIL);
7463 testq(tmp1, tmp1);
7464 jcc(Assembler::zero, SAME_TILL_END);
7465
7466 //bind(VECTOR64_TAIL);
7467 // AVX512 code to compare up to 63 byte vectors.
7468 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
7469 shlxq(tmp2, tmp2, tmp1);
7470 notq(tmp2);
7471 kmovql(k3, tmp2);
7472
7473 evmovdqub(rymm0, k3, Address(obja, result), false, Assembler::AVX_512bit);
7474 evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
7475
7476 ktestql(k7, k3);
7477 jcc(Assembler::below, SAME_TILL_END); // not mismatch
7478
7479 bind(VECTOR64_NOT_EQUAL);
7480 kmovql(tmp1, k7);
7481 notq(tmp1);
7482 tzcntq(tmp1, tmp1);
7483 addq(result, tmp1);
7484 shrq(result);
7485 jmp(DONE);
7486 bind(VECTOR32_TAIL);
7487 }
7488
7489 cmpq(length, 8);
7490 jcc(Assembler::equal, VECTOR8_LOOP);
7491 jcc(Assembler::less, VECTOR4_TAIL);
7492
7493 if (UseAVX >= 2) {
7494 Label VECTOR16_TAIL, VECTOR32_LOOP;
7495
7496 cmpq(length, 16);
7497 jcc(Assembler::equal, VECTOR16_LOOP);
7498 jcc(Assembler::less, VECTOR8_LOOP);
7499
7500 cmpq(length, 32);
7501 jccb(Assembler::less, VECTOR16_TAIL);
7502
7503 subq(length, 32);
7504 bind(VECTOR32_LOOP);
7505 vmovdqu(rymm0, Address(obja, result));
7506 vmovdqu(rymm1, Address(objb, result));
7507 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
7508 vptest(rymm2, rymm2);
7509 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
7510 addq(result, 32);
7511 subq(length, 32);
7512 jcc(Assembler::greaterEqual, VECTOR32_LOOP);
7513 addq(length, 32);
7514 jcc(Assembler::equal, SAME_TILL_END);
7515 //falling through if less than 32 bytes left //close the branch here.
7516
7517 bind(VECTOR16_TAIL);
7518 cmpq(length, 16);
7519 jccb(Assembler::less, VECTOR8_TAIL);
7520 bind(VECTOR16_LOOP);
7521 movdqu(rymm0, Address(obja, result));
7522 movdqu(rymm1, Address(objb, result));
7523 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
7524 ptest(rymm2, rymm2);
7525 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7526 addq(result, 16);
7527 subq(length, 16);
7528 jcc(Assembler::equal, SAME_TILL_END);
7529 //falling through if less than 16 bytes left
7530 } else {//regular intrinsics
7531
7532 cmpq(length, 16);
7533 jccb(Assembler::less, VECTOR8_TAIL);
7534
7535 subq(length, 16);
7536 bind(VECTOR16_LOOP);
7537 movdqu(rymm0, Address(obja, result));
7538 movdqu(rymm1, Address(objb, result));
7539 pxor(rymm0, rymm1);
7540 ptest(rymm0, rymm0);
7541 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7542 addq(result, 16);
7543 subq(length, 16);
7544 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
7545 addq(length, 16);
7546 jcc(Assembler::equal, SAME_TILL_END);
7547 //falling through if less than 16 bytes left
7548 }
7549
7550 bind(VECTOR8_TAIL);
7551 cmpq(length, 8);
7552 jccb(Assembler::less, VECTOR4_TAIL);
7553 bind(VECTOR8_LOOP);
7554 movq(tmp1, Address(obja, result));
7555 movq(tmp2, Address(objb, result));
7556 xorq(tmp1, tmp2);
7557 testq(tmp1, tmp1);
7558 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
7559 addq(result, 8);
7560 subq(length, 8);
7561 jcc(Assembler::equal, SAME_TILL_END);
7562 //falling through if less than 8 bytes left
7563
7564 bind(VECTOR4_TAIL);
7565 cmpq(length, 4);
7566 jccb(Assembler::less, BYTES_TAIL);
7567 bind(VECTOR4_LOOP);
7568 movl(tmp1, Address(obja, result));
7569 xorl(tmp1, Address(objb, result));
7570 testl(tmp1, tmp1);
7571 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
7572 addq(result, 4);
7573 subq(length, 4);
7574 jcc(Assembler::equal, SAME_TILL_END);
7575 //falling through if less than 4 bytes left
7576
7577 bind(BYTES_TAIL);
7578 bind(BYTES_LOOP);
7579 load_unsigned_byte(tmp1, Address(obja, result));
7580 load_unsigned_byte(tmp2, Address(objb, result));
7581 xorl(tmp1, tmp2);
7582 testl(tmp1, tmp1);
7583 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7584 decq(length);
7585 jcc(Assembler::zero, SAME_TILL_END);
7586 incq(result);
7587 load_unsigned_byte(tmp1, Address(obja, result));
7588 load_unsigned_byte(tmp2, Address(objb, result));
7589 xorl(tmp1, tmp2);
7590 testl(tmp1, tmp1);
7591 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7592 decq(length);
7593 jcc(Assembler::zero, SAME_TILL_END);
7594 incq(result);
7595 load_unsigned_byte(tmp1, Address(obja, result));
7596 load_unsigned_byte(tmp2, Address(objb, result));
7597 xorl(tmp1, tmp2);
7598 testl(tmp1, tmp1);
7599 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7600 jmp(SAME_TILL_END);
7601
7602 if (UseAVX >= 2) {
7603 bind(VECTOR32_NOT_EQUAL);
7604 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
7605 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
7606 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
7607 vpmovmskb(tmp1, rymm0);
7608 bsfq(tmp1, tmp1);
7609 addq(result, tmp1);
7610 shrq(result);
7611 jmp(DONE);
7612 }
7613
7614 bind(VECTOR16_NOT_EQUAL);
7615 if (UseAVX >= 2) {
7616 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
7617 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
7618 pxor(rymm0, rymm2);
7619 } else {
7620 pcmpeqb(rymm2, rymm2);
7621 pxor(rymm0, rymm1);
7622 pcmpeqb(rymm0, rymm1);
7623 pxor(rymm0, rymm2);
7624 }
7625 pmovmskb(tmp1, rymm0);
7626 bsfq(tmp1, tmp1);
7627 addq(result, tmp1);
7628 shrq(result);
7629 jmpb(DONE);
7630
7631 bind(VECTOR8_NOT_EQUAL);
7632 bind(VECTOR4_NOT_EQUAL);
7633 bsfq(tmp1, tmp1);
7634 shrq(tmp1, 3);
7635 addq(result, tmp1);
7636 bind(BYTES_NOT_EQUAL);
7637 shrq(result);
7638 jmpb(DONE);
7639
7640 bind(SAME_TILL_END);
7641 mov64(result, -1);
7642
7643 bind(DONE);
7644 }
7645
7646 //Helper functions for square_to_len()
7647
7648 /**
7649 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
7650 * Preserves x and z and modifies rest of the registers.
7651 */
7652 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7653 // Perform square and right shift by 1
7654 // Handle odd xlen case first, then for even xlen do the following
7655 // jlong carry = 0;
7656 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
7657 // huge_128 product = x[j:j+1] * x[j:j+1];
7658 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
7659 // z[i+2:i+3] = (jlong)(product >>> 1);
7660 // carry = (jlong)product;
7661 // }
7662
7663 xorq(tmp5, tmp5); // carry
7664 xorq(rdxReg, rdxReg);
7665 xorl(tmp1, tmp1); // index for x
7666 xorl(tmp4, tmp4); // index for z
7667
7668 Label L_first_loop, L_first_loop_exit;
7669
7670 testl(xlen, 1);
7671 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
7672
7673 // Square and right shift by 1 the odd element using 32 bit multiply
7674 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
7675 imulq(raxReg, raxReg);
7676 shrq(raxReg, 1);
7677 adcq(tmp5, 0);
7678 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
7679 incrementl(tmp1);
7680 addl(tmp4, 2);
7681
7682 // Square and right shift by 1 the rest using 64 bit multiply
7683 bind(L_first_loop);
7684 cmpptr(tmp1, xlen);
7685 jccb(Assembler::equal, L_first_loop_exit);
7686
7687 // Square
7688 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
7689 rorq(raxReg, 32); // convert big-endian to little-endian
7690 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
7691
7692 // Right shift by 1 and save carry
7693 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
7694 rcrq(rdxReg, 1);
7695 rcrq(raxReg, 1);
7696 adcq(tmp5, 0);
7697
7698 // Store result in z
7699 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
7700 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
7701
7702 // Update indices for x and z
7703 addl(tmp1, 2);
7704 addl(tmp4, 4);
7705 jmp(L_first_loop);
7706
7707 bind(L_first_loop_exit);
7708 }
7709
7710
7711 /**
7712 * Perform the following multiply add operation using BMI2 instructions
7713 * carry:sum = sum + op1*op2 + carry
7714 * op2 should be in rdx
7715 * op2 is preserved, all other registers are modified
7716 */
7717 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
7718 // assert op2 is rdx
7719 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
7720 addq(sum, carry);
7721 adcq(tmp2, 0);
7722 addq(sum, op1);
7723 adcq(tmp2, 0);
7724 movq(carry, tmp2);
7725 }
7726
7727 /**
7728 * Perform the following multiply add operation:
7729 * carry:sum = sum + op1*op2 + carry
7730 * Preserves op1, op2 and modifies rest of registers
7731 */
7732 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
7733 // rdx:rax = op1 * op2
7734 movq(raxReg, op2);
7735 mulq(op1);
7736
7737 // rdx:rax = sum + carry + rdx:rax
7738 addq(sum, carry);
7739 adcq(rdxReg, 0);
7740 addq(sum, raxReg);
7741 adcq(rdxReg, 0);
7742
7743 // carry:sum = rdx:sum
7744 movq(carry, rdxReg);
7745 }
7746
7747 /**
7748 * Add 64 bit long carry into z[] with carry propagation.
7749 * Preserves z and carry register values and modifies rest of registers.
7750 *
7751 */
7752 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
7753 Label L_fourth_loop, L_fourth_loop_exit;
7754
7755 movl(tmp1, 1);
7756 subl(zlen, 2);
7757 addq(Address(z, zlen, Address::times_4, 0), carry);
7758
7759 bind(L_fourth_loop);
7760 jccb(Assembler::carryClear, L_fourth_loop_exit);
7761 subl(zlen, 2);
7762 jccb(Assembler::negative, L_fourth_loop_exit);
7763 addq(Address(z, zlen, Address::times_4, 0), tmp1);
7764 jmp(L_fourth_loop);
7765 bind(L_fourth_loop_exit);
7766 }
7767
7768 /**
7769 * Shift z[] left by 1 bit.
7770 * Preserves x, len, z and zlen registers and modifies rest of the registers.
7771 *
7772 */
7773 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
7774
7775 Label L_fifth_loop, L_fifth_loop_exit;
7776
7777 // Fifth loop
7778 // Perform primitiveLeftShift(z, zlen, 1)
7779
7780 const Register prev_carry = tmp1;
7781 const Register new_carry = tmp4;
7782 const Register value = tmp2;
7783 const Register zidx = tmp3;
7784
7785 // int zidx, carry;
7786 // long value;
7787 // carry = 0;
7788 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
7789 // (carry:value) = (z[i] << 1) | carry ;
7790 // z[i] = value;
7791 // }
7792
7793 movl(zidx, zlen);
7794 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
7795
7796 bind(L_fifth_loop);
7797 decl(zidx); // Use decl to preserve carry flag
7798 decl(zidx);
7799 jccb(Assembler::negative, L_fifth_loop_exit);
7800
7801 if (UseBMI2Instructions) {
7802 movq(value, Address(z, zidx, Address::times_4, 0));
7803 rclq(value, 1);
7804 rorxq(value, value, 32);
7805 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7806 }
7807 else {
7808 // clear new_carry
7809 xorl(new_carry, new_carry);
7810
7811 // Shift z[i] by 1, or in previous carry and save new carry
7812 movq(value, Address(z, zidx, Address::times_4, 0));
7813 shlq(value, 1);
7814 adcl(new_carry, 0);
7815
7816 orq(value, prev_carry);
7817 rorq(value, 0x20);
7818 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7819
7820 // Set previous carry = new carry
7821 movl(prev_carry, new_carry);
7822 }
7823 jmp(L_fifth_loop);
7824
7825 bind(L_fifth_loop_exit);
7826 }
7827
7828
7829 /**
7830 * Code for BigInteger::squareToLen() intrinsic
7831 *
7832 * rdi: x
7833 * rsi: len
7834 * r8: z
7835 * rcx: zlen
7836 * r12: tmp1
7837 * r13: tmp2
7838 * r14: tmp3
7839 * r15: tmp4
7840 * rbx: tmp5
7841 *
7842 */
7843 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7844
7845 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
7846 push(tmp1);
7847 push(tmp2);
7848 push(tmp3);
7849 push(tmp4);
7850 push(tmp5);
7851
7852 // First loop
7853 // Store the squares, right shifted one bit (i.e., divided by 2).
7854 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
7855
7856 // Add in off-diagonal sums.
7857 //
7858 // Second, third (nested) and fourth loops.
7859 // zlen +=2;
7860 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
7861 // carry = 0;
7862 // long op2 = x[xidx:xidx+1];
7863 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
7864 // k -= 2;
7865 // long op1 = x[j:j+1];
7866 // long sum = z[k:k+1];
7867 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
7868 // z[k:k+1] = sum;
7869 // }
7870 // add_one_64(z, k, carry, tmp_regs);
7871 // }
7872
7873 const Register carry = tmp5;
7874 const Register sum = tmp3;
7875 const Register op1 = tmp4;
7876 Register op2 = tmp2;
7877
7878 push(zlen);
7879 push(len);
7880 addl(zlen,2);
7881 bind(L_second_loop);
7882 xorq(carry, carry);
7883 subl(zlen, 4);
7884 subl(len, 2);
7885 push(zlen);
7886 push(len);
7887 cmpl(len, 0);
7888 jccb(Assembler::lessEqual, L_second_loop_exit);
7889
7890 // Multiply an array by one 64 bit long.
7891 if (UseBMI2Instructions) {
7892 op2 = rdxReg;
7893 movq(op2, Address(x, len, Address::times_4, 0));
7894 rorxq(op2, op2, 32);
7895 }
7896 else {
7897 movq(op2, Address(x, len, Address::times_4, 0));
7898 rorq(op2, 32);
7899 }
7900
7901 bind(L_third_loop);
7902 decrementl(len);
7903 jccb(Assembler::negative, L_third_loop_exit);
7904 decrementl(len);
7905 jccb(Assembler::negative, L_last_x);
7906
7907 movq(op1, Address(x, len, Address::times_4, 0));
7908 rorq(op1, 32);
7909
7910 bind(L_multiply);
7911 subl(zlen, 2);
7912 movq(sum, Address(z, zlen, Address::times_4, 0));
7913
7914 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
7915 if (UseBMI2Instructions) {
7916 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
7917 }
7918 else {
7919 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7920 }
7921
7922 movq(Address(z, zlen, Address::times_4, 0), sum);
7923
7924 jmp(L_third_loop);
7925 bind(L_third_loop_exit);
7926
7927 // Fourth loop
7928 // Add 64 bit long carry into z with carry propagation.
7929 // Uses offsetted zlen.
7930 add_one_64(z, zlen, carry, tmp1);
7931
7932 pop(len);
7933 pop(zlen);
7934 jmp(L_second_loop);
7935
7936 // Next infrequent code is moved outside loops.
7937 bind(L_last_x);
7938 movl(op1, Address(x, 0));
7939 jmp(L_multiply);
7940
7941 bind(L_second_loop_exit);
7942 pop(len);
7943 pop(zlen);
7944 pop(len);
7945 pop(zlen);
7946
7947 // Fifth loop
7948 // Shift z left 1 bit.
7949 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
7950
7951 // z[zlen-1] |= x[len-1] & 1;
7952 movl(tmp3, Address(x, len, Address::times_4, -4));
7953 andl(tmp3, 1);
7954 orl(Address(z, zlen, Address::times_4, -4), tmp3);
7955
7956 pop(tmp5);
7957 pop(tmp4);
7958 pop(tmp3);
7959 pop(tmp2);
7960 pop(tmp1);
7961 }
7962
7963 /**
7964 * Helper function for mul_add()
7965 * Multiply the in[] by int k and add to out[] starting at offset offs using
7966 * 128 bit by 32 bit multiply and return the carry in tmp5.
7967 * Only quad int aligned length of in[] is operated on in this function.
7968 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
7969 * This function preserves out, in and k registers.
7970 * len and offset point to the appropriate index in "in" & "out" correspondingly
7971 * tmp5 has the carry.
7972 * other registers are temporary and are modified.
7973 *
7974 */
7975 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
7976 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
7977 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7978
7979 Label L_first_loop, L_first_loop_exit;
7980
7981 movl(tmp1, len);
7982 shrl(tmp1, 2);
7983
7984 bind(L_first_loop);
7985 subl(tmp1, 1);
7986 jccb(Assembler::negative, L_first_loop_exit);
7987
7988 subl(len, 4);
7989 subl(offset, 4);
7990
7991 Register op2 = tmp2;
7992 const Register sum = tmp3;
7993 const Register op1 = tmp4;
7994 const Register carry = tmp5;
7995
7996 if (UseBMI2Instructions) {
7997 op2 = rdxReg;
7998 }
7999
8000 movq(op1, Address(in, len, Address::times_4, 8));
8001 rorq(op1, 32);
8002 movq(sum, Address(out, offset, Address::times_4, 8));
8003 rorq(sum, 32);
8004 if (UseBMI2Instructions) {
8005 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8006 }
8007 else {
8008 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8009 }
8010 // Store back in big endian from little endian
8011 rorq(sum, 0x20);
8012 movq(Address(out, offset, Address::times_4, 8), sum);
8013
8014 movq(op1, Address(in, len, Address::times_4, 0));
8015 rorq(op1, 32);
8016 movq(sum, Address(out, offset, Address::times_4, 0));
8017 rorq(sum, 32);
8018 if (UseBMI2Instructions) {
8019 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8020 }
8021 else {
8022 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8023 }
8024 // Store back in big endian from little endian
8025 rorq(sum, 0x20);
8026 movq(Address(out, offset, Address::times_4, 0), sum);
8027
8028 jmp(L_first_loop);
8029 bind(L_first_loop_exit);
8030 }
8031
8032 /**
8033 * Code for BigInteger::mulAdd() intrinsic
8034 *
8035 * rdi: out
8036 * rsi: in
8037 * r11: offs (out.length - offset)
8038 * rcx: len
8039 * r8: k
8040 * r12: tmp1
8041 * r13: tmp2
8042 * r14: tmp3
8043 * r15: tmp4
8044 * rbx: tmp5
8045 * Multiply the in[] by word k and add to out[], return the carry in rax
8046 */
8047 void MacroAssembler::mul_add(Register out, Register in, Register offs,
8048 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
8049 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8050
8051 Label L_carry, L_last_in, L_done;
8052
8053 // carry = 0;
8054 // for (int j=len-1; j >= 0; j--) {
8055 // long product = (in[j] & LONG_MASK) * kLong +
8056 // (out[offs] & LONG_MASK) + carry;
8057 // out[offs--] = (int)product;
8058 // carry = product >>> 32;
8059 // }
8060 //
8061 push(tmp1);
8062 push(tmp2);
8063 push(tmp3);
8064 push(tmp4);
8065 push(tmp5);
8066
8067 Register op2 = tmp2;
8068 const Register sum = tmp3;
8069 const Register op1 = tmp4;
8070 const Register carry = tmp5;
8071
8072 if (UseBMI2Instructions) {
8073 op2 = rdxReg;
8074 movl(op2, k);
8075 }
8076 else {
8077 movl(op2, k);
8078 }
8079
8080 xorq(carry, carry);
8081
8082 //First loop
8083
8084 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
8085 //The carry is in tmp5
8086 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
8087
8088 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
8089 decrementl(len);
8090 jccb(Assembler::negative, L_carry);
8091 decrementl(len);
8092 jccb(Assembler::negative, L_last_in);
8093
8094 movq(op1, Address(in, len, Address::times_4, 0));
8095 rorq(op1, 32);
8096
8097 subl(offs, 2);
8098 movq(sum, Address(out, offs, Address::times_4, 0));
8099 rorq(sum, 32);
8100
8101 if (UseBMI2Instructions) {
8102 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8103 }
8104 else {
8105 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8106 }
8107
8108 // Store back in big endian from little endian
8109 rorq(sum, 0x20);
8110 movq(Address(out, offs, Address::times_4, 0), sum);
8111
8112 testl(len, len);
8113 jccb(Assembler::zero, L_carry);
8114
8115 //Multiply the last in[] entry, if any
8116 bind(L_last_in);
8117 movl(op1, Address(in, 0));
8118 movl(sum, Address(out, offs, Address::times_4, -4));
8119
8120 movl(raxReg, k);
8121 mull(op1); //tmp4 * eax -> edx:eax
8122 addl(sum, carry);
8123 adcl(rdxReg, 0);
8124 addl(sum, raxReg);
8125 adcl(rdxReg, 0);
8126 movl(carry, rdxReg);
8127
8128 movl(Address(out, offs, Address::times_4, -4), sum);
8129
8130 bind(L_carry);
8131 //return tmp5/carry as carry in rax
8132 movl(rax, carry);
8133
8134 bind(L_done);
8135 pop(tmp5);
8136 pop(tmp4);
8137 pop(tmp3);
8138 pop(tmp2);
8139 pop(tmp1);
8140 }
8141 #endif
8142
8143 /**
8144 * Emits code to update CRC-32 with a byte value according to constants in table
8145 *
8146 * @param [in,out]crc Register containing the crc.
8147 * @param [in]val Register containing the byte to fold into the CRC.
8148 * @param [in]table Register containing the table of crc constants.
8149 *
8150 * uint32_t crc;
8151 * val = crc_table[(val ^ crc) & 0xFF];
8152 * crc = val ^ (crc >> 8);
8153 *
8154 */
8155 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
8156 xorl(val, crc);
8157 andl(val, 0xFF);
8158 shrl(crc, 8); // unsigned shift
8159 xorl(crc, Address(table, val, Address::times_4, 0));
8160 }
8161
8162 /**
8163 * Fold 128-bit data chunk
8164 */
8165 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8166 if (UseAVX > 0) {
8167 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
8168 vpclmulldq(xcrc, xK, xcrc); // [63:0]
8169 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
8170 pxor(xcrc, xtmp);
8171 } else {
8172 movdqa(xtmp, xcrc);
8173 pclmulhdq(xtmp, xK); // [123:64]
8174 pclmulldq(xcrc, xK); // [63:0]
8175 pxor(xcrc, xtmp);
8176 movdqu(xtmp, Address(buf, offset));
8177 pxor(xcrc, xtmp);
8178 }
8179 }
8180
8181 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
8182 if (UseAVX > 0) {
8183 vpclmulhdq(xtmp, xK, xcrc);
8184 vpclmulldq(xcrc, xK, xcrc);
8185 pxor(xcrc, xbuf);
8186 pxor(xcrc, xtmp);
8187 } else {
8188 movdqa(xtmp, xcrc);
8189 pclmulhdq(xtmp, xK);
8190 pclmulldq(xcrc, xK);
8191 pxor(xcrc, xbuf);
8192 pxor(xcrc, xtmp);
8193 }
8194 }
8195
8196 /**
8197 * 8-bit folds to compute 32-bit CRC
8198 *
8199 * uint64_t xcrc;
8200 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
8201 */
8202 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
8203 movdl(tmp, xcrc);
8204 andl(tmp, 0xFF);
8205 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
8206 psrldq(xcrc, 1); // unsigned shift one byte
8207 pxor(xcrc, xtmp);
8208 }
8209
8210 /**
8211 * uint32_t crc;
8212 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
8213 */
8214 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
8215 movl(tmp, crc);
8216 andl(tmp, 0xFF);
8217 shrl(crc, 8);
8218 xorl(crc, Address(table, tmp, Address::times_4, 0));
8219 }
8220
8221 /**
8222 * @param crc register containing existing CRC (32-bit)
8223 * @param buf register pointing to input byte buffer (byte*)
8224 * @param len register containing number of bytes
8225 * @param table register that will contain address of CRC table
8226 * @param tmp scratch register
8227 */
8228 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
8229 assert_different_registers(crc, buf, len, table, tmp, rax);
8230
8231 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8232 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8233
8234 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8235 // context for the registers used, where all instructions below are using 128-bit mode
8236 // On EVEX without VL and BW, these instructions will all be AVX.
8237 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
8238 notl(crc); // ~crc
8239 cmpl(len, 16);
8240 jcc(Assembler::less, L_tail);
8241
8242 // Align buffer to 16 bytes
8243 movl(tmp, buf);
8244 andl(tmp, 0xF);
8245 jccb(Assembler::zero, L_aligned);
8246 subl(tmp, 16);
8247 addl(len, tmp);
8248
8249 align(4);
8250 BIND(L_align_loop);
8251 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8252 update_byte_crc32(crc, rax, table);
8253 increment(buf);
8254 incrementl(tmp);
8255 jccb(Assembler::less, L_align_loop);
8256
8257 BIND(L_aligned);
8258 movl(tmp, len); // save
8259 shrl(len, 4);
8260 jcc(Assembler::zero, L_tail_restore);
8261
8262 // Fold crc into first bytes of vector
8263 movdqa(xmm1, Address(buf, 0));
8264 movdl(rax, xmm1);
8265 xorl(crc, rax);
8266 if (VM_Version::supports_sse4_1()) {
8267 pinsrd(xmm1, crc, 0);
8268 } else {
8269 pinsrw(xmm1, crc, 0);
8270 shrl(crc, 16);
8271 pinsrw(xmm1, crc, 1);
8272 }
8273 addptr(buf, 16);
8274 subl(len, 4); // len > 0
8275 jcc(Assembler::less, L_fold_tail);
8276
8277 movdqa(xmm2, Address(buf, 0));
8278 movdqa(xmm3, Address(buf, 16));
8279 movdqa(xmm4, Address(buf, 32));
8280 addptr(buf, 48);
8281 subl(len, 3);
8282 jcc(Assembler::lessEqual, L_fold_512b);
8283
8284 // Fold total 512 bits of polynomial on each iteration,
8285 // 128 bits per each of 4 parallel streams.
8286 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32), rscratch1);
8287
8288 align32();
8289 BIND(L_fold_512b_loop);
8290 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8291 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
8292 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
8293 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
8294 addptr(buf, 64);
8295 subl(len, 4);
8296 jcc(Assembler::greater, L_fold_512b_loop);
8297
8298 // Fold 512 bits to 128 bits.
8299 BIND(L_fold_512b);
8300 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8301 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
8302 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
8303 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
8304
8305 // Fold the rest of 128 bits data chunks
8306 BIND(L_fold_tail);
8307 addl(len, 3);
8308 jccb(Assembler::lessEqual, L_fold_128b);
8309 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8310
8311 BIND(L_fold_tail_loop);
8312 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8313 addptr(buf, 16);
8314 decrementl(len);
8315 jccb(Assembler::greater, L_fold_tail_loop);
8316
8317 // Fold 128 bits in xmm1 down into 32 bits in crc register.
8318 BIND(L_fold_128b);
8319 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()), rscratch1);
8320 if (UseAVX > 0) {
8321 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
8322 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
8323 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
8324 } else {
8325 movdqa(xmm2, xmm0);
8326 pclmulqdq(xmm2, xmm1, 0x1);
8327 movdqa(xmm3, xmm0);
8328 pand(xmm3, xmm2);
8329 pclmulqdq(xmm0, xmm3, 0x1);
8330 }
8331 psrldq(xmm1, 8);
8332 psrldq(xmm2, 4);
8333 pxor(xmm0, xmm1);
8334 pxor(xmm0, xmm2);
8335
8336 // 8 8-bit folds to compute 32-bit CRC.
8337 for (int j = 0; j < 4; j++) {
8338 fold_8bit_crc32(xmm0, table, xmm1, rax);
8339 }
8340 movdl(crc, xmm0); // mov 32 bits to general register
8341 for (int j = 0; j < 4; j++) {
8342 fold_8bit_crc32(crc, table, rax);
8343 }
8344
8345 BIND(L_tail_restore);
8346 movl(len, tmp); // restore
8347 BIND(L_tail);
8348 andl(len, 0xf);
8349 jccb(Assembler::zero, L_exit);
8350
8351 // Fold the rest of bytes
8352 align(4);
8353 BIND(L_tail_loop);
8354 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8355 update_byte_crc32(crc, rax, table);
8356 increment(buf);
8357 decrementl(len);
8358 jccb(Assembler::greater, L_tail_loop);
8359
8360 BIND(L_exit);
8361 notl(crc); // ~c
8362 }
8363
8364 #ifdef _LP64
8365 // Helper function for AVX 512 CRC32
8366 // Fold 512-bit data chunks
8367 void MacroAssembler::fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf,
8368 Register pos, int offset) {
8369 evmovdquq(xmm3, Address(buf, pos, Address::times_1, offset), Assembler::AVX_512bit);
8370 evpclmulqdq(xtmp, xcrc, xK, 0x10, Assembler::AVX_512bit); // [123:64]
8371 evpclmulqdq(xmm2, xcrc, xK, 0x01, Assembler::AVX_512bit); // [63:0]
8372 evpxorq(xcrc, xtmp, xmm2, Assembler::AVX_512bit /* vector_len */);
8373 evpxorq(xcrc, xcrc, xmm3, Assembler::AVX_512bit /* vector_len */);
8374 }
8375
8376 // Helper function for AVX 512 CRC32
8377 // Compute CRC32 for < 256B buffers
8378 void MacroAssembler::kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register table, Register pos,
8379 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
8380 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup) {
8381
8382 Label L_less_than_32, L_exact_16_left, L_less_than_16_left;
8383 Label L_less_than_8_left, L_less_than_4_left, L_less_than_2_left, L_zero_left;
8384 Label L_only_less_than_4, L_only_less_than_3, L_only_less_than_2;
8385
8386 // check if there is enough buffer to be able to fold 16B at a time
8387 cmpl(len, 32);
8388 jcc(Assembler::less, L_less_than_32);
8389
8390 // if there is, load the constants
8391 movdqu(xmm10, Address(table, 1 * 16)); //rk1 and rk2 in xmm10
8392 movdl(xmm0, crc); // get the initial crc value
8393 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8394 pxor(xmm7, xmm0);
8395
8396 // update the buffer pointer
8397 addl(pos, 16);
8398 //update the counter.subtract 32 instead of 16 to save one instruction from the loop
8399 subl(len, 32);
8400 jmp(L_16B_reduction_loop);
8401
8402 bind(L_less_than_32);
8403 //mov initial crc to the return value. this is necessary for zero - length buffers.
8404 movl(rax, crc);
8405 testl(len, len);
8406 jcc(Assembler::equal, L_cleanup);
8407
8408 movdl(xmm0, crc); //get the initial crc value
8409
8410 cmpl(len, 16);
8411 jcc(Assembler::equal, L_exact_16_left);
8412 jcc(Assembler::less, L_less_than_16_left);
8413
8414 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8415 pxor(xmm7, xmm0); //xor the initial crc value
8416 addl(pos, 16);
8417 subl(len, 16);
8418 movdqu(xmm10, Address(table, 1 * 16)); // rk1 and rk2 in xmm10
8419 jmp(L_get_last_two_xmms);
8420
8421 bind(L_less_than_16_left);
8422 //use stack space to load data less than 16 bytes, zero - out the 16B in memory first.
8423 pxor(xmm1, xmm1);
8424 movptr(tmp1, rsp);
8425 movdqu(Address(tmp1, 0 * 16), xmm1);
8426
8427 cmpl(len, 4);
8428 jcc(Assembler::less, L_only_less_than_4);
8429
8430 //backup the counter value
8431 movl(tmp2, len);
8432 cmpl(len, 8);
8433 jcc(Assembler::less, L_less_than_8_left);
8434
8435 //load 8 Bytes
8436 movq(rax, Address(buf, pos, Address::times_1, 0 * 16));
8437 movq(Address(tmp1, 0 * 16), rax);
8438 addptr(tmp1, 8);
8439 subl(len, 8);
8440 addl(pos, 8);
8441
8442 bind(L_less_than_8_left);
8443 cmpl(len, 4);
8444 jcc(Assembler::less, L_less_than_4_left);
8445
8446 //load 4 Bytes
8447 movl(rax, Address(buf, pos, Address::times_1, 0));
8448 movl(Address(tmp1, 0 * 16), rax);
8449 addptr(tmp1, 4);
8450 subl(len, 4);
8451 addl(pos, 4);
8452
8453 bind(L_less_than_4_left);
8454 cmpl(len, 2);
8455 jcc(Assembler::less, L_less_than_2_left);
8456
8457 // load 2 Bytes
8458 movw(rax, Address(buf, pos, Address::times_1, 0));
8459 movl(Address(tmp1, 0 * 16), rax);
8460 addptr(tmp1, 2);
8461 subl(len, 2);
8462 addl(pos, 2);
8463
8464 bind(L_less_than_2_left);
8465 cmpl(len, 1);
8466 jcc(Assembler::less, L_zero_left);
8467
8468 // load 1 Byte
8469 movb(rax, Address(buf, pos, Address::times_1, 0));
8470 movb(Address(tmp1, 0 * 16), rax);
8471
8472 bind(L_zero_left);
8473 movdqu(xmm7, Address(rsp, 0));
8474 pxor(xmm7, xmm0); //xor the initial crc value
8475
8476 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8477 movdqu(xmm0, Address(rax, tmp2));
8478 pshufb(xmm7, xmm0);
8479 jmp(L_128_done);
8480
8481 bind(L_exact_16_left);
8482 movdqu(xmm7, Address(buf, pos, Address::times_1, 0));
8483 pxor(xmm7, xmm0); //xor the initial crc value
8484 jmp(L_128_done);
8485
8486 bind(L_only_less_than_4);
8487 cmpl(len, 3);
8488 jcc(Assembler::less, L_only_less_than_3);
8489
8490 // load 3 Bytes
8491 movb(rax, Address(buf, pos, Address::times_1, 0));
8492 movb(Address(tmp1, 0), rax);
8493
8494 movb(rax, Address(buf, pos, Address::times_1, 1));
8495 movb(Address(tmp1, 1), rax);
8496
8497 movb(rax, Address(buf, pos, Address::times_1, 2));
8498 movb(Address(tmp1, 2), rax);
8499
8500 movdqu(xmm7, Address(rsp, 0));
8501 pxor(xmm7, xmm0); //xor the initial crc value
8502
8503 pslldq(xmm7, 0x5);
8504 jmp(L_barrett);
8505 bind(L_only_less_than_3);
8506 cmpl(len, 2);
8507 jcc(Assembler::less, L_only_less_than_2);
8508
8509 // load 2 Bytes
8510 movb(rax, Address(buf, pos, Address::times_1, 0));
8511 movb(Address(tmp1, 0), rax);
8512
8513 movb(rax, Address(buf, pos, Address::times_1, 1));
8514 movb(Address(tmp1, 1), rax);
8515
8516 movdqu(xmm7, Address(rsp, 0));
8517 pxor(xmm7, xmm0); //xor the initial crc value
8518
8519 pslldq(xmm7, 0x6);
8520 jmp(L_barrett);
8521
8522 bind(L_only_less_than_2);
8523 //load 1 Byte
8524 movb(rax, Address(buf, pos, Address::times_1, 0));
8525 movb(Address(tmp1, 0), rax);
8526
8527 movdqu(xmm7, Address(rsp, 0));
8528 pxor(xmm7, xmm0); //xor the initial crc value
8529
8530 pslldq(xmm7, 0x7);
8531 }
8532
8533 /**
8534 * Compute CRC32 using AVX512 instructions
8535 * param crc register containing existing CRC (32-bit)
8536 * param buf register pointing to input byte buffer (byte*)
8537 * param len register containing number of bytes
8538 * param table address of crc or crc32c table
8539 * param tmp1 scratch register
8540 * param tmp2 scratch register
8541 * return rax result register
8542 *
8543 * This routine is identical for crc32c with the exception of the precomputed constant
8544 * table which will be passed as the table argument. The calculation steps are
8545 * the same for both variants.
8546 */
8547 void MacroAssembler::kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2) {
8548 assert_different_registers(crc, buf, len, table, tmp1, tmp2, rax, r12);
8549
8550 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8551 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8552 Label L_less_than_256, L_fold_128_B_loop, L_fold_256_B_loop;
8553 Label L_fold_128_B_register, L_final_reduction_for_128, L_16B_reduction_loop;
8554 Label L_128_done, L_get_last_two_xmms, L_barrett, L_cleanup;
8555
8556 const Register pos = r12;
8557 push(r12);
8558 subptr(rsp, 16 * 2 + 8);
8559
8560 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8561 // context for the registers used, where all instructions below are using 128-bit mode
8562 // On EVEX without VL and BW, these instructions will all be AVX.
8563 movl(pos, 0);
8564
8565 // check if smaller than 256B
8566 cmpl(len, 256);
8567 jcc(Assembler::less, L_less_than_256);
8568
8569 // load the initial crc value
8570 movdl(xmm10, crc);
8571
8572 // receive the initial 64B data, xor the initial crc value
8573 evmovdquq(xmm0, Address(buf, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
8574 evmovdquq(xmm4, Address(buf, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
8575 evpxorq(xmm0, xmm0, xmm10, Assembler::AVX_512bit);
8576 evbroadcasti32x4(xmm10, Address(table, 2 * 16), Assembler::AVX_512bit); //zmm10 has rk3 and rk4
8577
8578 subl(len, 256);
8579 cmpl(len, 256);
8580 jcc(Assembler::less, L_fold_128_B_loop);
8581
8582 evmovdquq(xmm7, Address(buf, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
8583 evmovdquq(xmm8, Address(buf, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
8584 evbroadcasti32x4(xmm16, Address(table, 0 * 16), Assembler::AVX_512bit); //zmm16 has rk-1 and rk-2
8585 subl(len, 256);
8586
8587 bind(L_fold_256_B_loop);
8588 addl(pos, 256);
8589 fold512bit_crc32_avx512(xmm0, xmm16, xmm1, buf, pos, 0 * 64);
8590 fold512bit_crc32_avx512(xmm4, xmm16, xmm1, buf, pos, 1 * 64);
8591 fold512bit_crc32_avx512(xmm7, xmm16, xmm1, buf, pos, 2 * 64);
8592 fold512bit_crc32_avx512(xmm8, xmm16, xmm1, buf, pos, 3 * 64);
8593
8594 subl(len, 256);
8595 jcc(Assembler::greaterEqual, L_fold_256_B_loop);
8596
8597 // Fold 256 into 128
8598 addl(pos, 256);
8599 evpclmulqdq(xmm1, xmm0, xmm10, 0x01, Assembler::AVX_512bit);
8600 evpclmulqdq(xmm2, xmm0, xmm10, 0x10, Assembler::AVX_512bit);
8601 vpternlogq(xmm7, 0x96, xmm1, xmm2, Assembler::AVX_512bit); // xor ABC
8602
8603 evpclmulqdq(xmm5, xmm4, xmm10, 0x01, Assembler::AVX_512bit);
8604 evpclmulqdq(xmm6, xmm4, xmm10, 0x10, Assembler::AVX_512bit);
8605 vpternlogq(xmm8, 0x96, xmm5, xmm6, Assembler::AVX_512bit); // xor ABC
8606
8607 evmovdquq(xmm0, xmm7, Assembler::AVX_512bit);
8608 evmovdquq(xmm4, xmm8, Assembler::AVX_512bit);
8609
8610 addl(len, 128);
8611 jmp(L_fold_128_B_register);
8612
8613 // at this section of the code, there is 128 * x + y(0 <= y<128) bytes of buffer.The fold_128_B_loop
8614 // loop will fold 128B at a time until we have 128 + y Bytes of buffer
8615
8616 // fold 128B at a time.This section of the code folds 8 xmm registers in parallel
8617 bind(L_fold_128_B_loop);
8618 addl(pos, 128);
8619 fold512bit_crc32_avx512(xmm0, xmm10, xmm1, buf, pos, 0 * 64);
8620 fold512bit_crc32_avx512(xmm4, xmm10, xmm1, buf, pos, 1 * 64);
8621
8622 subl(len, 128);
8623 jcc(Assembler::greaterEqual, L_fold_128_B_loop);
8624
8625 addl(pos, 128);
8626
8627 // at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128
8628 // the 128B of folded data is in 8 of the xmm registers : xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
8629 bind(L_fold_128_B_register);
8630 evmovdquq(xmm16, Address(table, 5 * 16), Assembler::AVX_512bit); // multiply by rk9-rk16
8631 evmovdquq(xmm11, Address(table, 9 * 16), Assembler::AVX_512bit); // multiply by rk17-rk20, rk1,rk2, 0,0
8632 evpclmulqdq(xmm1, xmm0, xmm16, 0x01, Assembler::AVX_512bit);
8633 evpclmulqdq(xmm2, xmm0, xmm16, 0x10, Assembler::AVX_512bit);
8634 // save last that has no multiplicand
8635 vextracti64x2(xmm7, xmm4, 3);
8636
8637 evpclmulqdq(xmm5, xmm4, xmm11, 0x01, Assembler::AVX_512bit);
8638 evpclmulqdq(xmm6, xmm4, xmm11, 0x10, Assembler::AVX_512bit);
8639 // Needed later in reduction loop
8640 movdqu(xmm10, Address(table, 1 * 16));
8641 vpternlogq(xmm1, 0x96, xmm2, xmm5, Assembler::AVX_512bit); // xor ABC
8642 vpternlogq(xmm1, 0x96, xmm6, xmm7, Assembler::AVX_512bit); // xor ABC
8643
8644 // Swap 1,0,3,2 - 01 00 11 10
8645 evshufi64x2(xmm8, xmm1, xmm1, 0x4e, Assembler::AVX_512bit);
8646 evpxorq(xmm8, xmm8, xmm1, Assembler::AVX_256bit);
8647 vextracti128(xmm5, xmm8, 1);
8648 evpxorq(xmm7, xmm5, xmm8, Assembler::AVX_128bit);
8649
8650 // instead of 128, we add 128 - 16 to the loop counter to save 1 instruction from the loop
8651 // instead of a cmp instruction, we use the negative flag with the jl instruction
8652 addl(len, 128 - 16);
8653 jcc(Assembler::less, L_final_reduction_for_128);
8654
8655 bind(L_16B_reduction_loop);
8656 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8657 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8658 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8659 movdqu(xmm0, Address(buf, pos, Address::times_1, 0 * 16));
8660 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8661 addl(pos, 16);
8662 subl(len, 16);
8663 jcc(Assembler::greaterEqual, L_16B_reduction_loop);
8664
8665 bind(L_final_reduction_for_128);
8666 addl(len, 16);
8667 jcc(Assembler::equal, L_128_done);
8668
8669 bind(L_get_last_two_xmms);
8670 movdqu(xmm2, xmm7);
8671 addl(pos, len);
8672 movdqu(xmm1, Address(buf, pos, Address::times_1, -16));
8673 subl(pos, len);
8674
8675 // get rid of the extra data that was loaded before
8676 // load the shift constant
8677 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8678 movdqu(xmm0, Address(rax, len));
8679 addl(rax, len);
8680
8681 vpshufb(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8682 //Change mask to 512
8683 vpxor(xmm0, xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 2 * 16), Assembler::AVX_128bit, tmp2);
8684 vpshufb(xmm2, xmm2, xmm0, Assembler::AVX_128bit);
8685
8686 blendvpb(xmm2, xmm2, xmm1, xmm0, Assembler::AVX_128bit);
8687 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8688 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8689 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8690 vpxor(xmm7, xmm7, xmm2, Assembler::AVX_128bit);
8691
8692 bind(L_128_done);
8693 // compute crc of a 128-bit value
8694 movdqu(xmm10, Address(table, 3 * 16));
8695 movdqu(xmm0, xmm7);
8696
8697 // 64b fold
8698 vpclmulqdq(xmm7, xmm7, xmm10, 0x0);
8699 vpsrldq(xmm0, xmm0, 0x8, Assembler::AVX_128bit);
8700 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8701
8702 // 32b fold
8703 movdqu(xmm0, xmm7);
8704 vpslldq(xmm7, xmm7, 0x4, Assembler::AVX_128bit);
8705 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8706 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8707 jmp(L_barrett);
8708
8709 bind(L_less_than_256);
8710 kernel_crc32_avx512_256B(crc, buf, len, table, pos, tmp1, tmp2, L_barrett, L_16B_reduction_loop, L_get_last_two_xmms, L_128_done, L_cleanup);
8711
8712 //barrett reduction
8713 bind(L_barrett);
8714 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 1 * 16), Assembler::AVX_128bit, tmp2);
8715 movdqu(xmm1, xmm7);
8716 movdqu(xmm2, xmm7);
8717 movdqu(xmm10, Address(table, 4 * 16));
8718
8719 pclmulqdq(xmm7, xmm10, 0x0);
8720 pxor(xmm7, xmm2);
8721 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr()), Assembler::AVX_128bit, tmp2);
8722 movdqu(xmm2, xmm7);
8723 pclmulqdq(xmm7, xmm10, 0x10);
8724 pxor(xmm7, xmm2);
8725 pxor(xmm7, xmm1);
8726 pextrd(crc, xmm7, 2);
8727
8728 bind(L_cleanup);
8729 addptr(rsp, 16 * 2 + 8);
8730 pop(r12);
8731 }
8732
8733 // S. Gueron / Information Processing Letters 112 (2012) 184
8734 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
8735 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
8736 // Output: the 64-bit carry-less product of B * CONST
8737 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
8738 Register tmp1, Register tmp2, Register tmp3) {
8739 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8740 if (n > 0) {
8741 addq(tmp3, n * 256 * 8);
8742 }
8743 // Q1 = TABLEExt[n][B & 0xFF];
8744 movl(tmp1, in);
8745 andl(tmp1, 0x000000FF);
8746 shll(tmp1, 3);
8747 addq(tmp1, tmp3);
8748 movq(tmp1, Address(tmp1, 0));
8749
8750 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
8751 movl(tmp2, in);
8752 shrl(tmp2, 8);
8753 andl(tmp2, 0x000000FF);
8754 shll(tmp2, 3);
8755 addq(tmp2, tmp3);
8756 movq(tmp2, Address(tmp2, 0));
8757
8758 shlq(tmp2, 8);
8759 xorq(tmp1, tmp2);
8760
8761 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
8762 movl(tmp2, in);
8763 shrl(tmp2, 16);
8764 andl(tmp2, 0x000000FF);
8765 shll(tmp2, 3);
8766 addq(tmp2, tmp3);
8767 movq(tmp2, Address(tmp2, 0));
8768
8769 shlq(tmp2, 16);
8770 xorq(tmp1, tmp2);
8771
8772 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
8773 shrl(in, 24);
8774 andl(in, 0x000000FF);
8775 shll(in, 3);
8776 addq(in, tmp3);
8777 movq(in, Address(in, 0));
8778
8779 shlq(in, 24);
8780 xorq(in, tmp1);
8781 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
8782 }
8783
8784 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
8785 Register in_out,
8786 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
8787 XMMRegister w_xtmp2,
8788 Register tmp1,
8789 Register n_tmp2, Register n_tmp3) {
8790 if (is_pclmulqdq_supported) {
8791 movdl(w_xtmp1, in_out); // modified blindly
8792
8793 movl(tmp1, const_or_pre_comp_const_index);
8794 movdl(w_xtmp2, tmp1);
8795 pclmulqdq(w_xtmp1, w_xtmp2, 0);
8796
8797 movdq(in_out, w_xtmp1);
8798 } else {
8799 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
8800 }
8801 }
8802
8803 // Recombination Alternative 2: No bit-reflections
8804 // T1 = (CRC_A * U1) << 1
8805 // T2 = (CRC_B * U2) << 1
8806 // C1 = T1 >> 32
8807 // C2 = T2 >> 32
8808 // T1 = T1 & 0xFFFFFFFF
8809 // T2 = T2 & 0xFFFFFFFF
8810 // T1 = CRC32(0, T1)
8811 // T2 = CRC32(0, T2)
8812 // C1 = C1 ^ T1
8813 // C2 = C2 ^ T2
8814 // CRC = C1 ^ C2 ^ CRC_C
8815 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
8816 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8817 Register tmp1, Register tmp2,
8818 Register n_tmp3) {
8819 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8820 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8821 shlq(in_out, 1);
8822 movl(tmp1, in_out);
8823 shrq(in_out, 32);
8824 xorl(tmp2, tmp2);
8825 crc32(tmp2, tmp1, 4);
8826 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
8827 shlq(in1, 1);
8828 movl(tmp1, in1);
8829 shrq(in1, 32);
8830 xorl(tmp2, tmp2);
8831 crc32(tmp2, tmp1, 4);
8832 xorl(in1, tmp2);
8833 xorl(in_out, in1);
8834 xorl(in_out, in2);
8835 }
8836
8837 // Set N to predefined value
8838 // Subtract from a length of a buffer
8839 // execute in a loop:
8840 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
8841 // for i = 1 to N do
8842 // CRC_A = CRC32(CRC_A, A[i])
8843 // CRC_B = CRC32(CRC_B, B[i])
8844 // CRC_C = CRC32(CRC_C, C[i])
8845 // end for
8846 // Recombine
8847 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
8848 Register in_out1, Register in_out2, Register in_out3,
8849 Register tmp1, Register tmp2, Register tmp3,
8850 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8851 Register tmp4, Register tmp5,
8852 Register n_tmp6) {
8853 Label L_processPartitions;
8854 Label L_processPartition;
8855 Label L_exit;
8856
8857 bind(L_processPartitions);
8858 cmpl(in_out1, 3 * size);
8859 jcc(Assembler::less, L_exit);
8860 xorl(tmp1, tmp1);
8861 xorl(tmp2, tmp2);
8862 movq(tmp3, in_out2);
8863 addq(tmp3, size);
8864
8865 bind(L_processPartition);
8866 crc32(in_out3, Address(in_out2, 0), 8);
8867 crc32(tmp1, Address(in_out2, size), 8);
8868 crc32(tmp2, Address(in_out2, size * 2), 8);
8869 addq(in_out2, 8);
8870 cmpq(in_out2, tmp3);
8871 jcc(Assembler::less, L_processPartition);
8872 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
8873 w_xtmp1, w_xtmp2, w_xtmp3,
8874 tmp4, tmp5,
8875 n_tmp6);
8876 addq(in_out2, 2 * size);
8877 subl(in_out1, 3 * size);
8878 jmp(L_processPartitions);
8879
8880 bind(L_exit);
8881 }
8882 #else
8883 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
8884 Register tmp1, Register tmp2, Register tmp3,
8885 XMMRegister xtmp1, XMMRegister xtmp2) {
8886 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8887 if (n > 0) {
8888 addl(tmp3, n * 256 * 8);
8889 }
8890 // Q1 = TABLEExt[n][B & 0xFF];
8891 movl(tmp1, in_out);
8892 andl(tmp1, 0x000000FF);
8893 shll(tmp1, 3);
8894 addl(tmp1, tmp3);
8895 movq(xtmp1, Address(tmp1, 0));
8896
8897 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
8898 movl(tmp2, in_out);
8899 shrl(tmp2, 8);
8900 andl(tmp2, 0x000000FF);
8901 shll(tmp2, 3);
8902 addl(tmp2, tmp3);
8903 movq(xtmp2, Address(tmp2, 0));
8904
8905 psllq(xtmp2, 8);
8906 pxor(xtmp1, xtmp2);
8907
8908 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
8909 movl(tmp2, in_out);
8910 shrl(tmp2, 16);
8911 andl(tmp2, 0x000000FF);
8912 shll(tmp2, 3);
8913 addl(tmp2, tmp3);
8914 movq(xtmp2, Address(tmp2, 0));
8915
8916 psllq(xtmp2, 16);
8917 pxor(xtmp1, xtmp2);
8918
8919 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
8920 shrl(in_out, 24);
8921 andl(in_out, 0x000000FF);
8922 shll(in_out, 3);
8923 addl(in_out, tmp3);
8924 movq(xtmp2, Address(in_out, 0));
8925
8926 psllq(xtmp2, 24);
8927 pxor(xtmp1, xtmp2); // Result in CXMM
8928 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
8929 }
8930
8931 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
8932 Register in_out,
8933 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
8934 XMMRegister w_xtmp2,
8935 Register tmp1,
8936 Register n_tmp2, Register n_tmp3) {
8937 if (is_pclmulqdq_supported) {
8938 movdl(w_xtmp1, in_out);
8939
8940 movl(tmp1, const_or_pre_comp_const_index);
8941 movdl(w_xtmp2, tmp1);
8942 pclmulqdq(w_xtmp1, w_xtmp2, 0);
8943 // Keep result in XMM since GPR is 32 bit in length
8944 } else {
8945 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
8946 }
8947 }
8948
8949 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
8950 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8951 Register tmp1, Register tmp2,
8952 Register n_tmp3) {
8953 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8954 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8955
8956 psllq(w_xtmp1, 1);
8957 movdl(tmp1, w_xtmp1);
8958 psrlq(w_xtmp1, 32);
8959 movdl(in_out, w_xtmp1);
8960
8961 xorl(tmp2, tmp2);
8962 crc32(tmp2, tmp1, 4);
8963 xorl(in_out, tmp2);
8964
8965 psllq(w_xtmp2, 1);
8966 movdl(tmp1, w_xtmp2);
8967 psrlq(w_xtmp2, 32);
8968 movdl(in1, w_xtmp2);
8969
8970 xorl(tmp2, tmp2);
8971 crc32(tmp2, tmp1, 4);
8972 xorl(in1, tmp2);
8973 xorl(in_out, in1);
8974 xorl(in_out, in2);
8975 }
8976
8977 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
8978 Register in_out1, Register in_out2, Register in_out3,
8979 Register tmp1, Register tmp2, Register tmp3,
8980 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8981 Register tmp4, Register tmp5,
8982 Register n_tmp6) {
8983 Label L_processPartitions;
8984 Label L_processPartition;
8985 Label L_exit;
8986
8987 bind(L_processPartitions);
8988 cmpl(in_out1, 3 * size);
8989 jcc(Assembler::less, L_exit);
8990 xorl(tmp1, tmp1);
8991 xorl(tmp2, tmp2);
8992 movl(tmp3, in_out2);
8993 addl(tmp3, size);
8994
8995 bind(L_processPartition);
8996 crc32(in_out3, Address(in_out2, 0), 4);
8997 crc32(tmp1, Address(in_out2, size), 4);
8998 crc32(tmp2, Address(in_out2, size*2), 4);
8999 crc32(in_out3, Address(in_out2, 0+4), 4);
9000 crc32(tmp1, Address(in_out2, size+4), 4);
9001 crc32(tmp2, Address(in_out2, size*2+4), 4);
9002 addl(in_out2, 8);
9003 cmpl(in_out2, tmp3);
9004 jcc(Assembler::less, L_processPartition);
9005
9006 push(tmp3);
9007 push(in_out1);
9008 push(in_out2);
9009 tmp4 = tmp3;
9010 tmp5 = in_out1;
9011 n_tmp6 = in_out2;
9012
9013 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9014 w_xtmp1, w_xtmp2, w_xtmp3,
9015 tmp4, tmp5,
9016 n_tmp6);
9017
9018 pop(in_out2);
9019 pop(in_out1);
9020 pop(tmp3);
9021
9022 addl(in_out2, 2 * size);
9023 subl(in_out1, 3 * size);
9024 jmp(L_processPartitions);
9025
9026 bind(L_exit);
9027 }
9028 #endif //LP64
9029
9030 #ifdef _LP64
9031 // Algorithm 2: Pipelined usage of the CRC32 instruction.
9032 // Input: A buffer I of L bytes.
9033 // Output: the CRC32C value of the buffer.
9034 // Notations:
9035 // Write L = 24N + r, with N = floor (L/24).
9036 // r = L mod 24 (0 <= r < 24).
9037 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
9038 // N quadwords, and R consists of r bytes.
9039 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
9040 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
9041 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
9042 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
9043 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9044 Register tmp1, Register tmp2, Register tmp3,
9045 Register tmp4, Register tmp5, Register tmp6,
9046 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9047 bool is_pclmulqdq_supported) {
9048 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9049 Label L_wordByWord;
9050 Label L_byteByByteProlog;
9051 Label L_byteByByte;
9052 Label L_exit;
9053
9054 if (is_pclmulqdq_supported ) {
9055 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
9056 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
9057
9058 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
9059 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
9060
9061 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
9062 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
9063 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
9064 } else {
9065 const_or_pre_comp_const_index[0] = 1;
9066 const_or_pre_comp_const_index[1] = 0;
9067
9068 const_or_pre_comp_const_index[2] = 3;
9069 const_or_pre_comp_const_index[3] = 2;
9070
9071 const_or_pre_comp_const_index[4] = 5;
9072 const_or_pre_comp_const_index[5] = 4;
9073 }
9074 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9075 in2, in1, in_out,
9076 tmp1, tmp2, tmp3,
9077 w_xtmp1, w_xtmp2, w_xtmp3,
9078 tmp4, tmp5,
9079 tmp6);
9080 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9081 in2, in1, in_out,
9082 tmp1, tmp2, tmp3,
9083 w_xtmp1, w_xtmp2, w_xtmp3,
9084 tmp4, tmp5,
9085 tmp6);
9086 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9087 in2, in1, in_out,
9088 tmp1, tmp2, tmp3,
9089 w_xtmp1, w_xtmp2, w_xtmp3,
9090 tmp4, tmp5,
9091 tmp6);
9092 movl(tmp1, in2);
9093 andl(tmp1, 0x00000007);
9094 negl(tmp1);
9095 addl(tmp1, in2);
9096 addq(tmp1, in1);
9097
9098 cmpq(in1, tmp1);
9099 jccb(Assembler::greaterEqual, L_byteByByteProlog);
9100 align(16);
9101 BIND(L_wordByWord);
9102 crc32(in_out, Address(in1, 0), 8);
9103 addq(in1, 8);
9104 cmpq(in1, tmp1);
9105 jcc(Assembler::less, L_wordByWord);
9106
9107 BIND(L_byteByByteProlog);
9108 andl(in2, 0x00000007);
9109 movl(tmp2, 1);
9110
9111 cmpl(tmp2, in2);
9112 jccb(Assembler::greater, L_exit);
9113 BIND(L_byteByByte);
9114 crc32(in_out, Address(in1, 0), 1);
9115 incq(in1);
9116 incl(tmp2);
9117 cmpl(tmp2, in2);
9118 jcc(Assembler::lessEqual, L_byteByByte);
9119
9120 BIND(L_exit);
9121 }
9122 #else
9123 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9124 Register tmp1, Register tmp2, Register tmp3,
9125 Register tmp4, Register tmp5, Register tmp6,
9126 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9127 bool is_pclmulqdq_supported) {
9128 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9129 Label L_wordByWord;
9130 Label L_byteByByteProlog;
9131 Label L_byteByByte;
9132 Label L_exit;
9133
9134 if (is_pclmulqdq_supported) {
9135 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
9136 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
9137
9138 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
9139 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
9140
9141 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
9142 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
9143 } else {
9144 const_or_pre_comp_const_index[0] = 1;
9145 const_or_pre_comp_const_index[1] = 0;
9146
9147 const_or_pre_comp_const_index[2] = 3;
9148 const_or_pre_comp_const_index[3] = 2;
9149
9150 const_or_pre_comp_const_index[4] = 5;
9151 const_or_pre_comp_const_index[5] = 4;
9152 }
9153 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9154 in2, in1, in_out,
9155 tmp1, tmp2, tmp3,
9156 w_xtmp1, w_xtmp2, w_xtmp3,
9157 tmp4, tmp5,
9158 tmp6);
9159 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9160 in2, in1, in_out,
9161 tmp1, tmp2, tmp3,
9162 w_xtmp1, w_xtmp2, w_xtmp3,
9163 tmp4, tmp5,
9164 tmp6);
9165 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9166 in2, in1, in_out,
9167 tmp1, tmp2, tmp3,
9168 w_xtmp1, w_xtmp2, w_xtmp3,
9169 tmp4, tmp5,
9170 tmp6);
9171 movl(tmp1, in2);
9172 andl(tmp1, 0x00000007);
9173 negl(tmp1);
9174 addl(tmp1, in2);
9175 addl(tmp1, in1);
9176
9177 BIND(L_wordByWord);
9178 cmpl(in1, tmp1);
9179 jcc(Assembler::greaterEqual, L_byteByByteProlog);
9180 crc32(in_out, Address(in1,0), 4);
9181 addl(in1, 4);
9182 jmp(L_wordByWord);
9183
9184 BIND(L_byteByByteProlog);
9185 andl(in2, 0x00000007);
9186 movl(tmp2, 1);
9187
9188 BIND(L_byteByByte);
9189 cmpl(tmp2, in2);
9190 jccb(Assembler::greater, L_exit);
9191 movb(tmp1, Address(in1, 0));
9192 crc32(in_out, tmp1, 1);
9193 incl(in1);
9194 incl(tmp2);
9195 jmp(L_byteByByte);
9196
9197 BIND(L_exit);
9198 }
9199 #endif // LP64
9200 #undef BIND
9201 #undef BLOCK_COMMENT
9202
9203 // Compress char[] array to byte[].
9204 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
9205 // Return the array length if every element in array can be encoded,
9206 // otherwise, the index of first non-latin1 (> 0xff) character.
9207 // @IntrinsicCandidate
9208 // public static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
9209 // for (int i = 0; i < len; i++) {
9210 // char c = src[srcOff];
9211 // if (c > 0xff) {
9212 // return i; // return index of non-latin1 char
9213 // }
9214 // dst[dstOff] = (byte)c;
9215 // srcOff++;
9216 // dstOff++;
9217 // }
9218 // return len;
9219 // }
9220 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
9221 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
9222 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
9223 Register tmp5, Register result, KRegister mask1, KRegister mask2) {
9224 Label copy_chars_loop, done, reset_sp, copy_tail;
9225
9226 // rsi: src
9227 // rdi: dst
9228 // rdx: len
9229 // rcx: tmp5
9230 // rax: result
9231
9232 // rsi holds start addr of source char[] to be compressed
9233 // rdi holds start addr of destination byte[]
9234 // rdx holds length
9235
9236 assert(len != result, "");
9237
9238 // save length for return
9239 movl(result, len);
9240
9241 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
9242 VM_Version::supports_avx512vlbw() &&
9243 VM_Version::supports_bmi2()) {
9244
9245 Label copy_32_loop, copy_loop_tail, below_threshold, reset_for_copy_tail;
9246
9247 // alignment
9248 Label post_alignment;
9249
9250 // if length of the string is less than 32, handle it the old fashioned way
9251 testl(len, -32);
9252 jcc(Assembler::zero, below_threshold);
9253
9254 // First check whether a character is compressible ( <= 0xFF).
9255 // Create mask to test for Unicode chars inside zmm vector
9256 movl(tmp5, 0x00FF);
9257 evpbroadcastw(tmp2Reg, tmp5, Assembler::AVX_512bit);
9258
9259 testl(len, -64);
9260 jccb(Assembler::zero, post_alignment);
9261
9262 movl(tmp5, dst);
9263 andl(tmp5, (32 - 1));
9264 negl(tmp5);
9265 andl(tmp5, (32 - 1));
9266
9267 // bail out when there is nothing to be done
9268 testl(tmp5, 0xFFFFFFFF);
9269 jccb(Assembler::zero, post_alignment);
9270
9271 // ~(~0 << len), where len is the # of remaining elements to process
9272 movl(len, 0xFFFFFFFF);
9273 shlxl(len, len, tmp5);
9274 notl(len);
9275 kmovdl(mask2, len);
9276 movl(len, result);
9277
9278 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9279 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9280 ktestd(mask1, mask2);
9281 jcc(Assembler::carryClear, copy_tail);
9282
9283 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9284
9285 addptr(src, tmp5);
9286 addptr(src, tmp5);
9287 addptr(dst, tmp5);
9288 subl(len, tmp5);
9289
9290 bind(post_alignment);
9291 // end of alignment
9292
9293 movl(tmp5, len);
9294 andl(tmp5, (32 - 1)); // tail count (in chars)
9295 andl(len, ~(32 - 1)); // vector count (in chars)
9296 jccb(Assembler::zero, copy_loop_tail);
9297
9298 lea(src, Address(src, len, Address::times_2));
9299 lea(dst, Address(dst, len, Address::times_1));
9300 negptr(len);
9301
9302 bind(copy_32_loop);
9303 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
9304 evpcmpuw(mask1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9305 kortestdl(mask1, mask1);
9306 jccb(Assembler::carryClear, reset_for_copy_tail);
9307
9308 // All elements in current processed chunk are valid candidates for
9309 // compression. Write a truncated byte elements to the memory.
9310 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
9311 addptr(len, 32);
9312 jccb(Assembler::notZero, copy_32_loop);
9313
9314 bind(copy_loop_tail);
9315 // bail out when there is nothing to be done
9316 testl(tmp5, 0xFFFFFFFF);
9317 jcc(Assembler::zero, done);
9318
9319 movl(len, tmp5);
9320
9321 // ~(~0 << len), where len is the # of remaining elements to process
9322 movl(tmp5, 0xFFFFFFFF);
9323 shlxl(tmp5, tmp5, len);
9324 notl(tmp5);
9325
9326 kmovdl(mask2, tmp5);
9327
9328 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9329 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9330 ktestd(mask1, mask2);
9331 jcc(Assembler::carryClear, copy_tail);
9332
9333 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9334 jmp(done);
9335
9336 bind(reset_for_copy_tail);
9337 lea(src, Address(src, tmp5, Address::times_2));
9338 lea(dst, Address(dst, tmp5, Address::times_1));
9339 subptr(len, tmp5);
9340 jmp(copy_chars_loop);
9341
9342 bind(below_threshold);
9343 }
9344
9345 if (UseSSE42Intrinsics) {
9346 Label copy_32_loop, copy_16, copy_tail_sse, reset_for_copy_tail;
9347
9348 // vectored compression
9349 testl(len, 0xfffffff8);
9350 jcc(Assembler::zero, copy_tail);
9351
9352 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
9353 movdl(tmp1Reg, tmp5);
9354 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
9355
9356 andl(len, 0xfffffff0);
9357 jccb(Assembler::zero, copy_16);
9358
9359 // compress 16 chars per iter
9360 pxor(tmp4Reg, tmp4Reg);
9361
9362 lea(src, Address(src, len, Address::times_2));
9363 lea(dst, Address(dst, len, Address::times_1));
9364 negptr(len);
9365
9366 bind(copy_32_loop);
9367 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
9368 por(tmp4Reg, tmp2Reg);
9369 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
9370 por(tmp4Reg, tmp3Reg);
9371 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
9372 jccb(Assembler::notZero, reset_for_copy_tail);
9373 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
9374 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
9375 addptr(len, 16);
9376 jccb(Assembler::notZero, copy_32_loop);
9377
9378 // compress next vector of 8 chars (if any)
9379 bind(copy_16);
9380 // len = 0
9381 testl(result, 0x00000008); // check if there's a block of 8 chars to compress
9382 jccb(Assembler::zero, copy_tail_sse);
9383
9384 pxor(tmp3Reg, tmp3Reg);
9385
9386 movdqu(tmp2Reg, Address(src, 0));
9387 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
9388 jccb(Assembler::notZero, reset_for_copy_tail);
9389 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
9390 movq(Address(dst, 0), tmp2Reg);
9391 addptr(src, 16);
9392 addptr(dst, 8);
9393 jmpb(copy_tail_sse);
9394
9395 bind(reset_for_copy_tail);
9396 movl(tmp5, result);
9397 andl(tmp5, 0x0000000f);
9398 lea(src, Address(src, tmp5, Address::times_2));
9399 lea(dst, Address(dst, tmp5, Address::times_1));
9400 subptr(len, tmp5);
9401 jmpb(copy_chars_loop);
9402
9403 bind(copy_tail_sse);
9404 movl(len, result);
9405 andl(len, 0x00000007); // tail count (in chars)
9406 }
9407 // compress 1 char per iter
9408 bind(copy_tail);
9409 testl(len, len);
9410 jccb(Assembler::zero, done);
9411 lea(src, Address(src, len, Address::times_2));
9412 lea(dst, Address(dst, len, Address::times_1));
9413 negptr(len);
9414
9415 bind(copy_chars_loop);
9416 load_unsigned_short(tmp5, Address(src, len, Address::times_2));
9417 testl(tmp5, 0xff00); // check if Unicode char
9418 jccb(Assembler::notZero, reset_sp);
9419 movb(Address(dst, len, Address::times_1), tmp5); // ASCII char; compress to 1 byte
9420 increment(len);
9421 jccb(Assembler::notZero, copy_chars_loop);
9422
9423 // add len then return (len will be zero if compress succeeded, otherwise negative)
9424 bind(reset_sp);
9425 addl(result, len);
9426
9427 bind(done);
9428 }
9429
9430 // Inflate byte[] array to char[].
9431 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
9432 // @IntrinsicCandidate
9433 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
9434 // for (int i = 0; i < len; i++) {
9435 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
9436 // }
9437 // }
9438 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
9439 XMMRegister tmp1, Register tmp2, KRegister mask) {
9440 Label copy_chars_loop, done, below_threshold, avx3_threshold;
9441 // rsi: src
9442 // rdi: dst
9443 // rdx: len
9444 // rcx: tmp2
9445
9446 // rsi holds start addr of source byte[] to be inflated
9447 // rdi holds start addr of destination char[]
9448 // rdx holds length
9449 assert_different_registers(src, dst, len, tmp2);
9450 movl(tmp2, len);
9451 if ((UseAVX > 2) && // AVX512
9452 VM_Version::supports_avx512vlbw() &&
9453 VM_Version::supports_bmi2()) {
9454
9455 Label copy_32_loop, copy_tail;
9456 Register tmp3_aliased = len;
9457
9458 // if length of the string is less than 16, handle it in an old fashioned way
9459 testl(len, -16);
9460 jcc(Assembler::zero, below_threshold);
9461
9462 testl(len, -1 * AVX3Threshold);
9463 jcc(Assembler::zero, avx3_threshold);
9464
9465 // In order to use only one arithmetic operation for the main loop we use
9466 // this pre-calculation
9467 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
9468 andl(len, -32); // vector count
9469 jccb(Assembler::zero, copy_tail);
9470
9471 lea(src, Address(src, len, Address::times_1));
9472 lea(dst, Address(dst, len, Address::times_2));
9473 negptr(len);
9474
9475
9476 // inflate 32 chars per iter
9477 bind(copy_32_loop);
9478 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
9479 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
9480 addptr(len, 32);
9481 jcc(Assembler::notZero, copy_32_loop);
9482
9483 bind(copy_tail);
9484 // bail out when there is nothing to be done
9485 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
9486 jcc(Assembler::zero, done);
9487
9488 // ~(~0 << length), where length is the # of remaining elements to process
9489 movl(tmp3_aliased, -1);
9490 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
9491 notl(tmp3_aliased);
9492 kmovdl(mask, tmp3_aliased);
9493 evpmovzxbw(tmp1, mask, Address(src, 0), Assembler::AVX_512bit);
9494 evmovdquw(Address(dst, 0), mask, tmp1, /*merge*/ true, Assembler::AVX_512bit);
9495
9496 jmp(done);
9497 bind(avx3_threshold);
9498 }
9499 if (UseSSE42Intrinsics) {
9500 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
9501
9502 if (UseAVX > 1) {
9503 andl(tmp2, (16 - 1));
9504 andl(len, -16);
9505 jccb(Assembler::zero, copy_new_tail);
9506 } else {
9507 andl(tmp2, 0x00000007); // tail count (in chars)
9508 andl(len, 0xfffffff8); // vector count (in chars)
9509 jccb(Assembler::zero, copy_tail);
9510 }
9511
9512 // vectored inflation
9513 lea(src, Address(src, len, Address::times_1));
9514 lea(dst, Address(dst, len, Address::times_2));
9515 negptr(len);
9516
9517 if (UseAVX > 1) {
9518 bind(copy_16_loop);
9519 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
9520 vmovdqu(Address(dst, len, Address::times_2), tmp1);
9521 addptr(len, 16);
9522 jcc(Assembler::notZero, copy_16_loop);
9523
9524 bind(below_threshold);
9525 bind(copy_new_tail);
9526 movl(len, tmp2);
9527 andl(tmp2, 0x00000007);
9528 andl(len, 0xFFFFFFF8);
9529 jccb(Assembler::zero, copy_tail);
9530
9531 pmovzxbw(tmp1, Address(src, 0));
9532 movdqu(Address(dst, 0), tmp1);
9533 addptr(src, 8);
9534 addptr(dst, 2 * 8);
9535
9536 jmp(copy_tail, true);
9537 }
9538
9539 // inflate 8 chars per iter
9540 bind(copy_8_loop);
9541 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
9542 movdqu(Address(dst, len, Address::times_2), tmp1);
9543 addptr(len, 8);
9544 jcc(Assembler::notZero, copy_8_loop);
9545
9546 bind(copy_tail);
9547 movl(len, tmp2);
9548
9549 cmpl(len, 4);
9550 jccb(Assembler::less, copy_bytes);
9551
9552 movdl(tmp1, Address(src, 0)); // load 4 byte chars
9553 pmovzxbw(tmp1, tmp1);
9554 movq(Address(dst, 0), tmp1);
9555 subptr(len, 4);
9556 addptr(src, 4);
9557 addptr(dst, 8);
9558
9559 bind(copy_bytes);
9560 } else {
9561 bind(below_threshold);
9562 }
9563
9564 testl(len, len);
9565 jccb(Assembler::zero, done);
9566 lea(src, Address(src, len, Address::times_1));
9567 lea(dst, Address(dst, len, Address::times_2));
9568 negptr(len);
9569
9570 // inflate 1 char per iter
9571 bind(copy_chars_loop);
9572 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
9573 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
9574 increment(len);
9575 jcc(Assembler::notZero, copy_chars_loop);
9576
9577 bind(done);
9578 }
9579
9580 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, XMMRegister src, bool merge, int vector_len) {
9581 switch(type) {
9582 case T_BYTE:
9583 case T_BOOLEAN:
9584 evmovdqub(dst, kmask, src, merge, vector_len);
9585 break;
9586 case T_CHAR:
9587 case T_SHORT:
9588 evmovdquw(dst, kmask, src, merge, vector_len);
9589 break;
9590 case T_INT:
9591 case T_FLOAT:
9592 evmovdqul(dst, kmask, src, merge, vector_len);
9593 break;
9594 case T_LONG:
9595 case T_DOUBLE:
9596 evmovdquq(dst, kmask, src, merge, vector_len);
9597 break;
9598 default:
9599 fatal("Unexpected type argument %s", type2name(type));
9600 break;
9601 }
9602 }
9603
9604
9605 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, bool merge, int vector_len) {
9606 switch(type) {
9607 case T_BYTE:
9608 case T_BOOLEAN:
9609 evmovdqub(dst, kmask, src, merge, vector_len);
9610 break;
9611 case T_CHAR:
9612 case T_SHORT:
9613 evmovdquw(dst, kmask, src, merge, vector_len);
9614 break;
9615 case T_INT:
9616 case T_FLOAT:
9617 evmovdqul(dst, kmask, src, merge, vector_len);
9618 break;
9619 case T_LONG:
9620 case T_DOUBLE:
9621 evmovdquq(dst, kmask, src, merge, vector_len);
9622 break;
9623 default:
9624 fatal("Unexpected type argument %s", type2name(type));
9625 break;
9626 }
9627 }
9628
9629 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, bool merge, int vector_len) {
9630 switch(type) {
9631 case T_BYTE:
9632 case T_BOOLEAN:
9633 evmovdqub(dst, kmask, src, merge, vector_len);
9634 break;
9635 case T_CHAR:
9636 case T_SHORT:
9637 evmovdquw(dst, kmask, src, merge, vector_len);
9638 break;
9639 case T_INT:
9640 case T_FLOAT:
9641 evmovdqul(dst, kmask, src, merge, vector_len);
9642 break;
9643 case T_LONG:
9644 case T_DOUBLE:
9645 evmovdquq(dst, kmask, src, merge, vector_len);
9646 break;
9647 default:
9648 fatal("Unexpected type argument %s", type2name(type));
9649 break;
9650 }
9651 }
9652
9653 void MacroAssembler::knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp, Register rtmp) {
9654 switch(masklen) {
9655 case 2:
9656 knotbl(dst, src);
9657 movl(rtmp, 3);
9658 kmovbl(ktmp, rtmp);
9659 kandbl(dst, ktmp, dst);
9660 break;
9661 case 4:
9662 knotbl(dst, src);
9663 movl(rtmp, 15);
9664 kmovbl(ktmp, rtmp);
9665 kandbl(dst, ktmp, dst);
9666 break;
9667 case 8:
9668 knotbl(dst, src);
9669 break;
9670 case 16:
9671 knotwl(dst, src);
9672 break;
9673 case 32:
9674 knotdl(dst, src);
9675 break;
9676 case 64:
9677 knotql(dst, src);
9678 break;
9679 default:
9680 fatal("Unexpected vector length %d", masklen);
9681 break;
9682 }
9683 }
9684
9685 void MacroAssembler::kand(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9686 switch(type) {
9687 case T_BOOLEAN:
9688 case T_BYTE:
9689 kandbl(dst, src1, src2);
9690 break;
9691 case T_CHAR:
9692 case T_SHORT:
9693 kandwl(dst, src1, src2);
9694 break;
9695 case T_INT:
9696 case T_FLOAT:
9697 kanddl(dst, src1, src2);
9698 break;
9699 case T_LONG:
9700 case T_DOUBLE:
9701 kandql(dst, src1, src2);
9702 break;
9703 default:
9704 fatal("Unexpected type argument %s", type2name(type));
9705 break;
9706 }
9707 }
9708
9709 void MacroAssembler::kor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9710 switch(type) {
9711 case T_BOOLEAN:
9712 case T_BYTE:
9713 korbl(dst, src1, src2);
9714 break;
9715 case T_CHAR:
9716 case T_SHORT:
9717 korwl(dst, src1, src2);
9718 break;
9719 case T_INT:
9720 case T_FLOAT:
9721 kordl(dst, src1, src2);
9722 break;
9723 case T_LONG:
9724 case T_DOUBLE:
9725 korql(dst, src1, src2);
9726 break;
9727 default:
9728 fatal("Unexpected type argument %s", type2name(type));
9729 break;
9730 }
9731 }
9732
9733 void MacroAssembler::kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9734 switch(type) {
9735 case T_BOOLEAN:
9736 case T_BYTE:
9737 kxorbl(dst, src1, src2);
9738 break;
9739 case T_CHAR:
9740 case T_SHORT:
9741 kxorwl(dst, src1, src2);
9742 break;
9743 case T_INT:
9744 case T_FLOAT:
9745 kxordl(dst, src1, src2);
9746 break;
9747 case T_LONG:
9748 case T_DOUBLE:
9749 kxorql(dst, src1, src2);
9750 break;
9751 default:
9752 fatal("Unexpected type argument %s", type2name(type));
9753 break;
9754 }
9755 }
9756
9757 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9758 switch(type) {
9759 case T_BOOLEAN:
9760 case T_BYTE:
9761 evpermb(dst, mask, nds, src, merge, vector_len); break;
9762 case T_CHAR:
9763 case T_SHORT:
9764 evpermw(dst, mask, nds, src, merge, vector_len); break;
9765 case T_INT:
9766 case T_FLOAT:
9767 evpermd(dst, mask, nds, src, merge, vector_len); break;
9768 case T_LONG:
9769 case T_DOUBLE:
9770 evpermq(dst, mask, nds, src, merge, vector_len); break;
9771 default:
9772 fatal("Unexpected type argument %s", type2name(type)); break;
9773 }
9774 }
9775
9776 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9777 switch(type) {
9778 case T_BOOLEAN:
9779 case T_BYTE:
9780 evpermb(dst, mask, nds, src, merge, vector_len); break;
9781 case T_CHAR:
9782 case T_SHORT:
9783 evpermw(dst, mask, nds, src, merge, vector_len); break;
9784 case T_INT:
9785 case T_FLOAT:
9786 evpermd(dst, mask, nds, src, merge, vector_len); break;
9787 case T_LONG:
9788 case T_DOUBLE:
9789 evpermq(dst, mask, nds, src, merge, vector_len); break;
9790 default:
9791 fatal("Unexpected type argument %s", type2name(type)); break;
9792 }
9793 }
9794
9795 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9796 switch(type) {
9797 case T_BYTE:
9798 evpminub(dst, mask, nds, src, merge, vector_len); break;
9799 case T_SHORT:
9800 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9801 case T_INT:
9802 evpminud(dst, mask, nds, src, merge, vector_len); break;
9803 case T_LONG:
9804 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9805 default:
9806 fatal("Unexpected type argument %s", type2name(type)); break;
9807 }
9808 }
9809
9810 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9811 switch(type) {
9812 case T_BYTE:
9813 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9814 case T_SHORT:
9815 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9816 case T_INT:
9817 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9818 case T_LONG:
9819 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9820 default:
9821 fatal("Unexpected type argument %s", type2name(type)); break;
9822 }
9823 }
9824
9825 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9826 switch(type) {
9827 case T_BYTE:
9828 evpminub(dst, mask, nds, src, merge, vector_len); break;
9829 case T_SHORT:
9830 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9831 case T_INT:
9832 evpminud(dst, mask, nds, src, merge, vector_len); break;
9833 case T_LONG:
9834 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9835 default:
9836 fatal("Unexpected type argument %s", type2name(type)); break;
9837 }
9838 }
9839
9840 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9841 switch(type) {
9842 case T_BYTE:
9843 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9844 case T_SHORT:
9845 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9846 case T_INT:
9847 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9848 case T_LONG:
9849 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9850 default:
9851 fatal("Unexpected type argument %s", type2name(type)); break;
9852 }
9853 }
9854
9855 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9856 switch(type) {
9857 case T_BYTE:
9858 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9859 case T_SHORT:
9860 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9861 case T_INT:
9862 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9863 case T_LONG:
9864 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9865 default:
9866 fatal("Unexpected type argument %s", type2name(type)); break;
9867 }
9868 }
9869
9870 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9871 switch(type) {
9872 case T_BYTE:
9873 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9874 case T_SHORT:
9875 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9876 case T_INT:
9877 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9878 case T_LONG:
9879 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9880 default:
9881 fatal("Unexpected type argument %s", type2name(type)); break;
9882 }
9883 }
9884
9885 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9886 switch(type) {
9887 case T_BYTE:
9888 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9889 case T_SHORT:
9890 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9891 case T_INT:
9892 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9893 case T_LONG:
9894 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9895 default:
9896 fatal("Unexpected type argument %s", type2name(type)); break;
9897 }
9898 }
9899
9900 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9901 switch(type) {
9902 case T_BYTE:
9903 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9904 case T_SHORT:
9905 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9906 case T_INT:
9907 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9908 case T_LONG:
9909 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9910 default:
9911 fatal("Unexpected type argument %s", type2name(type)); break;
9912 }
9913 }
9914
9915 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9916 switch(type) {
9917 case T_INT:
9918 evpxord(dst, mask, nds, src, merge, vector_len); break;
9919 case T_LONG:
9920 evpxorq(dst, mask, nds, src, merge, vector_len); break;
9921 default:
9922 fatal("Unexpected type argument %s", type2name(type)); break;
9923 }
9924 }
9925
9926 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9927 switch(type) {
9928 case T_INT:
9929 evpxord(dst, mask, nds, src, merge, vector_len); break;
9930 case T_LONG:
9931 evpxorq(dst, mask, nds, src, merge, vector_len); break;
9932 default:
9933 fatal("Unexpected type argument %s", type2name(type)); break;
9934 }
9935 }
9936
9937 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9938 switch(type) {
9939 case T_INT:
9940 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
9941 case T_LONG:
9942 evporq(dst, mask, nds, src, merge, vector_len); break;
9943 default:
9944 fatal("Unexpected type argument %s", type2name(type)); break;
9945 }
9946 }
9947
9948 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9949 switch(type) {
9950 case T_INT:
9951 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
9952 case T_LONG:
9953 evporq(dst, mask, nds, src, merge, vector_len); break;
9954 default:
9955 fatal("Unexpected type argument %s", type2name(type)); break;
9956 }
9957 }
9958
9959 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9960 switch(type) {
9961 case T_INT:
9962 evpandd(dst, mask, nds, src, merge, vector_len); break;
9963 case T_LONG:
9964 evpandq(dst, mask, nds, src, merge, vector_len); break;
9965 default:
9966 fatal("Unexpected type argument %s", type2name(type)); break;
9967 }
9968 }
9969
9970 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9971 switch(type) {
9972 case T_INT:
9973 evpandd(dst, mask, nds, src, merge, vector_len); break;
9974 case T_LONG:
9975 evpandq(dst, mask, nds, src, merge, vector_len); break;
9976 default:
9977 fatal("Unexpected type argument %s", type2name(type)); break;
9978 }
9979 }
9980
9981 void MacroAssembler::kortest(uint masklen, KRegister src1, KRegister src2) {
9982 switch(masklen) {
9983 case 8:
9984 kortestbl(src1, src2);
9985 break;
9986 case 16:
9987 kortestwl(src1, src2);
9988 break;
9989 case 32:
9990 kortestdl(src1, src2);
9991 break;
9992 case 64:
9993 kortestql(src1, src2);
9994 break;
9995 default:
9996 fatal("Unexpected mask length %d", masklen);
9997 break;
9998 }
9999 }
10000
10001
10002 void MacroAssembler::ktest(uint masklen, KRegister src1, KRegister src2) {
10003 switch(masklen) {
10004 case 8:
10005 ktestbl(src1, src2);
10006 break;
10007 case 16:
10008 ktestwl(src1, src2);
10009 break;
10010 case 32:
10011 ktestdl(src1, src2);
10012 break;
10013 case 64:
10014 ktestql(src1, src2);
10015 break;
10016 default:
10017 fatal("Unexpected mask length %d", masklen);
10018 break;
10019 }
10020 }
10021
10022 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
10023 switch(type) {
10024 case T_INT:
10025 evprold(dst, mask, src, shift, merge, vlen_enc); break;
10026 case T_LONG:
10027 evprolq(dst, mask, src, shift, merge, vlen_enc); break;
10028 default:
10029 fatal("Unexpected type argument %s", type2name(type)); break;
10030 break;
10031 }
10032 }
10033
10034 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
10035 switch(type) {
10036 case T_INT:
10037 evprord(dst, mask, src, shift, merge, vlen_enc); break;
10038 case T_LONG:
10039 evprorq(dst, mask, src, shift, merge, vlen_enc); break;
10040 default:
10041 fatal("Unexpected type argument %s", type2name(type)); break;
10042 }
10043 }
10044
10045 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
10046 switch(type) {
10047 case T_INT:
10048 evprolvd(dst, mask, src1, src2, merge, vlen_enc); break;
10049 case T_LONG:
10050 evprolvq(dst, mask, src1, src2, merge, vlen_enc); break;
10051 default:
10052 fatal("Unexpected type argument %s", type2name(type)); break;
10053 }
10054 }
10055
10056 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
10057 switch(type) {
10058 case T_INT:
10059 evprorvd(dst, mask, src1, src2, merge, vlen_enc); break;
10060 case T_LONG:
10061 evprorvq(dst, mask, src1, src2, merge, vlen_enc); break;
10062 default:
10063 fatal("Unexpected type argument %s", type2name(type)); break;
10064 }
10065 }
10066
10067 void MacroAssembler::evpandq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10068 assert(rscratch != noreg || always_reachable(src), "missing");
10069
10070 if (reachable(src)) {
10071 evpandq(dst, nds, as_Address(src), vector_len);
10072 } else {
10073 lea(rscratch, src);
10074 evpandq(dst, nds, Address(rscratch, 0), vector_len);
10075 }
10076 }
10077
10078 void MacroAssembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
10079 assert(rscratch != noreg || always_reachable(src), "missing");
10080
10081 if (reachable(src)) {
10082 Assembler::evpaddq(dst, mask, nds, as_Address(src), merge, vector_len);
10083 } else {
10084 lea(rscratch, src);
10085 Assembler::evpaddq(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
10086 }
10087 }
10088
10089 void MacroAssembler::evporq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10090 assert(rscratch != noreg || always_reachable(src), "missing");
10091
10092 if (reachable(src)) {
10093 evporq(dst, nds, as_Address(src), vector_len);
10094 } else {
10095 lea(rscratch, src);
10096 evporq(dst, nds, Address(rscratch, 0), vector_len);
10097 }
10098 }
10099
10100 void MacroAssembler::vpshufb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10101 assert(rscratch != noreg || always_reachable(src), "missing");
10102
10103 if (reachable(src)) {
10104 vpshufb(dst, nds, as_Address(src), vector_len);
10105 } else {
10106 lea(rscratch, src);
10107 vpshufb(dst, nds, Address(rscratch, 0), vector_len);
10108 }
10109 }
10110
10111 void MacroAssembler::vpor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10112 assert(rscratch != noreg || always_reachable(src), "missing");
10113
10114 if (reachable(src)) {
10115 Assembler::vpor(dst, nds, as_Address(src), vector_len);
10116 } else {
10117 lea(rscratch, src);
10118 Assembler::vpor(dst, nds, Address(rscratch, 0), vector_len);
10119 }
10120 }
10121
10122 void MacroAssembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, AddressLiteral src3, int vector_len, Register rscratch) {
10123 assert(rscratch != noreg || always_reachable(src3), "missing");
10124
10125 if (reachable(src3)) {
10126 vpternlogq(dst, imm8, src2, as_Address(src3), vector_len);
10127 } else {
10128 lea(rscratch, src3);
10129 vpternlogq(dst, imm8, src2, Address(rscratch, 0), vector_len);
10130 }
10131 }
10132
10133 #if COMPILER2_OR_JVMCI
10134
10135 void MacroAssembler::fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
10136 Register length, Register temp, int vec_enc) {
10137 // Computing mask for predicated vector store.
10138 movptr(temp, -1);
10139 bzhiq(temp, temp, length);
10140 kmov(mask, temp);
10141 evmovdqu(bt, mask, dst, xmm, true, vec_enc);
10142 }
10143
10144 // Set memory operation for length "less than" 64 bytes.
10145 void MacroAssembler::fill64_masked(uint shift, Register dst, int disp,
10146 XMMRegister xmm, KRegister mask, Register length,
10147 Register temp, bool use64byteVector) {
10148 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10149 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
10150 if (!use64byteVector) {
10151 fill32(dst, disp, xmm);
10152 subptr(length, 32 >> shift);
10153 fill32_masked(shift, dst, disp + 32, xmm, mask, length, temp);
10154 } else {
10155 assert(MaxVectorSize == 64, "vector length != 64");
10156 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_512bit);
10157 }
10158 }
10159
10160
10161 void MacroAssembler::fill32_masked(uint shift, Register dst, int disp,
10162 XMMRegister xmm, KRegister mask, Register length,
10163 Register temp) {
10164 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10165 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
10166 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_256bit);
10167 }
10168
10169
10170 void MacroAssembler::fill32(Address dst, XMMRegister xmm) {
10171 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10172 vmovdqu(dst, xmm);
10173 }
10174
10175 void MacroAssembler::fill32(Register dst, int disp, XMMRegister xmm) {
10176 fill32(Address(dst, disp), xmm);
10177 }
10178
10179 void MacroAssembler::fill64(Address dst, XMMRegister xmm, bool use64byteVector) {
10180 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10181 if (!use64byteVector) {
10182 fill32(dst, xmm);
10183 fill32(dst.plus_disp(32), xmm);
10184 } else {
10185 evmovdquq(dst, xmm, Assembler::AVX_512bit);
10186 }
10187 }
10188
10189 void MacroAssembler::fill64(Register dst, int disp, XMMRegister xmm, bool use64byteVector) {
10190 fill64(Address(dst, disp), xmm, use64byteVector);
10191 }
10192
10193 #ifdef _LP64
10194 void MacroAssembler::generate_fill_avx3(BasicType type, Register to, Register value,
10195 Register count, Register rtmp, XMMRegister xtmp) {
10196 Label L_exit;
10197 Label L_fill_start;
10198 Label L_fill_64_bytes;
10199 Label L_fill_96_bytes;
10200 Label L_fill_128_bytes;
10201 Label L_fill_128_bytes_loop;
10202 Label L_fill_128_loop_header;
10203 Label L_fill_128_bytes_loop_header;
10204 Label L_fill_128_bytes_loop_pre_header;
10205 Label L_fill_zmm_sequence;
10206
10207 int shift = -1;
10208 int avx3threshold = VM_Version::avx3_threshold();
10209 switch(type) {
10210 case T_BYTE: shift = 0;
10211 break;
10212 case T_SHORT: shift = 1;
10213 break;
10214 case T_INT: shift = 2;
10215 break;
10216 /* Uncomment when LONG fill stubs are supported.
10217 case T_LONG: shift = 3;
10218 break;
10219 */
10220 default:
10221 fatal("Unhandled type: %s\n", type2name(type));
10222 }
10223
10224 if ((avx3threshold != 0) || (MaxVectorSize == 32)) {
10225
10226 if (MaxVectorSize == 64) {
10227 cmpq(count, avx3threshold >> shift);
10228 jcc(Assembler::greater, L_fill_zmm_sequence);
10229 }
10230
10231 evpbroadcast(type, xtmp, value, Assembler::AVX_256bit);
10232
10233 bind(L_fill_start);
10234
10235 cmpq(count, 32 >> shift);
10236 jccb(Assembler::greater, L_fill_64_bytes);
10237 fill32_masked(shift, to, 0, xtmp, k2, count, rtmp);
10238 jmp(L_exit);
10239
10240 bind(L_fill_64_bytes);
10241 cmpq(count, 64 >> shift);
10242 jccb(Assembler::greater, L_fill_96_bytes);
10243 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp);
10244 jmp(L_exit);
10245
10246 bind(L_fill_96_bytes);
10247 cmpq(count, 96 >> shift);
10248 jccb(Assembler::greater, L_fill_128_bytes);
10249 fill64(to, 0, xtmp);
10250 subq(count, 64 >> shift);
10251 fill32_masked(shift, to, 64, xtmp, k2, count, rtmp);
10252 jmp(L_exit);
10253
10254 bind(L_fill_128_bytes);
10255 cmpq(count, 128 >> shift);
10256 jccb(Assembler::greater, L_fill_128_bytes_loop_pre_header);
10257 fill64(to, 0, xtmp);
10258 fill32(to, 64, xtmp);
10259 subq(count, 96 >> shift);
10260 fill32_masked(shift, to, 96, xtmp, k2, count, rtmp);
10261 jmp(L_exit);
10262
10263 bind(L_fill_128_bytes_loop_pre_header);
10264 {
10265 mov(rtmp, to);
10266 andq(rtmp, 31);
10267 jccb(Assembler::zero, L_fill_128_bytes_loop_header);
10268 negq(rtmp);
10269 addq(rtmp, 32);
10270 mov64(r8, -1L);
10271 bzhiq(r8, r8, rtmp);
10272 kmovql(k2, r8);
10273 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_256bit);
10274 addq(to, rtmp);
10275 shrq(rtmp, shift);
10276 subq(count, rtmp);
10277 }
10278
10279 cmpq(count, 128 >> shift);
10280 jcc(Assembler::less, L_fill_start);
10281
10282 bind(L_fill_128_bytes_loop_header);
10283 subq(count, 128 >> shift);
10284
10285 align32();
10286 bind(L_fill_128_bytes_loop);
10287 fill64(to, 0, xtmp);
10288 fill64(to, 64, xtmp);
10289 addq(to, 128);
10290 subq(count, 128 >> shift);
10291 jccb(Assembler::greaterEqual, L_fill_128_bytes_loop);
10292
10293 addq(count, 128 >> shift);
10294 jcc(Assembler::zero, L_exit);
10295 jmp(L_fill_start);
10296 }
10297
10298 if (MaxVectorSize == 64) {
10299 // Sequence using 64 byte ZMM register.
10300 Label L_fill_128_bytes_zmm;
10301 Label L_fill_192_bytes_zmm;
10302 Label L_fill_192_bytes_loop_zmm;
10303 Label L_fill_192_bytes_loop_header_zmm;
10304 Label L_fill_192_bytes_loop_pre_header_zmm;
10305 Label L_fill_start_zmm_sequence;
10306
10307 bind(L_fill_zmm_sequence);
10308 evpbroadcast(type, xtmp, value, Assembler::AVX_512bit);
10309
10310 bind(L_fill_start_zmm_sequence);
10311 cmpq(count, 64 >> shift);
10312 jccb(Assembler::greater, L_fill_128_bytes_zmm);
10313 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp, true);
10314 jmp(L_exit);
10315
10316 bind(L_fill_128_bytes_zmm);
10317 cmpq(count, 128 >> shift);
10318 jccb(Assembler::greater, L_fill_192_bytes_zmm);
10319 fill64(to, 0, xtmp, true);
10320 subq(count, 64 >> shift);
10321 fill64_masked(shift, to, 64, xtmp, k2, count, rtmp, true);
10322 jmp(L_exit);
10323
10324 bind(L_fill_192_bytes_zmm);
10325 cmpq(count, 192 >> shift);
10326 jccb(Assembler::greater, L_fill_192_bytes_loop_pre_header_zmm);
10327 fill64(to, 0, xtmp, true);
10328 fill64(to, 64, xtmp, true);
10329 subq(count, 128 >> shift);
10330 fill64_masked(shift, to, 128, xtmp, k2, count, rtmp, true);
10331 jmp(L_exit);
10332
10333 bind(L_fill_192_bytes_loop_pre_header_zmm);
10334 {
10335 movq(rtmp, to);
10336 andq(rtmp, 63);
10337 jccb(Assembler::zero, L_fill_192_bytes_loop_header_zmm);
10338 negq(rtmp);
10339 addq(rtmp, 64);
10340 mov64(r8, -1L);
10341 bzhiq(r8, r8, rtmp);
10342 kmovql(k2, r8);
10343 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_512bit);
10344 addq(to, rtmp);
10345 shrq(rtmp, shift);
10346 subq(count, rtmp);
10347 }
10348
10349 cmpq(count, 192 >> shift);
10350 jcc(Assembler::less, L_fill_start_zmm_sequence);
10351
10352 bind(L_fill_192_bytes_loop_header_zmm);
10353 subq(count, 192 >> shift);
10354
10355 align32();
10356 bind(L_fill_192_bytes_loop_zmm);
10357 fill64(to, 0, xtmp, true);
10358 fill64(to, 64, xtmp, true);
10359 fill64(to, 128, xtmp, true);
10360 addq(to, 192);
10361 subq(count, 192 >> shift);
10362 jccb(Assembler::greaterEqual, L_fill_192_bytes_loop_zmm);
10363
10364 addq(count, 192 >> shift);
10365 jcc(Assembler::zero, L_exit);
10366 jmp(L_fill_start_zmm_sequence);
10367 }
10368 bind(L_exit);
10369 }
10370 #endif
10371 #endif //COMPILER2_OR_JVMCI
10372
10373
10374 #ifdef _LP64
10375 void MacroAssembler::convert_f2i(Register dst, XMMRegister src) {
10376 Label done;
10377 cvttss2sil(dst, src);
10378 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10379 cmpl(dst, 0x80000000); // float_sign_flip
10380 jccb(Assembler::notEqual, done);
10381 subptr(rsp, 8);
10382 movflt(Address(rsp, 0), src);
10383 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10384 pop(dst);
10385 bind(done);
10386 }
10387
10388 void MacroAssembler::convert_d2i(Register dst, XMMRegister src) {
10389 Label done;
10390 cvttsd2sil(dst, src);
10391 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10392 cmpl(dst, 0x80000000); // float_sign_flip
10393 jccb(Assembler::notEqual, done);
10394 subptr(rsp, 8);
10395 movdbl(Address(rsp, 0), src);
10396 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10397 pop(dst);
10398 bind(done);
10399 }
10400
10401 void MacroAssembler::convert_f2l(Register dst, XMMRegister src) {
10402 Label done;
10403 cvttss2siq(dst, src);
10404 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10405 jccb(Assembler::notEqual, done);
10406 subptr(rsp, 8);
10407 movflt(Address(rsp, 0), src);
10408 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10409 pop(dst);
10410 bind(done);
10411 }
10412
10413 void MacroAssembler::round_float(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10414 // Following code is line by line assembly translation rounding algorithm.
10415 // Please refer to java.lang.Math.round(float) algorithm for details.
10416 const int32_t FloatConsts_EXP_BIT_MASK = 0x7F800000;
10417 const int32_t FloatConsts_SIGNIFICAND_WIDTH = 24;
10418 const int32_t FloatConsts_EXP_BIAS = 127;
10419 const int32_t FloatConsts_SIGNIF_BIT_MASK = 0x007FFFFF;
10420 const int32_t MINUS_32 = 0xFFFFFFE0;
10421 Label L_special_case, L_block1, L_exit;
10422 movl(rtmp, FloatConsts_EXP_BIT_MASK);
10423 movdl(dst, src);
10424 andl(dst, rtmp);
10425 sarl(dst, FloatConsts_SIGNIFICAND_WIDTH - 1);
10426 movl(rtmp, FloatConsts_SIGNIFICAND_WIDTH - 2 + FloatConsts_EXP_BIAS);
10427 subl(rtmp, dst);
10428 movl(rcx, rtmp);
10429 movl(dst, MINUS_32);
10430 testl(rtmp, dst);
10431 jccb(Assembler::notEqual, L_special_case);
10432 movdl(dst, src);
10433 andl(dst, FloatConsts_SIGNIF_BIT_MASK);
10434 orl(dst, FloatConsts_SIGNIF_BIT_MASK + 1);
10435 movdl(rtmp, src);
10436 testl(rtmp, rtmp);
10437 jccb(Assembler::greaterEqual, L_block1);
10438 negl(dst);
10439 bind(L_block1);
10440 sarl(dst);
10441 addl(dst, 0x1);
10442 sarl(dst, 0x1);
10443 jmp(L_exit);
10444 bind(L_special_case);
10445 convert_f2i(dst, src);
10446 bind(L_exit);
10447 }
10448
10449 void MacroAssembler::round_double(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10450 // Following code is line by line assembly translation rounding algorithm.
10451 // Please refer to java.lang.Math.round(double) algorithm for details.
10452 const int64_t DoubleConsts_EXP_BIT_MASK = 0x7FF0000000000000L;
10453 const int64_t DoubleConsts_SIGNIFICAND_WIDTH = 53;
10454 const int64_t DoubleConsts_EXP_BIAS = 1023;
10455 const int64_t DoubleConsts_SIGNIF_BIT_MASK = 0x000FFFFFFFFFFFFFL;
10456 const int64_t MINUS_64 = 0xFFFFFFFFFFFFFFC0L;
10457 Label L_special_case, L_block1, L_exit;
10458 mov64(rtmp, DoubleConsts_EXP_BIT_MASK);
10459 movq(dst, src);
10460 andq(dst, rtmp);
10461 sarq(dst, DoubleConsts_SIGNIFICAND_WIDTH - 1);
10462 mov64(rtmp, DoubleConsts_SIGNIFICAND_WIDTH - 2 + DoubleConsts_EXP_BIAS);
10463 subq(rtmp, dst);
10464 movq(rcx, rtmp);
10465 mov64(dst, MINUS_64);
10466 testq(rtmp, dst);
10467 jccb(Assembler::notEqual, L_special_case);
10468 movq(dst, src);
10469 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK);
10470 andq(dst, rtmp);
10471 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK + 1);
10472 orq(dst, rtmp);
10473 movq(rtmp, src);
10474 testq(rtmp, rtmp);
10475 jccb(Assembler::greaterEqual, L_block1);
10476 negq(dst);
10477 bind(L_block1);
10478 sarq(dst);
10479 addq(dst, 0x1);
10480 sarq(dst, 0x1);
10481 jmp(L_exit);
10482 bind(L_special_case);
10483 convert_d2l(dst, src);
10484 bind(L_exit);
10485 }
10486
10487 void MacroAssembler::convert_d2l(Register dst, XMMRegister src) {
10488 Label done;
10489 cvttsd2siq(dst, src);
10490 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10491 jccb(Assembler::notEqual, done);
10492 subptr(rsp, 8);
10493 movdbl(Address(rsp, 0), src);
10494 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10495 pop(dst);
10496 bind(done);
10497 }
10498
10499 void MacroAssembler::cache_wb(Address line)
10500 {
10501 // 64 bit cpus always support clflush
10502 assert(VM_Version::supports_clflush(), "clflush should be available");
10503 bool optimized = VM_Version::supports_clflushopt();
10504 bool no_evict = VM_Version::supports_clwb();
10505
10506 // prefer clwb (writeback without evict) otherwise
10507 // prefer clflushopt (potentially parallel writeback with evict)
10508 // otherwise fallback on clflush (serial writeback with evict)
10509
10510 if (optimized) {
10511 if (no_evict) {
10512 clwb(line);
10513 } else {
10514 clflushopt(line);
10515 }
10516 } else {
10517 // no need for fence when using CLFLUSH
10518 clflush(line);
10519 }
10520 }
10521
10522 void MacroAssembler::cache_wbsync(bool is_pre)
10523 {
10524 assert(VM_Version::supports_clflush(), "clflush should be available");
10525 bool optimized = VM_Version::supports_clflushopt();
10526 bool no_evict = VM_Version::supports_clwb();
10527
10528 // pick the correct implementation
10529
10530 if (!is_pre && (optimized || no_evict)) {
10531 // need an sfence for post flush when using clflushopt or clwb
10532 // otherwise no no need for any synchroniaztion
10533
10534 sfence();
10535 }
10536 }
10537
10538 #endif // _LP64
10539
10540 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
10541 switch (cond) {
10542 // Note some conditions are synonyms for others
10543 case Assembler::zero: return Assembler::notZero;
10544 case Assembler::notZero: return Assembler::zero;
10545 case Assembler::less: return Assembler::greaterEqual;
10546 case Assembler::lessEqual: return Assembler::greater;
10547 case Assembler::greater: return Assembler::lessEqual;
10548 case Assembler::greaterEqual: return Assembler::less;
10549 case Assembler::below: return Assembler::aboveEqual;
10550 case Assembler::belowEqual: return Assembler::above;
10551 case Assembler::above: return Assembler::belowEqual;
10552 case Assembler::aboveEqual: return Assembler::below;
10553 case Assembler::overflow: return Assembler::noOverflow;
10554 case Assembler::noOverflow: return Assembler::overflow;
10555 case Assembler::negative: return Assembler::positive;
10556 case Assembler::positive: return Assembler::negative;
10557 case Assembler::parity: return Assembler::noParity;
10558 case Assembler::noParity: return Assembler::parity;
10559 }
10560 ShouldNotReachHere(); return Assembler::overflow;
10561 }
10562
10563 // 32-bit Windows has its own fast-path implementation
10564 // of get_thread
10565 #if !defined(WIN32) || defined(_LP64)
10566
10567 // This is simply a call to Thread::current()
10568 void MacroAssembler::get_thread(Register thread) {
10569 if (thread != rax) {
10570 push(rax);
10571 }
10572 LP64_ONLY(push(rdi);)
10573 LP64_ONLY(push(rsi);)
10574 push(rdx);
10575 push(rcx);
10576 #ifdef _LP64
10577 push(r8);
10578 push(r9);
10579 push(r10);
10580 push(r11);
10581 #endif
10582
10583 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
10584
10585 #ifdef _LP64
10586 pop(r11);
10587 pop(r10);
10588 pop(r9);
10589 pop(r8);
10590 #endif
10591 pop(rcx);
10592 pop(rdx);
10593 LP64_ONLY(pop(rsi);)
10594 LP64_ONLY(pop(rdi);)
10595 if (thread != rax) {
10596 mov(thread, rax);
10597 pop(rax);
10598 }
10599 }
10600
10601
10602 #endif // !WIN32 || _LP64
10603
10604 void MacroAssembler::check_stack_alignment(Register sp, const char* msg, unsigned bias, Register tmp) {
10605 Label L_stack_ok;
10606 if (bias == 0) {
10607 testptr(sp, 2 * wordSize - 1);
10608 } else {
10609 // lea(tmp, Address(rsp, bias);
10610 mov(tmp, sp);
10611 addptr(tmp, bias);
10612 testptr(tmp, 2 * wordSize - 1);
10613 }
10614 jcc(Assembler::equal, L_stack_ok);
10615 block_comment(msg);
10616 stop(msg);
10617 bind(L_stack_ok);
10618 }
10619
10620 // Implements lightweight-locking.
10621 //
10622 // obj: the object to be locked
10623 // reg_rax: rax
10624 // thread: the thread which attempts to lock obj
10625 // tmp: a temporary register
10626 void MacroAssembler::lightweight_lock(Register basic_lock, Register obj, Register reg_rax, Register thread, Register tmp, Label& slow) {
10627 assert(reg_rax == rax, "");
10628 assert_different_registers(basic_lock, obj, reg_rax, thread, tmp);
10629
10630 Label push;
10631 const Register top = tmp;
10632
10633 // Preload the markWord. It is important that this is the first
10634 // instruction emitted as it is part of C1's null check semantics.
10635 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10636
10637 if (UseObjectMonitorTable) {
10638 // Clear cache in case fast locking succeeds.
10639 movptr(Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes()))), 0);
10640 }
10641
10642 // Load top.
10643 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10644
10645 // Check if the lock-stack is full.
10646 cmpl(top, LockStack::end_offset());
10647 jcc(Assembler::greaterEqual, slow);
10648
10649 // Check for recursion.
10650 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10651 jcc(Assembler::equal, push);
10652
10653 // Check header for monitor (0b10).
10654 testptr(reg_rax, markWord::monitor_value);
10655 jcc(Assembler::notZero, slow);
10656
10657 // Try to lock. Transition lock bits 0b01 => 0b00
10658 movptr(tmp, reg_rax);
10659 andptr(tmp, ~(int32_t)markWord::unlocked_value);
10660 orptr(reg_rax, markWord::unlocked_value);
10661 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10662 jcc(Assembler::notEqual, slow);
10663
10664 // Restore top, CAS clobbers register.
10665 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10666
10667 bind(push);
10668 // After successful lock, push object on lock-stack.
10669 movptr(Address(thread, top), obj);
10670 incrementl(top, oopSize);
10671 movl(Address(thread, JavaThread::lock_stack_top_offset()), top);
10672 }
10673
10674 // Implements lightweight-unlocking.
10675 //
10676 // obj: the object to be unlocked
10677 // reg_rax: rax
10678 // thread: the thread
10679 // tmp: a temporary register
10680 void MacroAssembler::lightweight_unlock(Register obj, Register reg_rax, Register thread, Register tmp, Label& slow) {
10681 assert(reg_rax == rax, "");
10682 assert_different_registers(obj, reg_rax, thread, tmp);
10683
10684 Label unlocked, push_and_slow;
10685 const Register top = tmp;
10686
10687 // Check if obj is top of lock-stack.
10688 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10689 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10690 jcc(Assembler::notEqual, slow);
10691
10692 // Pop lock-stack.
10693 DEBUG_ONLY(movptr(Address(thread, top, Address::times_1, -oopSize), 0);)
10694 subl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10695
10696 // Check if recursive.
10697 cmpptr(obj, Address(thread, top, Address::times_1, -2 * oopSize));
10698 jcc(Assembler::equal, unlocked);
10699
10700 // Not recursive. Check header for monitor (0b10).
10701 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10702 testptr(reg_rax, markWord::monitor_value);
10703 jcc(Assembler::notZero, push_and_slow);
10704
10705 #ifdef ASSERT
10706 // Check header not unlocked (0b01).
10707 Label not_unlocked;
10708 testptr(reg_rax, markWord::unlocked_value);
10709 jcc(Assembler::zero, not_unlocked);
10710 stop("lightweight_unlock already unlocked");
10711 bind(not_unlocked);
10712 #endif
10713
10714 // Try to unlock. Transition lock bits 0b00 => 0b01
10715 movptr(tmp, reg_rax);
10716 orptr(tmp, markWord::unlocked_value);
10717 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10718 jcc(Assembler::equal, unlocked);
10719
10720 bind(push_and_slow);
10721 // Restore lock-stack and handle the unlock in runtime.
10722 #ifdef ASSERT
10723 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10724 movptr(Address(thread, top), obj);
10725 #endif
10726 addl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10727 jmp(slow);
10728
10729 bind(unlocked);
10730 }
10731
10732 #ifdef _LP64
10733 // Saves legacy GPRs state on stack.
10734 void MacroAssembler::save_legacy_gprs() {
10735 subq(rsp, 16 * wordSize);
10736 movq(Address(rsp, 15 * wordSize), rax);
10737 movq(Address(rsp, 14 * wordSize), rcx);
10738 movq(Address(rsp, 13 * wordSize), rdx);
10739 movq(Address(rsp, 12 * wordSize), rbx);
10740 movq(Address(rsp, 10 * wordSize), rbp);
10741 movq(Address(rsp, 9 * wordSize), rsi);
10742 movq(Address(rsp, 8 * wordSize), rdi);
10743 movq(Address(rsp, 7 * wordSize), r8);
10744 movq(Address(rsp, 6 * wordSize), r9);
10745 movq(Address(rsp, 5 * wordSize), r10);
10746 movq(Address(rsp, 4 * wordSize), r11);
10747 movq(Address(rsp, 3 * wordSize), r12);
10748 movq(Address(rsp, 2 * wordSize), r13);
10749 movq(Address(rsp, wordSize), r14);
10750 movq(Address(rsp, 0), r15);
10751 }
10752
10753 // Resotres back legacy GPRs state from stack.
10754 void MacroAssembler::restore_legacy_gprs() {
10755 movq(r15, Address(rsp, 0));
10756 movq(r14, Address(rsp, wordSize));
10757 movq(r13, Address(rsp, 2 * wordSize));
10758 movq(r12, Address(rsp, 3 * wordSize));
10759 movq(r11, Address(rsp, 4 * wordSize));
10760 movq(r10, Address(rsp, 5 * wordSize));
10761 movq(r9, Address(rsp, 6 * wordSize));
10762 movq(r8, Address(rsp, 7 * wordSize));
10763 movq(rdi, Address(rsp, 8 * wordSize));
10764 movq(rsi, Address(rsp, 9 * wordSize));
10765 movq(rbp, Address(rsp, 10 * wordSize));
10766 movq(rbx, Address(rsp, 12 * wordSize));
10767 movq(rdx, Address(rsp, 13 * wordSize));
10768 movq(rcx, Address(rsp, 14 * wordSize));
10769 movq(rax, Address(rsp, 15 * wordSize));
10770 addq(rsp, 16 * wordSize);
10771 }
10772
10773 void MacroAssembler::setcc(Assembler::Condition comparison, Register dst) {
10774 if (VM_Version::supports_apx_f()) {
10775 esetzucc(comparison, dst);
10776 } else {
10777 setb(comparison, dst);
10778 movzbl(dst, dst);
10779 }
10780 }
10781 #endif