1 /*
2 * Copyright (c) 1997, 2024, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
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23 */
24
25 #ifndef CPU_X86_MACROASSEMBLER_X86_HPP
26 #define CPU_X86_MACROASSEMBLER_X86_HPP
27
28 #include "asm/assembler.hpp"
29 #include "asm/register.hpp"
30 #include "code/vmreg.inline.hpp"
31 #include "compiler/oopMap.hpp"
32 #include "utilities/macros.hpp"
33 #include "runtime/vm_version.hpp"
34 #include "utilities/checkedCast.hpp"
35
36 // MacroAssembler extends Assembler by frequently used macros.
37 //
38 // Instructions for which a 'better' code sequence exists depending
39 // on arguments should also go in here.
40
41 class MacroAssembler: public Assembler {
42 friend class LIR_Assembler;
43 friend class Runtime1; // as_Address()
44
45 public:
46 // Support for VM calls
47 //
48 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
49 // may customize this version by overriding it for its purposes (e.g., to save/restore
50 // additional registers when doing a VM call).
51
52 virtual void call_VM_leaf_base(
53 address entry_point, // the entry point
54 int number_of_arguments // the number of arguments to pop after the call
55 );
56
57 protected:
58 // This is the base routine called by the different versions of call_VM. The interpreter
59 // may customize this version by overriding it for its purposes (e.g., to save/restore
60 // additional registers when doing a VM call).
61 //
62 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
63 // returns the register which contains the thread upon return. If a thread register has been
64 // specified, the return value will correspond to that register. If no last_java_sp is specified
65 // (noreg) than rsp will be used instead.
66 virtual void call_VM_base( // returns the register containing the thread upon return
67 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
68 Register java_thread, // the thread if computed before ; use noreg otherwise
69 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
70 address entry_point, // the entry point
71 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
72 bool check_exceptions // whether to check for pending exceptions after return
73 );
74
75 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
76
77 // helpers for FPU flag access
78 // tmp is a temporary register, if none is available use noreg
79 void save_rax (Register tmp);
80 void restore_rax(Register tmp);
81
82 public:
83 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
84
85 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
86 // The implementation is only non-empty for the InterpreterMacroAssembler,
87 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
88 virtual void check_and_handle_popframe(Register java_thread);
89 virtual void check_and_handle_earlyret(Register java_thread);
90
91 Address as_Address(AddressLiteral adr);
92 Address as_Address(ArrayAddress adr, Register rscratch);
93
94 // Support for null-checks
95 //
96 // Generates code that causes a null OS exception if the content of reg is null.
97 // If the accessed location is M[reg + offset] and the offset is known, provide the
98 // offset. No explicit code generation is needed if the offset is within a certain
99 // range (0 <= offset <= page_size).
100
101 void null_check(Register reg, int offset = -1);
102 static bool needs_explicit_null_check(intptr_t offset);
103 static bool uses_implicit_null_check(void* address);
104
105 // Required platform-specific helpers for Label::patch_instructions.
106 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
107 void pd_patch_instruction(address branch, address target, const char* file, int line) {
108 unsigned char op = branch[0];
109 assert(op == 0xE8 /* call */ ||
110 op == 0xE9 /* jmp */ ||
111 op == 0xEB /* short jmp */ ||
112 (op & 0xF0) == 0x70 /* short jcc */ ||
113 (op == 0x0F && (branch[1] & 0xF0) == 0x80) /* jcc */ ||
114 (op == 0xC7 && branch[1] == 0xF8) /* xbegin */,
115 "Invalid opcode at patch point");
116
117 if (op == 0xEB || (op & 0xF0) == 0x70) {
118 // short offset operators (jmp and jcc)
119 char* disp = (char*) &branch[1];
120 int imm8 = checked_cast<int>(target - (address) &disp[1]);
121 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset at %s:%d",
122 file == nullptr ? "<null>" : file, line);
123 *disp = (char)imm8;
124 } else {
125 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
126 int imm32 = checked_cast<int>(target - (address) &disp[1]);
127 *disp = imm32;
128 }
129 }
130
131 // The following 4 methods return the offset of the appropriate move instruction
132
133 // Support for fast byte/short loading with zero extension (depending on particular CPU)
134 int load_unsigned_byte(Register dst, Address src);
135 int load_unsigned_short(Register dst, Address src);
136
137 // Support for fast byte/short loading with sign extension (depending on particular CPU)
138 int load_signed_byte(Register dst, Address src);
139 int load_signed_short(Register dst, Address src);
140
141 // Support for sign-extension (hi:lo = extend_sign(lo))
142 void extend_sign(Register hi, Register lo);
143
144 // Load and store values by size and signed-ness
145 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
146 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
147
148 // Support for inc/dec with optimal instruction selection depending on value
149
150 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
151 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
152 void increment(Address dst, int value = 1) { LP64_ONLY(incrementq(dst, value)) NOT_LP64(incrementl(dst, value)) ; }
153 void decrement(Address dst, int value = 1) { LP64_ONLY(decrementq(dst, value)) NOT_LP64(decrementl(dst, value)) ; }
154
155 void decrementl(Address dst, int value = 1);
156 void decrementl(Register reg, int value = 1);
157
158 void decrementq(Register reg, int value = 1);
159 void decrementq(Address dst, int value = 1);
160
161 void incrementl(Address dst, int value = 1);
162 void incrementl(Register reg, int value = 1);
163
164 void incrementq(Register reg, int value = 1);
165 void incrementq(Address dst, int value = 1);
166
167 void incrementl(AddressLiteral dst, Register rscratch = noreg);
168 void incrementl(ArrayAddress dst, Register rscratch);
169
170 void incrementq(AddressLiteral dst, Register rscratch = noreg);
171
172 // Support optimal SSE move instructions.
173 void movflt(XMMRegister dst, XMMRegister src) {
174 if (dst-> encoding() == src->encoding()) return;
175 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
176 else { movss (dst, src); return; }
177 }
178 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
179 void movflt(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
180 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
181
182 // Move with zero extension
183 void movfltz(XMMRegister dst, XMMRegister src) { movss(dst, src); }
184
185 void movdbl(XMMRegister dst, XMMRegister src) {
186 if (dst-> encoding() == src->encoding()) return;
187 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
188 else { movsd (dst, src); return; }
189 }
190
191 void movdbl(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
192
193 void movdbl(XMMRegister dst, Address src) {
194 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
195 else { movlpd(dst, src); return; }
196 }
197 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
198
199 void flt_to_flt16(Register dst, XMMRegister src, XMMRegister tmp) {
200 // Use separate tmp XMM register because caller may
201 // requires src XMM register to be unchanged (as in x86.ad).
202 vcvtps2ph(tmp, src, 0x04, Assembler::AVX_128bit);
203 movdl(dst, tmp);
204 movswl(dst, dst);
205 }
206
207 void flt16_to_flt(XMMRegister dst, Register src) {
208 movdl(dst, src);
209 vcvtph2ps(dst, dst, Assembler::AVX_128bit);
210 }
211
212 // Alignment
213 void align32();
214 void align64();
215 void align(uint modulus);
216 void align(uint modulus, uint target);
217
218 void post_call_nop();
219 // A 5 byte nop that is safe for patching (see patch_verified_entry)
220 void fat_nop();
221
222 // Stack frame creation/removal
223 void enter();
224 void leave();
225
226 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
227 // The pointer will be loaded into the thread register.
228 void get_thread(Register thread);
229
230 #ifdef _LP64
231 // Support for argument shuffling
232
233 // bias in bytes
234 void move32_64(VMRegPair src, VMRegPair dst, Register tmp = rax, int in_stk_bias = 0, int out_stk_bias = 0);
235 void long_move(VMRegPair src, VMRegPair dst, Register tmp = rax, int in_stk_bias = 0, int out_stk_bias = 0);
236 void float_move(VMRegPair src, VMRegPair dst, Register tmp = rax, int in_stk_bias = 0, int out_stk_bias = 0);
237 void double_move(VMRegPair src, VMRegPair dst, Register tmp = rax, int in_stk_bias = 0, int out_stk_bias = 0);
238 void move_ptr(VMRegPair src, VMRegPair dst);
239 void object_move(OopMap* map,
240 int oop_handle_offset,
241 int framesize_in_slots,
242 VMRegPair src,
243 VMRegPair dst,
244 bool is_receiver,
245 int* receiver_offset);
246 #endif // _LP64
247
248 // Support for VM calls
249 //
250 // It is imperative that all calls into the VM are handled via the call_VM macros.
251 // They make sure that the stack linkage is setup correctly. call_VM's correspond
252 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
253
254
255 void call_VM(Register oop_result,
256 address entry_point,
257 bool check_exceptions = true);
258 void call_VM(Register oop_result,
259 address entry_point,
260 Register arg_1,
261 bool check_exceptions = true);
262 void call_VM(Register oop_result,
263 address entry_point,
264 Register arg_1, Register arg_2,
265 bool check_exceptions = true);
266 void call_VM(Register oop_result,
267 address entry_point,
268 Register arg_1, Register arg_2, Register arg_3,
269 bool check_exceptions = true);
270
271 // Overloadings with last_Java_sp
272 void call_VM(Register oop_result,
273 Register last_java_sp,
274 address entry_point,
275 int number_of_arguments = 0,
276 bool check_exceptions = true);
277 void call_VM(Register oop_result,
278 Register last_java_sp,
279 address entry_point,
280 Register arg_1, bool
281 check_exceptions = true);
282 void call_VM(Register oop_result,
283 Register last_java_sp,
284 address entry_point,
285 Register arg_1, Register arg_2,
286 bool check_exceptions = true);
287 void call_VM(Register oop_result,
288 Register last_java_sp,
289 address entry_point,
290 Register arg_1, Register arg_2, Register arg_3,
291 bool check_exceptions = true);
292
293 void get_vm_result (Register oop_result, Register thread);
294 void get_vm_result_2(Register metadata_result, Register thread);
295
296 // These always tightly bind to MacroAssembler::call_VM_base
297 // bypassing the virtual implementation
298 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
299 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
300 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
301 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
302 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
303
304 void call_VM_leaf0(address entry_point);
305 void call_VM_leaf(address entry_point,
306 int number_of_arguments = 0);
307 void call_VM_leaf(address entry_point,
308 Register arg_1);
309 void call_VM_leaf(address entry_point,
310 Register arg_1, Register arg_2);
311 void call_VM_leaf(address entry_point,
312 Register arg_1, Register arg_2, Register arg_3);
313
314 void call_VM_leaf(address entry_point,
315 Register arg_1, Register arg_2, Register arg_3, Register arg_4);
316
317 // These always tightly bind to MacroAssembler::call_VM_leaf_base
318 // bypassing the virtual implementation
319 void super_call_VM_leaf(address entry_point);
320 void super_call_VM_leaf(address entry_point, Register arg_1);
321 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
322 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
323 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
324
325 // last Java Frame (fills frame anchor)
326 void set_last_Java_frame(Register thread,
327 Register last_java_sp,
328 Register last_java_fp,
329 address last_java_pc,
330 Register rscratch);
331
332 // thread in the default location (r15_thread on 64bit)
333 void set_last_Java_frame(Register last_java_sp,
334 Register last_java_fp,
335 address last_java_pc,
336 Register rscratch);
337
338 void reset_last_Java_frame(Register thread, bool clear_fp);
339
340 // thread in the default location (r15_thread on 64bit)
341 void reset_last_Java_frame(bool clear_fp);
342
343 // jobjects
344 void clear_jobject_tag(Register possibly_non_local);
345 void resolve_jobject(Register value, Register thread, Register tmp);
346 void resolve_global_jobject(Register value, Register thread, Register tmp);
347
348 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
349 void c2bool(Register x);
350
351 // C++ bool manipulation
352
353 void movbool(Register dst, Address src);
354 void movbool(Address dst, bool boolconst);
355 void movbool(Address dst, Register src);
356 void testbool(Register dst);
357
358 void resolve_oop_handle(Register result, Register tmp);
359 void resolve_weak_handle(Register result, Register tmp);
360 void load_mirror(Register mirror, Register method, Register tmp);
361 void load_method_holder_cld(Register rresult, Register rmethod);
362
363 void load_method_holder(Register holder, Register method);
364
365 // oop manipulations
366 void load_klass(Register dst, Register src, Register tmp);
367 void store_klass(Register dst, Register src, Register tmp);
368
369 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
370 Register tmp1, Register thread_tmp);
371 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
372 Register tmp1, Register tmp2, Register tmp3);
373
374 void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
375 Register thread_tmp = noreg, DecoratorSet decorators = 0);
376 void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
377 Register thread_tmp = noreg, DecoratorSet decorators = 0);
378 void store_heap_oop(Address dst, Register val, Register tmp1 = noreg,
379 Register tmp2 = noreg, Register tmp3 = noreg, DecoratorSet decorators = 0);
380
381 // Used for storing null. All other oop constants should be
382 // stored using routines that take a jobject.
383 void store_heap_oop_null(Address dst);
384
385 #ifdef _LP64
386 void store_klass_gap(Register dst, Register src);
387
388 // This dummy is to prevent a call to store_heap_oop from
389 // converting a zero (like null) into a Register by giving
390 // the compiler two choices it can't resolve
391
392 void store_heap_oop(Address dst, void* dummy);
393
394 void encode_heap_oop(Register r);
395 void decode_heap_oop(Register r);
396 void encode_heap_oop_not_null(Register r);
397 void decode_heap_oop_not_null(Register r);
398 void encode_heap_oop_not_null(Register dst, Register src);
399 void decode_heap_oop_not_null(Register dst, Register src);
400
401 void set_narrow_oop(Register dst, jobject obj);
402 void set_narrow_oop(Address dst, jobject obj);
403 void cmp_narrow_oop(Register dst, jobject obj);
404 void cmp_narrow_oop(Address dst, jobject obj);
405
406 void encode_klass_not_null(Register r, Register tmp);
407 void decode_klass_not_null(Register r, Register tmp);
408 void encode_and_move_klass_not_null(Register dst, Register src);
409 void decode_and_move_klass_not_null(Register dst, Register src);
410 void set_narrow_klass(Register dst, Klass* k);
411 void set_narrow_klass(Address dst, Klass* k);
412 void cmp_narrow_klass(Register dst, Klass* k);
413 void cmp_narrow_klass(Address dst, Klass* k);
414
415 // if heap base register is used - reinit it with the correct value
416 void reinit_heapbase();
417
418 DEBUG_ONLY(void verify_heapbase(const char* msg);)
419
420 #endif // _LP64
421
422 // Int division/remainder for Java
423 // (as idivl, but checks for special case as described in JVM spec.)
424 // returns idivl instruction offset for implicit exception handling
425 int corrected_idivl(Register reg);
426
427 // Long division/remainder for Java
428 // (as idivq, but checks for special case as described in JVM spec.)
429 // returns idivq instruction offset for implicit exception handling
430 int corrected_idivq(Register reg);
431
432 void int3();
433
434 // Long operation macros for a 32bit cpu
435 // Long negation for Java
436 void lneg(Register hi, Register lo);
437
438 // Long multiplication for Java
439 // (destroys contents of eax, ebx, ecx and edx)
440 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
441
442 // Long shifts for Java
443 // (semantics as described in JVM spec.)
444 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
445 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
446
447 // Long compare for Java
448 // (semantics as described in JVM spec.)
449 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
450
451
452 // misc
453
454 // Sign extension
455 void sign_extend_short(Register reg);
456 void sign_extend_byte(Register reg);
457
458 // Division by power of 2, rounding towards 0
459 void division_with_shift(Register reg, int shift_value);
460
461 #ifndef _LP64
462 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
463 //
464 // CF (corresponds to C0) if x < y
465 // PF (corresponds to C2) if unordered
466 // ZF (corresponds to C3) if x = y
467 //
468 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
469 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
470 void fcmp(Register tmp);
471 // Variant of the above which allows y to be further down the stack
472 // and which only pops x and y if specified. If pop_right is
473 // specified then pop_left must also be specified.
474 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
475
476 // Floating-point comparison for Java
477 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
478 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
479 // (semantics as described in JVM spec.)
480 void fcmp2int(Register dst, bool unordered_is_less);
481 // Variant of the above which allows y to be further down the stack
482 // and which only pops x and y if specified. If pop_right is
483 // specified then pop_left must also be specified.
484 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
485
486 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
487 // tmp is a temporary register, if none is available use noreg
488 void fremr(Register tmp);
489
490 // only if +VerifyFPU
491 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
492 #endif // !LP64
493
494 // dst = c = a * b + c
495 void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
496 void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
497
498 void vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
499 void vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
500 void vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
501 void vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
502
503
504 // same as fcmp2int, but using SSE2
505 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
506 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
507
508 // branch to L if FPU flag C2 is set/not set
509 // tmp is a temporary register, if none is available use noreg
510 void jC2 (Register tmp, Label& L);
511 void jnC2(Register tmp, Label& L);
512
513 // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
514 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
515 void load_float(Address src);
516
517 // Store float value to 'address'. If UseSSE >= 1, the value is stored
518 // from register xmm0. Otherwise, the value is stored from the FPU stack.
519 void store_float(Address dst);
520
521 // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
522 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
523 void load_double(Address src);
524
525 // Store double value to 'address'. If UseSSE >= 2, the value is stored
526 // from register xmm0. Otherwise, the value is stored from the FPU stack.
527 void store_double(Address dst);
528
529 #ifndef _LP64
530 // Pop ST (ffree & fincstp combined)
531 void fpop();
532
533 void empty_FPU_stack();
534 #endif // !_LP64
535
536 void push_IU_state();
537 void pop_IU_state();
538
539 void push_FPU_state();
540 void pop_FPU_state();
541
542 void push_CPU_state();
543 void pop_CPU_state();
544
545 void push_cont_fastpath();
546 void pop_cont_fastpath();
547
548 void inc_held_monitor_count();
549 void dec_held_monitor_count();
550
551 DEBUG_ONLY(void stop_if_in_cont(Register cont_reg, const char* name);)
552
553 // Round up to a power of two
554 void round_to(Register reg, int modulus);
555
556 private:
557 // General purpose and XMM registers potentially clobbered by native code; there
558 // is no need for FPU or AVX opmask related methods because C1/interpreter
559 // - we save/restore FPU state as a whole always
560 // - do not care about AVX-512 opmask
561 static RegSet call_clobbered_gp_registers();
562 static XMMRegSet call_clobbered_xmm_registers();
563
564 void push_set(XMMRegSet set, int offset);
565 void pop_set(XMMRegSet set, int offset);
566
567 public:
568 void push_set(RegSet set, int offset = -1);
569 void pop_set(RegSet set, int offset = -1);
570
571 // Push and pop everything that might be clobbered by a native
572 // runtime call.
573 // Only save the lower 64 bits of each vector register.
574 // Additional registers can be excluded in a passed RegSet.
575 void push_call_clobbered_registers_except(RegSet exclude, bool save_fpu = true);
576 void pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu = true);
577
578 void push_call_clobbered_registers(bool save_fpu = true) {
579 push_call_clobbered_registers_except(RegSet(), save_fpu);
580 }
581 void pop_call_clobbered_registers(bool restore_fpu = true) {
582 pop_call_clobbered_registers_except(RegSet(), restore_fpu);
583 }
584
585 // allocation
586 void tlab_allocate(
587 Register thread, // Current thread
588 Register obj, // result: pointer to object after successful allocation
589 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
590 int con_size_in_bytes, // object size in bytes if known at compile time
591 Register t1, // temp register
592 Register t2, // temp register
593 Label& slow_case // continuation point if fast allocation fails
594 );
595 void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
596
597 void population_count(Register dst, Register src, Register scratch1, Register scratch2);
598
599 // interface method calling
600 void lookup_interface_method(Register recv_klass,
601 Register intf_klass,
602 RegisterOrConstant itable_index,
603 Register method_result,
604 Register scan_temp,
605 Label& no_such_interface,
606 bool return_method = true);
607
608 void lookup_interface_method_stub(Register recv_klass,
609 Register holder_klass,
610 Register resolved_klass,
611 Register method_result,
612 Register scan_temp,
613 Register temp_reg2,
614 Register receiver,
615 int itable_index,
616 Label& L_no_such_interface);
617
618 // virtual method calling
619 void lookup_virtual_method(Register recv_klass,
620 RegisterOrConstant vtable_index,
621 Register method_result);
622
623 // Test sub_klass against super_klass, with fast and slow paths.
624
625 // The fast path produces a tri-state answer: yes / no / maybe-slow.
626 // One of the three labels can be null, meaning take the fall-through.
627 // If super_check_offset is -1, the value is loaded up from super_klass.
628 // No registers are killed, except temp_reg.
629 void check_klass_subtype_fast_path(Register sub_klass,
630 Register super_klass,
631 Register temp_reg,
632 Label* L_success,
633 Label* L_failure,
634 Label* L_slow_path,
635 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
636
637 // The rest of the type check; must be wired to a corresponding fast path.
638 // It does not repeat the fast path logic, so don't use it standalone.
639 // The temp_reg and temp2_reg can be noreg, if no temps are available.
640 // Updates the sub's secondary super cache as necessary.
641 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
642 void check_klass_subtype_slow_path(Register sub_klass,
643 Register super_klass,
644 Register temp_reg,
645 Register temp2_reg,
646 Label* L_success,
647 Label* L_failure,
648 bool set_cond_codes = false);
649
650 #ifdef _LP64
651 // The 64-bit version, which may do a hashed subclass lookup.
652 void check_klass_subtype_slow_path(Register sub_klass,
653 Register super_klass,
654 Register temp_reg,
655 Register temp2_reg,
656 Register temp3_reg,
657 Register temp4_reg,
658 Label* L_success,
659 Label* L_failure);
660 #endif
661
662 // Three parts of a hashed subclass lookup: a simple linear search,
663 // a table lookup, and a fallback that does linear probing in the
664 // event of a hash collision.
665 void check_klass_subtype_slow_path_linear(Register sub_klass,
666 Register super_klass,
667 Register temp_reg,
668 Register temp2_reg,
669 Label* L_success,
670 Label* L_failure,
671 bool set_cond_codes = false);
672 void check_klass_subtype_slow_path_table(Register sub_klass,
673 Register super_klass,
674 Register temp_reg,
675 Register temp2_reg,
676 Register temp3_reg,
677 Register result_reg,
678 Label* L_success,
679 Label* L_failure);
680 void hashed_check_klass_subtype_slow_path(Register sub_klass,
681 Register super_klass,
682 Register temp_reg,
683 Label* L_success,
684 Label* L_failure);
685
686 // As above, but with a constant super_klass.
687 // The result is in Register result, not the condition codes.
688 void lookup_secondary_supers_table_const(Register sub_klass,
689 Register super_klass,
690 Register temp1,
691 Register temp2,
692 Register temp3,
693 Register temp4,
694 Register result,
695 u1 super_klass_slot);
696
697 #ifdef _LP64
698 using Assembler::salq;
699 void salq(Register dest, Register count);
700 using Assembler::rorq;
701 void rorq(Register dest, Register count);
702 void lookup_secondary_supers_table_var(Register sub_klass,
703 Register super_klass,
704 Register temp1,
705 Register temp2,
706 Register temp3,
707 Register temp4,
708 Register result);
709
710 void lookup_secondary_supers_table_slow_path(Register r_super_klass,
711 Register r_array_base,
712 Register r_array_index,
713 Register r_bitmap,
714 Register temp1,
715 Register temp2,
716 Label* L_success,
717 Label* L_failure = nullptr);
718
719 void verify_secondary_supers_table(Register r_sub_klass,
720 Register r_super_klass,
721 Register expected,
722 Register temp1,
723 Register temp2,
724 Register temp3);
725 #endif
726
727 void repne_scanq(Register addr, Register value, Register count, Register limit,
728 Label* L_success,
729 Label* L_failure = nullptr);
730
731 // If r is valid, return r.
732 // If r is invalid, remove a register r2 from available_regs, add r2
733 // to regs_to_push, then return r2.
734 Register allocate_if_noreg(const Register r,
735 RegSetIterator<Register> &available_regs,
736 RegSet ®s_to_push);
737
738 // Simplified, combined version, good for typical uses.
739 // Falls through on failure.
740 void check_klass_subtype(Register sub_klass,
741 Register super_klass,
742 Register temp_reg,
743 Label& L_success);
744
745 void clinit_barrier(Register klass,
746 Register thread,
747 Label* L_fast_path = nullptr,
748 Label* L_slow_path = nullptr);
749
750 // method handles (JSR 292)
751 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
752
753 // Debugging
754
755 // only if +VerifyOops
756 void _verify_oop(Register reg, const char* s, const char* file, int line);
757 void _verify_oop_addr(Address addr, const char* s, const char* file, int line);
758
759 void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
760 if (VerifyOops) {
761 _verify_oop(reg, s, file, line);
762 }
763 }
764 void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
765 if (VerifyOops) {
766 _verify_oop_addr(reg, s, file, line);
767 }
768 }
769
770 // TODO: verify method and klass metadata (compare against vptr?)
771 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
772 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
773
774 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
775 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
776 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
777 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
778 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
779
780 // Verify or restore cpu control state after JNI call
781 void restore_cpu_control_state_after_jni(Register rscratch);
782
783 // prints msg, dumps registers and stops execution
784 void stop(const char* msg);
785
786 // prints msg and continues
787 void warn(const char* msg);
788
789 // dumps registers and other state
790 void print_state();
791
792 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
793 static void debug64(char* msg, int64_t pc, int64_t regs[]);
794 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
795 static void print_state64(int64_t pc, int64_t regs[]);
796
797 void os_breakpoint();
798
799 void untested() { stop("untested"); }
800
801 void unimplemented(const char* what = "");
802
803 void should_not_reach_here() { stop("should not reach here"); }
804
805 void print_CPU_state();
806
807 // Stack overflow checking
808 void bang_stack_with_offset(int offset) {
809 // stack grows down, caller passes positive offset
810 assert(offset > 0, "must bang with negative offset");
811 movl(Address(rsp, (-offset)), rax);
812 }
813
814 // Writes to stack successive pages until offset reached to check for
815 // stack overflow + shadow pages. Also, clobbers tmp
816 void bang_stack_size(Register size, Register tmp);
817
818 // Check for reserved stack access in method being exited (for JIT)
819 void reserved_stack_check();
820
821 void safepoint_poll(Label& slow_path, Register thread_reg, bool at_return, bool in_nmethod);
822
823 void verify_tlab();
824
825 static Condition negate_condition(Condition cond);
826
827 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
828 // operands. In general the names are modified to avoid hiding the instruction in Assembler
829 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
830 // here in MacroAssembler. The major exception to this rule is call
831
832 // Arithmetics
833
834
835 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
836 void addptr(Address dst, Register src);
837
838 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
839 void addptr(Register dst, int32_t src);
840 void addptr(Register dst, Register src);
841 void addptr(Register dst, RegisterOrConstant src) {
842 if (src.is_constant()) addptr(dst, checked_cast<int>(src.as_constant()));
843 else addptr(dst, src.as_register());
844 }
845
846 void andptr(Register dst, int32_t src);
847 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
848
849 #ifdef _LP64
850 using Assembler::andq;
851 void andq(Register dst, AddressLiteral src, Register rscratch = noreg);
852 #endif
853
854 void cmp8(AddressLiteral src1, int imm, Register rscratch = noreg);
855
856 // renamed to drag out the casting of address to int32_t/intptr_t
857 void cmp32(Register src1, int32_t imm);
858
859 void cmp32(AddressLiteral src1, int32_t imm, Register rscratch = noreg);
860 // compare reg - mem, or reg - &mem
861 void cmp32(Register src1, AddressLiteral src2, Register rscratch = noreg);
862
863 void cmp32(Register src1, Address src2);
864
865 #ifndef _LP64
866 void cmpklass(Address dst, Metadata* obj);
867 void cmpklass(Register dst, Metadata* obj);
868 void cmpoop(Address dst, jobject obj);
869 #endif // _LP64
870
871 void cmpoop(Register src1, Register src2);
872 void cmpoop(Register src1, Address src2);
873 void cmpoop(Register dst, jobject obj, Register rscratch);
874
875 // NOTE src2 must be the lval. This is NOT an mem-mem compare
876 void cmpptr(Address src1, AddressLiteral src2, Register rscratch);
877
878 void cmpptr(Register src1, AddressLiteral src2, Register rscratch = noreg);
879
880 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
881 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
882 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
883
884 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
885 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
886
887 // cmp64 to avoild hiding cmpq
888 void cmp64(Register src1, AddressLiteral src, Register rscratch = noreg);
889
890 void cmpxchgptr(Register reg, Address adr);
891
892 void locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch = noreg);
893
894 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
895 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
896
897
898 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
899
900 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
901
902 void shlptr(Register dst, int32_t shift);
903 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
904
905 void shrptr(Register dst, int32_t shift);
906 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
907
908 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
909 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
910
911 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
912
913 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
914 void subptr(Register dst, int32_t src);
915 // Force generation of a 4 byte immediate value even if it fits into 8bit
916 void subptr_imm32(Register dst, int32_t src);
917 void subptr(Register dst, Register src);
918 void subptr(Register dst, RegisterOrConstant src) {
919 if (src.is_constant()) subptr(dst, (int) src.as_constant());
920 else subptr(dst, src.as_register());
921 }
922
923 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
924 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
925
926 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
927 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
928
929 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
930
931
932
933 // Helper functions for statistics gathering.
934 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
935 void cond_inc32(Condition cond, AddressLiteral counter_addr, Register rscratch = noreg);
936 // Unconditional atomic increment.
937 void atomic_incl(Address counter_addr);
938 void atomic_incl(AddressLiteral counter_addr, Register rscratch = noreg);
939 #ifdef _LP64
940 void atomic_incq(Address counter_addr);
941 void atomic_incq(AddressLiteral counter_addr, Register rscratch = noreg);
942 #endif
943 void atomic_incptr(AddressLiteral counter_addr, Register rscratch = noreg) { LP64_ONLY(atomic_incq(counter_addr, rscratch)) NOT_LP64(atomic_incl(counter_addr, rscratch)) ; }
944 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
945
946 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
947 void lea(Register dst, AddressLiteral adr);
948 void lea(Address dst, AddressLiteral adr, Register rscratch);
949
950 void leal32(Register dst, Address src) { leal(dst, src); }
951
952 // Import other testl() methods from the parent class or else
953 // they will be hidden by the following overriding declaration.
954 using Assembler::testl;
955 void testl(Address dst, int32_t imm32);
956 void testl(Register dst, int32_t imm32);
957 void testl(Register dst, AddressLiteral src); // requires reachable address
958 using Assembler::testq;
959 void testq(Address dst, int32_t imm32);
960 void testq(Register dst, int32_t imm32);
961
962 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
963 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
964 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
965 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
966
967 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
968 void testptr(Register src1, Address src2) { LP64_ONLY(testq(src1, src2)) NOT_LP64(testl(src1, src2)); }
969 void testptr(Address src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
970 void testptr(Register src1, Register src2);
971
972 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
973 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
974
975 // Calls
976
977 void call(Label& L, relocInfo::relocType rtype);
978 void call(Register entry);
979 void call(Address addr) { Assembler::call(addr); }
980
981 // NOTE: this call transfers to the effective address of entry NOT
982 // the address contained by entry. This is because this is more natural
983 // for jumps/calls.
984 void call(AddressLiteral entry, Register rscratch = rax);
985
986 // Emit the CompiledIC call idiom
987 void ic_call(address entry, jint method_index = 0);
988 static int ic_check_size();
989 int ic_check(int end_alignment);
990
991 void emit_static_call_stub();
992
993 // Jumps
994
995 // NOTE: these jumps transfer to the effective address of dst NOT
996 // the address contained by dst. This is because this is more natural
997 // for jumps/calls.
998 void jump(AddressLiteral dst, Register rscratch = noreg);
999
1000 void jump_cc(Condition cc, AddressLiteral dst, Register rscratch = noreg);
1001
1002 // 32bit can do a case table jump in one instruction but we no longer allow the base
1003 // to be installed in the Address class. This jump will transfer to the address
1004 // contained in the location described by entry (not the address of entry)
1005 void jump(ArrayAddress entry, Register rscratch);
1006
1007 // Adding more natural conditional jump instructions
1008 void ALWAYSINLINE jo(Label& L, bool maybe_short = true) { jcc(Assembler::overflow, L, maybe_short); }
1009 void ALWAYSINLINE jno(Label& L, bool maybe_short = true) { jcc(Assembler::noOverflow, L, maybe_short); }
1010 void ALWAYSINLINE js(Label& L, bool maybe_short = true) { jcc(Assembler::negative, L, maybe_short); }
1011 void ALWAYSINLINE jns(Label& L, bool maybe_short = true) { jcc(Assembler::positive, L, maybe_short); }
1012 void ALWAYSINLINE je(Label& L, bool maybe_short = true) { jcc(Assembler::equal, L, maybe_short); }
1013 void ALWAYSINLINE jz(Label& L, bool maybe_short = true) { jcc(Assembler::zero, L, maybe_short); }
1014 void ALWAYSINLINE jne(Label& L, bool maybe_short = true) { jcc(Assembler::notEqual, L, maybe_short); }
1015 void ALWAYSINLINE jnz(Label& L, bool maybe_short = true) { jcc(Assembler::notZero, L, maybe_short); }
1016 void ALWAYSINLINE jb(Label& L, bool maybe_short = true) { jcc(Assembler::below, L, maybe_short); }
1017 void ALWAYSINLINE jnae(Label& L, bool maybe_short = true) { jcc(Assembler::below, L, maybe_short); }
1018 void ALWAYSINLINE jc(Label& L, bool maybe_short = true) { jcc(Assembler::carrySet, L, maybe_short); }
1019 void ALWAYSINLINE jnb(Label& L, bool maybe_short = true) { jcc(Assembler::aboveEqual, L, maybe_short); }
1020 void ALWAYSINLINE jae(Label& L, bool maybe_short = true) { jcc(Assembler::aboveEqual, L, maybe_short); }
1021 void ALWAYSINLINE jnc(Label& L, bool maybe_short = true) { jcc(Assembler::carryClear, L, maybe_short); }
1022 void ALWAYSINLINE jbe(Label& L, bool maybe_short = true) { jcc(Assembler::belowEqual, L, maybe_short); }
1023 void ALWAYSINLINE jna(Label& L, bool maybe_short = true) { jcc(Assembler::belowEqual, L, maybe_short); }
1024 void ALWAYSINLINE ja(Label& L, bool maybe_short = true) { jcc(Assembler::above, L, maybe_short); }
1025 void ALWAYSINLINE jnbe(Label& L, bool maybe_short = true) { jcc(Assembler::above, L, maybe_short); }
1026 void ALWAYSINLINE jl(Label& L, bool maybe_short = true) { jcc(Assembler::less, L, maybe_short); }
1027 void ALWAYSINLINE jnge(Label& L, bool maybe_short = true) { jcc(Assembler::less, L, maybe_short); }
1028 void ALWAYSINLINE jge(Label& L, bool maybe_short = true) { jcc(Assembler::greaterEqual, L, maybe_short); }
1029 void ALWAYSINLINE jnl(Label& L, bool maybe_short = true) { jcc(Assembler::greaterEqual, L, maybe_short); }
1030 void ALWAYSINLINE jle(Label& L, bool maybe_short = true) { jcc(Assembler::lessEqual, L, maybe_short); }
1031 void ALWAYSINLINE jng(Label& L, bool maybe_short = true) { jcc(Assembler::lessEqual, L, maybe_short); }
1032 void ALWAYSINLINE jg(Label& L, bool maybe_short = true) { jcc(Assembler::greater, L, maybe_short); }
1033 void ALWAYSINLINE jnle(Label& L, bool maybe_short = true) { jcc(Assembler::greater, L, maybe_short); }
1034 void ALWAYSINLINE jp(Label& L, bool maybe_short = true) { jcc(Assembler::parity, L, maybe_short); }
1035 void ALWAYSINLINE jpe(Label& L, bool maybe_short = true) { jcc(Assembler::parity, L, maybe_short); }
1036 void ALWAYSINLINE jnp(Label& L, bool maybe_short = true) { jcc(Assembler::noParity, L, maybe_short); }
1037 void ALWAYSINLINE jpo(Label& L, bool maybe_short = true) { jcc(Assembler::noParity, L, maybe_short); }
1038 // * No condition for this * void ALWAYSINLINE jcxz(Label& L, bool maybe_short = true) { jcc(Assembler::cxz, L, maybe_short); }
1039 // * No condition for this * void ALWAYSINLINE jecxz(Label& L, bool maybe_short = true) { jcc(Assembler::cxz, L, maybe_short); }
1040
1041 // Short versions of the above
1042 void ALWAYSINLINE jo_b(Label& L) { jccb(Assembler::overflow, L); }
1043 void ALWAYSINLINE jno_b(Label& L) { jccb(Assembler::noOverflow, L); }
1044 void ALWAYSINLINE js_b(Label& L) { jccb(Assembler::negative, L); }
1045 void ALWAYSINLINE jns_b(Label& L) { jccb(Assembler::positive, L); }
1046 void ALWAYSINLINE je_b(Label& L) { jccb(Assembler::equal, L); }
1047 void ALWAYSINLINE jz_b(Label& L) { jccb(Assembler::zero, L); }
1048 void ALWAYSINLINE jne_b(Label& L) { jccb(Assembler::notEqual, L); }
1049 void ALWAYSINLINE jnz_b(Label& L) { jccb(Assembler::notZero, L); }
1050 void ALWAYSINLINE jb_b(Label& L) { jccb(Assembler::below, L); }
1051 void ALWAYSINLINE jnae_b(Label& L) { jccb(Assembler::below, L); }
1052 void ALWAYSINLINE jc_b(Label& L) { jccb(Assembler::carrySet, L); }
1053 void ALWAYSINLINE jnb_b(Label& L) { jccb(Assembler::aboveEqual, L); }
1054 void ALWAYSINLINE jae_b(Label& L) { jccb(Assembler::aboveEqual, L); }
1055 void ALWAYSINLINE jnc_b(Label& L) { jccb(Assembler::carryClear, L); }
1056 void ALWAYSINLINE jbe_b(Label& L) { jccb(Assembler::belowEqual, L); }
1057 void ALWAYSINLINE jna_b(Label& L) { jccb(Assembler::belowEqual, L); }
1058 void ALWAYSINLINE ja_b(Label& L) { jccb(Assembler::above, L); }
1059 void ALWAYSINLINE jnbe_b(Label& L) { jccb(Assembler::above, L); }
1060 void ALWAYSINLINE jl_b(Label& L) { jccb(Assembler::less, L); }
1061 void ALWAYSINLINE jnge_b(Label& L) { jccb(Assembler::less, L); }
1062 void ALWAYSINLINE jge_b(Label& L) { jccb(Assembler::greaterEqual, L); }
1063 void ALWAYSINLINE jnl_b(Label& L) { jccb(Assembler::greaterEqual, L); }
1064 void ALWAYSINLINE jle_b(Label& L) { jccb(Assembler::lessEqual, L); }
1065 void ALWAYSINLINE jng_b(Label& L) { jccb(Assembler::lessEqual, L); }
1066 void ALWAYSINLINE jg_b(Label& L) { jccb(Assembler::greater, L); }
1067 void ALWAYSINLINE jnle_b(Label& L) { jccb(Assembler::greater, L); }
1068 void ALWAYSINLINE jp_b(Label& L) { jccb(Assembler::parity, L); }
1069 void ALWAYSINLINE jpe_b(Label& L) { jccb(Assembler::parity, L); }
1070 void ALWAYSINLINE jnp_b(Label& L) { jccb(Assembler::noParity, L); }
1071 void ALWAYSINLINE jpo_b(Label& L) { jccb(Assembler::noParity, L); }
1072 // * No condition for this * void ALWAYSINLINE jcxz_b(Label& L) { jccb(Assembler::cxz, L); }
1073 // * No condition for this * void ALWAYSINLINE jecxz_b(Label& L) { jccb(Assembler::cxz, L); }
1074
1075 // Floating
1076
1077 void push_f(XMMRegister r);
1078 void pop_f(XMMRegister r);
1079 void push_d(XMMRegister r);
1080 void pop_d(XMMRegister r);
1081
1082 void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
1083 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
1084 void andpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1085
1086 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
1087 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
1088 void andps(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1089
1090 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
1091 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
1092 void comiss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1093
1094 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
1095 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
1096 void comisd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1097
1098 #ifndef _LP64
1099 void fadd_s(Address src) { Assembler::fadd_s(src); }
1100 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
1101
1102 void fldcw(Address src) { Assembler::fldcw(src); }
1103 void fldcw(AddressLiteral src);
1104
1105 void fld_s(int index) { Assembler::fld_s(index); }
1106 void fld_s(Address src) { Assembler::fld_s(src); }
1107 void fld_s(AddressLiteral src);
1108
1109 void fld_d(Address src) { Assembler::fld_d(src); }
1110 void fld_d(AddressLiteral src);
1111
1112 void fld_x(Address src) { Assembler::fld_x(src); }
1113 void fld_x(AddressLiteral src) { Assembler::fld_x(as_Address(src)); }
1114
1115 void fmul_s(Address src) { Assembler::fmul_s(src); }
1116 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
1117 #endif // !_LP64
1118
1119 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
1120 void ldmxcsr(AddressLiteral src, Register rscratch = noreg);
1121
1122 #ifdef _LP64
1123 private:
1124 void sha256_AVX2_one_round_compute(
1125 Register reg_old_h,
1126 Register reg_a,
1127 Register reg_b,
1128 Register reg_c,
1129 Register reg_d,
1130 Register reg_e,
1131 Register reg_f,
1132 Register reg_g,
1133 Register reg_h,
1134 int iter);
1135 void sha256_AVX2_four_rounds_compute_first(int start);
1136 void sha256_AVX2_four_rounds_compute_last(int start);
1137 void sha256_AVX2_one_round_and_sched(
1138 XMMRegister xmm_0, /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
1139 XMMRegister xmm_1, /* ymm5 */ /* full cycle is 16 iterations */
1140 XMMRegister xmm_2, /* ymm6 */
1141 XMMRegister xmm_3, /* ymm7 */
1142 Register reg_a, /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
1143 Register reg_b, /* ebx */ /* full cycle is 8 iterations */
1144 Register reg_c, /* edi */
1145 Register reg_d, /* esi */
1146 Register reg_e, /* r8d */
1147 Register reg_f, /* r9d */
1148 Register reg_g, /* r10d */
1149 Register reg_h, /* r11d */
1150 int iter);
1151
1152 void addm(int disp, Register r1, Register r2);
1153
1154 void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d,
1155 Register e, Register f, Register g, Register h, int iteration);
1156
1157 void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1158 Register a, Register b, Register c, Register d, Register e, Register f,
1159 Register g, Register h, int iteration);
1160
1161 void addmq(int disp, Register r1, Register r2);
1162 public:
1163 void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1164 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1165 Register buf, Register state, Register ofs, Register limit, Register rsp,
1166 bool multi_block, XMMRegister shuf_mask);
1167 void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1168 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1169 Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block,
1170 XMMRegister shuf_mask);
1171 void sha512_update_ni_x1(Register arg_hash, Register arg_msg, Register ofs, Register limit, bool multi_block);
1172 #endif // _LP64
1173
1174 void fast_md5(Register buf, Address state, Address ofs, Address limit,
1175 bool multi_block);
1176
1177 void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
1178 XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
1179 Register buf, Register state, Register ofs, Register limit, Register rsp,
1180 bool multi_block);
1181
1182 #ifdef _LP64
1183 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1184 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1185 Register buf, Register state, Register ofs, Register limit, Register rsp,
1186 bool multi_block, XMMRegister shuf_mask);
1187 #else
1188 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1189 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1190 Register buf, Register state, Register ofs, Register limit, Register rsp,
1191 bool multi_block);
1192 #endif
1193
1194 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1195 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1196 Register rax, Register rcx, Register rdx, Register tmp);
1197
1198 #ifndef _LP64
1199 private:
1200 // Initialized in macroAssembler_x86_constants.cpp
1201 static address ONES;
1202 static address L_2IL0FLOATPACKET_0;
1203 static address PI4_INV;
1204 static address PI4X3;
1205 static address PI4X4;
1206
1207 public:
1208 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1209 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1210 Register rax, Register rcx, Register rdx, Register tmp1);
1211
1212 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1213 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1214 Register rax, Register rcx, Register rdx, Register tmp);
1215
1216 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1217 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1218 Register rdx, Register tmp);
1219
1220 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1221 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1222 Register rax, Register rbx, Register rdx);
1223
1224 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1225 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1226 Register rax, Register rcx, Register rdx, Register tmp);
1227
1228 void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1229 Register edx, Register ebx, Register esi, Register edi,
1230 Register ebp, Register esp);
1231
1232 void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
1233 Register esi, Register edi, Register ebp, Register esp);
1234
1235 void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1236 Register edx, Register ebx, Register esi, Register edi,
1237 Register ebp, Register esp);
1238
1239 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1240 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1241 Register rax, Register rcx, Register rdx, Register tmp);
1242 #endif // !_LP64
1243
1244 private:
1245
1246 // these are private because users should be doing movflt/movdbl
1247
1248 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
1249 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1250 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
1251 void movss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1252
1253 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
1254 void movlpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1255
1256 public:
1257
1258 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
1259 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
1260 void addsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1261
1262 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
1263 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
1264 void addss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1265
1266 void addpd(XMMRegister dst, XMMRegister src) { Assembler::addpd(dst, src); }
1267 void addpd(XMMRegister dst, Address src) { Assembler::addpd(dst, src); }
1268 void addpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1269
1270 using Assembler::vbroadcasti128;
1271 void vbroadcasti128(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1272
1273 using Assembler::vbroadcastsd;
1274 void vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1275
1276 using Assembler::vbroadcastss;
1277 void vbroadcastss(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1278
1279 // Vector float blend
1280 void vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg);
1281 void vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg);
1282
1283 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
1284 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
1285 void divsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1286
1287 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
1288 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
1289 void divss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1290
1291 // Move Unaligned Double Quadword
1292 void movdqu(Address dst, XMMRegister src);
1293 void movdqu(XMMRegister dst, XMMRegister src);
1294 void movdqu(XMMRegister dst, Address src);
1295 void movdqu(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1296
1297 void kmovwl(Register dst, KRegister src) { Assembler::kmovwl(dst, src); }
1298 void kmovwl(Address dst, KRegister src) { Assembler::kmovwl(dst, src); }
1299 void kmovwl(KRegister dst, KRegister src) { Assembler::kmovwl(dst, src); }
1300 void kmovwl(KRegister dst, Register src) { Assembler::kmovwl(dst, src); }
1301 void kmovwl(KRegister dst, Address src) { Assembler::kmovwl(dst, src); }
1302 void kmovwl(KRegister dst, AddressLiteral src, Register rscratch = noreg);
1303
1304 void kmovql(KRegister dst, KRegister src) { Assembler::kmovql(dst, src); }
1305 void kmovql(KRegister dst, Register src) { Assembler::kmovql(dst, src); }
1306 void kmovql(Register dst, KRegister src) { Assembler::kmovql(dst, src); }
1307 void kmovql(KRegister dst, Address src) { Assembler::kmovql(dst, src); }
1308 void kmovql(Address dst, KRegister src) { Assembler::kmovql(dst, src); }
1309 void kmovql(KRegister dst, AddressLiteral src, Register rscratch = noreg);
1310
1311 // Safe move operation, lowers down to 16bit moves for targets supporting
1312 // AVX512F feature and 64bit moves for targets supporting AVX512BW feature.
1313 void kmov(Address dst, KRegister src);
1314 void kmov(KRegister dst, Address src);
1315 void kmov(KRegister dst, KRegister src);
1316 void kmov(Register dst, KRegister src);
1317 void kmov(KRegister dst, Register src);
1318
1319 using Assembler::movddup;
1320 void movddup(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1321
1322 using Assembler::vmovddup;
1323 void vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1324
1325 // AVX Unaligned forms
1326 void vmovdqu(Address dst, XMMRegister src);
1327 void vmovdqu(XMMRegister dst, Address src);
1328 void vmovdqu(XMMRegister dst, XMMRegister src);
1329 void vmovdqu(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1330 void vmovdqu(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1331
1332 // AVX512 Unaligned
1333 void evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, bool merge, int vector_len);
1334 void evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, bool merge, int vector_len);
1335 void evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, XMMRegister src, bool merge, int vector_len);
1336
1337 void evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::evmovdqub(dst, src, vector_len); }
1338 void evmovdqub(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdqub(dst, src, vector_len); }
1339
1340 void evmovdqub(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1341 if (dst->encoding() != src->encoding() || mask != k0) {
1342 Assembler::evmovdqub(dst, mask, src, merge, vector_len);
1343 }
1344 }
1345 void evmovdqub(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdqub(dst, mask, src, merge, vector_len); }
1346 void evmovdqub(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdqub(dst, mask, src, merge, vector_len); }
1347 void evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1348
1349 void evmovdquw(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::evmovdquw(dst, src, vector_len); }
1350 void evmovdquw(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdquw(dst, src, vector_len); }
1351 void evmovdquw(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdquw(dst, src, vector_len); }
1352
1353 void evmovdquw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1354 if (dst->encoding() != src->encoding() || mask != k0) {
1355 Assembler::evmovdquw(dst, mask, src, merge, vector_len);
1356 }
1357 }
1358 void evmovdquw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdquw(dst, mask, src, merge, vector_len); }
1359 void evmovdquw(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdquw(dst, mask, src, merge, vector_len); }
1360 void evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1361
1362 void evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
1363 if (dst->encoding() != src->encoding()) {
1364 Assembler::evmovdqul(dst, src, vector_len);
1365 }
1366 }
1367 void evmovdqul(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdqul(dst, src, vector_len); }
1368 void evmovdqul(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdqul(dst, src, vector_len); }
1369
1370 void evmovdqul(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1371 if (dst->encoding() != src->encoding() || mask != k0) {
1372 Assembler::evmovdqul(dst, mask, src, merge, vector_len);
1373 }
1374 }
1375 void evmovdqul(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdqul(dst, mask, src, merge, vector_len); }
1376 void evmovdqul(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdqul(dst, mask, src, merge, vector_len); }
1377 void evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1378
1379 void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
1380 if (dst->encoding() != src->encoding()) {
1381 Assembler::evmovdquq(dst, src, vector_len);
1382 }
1383 }
1384 void evmovdquq(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1385 void evmovdquq(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1386 void evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1387
1388 void evmovdquq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1389 if (dst->encoding() != src->encoding() || mask != k0) {
1390 Assembler::evmovdquq(dst, mask, src, merge, vector_len);
1391 }
1392 }
1393 void evmovdquq(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdquq(dst, mask, src, merge, vector_len); }
1394 void evmovdquq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdquq(dst, mask, src, merge, vector_len); }
1395 void evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1396
1397 // Move Aligned Double Quadword
1398 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
1399 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
1400 void movdqa(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1401
1402 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
1403 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1404 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
1405 void movsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1406
1407 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); }
1408 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); }
1409 void mulpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1410
1411 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
1412 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
1413 void mulsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1414
1415 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
1416 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
1417 void mulss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1418
1419 // Carry-Less Multiplication Quadword
1420 void pclmulldq(XMMRegister dst, XMMRegister src) {
1421 // 0x00 - multiply lower 64 bits [0:63]
1422 Assembler::pclmulqdq(dst, src, 0x00);
1423 }
1424 void pclmulhdq(XMMRegister dst, XMMRegister src) {
1425 // 0x11 - multiply upper 64 bits [64:127]
1426 Assembler::pclmulqdq(dst, src, 0x11);
1427 }
1428
1429 void pcmpeqb(XMMRegister dst, XMMRegister src);
1430 void pcmpeqw(XMMRegister dst, XMMRegister src);
1431
1432 void pcmpestri(XMMRegister dst, Address src, int imm8);
1433 void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1434
1435 void pmovzxbw(XMMRegister dst, XMMRegister src);
1436 void pmovzxbw(XMMRegister dst, Address src);
1437
1438 void pmovmskb(Register dst, XMMRegister src);
1439
1440 void ptest(XMMRegister dst, XMMRegister src);
1441
1442 void roundsd(XMMRegister dst, XMMRegister src, int32_t rmode) { Assembler::roundsd(dst, src, rmode); }
1443 void roundsd(XMMRegister dst, Address src, int32_t rmode) { Assembler::roundsd(dst, src, rmode); }
1444 void roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register rscratch = noreg);
1445
1446 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
1447 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
1448 void sqrtss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1449
1450 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
1451 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
1452 void subsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1453
1454 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
1455 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
1456 void subss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1457
1458 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1459 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1460 void ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1461
1462 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1463 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1464 void ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1465
1466 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1467 void xorpd(XMMRegister dst, XMMRegister src);
1468 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1469 void xorpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1470
1471 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1472 void xorps(XMMRegister dst, XMMRegister src);
1473 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1474 void xorps(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1475
1476 // Shuffle Bytes
1477 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1478 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
1479 void pshufb(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1480 // AVX 3-operands instructions
1481
1482 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1483 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
1484 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1485
1486 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1487 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
1488 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1489
1490 void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch = noreg);
1491 void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch = noreg);
1492
1493 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1494 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1495 void vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1496
1497 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1498 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1499
1500 void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpaddd(dst, nds, src, vector_len); }
1501 void vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpaddd(dst, nds, src, vector_len); }
1502 void vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1503
1504 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1505 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1506 void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1507
1508 using Assembler::vpbroadcastd;
1509 void vpbroadcastd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1510
1511 using Assembler::vpbroadcastq;
1512 void vpbroadcastq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1513
1514 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1515 void vpcmpeqb(XMMRegister dst, XMMRegister src1, Address src2, int vector_len);
1516
1517 void vpcmpeqw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1518 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1519 void evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1520
1521 // Vector compares
1522 void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int comparison, bool is_signed, int vector_len) {
1523 Assembler::evpcmpd(kdst, mask, nds, src, comparison, is_signed, vector_len);
1524 }
1525 void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int comparison, bool is_signed, int vector_len, Register rscratch = noreg);
1526
1527 void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int comparison, bool is_signed, int vector_len) {
1528 Assembler::evpcmpq(kdst, mask, nds, src, comparison, is_signed, vector_len);
1529 }
1530 void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int comparison, bool is_signed, int vector_len, Register rscratch = noreg);
1531
1532 void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int comparison, bool is_signed, int vector_len) {
1533 Assembler::evpcmpb(kdst, mask, nds, src, comparison, is_signed, vector_len);
1534 }
1535 void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int comparison, bool is_signed, int vector_len, Register rscratch = noreg);
1536
1537 void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int comparison, bool is_signed, int vector_len) {
1538 Assembler::evpcmpw(kdst, mask, nds, src, comparison, is_signed, vector_len);
1539 }
1540 void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int comparison, bool is_signed, int vector_len, Register rscratch = noreg);
1541
1542 void evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len);
1543
1544 // Emit comparison instruction for the specified comparison predicate.
1545 void vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len);
1546 void vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len);
1547
1548 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1549 void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vpmovzxbw(dst, src, vector_len); }
1550
1551 void vpmovmskb(Register dst, XMMRegister src, int vector_len = Assembler::AVX_256bit);
1552
1553 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1554 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1555
1556 void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpmulld(dst, nds, src, vector_len); }
1557 void vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpmulld(dst, nds, src, vector_len); }
1558 void vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1559
1560 void vpmuldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpmuldq(dst, nds, src, vector_len); }
1561
1562 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1563 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1564
1565 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1566 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1567
1568 void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1569 void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1570
1571 void evpsrad(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1572 void evpsrad(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1573
1574 void evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1575 void evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1576
1577 using Assembler::evpsllw;
1578 void evpsllw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1579 if (!is_varshift) {
1580 Assembler::evpsllw(dst, mask, nds, src, merge, vector_len);
1581 } else {
1582 Assembler::evpsllvw(dst, mask, nds, src, merge, vector_len);
1583 }
1584 }
1585 void evpslld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1586 if (!is_varshift) {
1587 Assembler::evpslld(dst, mask, nds, src, merge, vector_len);
1588 } else {
1589 Assembler::evpsllvd(dst, mask, nds, src, merge, vector_len);
1590 }
1591 }
1592 void evpsllq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1593 if (!is_varshift) {
1594 Assembler::evpsllq(dst, mask, nds, src, merge, vector_len);
1595 } else {
1596 Assembler::evpsllvq(dst, mask, nds, src, merge, vector_len);
1597 }
1598 }
1599 void evpsrlw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1600 if (!is_varshift) {
1601 Assembler::evpsrlw(dst, mask, nds, src, merge, vector_len);
1602 } else {
1603 Assembler::evpsrlvw(dst, mask, nds, src, merge, vector_len);
1604 }
1605 }
1606 void evpsrld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1607 if (!is_varshift) {
1608 Assembler::evpsrld(dst, mask, nds, src, merge, vector_len);
1609 } else {
1610 Assembler::evpsrlvd(dst, mask, nds, src, merge, vector_len);
1611 }
1612 }
1613
1614 using Assembler::evpsrlq;
1615 void evpsrlq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1616 if (!is_varshift) {
1617 Assembler::evpsrlq(dst, mask, nds, src, merge, vector_len);
1618 } else {
1619 Assembler::evpsrlvq(dst, mask, nds, src, merge, vector_len);
1620 }
1621 }
1622 using Assembler::evpsraw;
1623 void evpsraw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1624 if (!is_varshift) {
1625 Assembler::evpsraw(dst, mask, nds, src, merge, vector_len);
1626 } else {
1627 Assembler::evpsravw(dst, mask, nds, src, merge, vector_len);
1628 }
1629 }
1630 using Assembler::evpsrad;
1631 void evpsrad(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1632 if (!is_varshift) {
1633 Assembler::evpsrad(dst, mask, nds, src, merge, vector_len);
1634 } else {
1635 Assembler::evpsravd(dst, mask, nds, src, merge, vector_len);
1636 }
1637 }
1638 using Assembler::evpsraq;
1639 void evpsraq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1640 if (!is_varshift) {
1641 Assembler::evpsraq(dst, mask, nds, src, merge, vector_len);
1642 } else {
1643 Assembler::evpsravq(dst, mask, nds, src, merge, vector_len);
1644 }
1645 }
1646
1647 void evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1648 void evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1649 void evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1650 void evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1651
1652 void evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1653 void evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1654 void evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1655 void evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1656
1657 void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1658 void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1659
1660 void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1661 void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1662
1663 void vptest(XMMRegister dst, XMMRegister src);
1664 void vptest(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vptest(dst, src, vector_len); }
1665
1666 void punpcklbw(XMMRegister dst, XMMRegister src);
1667 void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1668
1669 void pshufd(XMMRegister dst, Address src, int mode);
1670 void pshufd(XMMRegister dst, XMMRegister src, int mode) { Assembler::pshufd(dst, src, mode); }
1671
1672 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1673 void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1674
1675 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1676 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1677 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1678
1679 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1680 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1681 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1682
1683 void evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1684
1685 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1686 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
1687 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1688
1689 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1690 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
1691 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1692
1693 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1694 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
1695 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1696
1697 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1698 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
1699 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1700
1701 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1702 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
1703 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1704
1705 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1706 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
1707 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1708
1709 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1710 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1711
1712 // AVX Vector instructions
1713
1714 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1715 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1716 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1717
1718 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1719 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1720 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1721
1722 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1723 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1724 Assembler::vpxor(dst, nds, src, vector_len);
1725 else
1726 Assembler::vxorpd(dst, nds, src, vector_len);
1727 }
1728 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1729 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1730 Assembler::vpxor(dst, nds, src, vector_len);
1731 else
1732 Assembler::vxorpd(dst, nds, src, vector_len);
1733 }
1734 void vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1735
1736 // Simple version for AVX2 256bit vectors
1737 void vpxor(XMMRegister dst, XMMRegister src) {
1738 assert(UseAVX >= 2, "Should be at least AVX2");
1739 Assembler::vpxor(dst, dst, src, AVX_256bit);
1740 }
1741 void vpxor(XMMRegister dst, Address src) {
1742 assert(UseAVX >= 2, "Should be at least AVX2");
1743 Assembler::vpxor(dst, dst, src, AVX_256bit);
1744 }
1745
1746 void vpermd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpermd(dst, nds, src, vector_len); }
1747 void vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1748
1749 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1750 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1751 Assembler::vinserti32x4(dst, nds, src, imm8);
1752 } else if (UseAVX > 1) {
1753 // vinserti128 is available only in AVX2
1754 Assembler::vinserti128(dst, nds, src, imm8);
1755 } else {
1756 Assembler::vinsertf128(dst, nds, src, imm8);
1757 }
1758 }
1759
1760 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1761 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1762 Assembler::vinserti32x4(dst, nds, src, imm8);
1763 } else if (UseAVX > 1) {
1764 // vinserti128 is available only in AVX2
1765 Assembler::vinserti128(dst, nds, src, imm8);
1766 } else {
1767 Assembler::vinsertf128(dst, nds, src, imm8);
1768 }
1769 }
1770
1771 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1772 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1773 Assembler::vextracti32x4(dst, src, imm8);
1774 } else if (UseAVX > 1) {
1775 // vextracti128 is available only in AVX2
1776 Assembler::vextracti128(dst, src, imm8);
1777 } else {
1778 Assembler::vextractf128(dst, src, imm8);
1779 }
1780 }
1781
1782 void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1783 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1784 Assembler::vextracti32x4(dst, src, imm8);
1785 } else if (UseAVX > 1) {
1786 // vextracti128 is available only in AVX2
1787 Assembler::vextracti128(dst, src, imm8);
1788 } else {
1789 Assembler::vextractf128(dst, src, imm8);
1790 }
1791 }
1792
1793 // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1794 void vinserti128_high(XMMRegister dst, XMMRegister src) {
1795 vinserti128(dst, dst, src, 1);
1796 }
1797 void vinserti128_high(XMMRegister dst, Address src) {
1798 vinserti128(dst, dst, src, 1);
1799 }
1800 void vextracti128_high(XMMRegister dst, XMMRegister src) {
1801 vextracti128(dst, src, 1);
1802 }
1803 void vextracti128_high(Address dst, XMMRegister src) {
1804 vextracti128(dst, src, 1);
1805 }
1806
1807 void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1808 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1809 Assembler::vinsertf32x4(dst, dst, src, 1);
1810 } else {
1811 Assembler::vinsertf128(dst, dst, src, 1);
1812 }
1813 }
1814
1815 void vinsertf128_high(XMMRegister dst, Address src) {
1816 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1817 Assembler::vinsertf32x4(dst, dst, src, 1);
1818 } else {
1819 Assembler::vinsertf128(dst, dst, src, 1);
1820 }
1821 }
1822
1823 void vextractf128_high(XMMRegister dst, XMMRegister src) {
1824 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1825 Assembler::vextractf32x4(dst, src, 1);
1826 } else {
1827 Assembler::vextractf128(dst, src, 1);
1828 }
1829 }
1830
1831 void vextractf128_high(Address dst, XMMRegister src) {
1832 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1833 Assembler::vextractf32x4(dst, src, 1);
1834 } else {
1835 Assembler::vextractf128(dst, src, 1);
1836 }
1837 }
1838
1839 // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1840 void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1841 Assembler::vinserti64x4(dst, dst, src, 1);
1842 }
1843 void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1844 Assembler::vinsertf64x4(dst, dst, src, 1);
1845 }
1846 void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1847 Assembler::vextracti64x4(dst, src, 1);
1848 }
1849 void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1850 Assembler::vextractf64x4(dst, src, 1);
1851 }
1852 void vextractf64x4_high(Address dst, XMMRegister src) {
1853 Assembler::vextractf64x4(dst, src, 1);
1854 }
1855 void vinsertf64x4_high(XMMRegister dst, Address src) {
1856 Assembler::vinsertf64x4(dst, dst, src, 1);
1857 }
1858
1859 // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1860 void vinserti128_low(XMMRegister dst, XMMRegister src) {
1861 vinserti128(dst, dst, src, 0);
1862 }
1863 void vinserti128_low(XMMRegister dst, Address src) {
1864 vinserti128(dst, dst, src, 0);
1865 }
1866 void vextracti128_low(XMMRegister dst, XMMRegister src) {
1867 vextracti128(dst, src, 0);
1868 }
1869 void vextracti128_low(Address dst, XMMRegister src) {
1870 vextracti128(dst, src, 0);
1871 }
1872
1873 void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1874 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1875 Assembler::vinsertf32x4(dst, dst, src, 0);
1876 } else {
1877 Assembler::vinsertf128(dst, dst, src, 0);
1878 }
1879 }
1880
1881 void vinsertf128_low(XMMRegister dst, Address src) {
1882 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1883 Assembler::vinsertf32x4(dst, dst, src, 0);
1884 } else {
1885 Assembler::vinsertf128(dst, dst, src, 0);
1886 }
1887 }
1888
1889 void vextractf128_low(XMMRegister dst, XMMRegister src) {
1890 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1891 Assembler::vextractf32x4(dst, src, 0);
1892 } else {
1893 Assembler::vextractf128(dst, src, 0);
1894 }
1895 }
1896
1897 void vextractf128_low(Address dst, XMMRegister src) {
1898 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1899 Assembler::vextractf32x4(dst, src, 0);
1900 } else {
1901 Assembler::vextractf128(dst, src, 0);
1902 }
1903 }
1904
1905 // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1906 void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1907 Assembler::vinserti64x4(dst, dst, src, 0);
1908 }
1909 void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1910 Assembler::vinsertf64x4(dst, dst, src, 0);
1911 }
1912 void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1913 Assembler::vextracti64x4(dst, src, 0);
1914 }
1915 void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1916 Assembler::vextractf64x4(dst, src, 0);
1917 }
1918 void vextractf64x4_low(Address dst, XMMRegister src) {
1919 Assembler::vextractf64x4(dst, src, 0);
1920 }
1921 void vinsertf64x4_low(XMMRegister dst, Address src) {
1922 Assembler::vinsertf64x4(dst, dst, src, 0);
1923 }
1924
1925 // Carry-Less Multiplication Quadword
1926 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1927 // 0x00 - multiply lower 64 bits [0:63]
1928 Assembler::vpclmulqdq(dst, nds, src, 0x00);
1929 }
1930 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1931 // 0x11 - multiply upper 64 bits [64:127]
1932 Assembler::vpclmulqdq(dst, nds, src, 0x11);
1933 }
1934 void vpclmullqhqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1935 // 0x10 - multiply nds[0:63] and src[64:127]
1936 Assembler::vpclmulqdq(dst, nds, src, 0x10);
1937 }
1938 void vpclmulhqlqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1939 //0x01 - multiply nds[64:127] and src[0:63]
1940 Assembler::vpclmulqdq(dst, nds, src, 0x01);
1941 }
1942
1943 void evpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1944 // 0x00 - multiply lower 64 bits [0:63]
1945 Assembler::evpclmulqdq(dst, nds, src, 0x00, vector_len);
1946 }
1947 void evpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1948 // 0x11 - multiply upper 64 bits [64:127]
1949 Assembler::evpclmulqdq(dst, nds, src, 0x11, vector_len);
1950 }
1951
1952 // AVX-512 mask operations.
1953 void kand(BasicType etype, KRegister dst, KRegister src1, KRegister src2);
1954 void kor(BasicType type, KRegister dst, KRegister src1, KRegister src2);
1955 void knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp = knoreg, Register rtmp = noreg);
1956 void kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2);
1957 void kortest(uint masklen, KRegister src1, KRegister src2);
1958 void ktest(uint masklen, KRegister src1, KRegister src2);
1959
1960 void evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1961 void evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1962
1963 void evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1964 void evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1965
1966 void evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1967 void evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1968
1969 void evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1970 void evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1971
1972 void evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc);
1973 void evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc);
1974 void evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc);
1975 void evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc);
1976
1977 using Assembler::evpandq;
1978 void evpandq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1979
1980 using Assembler::evpaddq;
1981 void evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1982
1983 using Assembler::evporq;
1984 void evporq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1985
1986 using Assembler::vpshufb;
1987 void vpshufb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1988
1989 using Assembler::vpor;
1990 void vpor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1991
1992 using Assembler::vpternlogq;
1993 void vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, AddressLiteral src3, int vector_len, Register rscratch = noreg);
1994
1995 void cmov32( Condition cc, Register dst, Address src);
1996 void cmov32( Condition cc, Register dst, Register src);
1997
1998 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1999
2000 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
2001 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
2002
2003 void movoop(Register dst, jobject obj);
2004 void movoop(Address dst, jobject obj, Register rscratch);
2005
2006 void mov_metadata(Register dst, Metadata* obj);
2007 void mov_metadata(Address dst, Metadata* obj, Register rscratch);
2008
2009 void movptr(Register dst, Register src);
2010 void movptr(Register dst, Address src);
2011 void movptr(Register dst, AddressLiteral src);
2012 void movptr(Register dst, ArrayAddress src);
2013 void movptr(Register dst, intptr_t src);
2014 void movptr(Address dst, Register src);
2015 void movptr(Address dst, int32_t imm);
2016 void movptr(Address dst, intptr_t src, Register rscratch);
2017 void movptr(ArrayAddress dst, Register src, Register rscratch);
2018
2019 void movptr(Register dst, RegisterOrConstant src) {
2020 if (src.is_constant()) movptr(dst, src.as_constant());
2021 else movptr(dst, src.as_register());
2022 }
2023
2024
2025 // to avoid hiding movl
2026 void mov32(Register dst, AddressLiteral src);
2027 void mov32(AddressLiteral dst, Register src, Register rscratch = noreg);
2028
2029 // Import other mov() methods from the parent class or else
2030 // they will be hidden by the following overriding declaration.
2031 using Assembler::movdl;
2032 void movdl(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
2033
2034 using Assembler::movq;
2035 void movq(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
2036
2037 // Can push value or effective address
2038 void pushptr(AddressLiteral src, Register rscratch);
2039
2040 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
2041 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
2042
2043 void pushoop(jobject obj, Register rscratch);
2044 void pushklass(Metadata* obj, Register rscratch);
2045
2046 // sign extend as need a l to ptr sized element
2047 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
2048 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
2049
2050
2051 public:
2052 // clear memory of size 'cnt' qwords, starting at 'base';
2053 // if 'is_large' is set, do not try to produce short loop
2054 void clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, bool is_large, KRegister mask=knoreg);
2055
2056 // clear memory initialization sequence for constant size;
2057 void clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask=knoreg);
2058
2059 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
2060 void xmm_clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, KRegister mask=knoreg);
2061
2062 // Fill primitive arrays
2063 void generate_fill(BasicType t, bool aligned,
2064 Register to, Register value, Register count,
2065 Register rtmp, XMMRegister xtmp);
2066
2067 void encode_iso_array(Register src, Register dst, Register len,
2068 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
2069 XMMRegister tmp4, Register tmp5, Register result, bool ascii);
2070
2071 #ifdef _LP64
2072 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
2073 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
2074 Register y, Register y_idx, Register z,
2075 Register carry, Register product,
2076 Register idx, Register kdx);
2077 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
2078 Register yz_idx, Register idx,
2079 Register carry, Register product, int offset);
2080 void multiply_128_x_128_bmi2_loop(Register y, Register z,
2081 Register carry, Register carry2,
2082 Register idx, Register jdx,
2083 Register yz_idx1, Register yz_idx2,
2084 Register tmp, Register tmp3, Register tmp4);
2085 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
2086 Register yz_idx, Register idx, Register jdx,
2087 Register carry, Register product,
2088 Register carry2);
2089 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register tmp0,
2090 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
2091 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
2092 Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
2093 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
2094 Register tmp2);
2095 void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
2096 Register rdxReg, Register raxReg);
2097 void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
2098 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
2099 Register tmp3, Register tmp4);
2100 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
2101 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
2102
2103 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
2104 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
2105 Register raxReg);
2106 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
2107 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
2108 Register raxReg);
2109 void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
2110 Register result, Register tmp1, Register tmp2,
2111 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
2112 #endif
2113
2114 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
2115 void update_byte_crc32(Register crc, Register val, Register table);
2116 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
2117
2118
2119 #ifdef _LP64
2120 void kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2);
2121 void kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register key, Register pos,
2122 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
2123 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup);
2124 #endif // _LP64
2125
2126 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
2127 // Note on a naming convention:
2128 // Prefix w = register only used on a Westmere+ architecture
2129 // Prefix n = register only used on a Nehalem architecture
2130 #ifdef _LP64
2131 void crc32c_ipl_alg4(Register in_out, uint32_t n,
2132 Register tmp1, Register tmp2, Register tmp3);
2133 #else
2134 void crc32c_ipl_alg4(Register in_out, uint32_t n,
2135 Register tmp1, Register tmp2, Register tmp3,
2136 XMMRegister xtmp1, XMMRegister xtmp2);
2137 #endif
2138 void crc32c_pclmulqdq(XMMRegister w_xtmp1,
2139 Register in_out,
2140 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
2141 XMMRegister w_xtmp2,
2142 Register tmp1,
2143 Register n_tmp2, Register n_tmp3);
2144 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
2145 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
2146 Register tmp1, Register tmp2,
2147 Register n_tmp3);
2148 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
2149 Register in_out1, Register in_out2, Register in_out3,
2150 Register tmp1, Register tmp2, Register tmp3,
2151 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
2152 Register tmp4, Register tmp5,
2153 Register n_tmp6);
2154 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
2155 Register tmp1, Register tmp2, Register tmp3,
2156 Register tmp4, Register tmp5, Register tmp6,
2157 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
2158 bool is_pclmulqdq_supported);
2159 // Fold 128-bit data chunk
2160 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
2161 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
2162 #ifdef _LP64
2163 // Fold 512-bit data chunk
2164 void fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, Register pos, int offset);
2165 #endif // _LP64
2166 // Fold 8-bit data
2167 void fold_8bit_crc32(Register crc, Register table, Register tmp);
2168 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
2169
2170 // Compress char[] array to byte[].
2171 void char_array_compress(Register src, Register dst, Register len,
2172 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
2173 XMMRegister tmp4, Register tmp5, Register result,
2174 KRegister mask1 = knoreg, KRegister mask2 = knoreg);
2175
2176 // Inflate byte[] array to char[].
2177 void byte_array_inflate(Register src, Register dst, Register len,
2178 XMMRegister tmp1, Register tmp2, KRegister mask = knoreg);
2179
2180 void fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
2181 Register length, Register temp, int vec_enc);
2182
2183 void fill64_masked(uint shift, Register dst, int disp,
2184 XMMRegister xmm, KRegister mask, Register length,
2185 Register temp, bool use64byteVector = false);
2186
2187 void fill32_masked(uint shift, Register dst, int disp,
2188 XMMRegister xmm, KRegister mask, Register length,
2189 Register temp);
2190
2191 void fill32(Address dst, XMMRegister xmm);
2192
2193 void fill32(Register dst, int disp, XMMRegister xmm);
2194
2195 void fill64(Address dst, XMMRegister xmm, bool use64byteVector = false);
2196
2197 void fill64(Register dst, int dis, XMMRegister xmm, bool use64byteVector = false);
2198
2199 #ifdef _LP64
2200 void convert_f2i(Register dst, XMMRegister src);
2201 void convert_d2i(Register dst, XMMRegister src);
2202 void convert_f2l(Register dst, XMMRegister src);
2203 void convert_d2l(Register dst, XMMRegister src);
2204 void round_double(Register dst, XMMRegister src, Register rtmp, Register rcx);
2205 void round_float(Register dst, XMMRegister src, Register rtmp, Register rcx);
2206
2207 void cache_wb(Address line);
2208 void cache_wbsync(bool is_pre);
2209
2210 #ifdef COMPILER2_OR_JVMCI
2211 void generate_fill_avx3(BasicType type, Register to, Register value,
2212 Register count, Register rtmp, XMMRegister xtmp);
2213 #endif // COMPILER2_OR_JVMCI
2214 #endif // _LP64
2215
2216 void vallones(XMMRegister dst, int vector_len);
2217
2218 void check_stack_alignment(Register sp, const char* msg, unsigned bias = 0, Register tmp = noreg);
2219
2220 void lightweight_lock(Register basic_lock, Register obj, Register reg_rax, Register thread, Register tmp, Label& slow);
2221 void lightweight_unlock(Register obj, Register reg_rax, Register thread, Register tmp, Label& slow);
2222
2223 #ifdef _LP64
2224 void save_legacy_gprs();
2225 void restore_legacy_gprs();
2226 void setcc(Assembler::Condition comparison, Register dst);
2227 #endif
2228 };
2229
2230 #endif // CPU_X86_MACROASSEMBLER_X86_HPP