1 //
2 // Copyright (c) 2003, 2024, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // architecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131 reg_def R16 (SOC, SOC, Op_RegI, 16, r16->as_VMReg());
132 reg_def R16_H(SOC, SOC, Op_RegI, 16, r16->as_VMReg()->next());
133
134 reg_def R17 (SOC, SOC, Op_RegI, 17, r17->as_VMReg());
135 reg_def R17_H(SOC, SOC, Op_RegI, 17, r17->as_VMReg()->next());
136
137 reg_def R18 (SOC, SOC, Op_RegI, 18, r18->as_VMReg());
138 reg_def R18_H(SOC, SOC, Op_RegI, 18, r18->as_VMReg()->next());
139
140 reg_def R19 (SOC, SOC, Op_RegI, 19, r19->as_VMReg());
141 reg_def R19_H(SOC, SOC, Op_RegI, 19, r19->as_VMReg()->next());
142
143 reg_def R20 (SOC, SOC, Op_RegI, 20, r20->as_VMReg());
144 reg_def R20_H(SOC, SOC, Op_RegI, 20, r20->as_VMReg()->next());
145
146 reg_def R21 (SOC, SOC, Op_RegI, 21, r21->as_VMReg());
147 reg_def R21_H(SOC, SOC, Op_RegI, 21, r21->as_VMReg()->next());
148
149 reg_def R22 (SOC, SOC, Op_RegI, 22, r22->as_VMReg());
150 reg_def R22_H(SOC, SOC, Op_RegI, 22, r22->as_VMReg()->next());
151
152 reg_def R23 (SOC, SOC, Op_RegI, 23, r23->as_VMReg());
153 reg_def R23_H(SOC, SOC, Op_RegI, 23, r23->as_VMReg()->next());
154
155 reg_def R24 (SOC, SOC, Op_RegI, 24, r24->as_VMReg());
156 reg_def R24_H(SOC, SOC, Op_RegI, 24, r24->as_VMReg()->next());
157
158 reg_def R25 (SOC, SOC, Op_RegI, 25, r25->as_VMReg());
159 reg_def R25_H(SOC, SOC, Op_RegI, 25, r25->as_VMReg()->next());
160
161 reg_def R26 (SOC, SOC, Op_RegI, 26, r26->as_VMReg());
162 reg_def R26_H(SOC, SOC, Op_RegI, 26, r26->as_VMReg()->next());
163
164 reg_def R27 (SOC, SOC, Op_RegI, 27, r27->as_VMReg());
165 reg_def R27_H(SOC, SOC, Op_RegI, 27, r27->as_VMReg()->next());
166
167 reg_def R28 (SOC, SOC, Op_RegI, 28, r28->as_VMReg());
168 reg_def R28_H(SOC, SOC, Op_RegI, 28, r28->as_VMReg()->next());
169
170 reg_def R29 (SOC, SOC, Op_RegI, 29, r29->as_VMReg());
171 reg_def R29_H(SOC, SOC, Op_RegI, 29, r29->as_VMReg()->next());
172
173 reg_def R30 (SOC, SOC, Op_RegI, 30, r30->as_VMReg());
174 reg_def R30_H(SOC, SOC, Op_RegI, 30, r30->as_VMReg()->next());
175
176 reg_def R31 (SOC, SOC, Op_RegI, 31, r31->as_VMReg());
177 reg_def R31_H(SOC, SOC, Op_RegI, 31, r31->as_VMReg()->next());
178
179 // Floating Point Registers
180
181 // Specify priority of register selection within phases of register
182 // allocation. Highest priority is first. A useful heuristic is to
183 // give registers a low priority when they are required by machine
184 // instructions, like EAX and EDX on I486, and choose no-save registers
185 // before save-on-call, & save-on-call before save-on-entry. Registers
186 // which participate in fixed calling sequences should come last.
187 // Registers which are used as pairs must fall on an even boundary.
188
189 alloc_class chunk0(R10, R10_H,
190 R11, R11_H,
191 R8, R8_H,
192 R9, R9_H,
193 R12, R12_H,
194 RCX, RCX_H,
195 RBX, RBX_H,
196 RDI, RDI_H,
197 RDX, RDX_H,
198 RSI, RSI_H,
199 RAX, RAX_H,
200 RBP, RBP_H,
201 R13, R13_H,
202 R14, R14_H,
203 R15, R15_H,
204 R16, R16_H,
205 R17, R17_H,
206 R18, R18_H,
207 R19, R19_H,
208 R20, R20_H,
209 R21, R21_H,
210 R22, R22_H,
211 R23, R23_H,
212 R24, R24_H,
213 R25, R25_H,
214 R26, R26_H,
215 R27, R27_H,
216 R28, R28_H,
217 R29, R29_H,
218 R30, R30_H,
219 R31, R31_H,
220 RSP, RSP_H);
221
222
223 //----------Architecture Description Register Classes--------------------------
224 // Several register classes are automatically defined based upon information in
225 // this architecture description.
226 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
227 // 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
228 //
229
230 // Empty register class.
231 reg_class no_reg();
232
233 // Class for all pointer/long registers including APX extended GPRs.
234 reg_class all_reg(RAX, RAX_H,
235 RDX, RDX_H,
236 RBP, RBP_H,
237 RDI, RDI_H,
238 RSI, RSI_H,
239 RCX, RCX_H,
240 RBX, RBX_H,
241 RSP, RSP_H,
242 R8, R8_H,
243 R9, R9_H,
244 R10, R10_H,
245 R11, R11_H,
246 R12, R12_H,
247 R13, R13_H,
248 R14, R14_H,
249 R15, R15_H,
250 R16, R16_H,
251 R17, R17_H,
252 R18, R18_H,
253 R19, R19_H,
254 R20, R20_H,
255 R21, R21_H,
256 R22, R22_H,
257 R23, R23_H,
258 R24, R24_H,
259 R25, R25_H,
260 R26, R26_H,
261 R27, R27_H,
262 R28, R28_H,
263 R29, R29_H,
264 R30, R30_H,
265 R31, R31_H);
266
267 // Class for all int registers including APX extended GPRs.
268 reg_class all_int_reg(RAX
269 RDX,
270 RBP,
271 RDI,
272 RSI,
273 RCX,
274 RBX,
275 R8,
276 R9,
277 R10,
278 R11,
279 R12,
280 R13,
281 R14,
282 R16,
283 R17,
284 R18,
285 R19,
286 R20,
287 R21,
288 R22,
289 R23,
290 R24,
291 R25,
292 R26,
293 R27,
294 R28,
295 R29,
296 R30,
297 R31);
298
299 // Class for all pointer registers
300 reg_class any_reg %{
301 return _ANY_REG_mask;
302 %}
303
304 // Class for all pointer registers (excluding RSP)
305 reg_class ptr_reg %{
306 return _PTR_REG_mask;
307 %}
308
309 // Class for all pointer registers (excluding RSP and RBP)
310 reg_class ptr_reg_no_rbp %{
311 return _PTR_REG_NO_RBP_mask;
312 %}
313
314 // Class for all pointer registers (excluding RAX and RSP)
315 reg_class ptr_no_rax_reg %{
316 return _PTR_NO_RAX_REG_mask;
317 %}
318
319 // Class for all pointer registers (excluding RAX, RBX, and RSP)
320 reg_class ptr_no_rax_rbx_reg %{
321 return _PTR_NO_RAX_RBX_REG_mask;
322 %}
323
324 // Class for all long registers (excluding RSP)
325 reg_class long_reg %{
326 return _LONG_REG_mask;
327 %}
328
329 // Class for all long registers (excluding RAX, RDX and RSP)
330 reg_class long_no_rax_rdx_reg %{
331 return _LONG_NO_RAX_RDX_REG_mask;
332 %}
333
334 // Class for all long registers (excluding RCX and RSP)
335 reg_class long_no_rcx_reg %{
336 return _LONG_NO_RCX_REG_mask;
337 %}
338
339 // Class for all long registers (excluding RBP and R13)
340 reg_class long_no_rbp_r13_reg %{
341 return _LONG_NO_RBP_R13_REG_mask;
342 %}
343
344 // Class for all int registers (excluding RSP)
345 reg_class int_reg %{
346 return _INT_REG_mask;
347 %}
348
349 // Class for all int registers (excluding RAX, RDX, and RSP)
350 reg_class int_no_rax_rdx_reg %{
351 return _INT_NO_RAX_RDX_REG_mask;
352 %}
353
354 // Class for all int registers (excluding RCX and RSP)
355 reg_class int_no_rcx_reg %{
356 return _INT_NO_RCX_REG_mask;
357 %}
358
359 // Class for all int registers (excluding RBP and R13)
360 reg_class int_no_rbp_r13_reg %{
361 return _INT_NO_RBP_R13_REG_mask;
362 %}
363
364 // Singleton class for RAX pointer register
365 reg_class ptr_rax_reg(RAX, RAX_H);
366
367 // Singleton class for RBX pointer register
368 reg_class ptr_rbx_reg(RBX, RBX_H);
369
370 // Singleton class for RSI pointer register
371 reg_class ptr_rsi_reg(RSI, RSI_H);
372
373 // Singleton class for RBP pointer register
374 reg_class ptr_rbp_reg(RBP, RBP_H);
375
376 // Singleton class for RDI pointer register
377 reg_class ptr_rdi_reg(RDI, RDI_H);
378
379 // Singleton class for stack pointer
380 reg_class ptr_rsp_reg(RSP, RSP_H);
381
382 // Singleton class for TLS pointer
383 reg_class ptr_r15_reg(R15, R15_H);
384
385 // Singleton class for RAX long register
386 reg_class long_rax_reg(RAX, RAX_H);
387
388 // Singleton class for RCX long register
389 reg_class long_rcx_reg(RCX, RCX_H);
390
391 // Singleton class for RDX long register
392 reg_class long_rdx_reg(RDX, RDX_H);
393
394 // Singleton class for R11 long register
395 reg_class long_r11_reg(R11, R11_H);
396
397 // Singleton class for RAX int register
398 reg_class int_rax_reg(RAX);
399
400 // Singleton class for RBX int register
401 reg_class int_rbx_reg(RBX);
402
403 // Singleton class for RCX int register
404 reg_class int_rcx_reg(RCX);
405
406 // Singleton class for RDX int register
407 reg_class int_rdx_reg(RDX);
408
409 // Singleton class for RDI int register
410 reg_class int_rdi_reg(RDI);
411
412 // Singleton class for instruction pointer
413 // reg_class ip_reg(RIP);
414
415 %}
416
417 //----------SOURCE BLOCK-------------------------------------------------------
418 // This is a block of C++ code which provides values, functions, and
419 // definitions necessary in the rest of the architecture description
420
421 source_hpp %{
422
423 #include "peephole_x86_64.hpp"
424
425 %}
426
427 // Register masks
428 source_hpp %{
429
430 extern RegMask _ANY_REG_mask;
431 extern RegMask _PTR_REG_mask;
432 extern RegMask _PTR_REG_NO_RBP_mask;
433 extern RegMask _PTR_NO_RAX_REG_mask;
434 extern RegMask _PTR_NO_RAX_RBX_REG_mask;
435 extern RegMask _LONG_REG_mask;
436 extern RegMask _LONG_NO_RAX_RDX_REG_mask;
437 extern RegMask _LONG_NO_RCX_REG_mask;
438 extern RegMask _LONG_NO_RBP_R13_REG_mask;
439 extern RegMask _INT_REG_mask;
440 extern RegMask _INT_NO_RAX_RDX_REG_mask;
441 extern RegMask _INT_NO_RCX_REG_mask;
442 extern RegMask _INT_NO_RBP_R13_REG_mask;
443 extern RegMask _FLOAT_REG_mask;
444
445 extern RegMask _STACK_OR_PTR_REG_mask;
446 extern RegMask _STACK_OR_LONG_REG_mask;
447 extern RegMask _STACK_OR_INT_REG_mask;
448
449 inline const RegMask& STACK_OR_PTR_REG_mask() { return _STACK_OR_PTR_REG_mask; }
450 inline const RegMask& STACK_OR_LONG_REG_mask() { return _STACK_OR_LONG_REG_mask; }
451 inline const RegMask& STACK_OR_INT_REG_mask() { return _STACK_OR_INT_REG_mask; }
452
453 %}
454
455 source %{
456 #define RELOC_IMM64 Assembler::imm_operand
457 #define RELOC_DISP32 Assembler::disp32_operand
458
459 #define __ masm->
460
461 RegMask _ANY_REG_mask;
462 RegMask _PTR_REG_mask;
463 RegMask _PTR_REG_NO_RBP_mask;
464 RegMask _PTR_NO_RAX_REG_mask;
465 RegMask _PTR_NO_RAX_RBX_REG_mask;
466 RegMask _LONG_REG_mask;
467 RegMask _LONG_NO_RAX_RDX_REG_mask;
468 RegMask _LONG_NO_RCX_REG_mask;
469 RegMask _LONG_NO_RBP_R13_REG_mask;
470 RegMask _INT_REG_mask;
471 RegMask _INT_NO_RAX_RDX_REG_mask;
472 RegMask _INT_NO_RCX_REG_mask;
473 RegMask _INT_NO_RBP_R13_REG_mask;
474 RegMask _FLOAT_REG_mask;
475 RegMask _STACK_OR_PTR_REG_mask;
476 RegMask _STACK_OR_LONG_REG_mask;
477 RegMask _STACK_OR_INT_REG_mask;
478
479 static bool need_r12_heapbase() {
480 return UseCompressedOops;
481 }
482
483 void reg_mask_init() {
484 constexpr Register egprs[] = {r16, r17, r18, r19, r20, r21, r22, r23, r24, r25, r26, r27, r28, r29, r30, r31};
485
486 // _ALL_REG_mask is generated by adlc from the all_reg register class below.
487 // We derive a number of subsets from it.
488 _ANY_REG_mask = _ALL_REG_mask;
489
490 if (PreserveFramePointer) {
491 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
492 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
493 }
494 if (need_r12_heapbase()) {
495 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
496 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()->next()));
497 }
498
499 _PTR_REG_mask = _ANY_REG_mask;
500 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()));
501 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()->next()));
502 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()));
503 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()->next()));
504 if (!UseAPX) {
505 for (uint i = 0; i < sizeof(egprs)/sizeof(Register); i++) {
506 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(egprs[i]->as_VMReg()));
507 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(egprs[i]->as_VMReg()->next()));
508 }
509 }
510
511 _STACK_OR_PTR_REG_mask = _PTR_REG_mask;
512 _STACK_OR_PTR_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
513
514 _PTR_REG_NO_RBP_mask = _PTR_REG_mask;
515 _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
516 _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
517
518 _PTR_NO_RAX_REG_mask = _PTR_REG_mask;
519 _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
520 _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
521
522 _PTR_NO_RAX_RBX_REG_mask = _PTR_NO_RAX_REG_mask;
523 _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()));
524 _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()->next()));
525
526
527 _LONG_REG_mask = _PTR_REG_mask;
528 _STACK_OR_LONG_REG_mask = _LONG_REG_mask;
529 _STACK_OR_LONG_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
530
531 _LONG_NO_RAX_RDX_REG_mask = _LONG_REG_mask;
532 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
533 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
534 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
535 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()->next()));
536
537 _LONG_NO_RCX_REG_mask = _LONG_REG_mask;
538 _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
539 _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()->next()));
540
541 _LONG_NO_RBP_R13_REG_mask = _LONG_REG_mask;
542 _LONG_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
543 _LONG_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
544 _LONG_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(r13->as_VMReg()));
545 _LONG_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(r13->as_VMReg()->next()));
546
547 _INT_REG_mask = _ALL_INT_REG_mask;
548 if (!UseAPX) {
549 for (uint i = 0; i < sizeof(egprs)/sizeof(Register); i++) {
550 _INT_REG_mask.Remove(OptoReg::as_OptoReg(egprs[i]->as_VMReg()));
551 }
552 }
553
554 if (PreserveFramePointer) {
555 _INT_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
556 }
557 if (need_r12_heapbase()) {
558 _INT_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
559 }
560
561 _STACK_OR_INT_REG_mask = _INT_REG_mask;
562 _STACK_OR_INT_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
563
564 _INT_NO_RAX_RDX_REG_mask = _INT_REG_mask;
565 _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
566 _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
567
568 _INT_NO_RCX_REG_mask = _INT_REG_mask;
569 _INT_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
570
571 _INT_NO_RBP_R13_REG_mask = _INT_REG_mask;
572 _INT_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
573 _INT_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(r13->as_VMReg()));
574
575 // _FLOAT_REG_LEGACY_mask/_FLOAT_REG_EVEX_mask is generated by adlc
576 // from the float_reg_legacy/float_reg_evex register class.
577 _FLOAT_REG_mask = VM_Version::supports_evex() ? _FLOAT_REG_EVEX_mask : _FLOAT_REG_LEGACY_mask;
578 }
579
580 static bool generate_vzeroupper(Compile* C) {
581 return (VM_Version::supports_vzeroupper() && (C->max_vector_size() > 16 || C->clear_upper_avx() == true)) ? true: false; // Generate vzeroupper
582 }
583
584 static int clear_avx_size() {
585 return generate_vzeroupper(Compile::current()) ? 3: 0; // vzeroupper
586 }
587
588 // !!!!! Special hack to get all types of calls to specify the byte offset
589 // from the start of the call to the point where the return address
590 // will point.
591 int MachCallStaticJavaNode::ret_addr_offset()
592 {
593 int offset = 5; // 5 bytes from start of call to where return address points
594 offset += clear_avx_size();
595 return offset;
596 }
597
598 int MachCallDynamicJavaNode::ret_addr_offset()
599 {
600 int offset = 15; // 15 bytes from start of call to where return address points
601 offset += clear_avx_size();
602 return offset;
603 }
604
605 int MachCallRuntimeNode::ret_addr_offset() {
606 int offset = 13; // movq r10,#addr; callq (r10)
607 if (this->ideal_Opcode() != Op_CallLeafVector) {
608 offset += clear_avx_size();
609 }
610 return offset;
611 }
612 //
613 // Compute padding required for nodes which need alignment
614 //
615
616 // The address of the call instruction needs to be 4-byte aligned to
617 // ensure that it does not span a cache line so that it can be patched.
618 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
619 {
620 current_offset += clear_avx_size(); // skip vzeroupper
621 current_offset += 1; // skip call opcode byte
622 return align_up(current_offset, alignment_required()) - current_offset;
623 }
624
625 // The address of the call instruction needs to be 4-byte aligned to
626 // ensure that it does not span a cache line so that it can be patched.
627 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
628 {
629 current_offset += clear_avx_size(); // skip vzeroupper
630 current_offset += 11; // skip movq instruction + call opcode byte
631 return align_up(current_offset, alignment_required()) - current_offset;
632 }
633
634 // This could be in MacroAssembler but it's fairly C2 specific
635 static void emit_cmpfp_fixup(MacroAssembler* masm) {
636 Label exit;
637 __ jccb(Assembler::noParity, exit);
638 __ pushf();
639 //
640 // comiss/ucomiss instructions set ZF,PF,CF flags and
641 // zero OF,AF,SF for NaN values.
642 // Fixup flags by zeroing ZF,PF so that compare of NaN
643 // values returns 'less than' result (CF is set).
644 // Leave the rest of flags unchanged.
645 //
646 // 7 6 5 4 3 2 1 0
647 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
648 // 0 0 1 0 1 0 1 1 (0x2B)
649 //
650 __ andq(Address(rsp, 0), 0xffffff2b);
651 __ popf();
652 __ bind(exit);
653 }
654
655 static void emit_cmpfp3(MacroAssembler* masm, Register dst) {
656 Label done;
657 __ movl(dst, -1);
658 __ jcc(Assembler::parity, done);
659 __ jcc(Assembler::below, done);
660 __ setcc(Assembler::notEqual, dst);
661 __ bind(done);
662 }
663
664 // Math.min() # Math.max()
665 // --------------------------
666 // ucomis[s/d] #
667 // ja -> b # a
668 // jp -> NaN # NaN
669 // jb -> a # b
670 // je #
671 // |-jz -> a | b # a & b
672 // | -> a #
673 static void emit_fp_min_max(MacroAssembler* masm, XMMRegister dst,
674 XMMRegister a, XMMRegister b,
675 XMMRegister xmmt, Register rt,
676 bool min, bool single) {
677
678 Label nan, zero, below, above, done;
679
680 if (single)
681 __ ucomiss(a, b);
682 else
683 __ ucomisd(a, b);
684
685 if (dst->encoding() != (min ? b : a)->encoding())
686 __ jccb(Assembler::above, above); // CF=0 & ZF=0
687 else
688 __ jccb(Assembler::above, done);
689
690 __ jccb(Assembler::parity, nan); // PF=1
691 __ jccb(Assembler::below, below); // CF=1
692
693 // equal
694 __ vpxor(xmmt, xmmt, xmmt, Assembler::AVX_128bit);
695 if (single) {
696 __ ucomiss(a, xmmt);
697 __ jccb(Assembler::equal, zero);
698
699 __ movflt(dst, a);
700 __ jmp(done);
701 }
702 else {
703 __ ucomisd(a, xmmt);
704 __ jccb(Assembler::equal, zero);
705
706 __ movdbl(dst, a);
707 __ jmp(done);
708 }
709
710 __ bind(zero);
711 if (min)
712 __ vpor(dst, a, b, Assembler::AVX_128bit);
713 else
714 __ vpand(dst, a, b, Assembler::AVX_128bit);
715
716 __ jmp(done);
717
718 __ bind(above);
719 if (single)
720 __ movflt(dst, min ? b : a);
721 else
722 __ movdbl(dst, min ? b : a);
723
724 __ jmp(done);
725
726 __ bind(nan);
727 if (single) {
728 __ movl(rt, 0x7fc00000); // Float.NaN
729 __ movdl(dst, rt);
730 }
731 else {
732 __ mov64(rt, 0x7ff8000000000000L); // Double.NaN
733 __ movdq(dst, rt);
734 }
735 __ jmp(done);
736
737 __ bind(below);
738 if (single)
739 __ movflt(dst, min ? a : b);
740 else
741 __ movdbl(dst, min ? a : b);
742
743 __ bind(done);
744 }
745
746 //=============================================================================
747 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
748
749 int ConstantTable::calculate_table_base_offset() const {
750 return 0; // absolute addressing, no offset
751 }
752
753 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
754 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
755 ShouldNotReachHere();
756 }
757
758 void MachConstantBaseNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const {
759 // Empty encoding
760 }
761
762 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
763 return 0;
764 }
765
766 #ifndef PRODUCT
767 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
768 st->print("# MachConstantBaseNode (empty encoding)");
769 }
770 #endif
771
772
773 //=============================================================================
774 #ifndef PRODUCT
775 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
776 Compile* C = ra_->C;
777
778 int framesize = C->output()->frame_size_in_bytes();
779 int bangsize = C->output()->bang_size_in_bytes();
780 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
781 // Remove wordSize for return addr which is already pushed.
782 framesize -= wordSize;
783
784 if (C->output()->need_stack_bang(bangsize)) {
785 framesize -= wordSize;
786 st->print("# stack bang (%d bytes)", bangsize);
787 st->print("\n\t");
788 st->print("pushq rbp\t# Save rbp");
789 if (PreserveFramePointer) {
790 st->print("\n\t");
791 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
792 }
793 if (framesize) {
794 st->print("\n\t");
795 st->print("subq rsp, #%d\t# Create frame",framesize);
796 }
797 } else {
798 st->print("subq rsp, #%d\t# Create frame",framesize);
799 st->print("\n\t");
800 framesize -= wordSize;
801 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
802 if (PreserveFramePointer) {
803 st->print("\n\t");
804 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
805 if (framesize > 0) {
806 st->print("\n\t");
807 st->print("addq rbp, #%d", framesize);
808 }
809 }
810 }
811
812 if (VerifyStackAtCalls) {
813 st->print("\n\t");
814 framesize -= wordSize;
815 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
816 #ifdef ASSERT
817 st->print("\n\t");
818 st->print("# stack alignment check");
819 #endif
820 }
821 if (C->stub_function() != nullptr && BarrierSet::barrier_set()->barrier_set_nmethod() != nullptr) {
822 st->print("\n\t");
823 st->print("cmpl [r15_thread + #disarmed_guard_value_offset], #disarmed_guard_value\t");
824 st->print("\n\t");
825 st->print("je fast_entry\t");
826 st->print("\n\t");
827 st->print("call #nmethod_entry_barrier_stub\t");
828 st->print("\n\tfast_entry:");
829 }
830 st->cr();
831 }
832 #endif
833
834 void MachPrologNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
835 Compile* C = ra_->C;
836
837 int framesize = C->output()->frame_size_in_bytes();
838 int bangsize = C->output()->bang_size_in_bytes();
839
840 if (C->clinit_barrier_on_entry()) {
841 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
842 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
843
844 Label L_skip_barrier;
845 Register klass = rscratch1;
846
847 __ mov_metadata(klass, C->method()->holder()->constant_encoding());
848 __ clinit_barrier(klass, r15_thread, &L_skip_barrier /*L_fast_path*/);
849
850 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); // slow path
851
852 __ bind(L_skip_barrier);
853 }
854
855 __ verified_entry(framesize, C->output()->need_stack_bang(bangsize)?bangsize:0, false, C->stub_function() != nullptr);
856
857 C->output()->set_frame_complete(__ offset());
858
859 if (C->has_mach_constant_base_node()) {
860 // NOTE: We set the table base offset here because users might be
861 // emitted before MachConstantBaseNode.
862 ConstantTable& constant_table = C->output()->constant_table();
863 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
864 }
865 }
866
867 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
868 {
869 return MachNode::size(ra_); // too many variables; just compute it
870 // the hard way
871 }
872
873 int MachPrologNode::reloc() const
874 {
875 return 0; // a large enough number
876 }
877
878 //=============================================================================
879 #ifndef PRODUCT
880 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
881 {
882 Compile* C = ra_->C;
883 if (generate_vzeroupper(C)) {
884 st->print("vzeroupper");
885 st->cr(); st->print("\t");
886 }
887
888 int framesize = C->output()->frame_size_in_bytes();
889 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
890 // Remove word for return adr already pushed
891 // and RBP
892 framesize -= 2*wordSize;
893
894 if (framesize) {
895 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
896 st->print("\t");
897 }
898
899 st->print_cr("popq rbp");
900 if (do_polling() && C->is_method_compilation()) {
901 st->print("\t");
902 st->print_cr("cmpq rsp, poll_offset[r15_thread] \n\t"
903 "ja #safepoint_stub\t"
904 "# Safepoint: poll for GC");
905 }
906 }
907 #endif
908
909 void MachEpilogNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const
910 {
911 Compile* C = ra_->C;
912
913 if (generate_vzeroupper(C)) {
914 // Clear upper bits of YMM registers when current compiled code uses
915 // wide vectors to avoid AVX <-> SSE transition penalty during call.
916 __ vzeroupper();
917 }
918
919 int framesize = C->output()->frame_size_in_bytes();
920 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
921 // Remove word for return adr already pushed
922 // and RBP
923 framesize -= 2*wordSize;
924
925 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
926
927 if (framesize) {
928 __ addq(rsp, framesize);
929 }
930
931 __ popq(rbp);
932
933 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
934 __ reserved_stack_check();
935 }
936
937 if (do_polling() && C->is_method_compilation()) {
938 Label dummy_label;
939 Label* code_stub = &dummy_label;
940 if (!C->output()->in_scratch_emit_size()) {
941 C2SafepointPollStub* stub = new (C->comp_arena()) C2SafepointPollStub(__ offset());
942 C->output()->add_stub(stub);
943 code_stub = &stub->entry();
944 }
945 __ relocate(relocInfo::poll_return_type);
946 __ safepoint_poll(*code_stub, r15_thread, true /* at_return */, true /* in_nmethod */);
947 }
948 }
949
950 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
951 {
952 return MachNode::size(ra_); // too many variables; just compute it
953 // the hard way
954 }
955
956 int MachEpilogNode::reloc() const
957 {
958 return 2; // a large enough number
959 }
960
961 const Pipeline* MachEpilogNode::pipeline() const
962 {
963 return MachNode::pipeline_class();
964 }
965
966 //=============================================================================
967
968 enum RC {
969 rc_bad,
970 rc_int,
971 rc_kreg,
972 rc_float,
973 rc_stack
974 };
975
976 static enum RC rc_class(OptoReg::Name reg)
977 {
978 if( !OptoReg::is_valid(reg) ) return rc_bad;
979
980 if (OptoReg::is_stack(reg)) return rc_stack;
981
982 VMReg r = OptoReg::as_VMReg(reg);
983
984 if (r->is_Register()) return rc_int;
985
986 if (r->is_KRegister()) return rc_kreg;
987
988 assert(r->is_XMMRegister(), "must be");
989 return rc_float;
990 }
991
992 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
993 static void vec_mov_helper(C2_MacroAssembler *masm, int src_lo, int dst_lo,
994 int src_hi, int dst_hi, uint ireg, outputStream* st);
995
996 void vec_spill_helper(C2_MacroAssembler *masm, bool is_load,
997 int stack_offset, int reg, uint ireg, outputStream* st);
998
999 static void vec_stack_to_stack_helper(C2_MacroAssembler *masm, int src_offset,
1000 int dst_offset, uint ireg, outputStream* st) {
1001 if (masm) {
1002 switch (ireg) {
1003 case Op_VecS:
1004 __ movq(Address(rsp, -8), rax);
1005 __ movl(rax, Address(rsp, src_offset));
1006 __ movl(Address(rsp, dst_offset), rax);
1007 __ movq(rax, Address(rsp, -8));
1008 break;
1009 case Op_VecD:
1010 __ pushq(Address(rsp, src_offset));
1011 __ popq (Address(rsp, dst_offset));
1012 break;
1013 case Op_VecX:
1014 __ pushq(Address(rsp, src_offset));
1015 __ popq (Address(rsp, dst_offset));
1016 __ pushq(Address(rsp, src_offset+8));
1017 __ popq (Address(rsp, dst_offset+8));
1018 break;
1019 case Op_VecY:
1020 __ vmovdqu(Address(rsp, -32), xmm0);
1021 __ vmovdqu(xmm0, Address(rsp, src_offset));
1022 __ vmovdqu(Address(rsp, dst_offset), xmm0);
1023 __ vmovdqu(xmm0, Address(rsp, -32));
1024 break;
1025 case Op_VecZ:
1026 __ evmovdquq(Address(rsp, -64), xmm0, 2);
1027 __ evmovdquq(xmm0, Address(rsp, src_offset), 2);
1028 __ evmovdquq(Address(rsp, dst_offset), xmm0, 2);
1029 __ evmovdquq(xmm0, Address(rsp, -64), 2);
1030 break;
1031 default:
1032 ShouldNotReachHere();
1033 }
1034 #ifndef PRODUCT
1035 } else {
1036 switch (ireg) {
1037 case Op_VecS:
1038 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1039 "movl rax, [rsp + #%d]\n\t"
1040 "movl [rsp + #%d], rax\n\t"
1041 "movq rax, [rsp - #8]",
1042 src_offset, dst_offset);
1043 break;
1044 case Op_VecD:
1045 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1046 "popq [rsp + #%d]",
1047 src_offset, dst_offset);
1048 break;
1049 case Op_VecX:
1050 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
1051 "popq [rsp + #%d]\n\t"
1052 "pushq [rsp + #%d]\n\t"
1053 "popq [rsp + #%d]",
1054 src_offset, dst_offset, src_offset+8, dst_offset+8);
1055 break;
1056 case Op_VecY:
1057 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
1058 "vmovdqu xmm0, [rsp + #%d]\n\t"
1059 "vmovdqu [rsp + #%d], xmm0\n\t"
1060 "vmovdqu xmm0, [rsp - #32]",
1061 src_offset, dst_offset);
1062 break;
1063 case Op_VecZ:
1064 st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
1065 "vmovdqu xmm0, [rsp + #%d]\n\t"
1066 "vmovdqu [rsp + #%d], xmm0\n\t"
1067 "vmovdqu xmm0, [rsp - #64]",
1068 src_offset, dst_offset);
1069 break;
1070 default:
1071 ShouldNotReachHere();
1072 }
1073 #endif
1074 }
1075 }
1076
1077 uint MachSpillCopyNode::implementation(C2_MacroAssembler* masm,
1078 PhaseRegAlloc* ra_,
1079 bool do_size,
1080 outputStream* st) const {
1081 assert(masm != nullptr || st != nullptr, "sanity");
1082 // Get registers to move
1083 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1084 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1085 OptoReg::Name dst_second = ra_->get_reg_second(this);
1086 OptoReg::Name dst_first = ra_->get_reg_first(this);
1087
1088 enum RC src_second_rc = rc_class(src_second);
1089 enum RC src_first_rc = rc_class(src_first);
1090 enum RC dst_second_rc = rc_class(dst_second);
1091 enum RC dst_first_rc = rc_class(dst_first);
1092
1093 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1094 "must move at least 1 register" );
1095
1096 if (src_first == dst_first && src_second == dst_second) {
1097 // Self copy, no move
1098 return 0;
1099 }
1100 if (bottom_type()->isa_vect() != nullptr && bottom_type()->isa_vectmask() == nullptr) {
1101 uint ireg = ideal_reg();
1102 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1103 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity");
1104 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1105 // mem -> mem
1106 int src_offset = ra_->reg2offset(src_first);
1107 int dst_offset = ra_->reg2offset(dst_first);
1108 vec_stack_to_stack_helper(masm, src_offset, dst_offset, ireg, st);
1109 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
1110 vec_mov_helper(masm, src_first, dst_first, src_second, dst_second, ireg, st);
1111 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1112 int stack_offset = ra_->reg2offset(dst_first);
1113 vec_spill_helper(masm, false, stack_offset, src_first, ireg, st);
1114 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
1115 int stack_offset = ra_->reg2offset(src_first);
1116 vec_spill_helper(masm, true, stack_offset, dst_first, ireg, st);
1117 } else {
1118 ShouldNotReachHere();
1119 }
1120 return 0;
1121 }
1122 if (src_first_rc == rc_stack) {
1123 // mem ->
1124 if (dst_first_rc == rc_stack) {
1125 // mem -> mem
1126 assert(src_second != dst_first, "overlap");
1127 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1128 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1129 // 64-bit
1130 int src_offset = ra_->reg2offset(src_first);
1131 int dst_offset = ra_->reg2offset(dst_first);
1132 if (masm) {
1133 __ pushq(Address(rsp, src_offset));
1134 __ popq (Address(rsp, dst_offset));
1135 #ifndef PRODUCT
1136 } else {
1137 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1138 "popq [rsp + #%d]",
1139 src_offset, dst_offset);
1140 #endif
1141 }
1142 } else {
1143 // 32-bit
1144 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1145 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1146 // No pushl/popl, so:
1147 int src_offset = ra_->reg2offset(src_first);
1148 int dst_offset = ra_->reg2offset(dst_first);
1149 if (masm) {
1150 __ movq(Address(rsp, -8), rax);
1151 __ movl(rax, Address(rsp, src_offset));
1152 __ movl(Address(rsp, dst_offset), rax);
1153 __ movq(rax, Address(rsp, -8));
1154 #ifndef PRODUCT
1155 } else {
1156 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1157 "movl rax, [rsp + #%d]\n\t"
1158 "movl [rsp + #%d], rax\n\t"
1159 "movq rax, [rsp - #8]",
1160 src_offset, dst_offset);
1161 #endif
1162 }
1163 }
1164 return 0;
1165 } else if (dst_first_rc == rc_int) {
1166 // mem -> gpr
1167 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1168 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1169 // 64-bit
1170 int offset = ra_->reg2offset(src_first);
1171 if (masm) {
1172 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1173 #ifndef PRODUCT
1174 } else {
1175 st->print("movq %s, [rsp + #%d]\t# spill",
1176 Matcher::regName[dst_first],
1177 offset);
1178 #endif
1179 }
1180 } else {
1181 // 32-bit
1182 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1183 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1184 int offset = ra_->reg2offset(src_first);
1185 if (masm) {
1186 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1187 #ifndef PRODUCT
1188 } else {
1189 st->print("movl %s, [rsp + #%d]\t# spill",
1190 Matcher::regName[dst_first],
1191 offset);
1192 #endif
1193 }
1194 }
1195 return 0;
1196 } else if (dst_first_rc == rc_float) {
1197 // mem-> xmm
1198 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1199 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1200 // 64-bit
1201 int offset = ra_->reg2offset(src_first);
1202 if (masm) {
1203 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1204 #ifndef PRODUCT
1205 } else {
1206 st->print("%s %s, [rsp + #%d]\t# spill",
1207 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1208 Matcher::regName[dst_first],
1209 offset);
1210 #endif
1211 }
1212 } else {
1213 // 32-bit
1214 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1215 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1216 int offset = ra_->reg2offset(src_first);
1217 if (masm) {
1218 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1219 #ifndef PRODUCT
1220 } else {
1221 st->print("movss %s, [rsp + #%d]\t# spill",
1222 Matcher::regName[dst_first],
1223 offset);
1224 #endif
1225 }
1226 }
1227 return 0;
1228 } else if (dst_first_rc == rc_kreg) {
1229 // mem -> kreg
1230 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1231 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1232 // 64-bit
1233 int offset = ra_->reg2offset(src_first);
1234 if (masm) {
1235 __ kmov(as_KRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1236 #ifndef PRODUCT
1237 } else {
1238 st->print("kmovq %s, [rsp + #%d]\t# spill",
1239 Matcher::regName[dst_first],
1240 offset);
1241 #endif
1242 }
1243 }
1244 return 0;
1245 }
1246 } else if (src_first_rc == rc_int) {
1247 // gpr ->
1248 if (dst_first_rc == rc_stack) {
1249 // gpr -> mem
1250 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1251 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1252 // 64-bit
1253 int offset = ra_->reg2offset(dst_first);
1254 if (masm) {
1255 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1256 #ifndef PRODUCT
1257 } else {
1258 st->print("movq [rsp + #%d], %s\t# spill",
1259 offset,
1260 Matcher::regName[src_first]);
1261 #endif
1262 }
1263 } else {
1264 // 32-bit
1265 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1266 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1267 int offset = ra_->reg2offset(dst_first);
1268 if (masm) {
1269 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1270 #ifndef PRODUCT
1271 } else {
1272 st->print("movl [rsp + #%d], %s\t# spill",
1273 offset,
1274 Matcher::regName[src_first]);
1275 #endif
1276 }
1277 }
1278 return 0;
1279 } else if (dst_first_rc == rc_int) {
1280 // gpr -> gpr
1281 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1282 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1283 // 64-bit
1284 if (masm) {
1285 __ movq(as_Register(Matcher::_regEncode[dst_first]),
1286 as_Register(Matcher::_regEncode[src_first]));
1287 #ifndef PRODUCT
1288 } else {
1289 st->print("movq %s, %s\t# spill",
1290 Matcher::regName[dst_first],
1291 Matcher::regName[src_first]);
1292 #endif
1293 }
1294 return 0;
1295 } else {
1296 // 32-bit
1297 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1298 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1299 if (masm) {
1300 __ movl(as_Register(Matcher::_regEncode[dst_first]),
1301 as_Register(Matcher::_regEncode[src_first]));
1302 #ifndef PRODUCT
1303 } else {
1304 st->print("movl %s, %s\t# spill",
1305 Matcher::regName[dst_first],
1306 Matcher::regName[src_first]);
1307 #endif
1308 }
1309 return 0;
1310 }
1311 } else if (dst_first_rc == rc_float) {
1312 // gpr -> xmm
1313 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1314 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1315 // 64-bit
1316 if (masm) {
1317 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1318 #ifndef PRODUCT
1319 } else {
1320 st->print("movdq %s, %s\t# spill",
1321 Matcher::regName[dst_first],
1322 Matcher::regName[src_first]);
1323 #endif
1324 }
1325 } else {
1326 // 32-bit
1327 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1328 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1329 if (masm) {
1330 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1331 #ifndef PRODUCT
1332 } else {
1333 st->print("movdl %s, %s\t# spill",
1334 Matcher::regName[dst_first],
1335 Matcher::regName[src_first]);
1336 #endif
1337 }
1338 }
1339 return 0;
1340 } else if (dst_first_rc == rc_kreg) {
1341 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1342 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1343 // 64-bit
1344 if (masm) {
1345 __ kmov(as_KRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1346 #ifndef PRODUCT
1347 } else {
1348 st->print("kmovq %s, %s\t# spill",
1349 Matcher::regName[dst_first],
1350 Matcher::regName[src_first]);
1351 #endif
1352 }
1353 }
1354 Unimplemented();
1355 return 0;
1356 }
1357 } else if (src_first_rc == rc_float) {
1358 // xmm ->
1359 if (dst_first_rc == rc_stack) {
1360 // xmm -> mem
1361 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1362 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1363 // 64-bit
1364 int offset = ra_->reg2offset(dst_first);
1365 if (masm) {
1366 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1367 #ifndef PRODUCT
1368 } else {
1369 st->print("movsd [rsp + #%d], %s\t# spill",
1370 offset,
1371 Matcher::regName[src_first]);
1372 #endif
1373 }
1374 } else {
1375 // 32-bit
1376 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1377 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1378 int offset = ra_->reg2offset(dst_first);
1379 if (masm) {
1380 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1381 #ifndef PRODUCT
1382 } else {
1383 st->print("movss [rsp + #%d], %s\t# spill",
1384 offset,
1385 Matcher::regName[src_first]);
1386 #endif
1387 }
1388 }
1389 return 0;
1390 } else if (dst_first_rc == rc_int) {
1391 // xmm -> gpr
1392 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1393 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1394 // 64-bit
1395 if (masm) {
1396 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1397 #ifndef PRODUCT
1398 } else {
1399 st->print("movdq %s, %s\t# spill",
1400 Matcher::regName[dst_first],
1401 Matcher::regName[src_first]);
1402 #endif
1403 }
1404 } else {
1405 // 32-bit
1406 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1407 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1408 if (masm) {
1409 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1410 #ifndef PRODUCT
1411 } else {
1412 st->print("movdl %s, %s\t# spill",
1413 Matcher::regName[dst_first],
1414 Matcher::regName[src_first]);
1415 #endif
1416 }
1417 }
1418 return 0;
1419 } else if (dst_first_rc == rc_float) {
1420 // xmm -> xmm
1421 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1422 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1423 // 64-bit
1424 if (masm) {
1425 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1426 #ifndef PRODUCT
1427 } else {
1428 st->print("%s %s, %s\t# spill",
1429 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1430 Matcher::regName[dst_first],
1431 Matcher::regName[src_first]);
1432 #endif
1433 }
1434 } else {
1435 // 32-bit
1436 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1437 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1438 if (masm) {
1439 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1440 #ifndef PRODUCT
1441 } else {
1442 st->print("%s %s, %s\t# spill",
1443 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1444 Matcher::regName[dst_first],
1445 Matcher::regName[src_first]);
1446 #endif
1447 }
1448 }
1449 return 0;
1450 } else if (dst_first_rc == rc_kreg) {
1451 assert(false, "Illegal spilling");
1452 return 0;
1453 }
1454 } else if (src_first_rc == rc_kreg) {
1455 if (dst_first_rc == rc_stack) {
1456 // mem -> kreg
1457 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1458 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1459 // 64-bit
1460 int offset = ra_->reg2offset(dst_first);
1461 if (masm) {
1462 __ kmov(Address(rsp, offset), as_KRegister(Matcher::_regEncode[src_first]));
1463 #ifndef PRODUCT
1464 } else {
1465 st->print("kmovq [rsp + #%d] , %s\t# spill",
1466 offset,
1467 Matcher::regName[src_first]);
1468 #endif
1469 }
1470 }
1471 return 0;
1472 } else if (dst_first_rc == rc_int) {
1473 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1474 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1475 // 64-bit
1476 if (masm) {
1477 __ kmov(as_Register(Matcher::_regEncode[dst_first]), as_KRegister(Matcher::_regEncode[src_first]));
1478 #ifndef PRODUCT
1479 } else {
1480 st->print("kmovq %s, %s\t# spill",
1481 Matcher::regName[dst_first],
1482 Matcher::regName[src_first]);
1483 #endif
1484 }
1485 }
1486 Unimplemented();
1487 return 0;
1488 } else if (dst_first_rc == rc_kreg) {
1489 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1490 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1491 // 64-bit
1492 if (masm) {
1493 __ kmov(as_KRegister(Matcher::_regEncode[dst_first]), as_KRegister(Matcher::_regEncode[src_first]));
1494 #ifndef PRODUCT
1495 } else {
1496 st->print("kmovq %s, %s\t# spill",
1497 Matcher::regName[dst_first],
1498 Matcher::regName[src_first]);
1499 #endif
1500 }
1501 }
1502 return 0;
1503 } else if (dst_first_rc == rc_float) {
1504 assert(false, "Illegal spill");
1505 return 0;
1506 }
1507 }
1508
1509 assert(0," foo ");
1510 Unimplemented();
1511 return 0;
1512 }
1513
1514 #ifndef PRODUCT
1515 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1516 implementation(nullptr, ra_, false, st);
1517 }
1518 #endif
1519
1520 void MachSpillCopyNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
1521 implementation(masm, ra_, false, nullptr);
1522 }
1523
1524 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1525 return MachNode::size(ra_);
1526 }
1527
1528 //=============================================================================
1529 #ifndef PRODUCT
1530 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1531 {
1532 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1533 int reg = ra_->get_reg_first(this);
1534 st->print("leaq %s, [rsp + #%d]\t# box lock",
1535 Matcher::regName[reg], offset);
1536 }
1537 #endif
1538
1539 void BoxLockNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const
1540 {
1541 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1542 int reg = ra_->get_encode(this);
1543
1544 __ lea(as_Register(reg), Address(rsp, offset));
1545 }
1546
1547 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1548 {
1549 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1550 return (offset < 0x80) ? 5 : 8; // REX
1551 }
1552
1553 //=============================================================================
1554 #ifndef PRODUCT
1555 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1556 {
1557 if (UseCompressedClassPointers) {
1558 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1559 st->print_cr("\tcmpl rscratch1, [rax + CompiledICData::speculated_klass_offset()]\t # Inline cache check");
1560 } else {
1561 st->print_cr("movq rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1562 st->print_cr("\tcmpq rscratch1, [rax + CompiledICData::speculated_klass_offset()]\t # Inline cache check");
1563 }
1564 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1565 }
1566 #endif
1567
1568 void MachUEPNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const
1569 {
1570 __ ic_check(InteriorEntryAlignment);
1571 }
1572
1573 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1574 {
1575 return MachNode::size(ra_); // too many variables; just compute it
1576 // the hard way
1577 }
1578
1579
1580 //=============================================================================
1581
1582 bool Matcher::supports_vector_calling_convention(void) {
1583 if (EnableVectorSupport && UseVectorStubs) {
1584 return true;
1585 }
1586 return false;
1587 }
1588
1589 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
1590 assert(EnableVectorSupport && UseVectorStubs, "sanity");
1591 int lo = XMM0_num;
1592 int hi = XMM0b_num;
1593 if (ideal_reg == Op_VecX) hi = XMM0d_num;
1594 else if (ideal_reg == Op_VecY) hi = XMM0h_num;
1595 else if (ideal_reg == Op_VecZ) hi = XMM0p_num;
1596 return OptoRegPair(hi, lo);
1597 }
1598
1599 // Is this branch offset short enough that a short branch can be used?
1600 //
1601 // NOTE: If the platform does not provide any short branch variants, then
1602 // this method should return false for offset 0.
1603 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1604 // The passed offset is relative to address of the branch.
1605 // On 86 a branch displacement is calculated relative to address
1606 // of a next instruction.
1607 offset -= br_size;
1608
1609 // the short version of jmpConUCF2 contains multiple branches,
1610 // making the reach slightly less
1611 if (rule == jmpConUCF2_rule)
1612 return (-126 <= offset && offset <= 125);
1613 return (-128 <= offset && offset <= 127);
1614 }
1615
1616 // Return whether or not this register is ever used as an argument.
1617 // This function is used on startup to build the trampoline stubs in
1618 // generateOptoStub. Registers not mentioned will be killed by the VM
1619 // call in the trampoline, and arguments in those registers not be
1620 // available to the callee.
1621 bool Matcher::can_be_java_arg(int reg)
1622 {
1623 return
1624 reg == RDI_num || reg == RDI_H_num ||
1625 reg == RSI_num || reg == RSI_H_num ||
1626 reg == RDX_num || reg == RDX_H_num ||
1627 reg == RCX_num || reg == RCX_H_num ||
1628 reg == R8_num || reg == R8_H_num ||
1629 reg == R9_num || reg == R9_H_num ||
1630 reg == R12_num || reg == R12_H_num ||
1631 reg == XMM0_num || reg == XMM0b_num ||
1632 reg == XMM1_num || reg == XMM1b_num ||
1633 reg == XMM2_num || reg == XMM2b_num ||
1634 reg == XMM3_num || reg == XMM3b_num ||
1635 reg == XMM4_num || reg == XMM4b_num ||
1636 reg == XMM5_num || reg == XMM5b_num ||
1637 reg == XMM6_num || reg == XMM6b_num ||
1638 reg == XMM7_num || reg == XMM7b_num;
1639 }
1640
1641 bool Matcher::is_spillable_arg(int reg)
1642 {
1643 return can_be_java_arg(reg);
1644 }
1645
1646 uint Matcher::int_pressure_limit()
1647 {
1648 return (INTPRESSURE == -1) ? _INT_REG_mask.Size() : INTPRESSURE;
1649 }
1650
1651 uint Matcher::float_pressure_limit()
1652 {
1653 // After experiment around with different values, the following default threshold
1654 // works best for LCM's register pressure scheduling on x64.
1655 uint dec_count = VM_Version::supports_evex() ? 4 : 2;
1656 uint default_float_pressure_threshold = _FLOAT_REG_mask.Size() - dec_count;
1657 return (FLOATPRESSURE == -1) ? default_float_pressure_threshold : FLOATPRESSURE;
1658 }
1659
1660 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1661 // In 64 bit mode a code which use multiply when
1662 // devisor is constant is faster than hardware
1663 // DIV instruction (it uses MulHiL).
1664 return false;
1665 }
1666
1667 // Register for DIVI projection of divmodI
1668 RegMask Matcher::divI_proj_mask() {
1669 return INT_RAX_REG_mask();
1670 }
1671
1672 // Register for MODI projection of divmodI
1673 RegMask Matcher::modI_proj_mask() {
1674 return INT_RDX_REG_mask();
1675 }
1676
1677 // Register for DIVL projection of divmodL
1678 RegMask Matcher::divL_proj_mask() {
1679 return LONG_RAX_REG_mask();
1680 }
1681
1682 // Register for MODL projection of divmodL
1683 RegMask Matcher::modL_proj_mask() {
1684 return LONG_RDX_REG_mask();
1685 }
1686
1687 // Register for saving SP into on method handle invokes. Not used on x86_64.
1688 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1689 return NO_REG_mask();
1690 }
1691
1692 %}
1693
1694 //----------ENCODING BLOCK-----------------------------------------------------
1695 // This block specifies the encoding classes used by the compiler to
1696 // output byte streams. Encoding classes are parameterized macros
1697 // used by Machine Instruction Nodes in order to generate the bit
1698 // encoding of the instruction. Operands specify their base encoding
1699 // interface with the interface keyword. There are currently
1700 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1701 // COND_INTER. REG_INTER causes an operand to generate a function
1702 // which returns its register number when queried. CONST_INTER causes
1703 // an operand to generate a function which returns the value of the
1704 // constant when queried. MEMORY_INTER causes an operand to generate
1705 // four functions which return the Base Register, the Index Register,
1706 // the Scale Value, and the Offset Value of the operand when queried.
1707 // COND_INTER causes an operand to generate six functions which return
1708 // the encoding code (ie - encoding bits for the instruction)
1709 // associated with each basic boolean condition for a conditional
1710 // instruction.
1711 //
1712 // Instructions specify two basic values for encoding. Again, a
1713 // function is available to check if the constant displacement is an
1714 // oop. They use the ins_encode keyword to specify their encoding
1715 // classes (which must be a sequence of enc_class names, and their
1716 // parameters, specified in the encoding block), and they use the
1717 // opcode keyword to specify, in order, their primary, secondary, and
1718 // tertiary opcode. Only the opcode sections which a particular
1719 // instruction needs for encoding need to be specified.
1720 encode %{
1721 enc_class cdql_enc(no_rax_rdx_RegI div)
1722 %{
1723 // Full implementation of Java idiv and irem; checks for
1724 // special case as described in JVM spec., p.243 & p.271.
1725 //
1726 // normal case special case
1727 //
1728 // input : rax: dividend min_int
1729 // reg: divisor -1
1730 //
1731 // output: rax: quotient (= rax idiv reg) min_int
1732 // rdx: remainder (= rax irem reg) 0
1733 //
1734 // Code sequnce:
1735 //
1736 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
1737 // 5: 75 07/08 jne e <normal>
1738 // 7: 33 d2 xor %edx,%edx
1739 // [div >= 8 -> offset + 1]
1740 // [REX_B]
1741 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
1742 // c: 74 03/04 je 11 <done>
1743 // 000000000000000e <normal>:
1744 // e: 99 cltd
1745 // [div >= 8 -> offset + 1]
1746 // [REX_B]
1747 // f: f7 f9 idiv $div
1748 // 0000000000000011 <done>:
1749 Label normal;
1750 Label done;
1751
1752 // cmp $0x80000000,%eax
1753 __ cmpl(as_Register(RAX_enc), 0x80000000);
1754
1755 // jne e <normal>
1756 __ jccb(Assembler::notEqual, normal);
1757
1758 // xor %edx,%edx
1759 __ xorl(as_Register(RDX_enc), as_Register(RDX_enc));
1760
1761 // cmp $0xffffffffffffffff,%ecx
1762 __ cmpl($div$$Register, -1);
1763
1764 // je 11 <done>
1765 __ jccb(Assembler::equal, done);
1766
1767 // <normal>
1768 // cltd
1769 __ bind(normal);
1770 __ cdql();
1771
1772 // idivl
1773 // <done>
1774 __ idivl($div$$Register);
1775 __ bind(done);
1776 %}
1777
1778 enc_class cdqq_enc(no_rax_rdx_RegL div)
1779 %{
1780 // Full implementation of Java ldiv and lrem; checks for
1781 // special case as described in JVM spec., p.243 & p.271.
1782 //
1783 // normal case special case
1784 //
1785 // input : rax: dividend min_long
1786 // reg: divisor -1
1787 //
1788 // output: rax: quotient (= rax idiv reg) min_long
1789 // rdx: remainder (= rax irem reg) 0
1790 //
1791 // Code sequnce:
1792 //
1793 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
1794 // 7: 00 00 80
1795 // a: 48 39 d0 cmp %rdx,%rax
1796 // d: 75 08 jne 17 <normal>
1797 // f: 33 d2 xor %edx,%edx
1798 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
1799 // 15: 74 05 je 1c <done>
1800 // 0000000000000017 <normal>:
1801 // 17: 48 99 cqto
1802 // 19: 48 f7 f9 idiv $div
1803 // 000000000000001c <done>:
1804 Label normal;
1805 Label done;
1806
1807 // mov $0x8000000000000000,%rdx
1808 __ mov64(as_Register(RDX_enc), 0x8000000000000000);
1809
1810 // cmp %rdx,%rax
1811 __ cmpq(as_Register(RAX_enc), as_Register(RDX_enc));
1812
1813 // jne 17 <normal>
1814 __ jccb(Assembler::notEqual, normal);
1815
1816 // xor %edx,%edx
1817 __ xorl(as_Register(RDX_enc), as_Register(RDX_enc));
1818
1819 // cmp $0xffffffffffffffff,$div
1820 __ cmpq($div$$Register, -1);
1821
1822 // je 1e <done>
1823 __ jccb(Assembler::equal, done);
1824
1825 // <normal>
1826 // cqto
1827 __ bind(normal);
1828 __ cdqq();
1829
1830 // idivq (note: must be emitted by the user of this rule)
1831 // <done>
1832 __ idivq($div$$Register);
1833 __ bind(done);
1834 %}
1835
1836 enc_class clear_avx %{
1837 debug_only(int off0 = __ offset());
1838 if (generate_vzeroupper(Compile::current())) {
1839 // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
1840 // Clear upper bits of YMM registers when current compiled code uses
1841 // wide vectors to avoid AVX <-> SSE transition penalty during call.
1842 __ vzeroupper();
1843 }
1844 debug_only(int off1 = __ offset());
1845 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
1846 %}
1847
1848 enc_class Java_To_Runtime(method meth) %{
1849 // No relocation needed
1850 __ mov64(r10, (int64_t) $meth$$method);
1851 __ call(r10);
1852 __ post_call_nop();
1853 %}
1854
1855 enc_class Java_Static_Call(method meth)
1856 %{
1857 // JAVA STATIC CALL
1858 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
1859 // determine who we intended to call.
1860 if (!_method) {
1861 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, $meth$$method)));
1862 } else if (_method->intrinsic_id() == vmIntrinsicID::_ensureMaterializedForStackWalk) {
1863 // The NOP here is purely to ensure that eliding a call to
1864 // JVM_EnsureMaterializedForStackWalk doesn't change the code size.
1865 __ addr_nop_5();
1866 __ block_comment("call JVM_EnsureMaterializedForStackWalk (elided)");
1867 } else {
1868 int method_index = resolved_method_index(masm);
1869 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
1870 : static_call_Relocation::spec(method_index);
1871 address mark = __ pc();
1872 int call_offset = __ offset();
1873 __ call(AddressLiteral(CAST_FROM_FN_PTR(address, $meth$$method), rspec));
1874 if (CodeBuffer::supports_shared_stubs() && _method->can_be_statically_bound()) {
1875 // Calls of the same statically bound method can share
1876 // a stub to the interpreter.
1877 __ code()->shared_stub_to_interp_for(_method, call_offset);
1878 } else {
1879 // Emit stubs for static call.
1880 address stub = CompiledDirectCall::emit_to_interp_stub(masm, mark);
1881 __ clear_inst_mark();
1882 if (stub == nullptr) {
1883 ciEnv::current()->record_failure("CodeCache is full");
1884 return;
1885 }
1886 }
1887 }
1888 __ post_call_nop();
1889 %}
1890
1891 enc_class Java_Dynamic_Call(method meth) %{
1892 __ ic_call((address)$meth$$method, resolved_method_index(masm));
1893 __ post_call_nop();
1894 %}
1895
1896 %}
1897
1898
1899
1900 //----------FRAME--------------------------------------------------------------
1901 // Definition of frame structure and management information.
1902 //
1903 // S T A C K L A Y O U T Allocators stack-slot number
1904 // | (to get allocators register number
1905 // G Owned by | | v add OptoReg::stack0())
1906 // r CALLER | |
1907 // o | +--------+ pad to even-align allocators stack-slot
1908 // w V | pad0 | numbers; owned by CALLER
1909 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
1910 // h ^ | in | 5
1911 // | | args | 4 Holes in incoming args owned by SELF
1912 // | | | | 3
1913 // | | +--------+
1914 // V | | old out| Empty on Intel, window on Sparc
1915 // | old |preserve| Must be even aligned.
1916 // | SP-+--------+----> Matcher::_old_SP, even aligned
1917 // | | in | 3 area for Intel ret address
1918 // Owned by |preserve| Empty on Sparc.
1919 // SELF +--------+
1920 // | | pad2 | 2 pad to align old SP
1921 // | +--------+ 1
1922 // | | locks | 0
1923 // | +--------+----> OptoReg::stack0(), even aligned
1924 // | | pad1 | 11 pad to align new SP
1925 // | +--------+
1926 // | | | 10
1927 // | | spills | 9 spills
1928 // V | | 8 (pad0 slot for callee)
1929 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
1930 // ^ | out | 7
1931 // | | args | 6 Holes in outgoing args owned by CALLEE
1932 // Owned by +--------+
1933 // CALLEE | new out| 6 Empty on Intel, window on Sparc
1934 // | new |preserve| Must be even-aligned.
1935 // | SP-+--------+----> Matcher::_new_SP, even aligned
1936 // | | |
1937 //
1938 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
1939 // known from SELF's arguments and the Java calling convention.
1940 // Region 6-7 is determined per call site.
1941 // Note 2: If the calling convention leaves holes in the incoming argument
1942 // area, those holes are owned by SELF. Holes in the outgoing area
1943 // are owned by the CALLEE. Holes should not be necessary in the
1944 // incoming area, as the Java calling convention is completely under
1945 // the control of the AD file. Doubles can be sorted and packed to
1946 // avoid holes. Holes in the outgoing arguments may be necessary for
1947 // varargs C calling conventions.
1948 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
1949 // even aligned with pad0 as needed.
1950 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
1951 // region 6-11 is even aligned; it may be padded out more so that
1952 // the region from SP to FP meets the minimum stack alignment.
1953 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
1954 // alignment. Region 11, pad1, may be dynamically extended so that
1955 // SP meets the minimum alignment.
1956
1957 frame
1958 %{
1959 // These three registers define part of the calling convention
1960 // between compiled code and the interpreter.
1961 inline_cache_reg(RAX); // Inline Cache Register
1962
1963 // Optional: name the operand used by cisc-spilling to access
1964 // [stack_pointer + offset]
1965 cisc_spilling_operand_name(indOffset32);
1966
1967 // Number of stack slots consumed by locking an object
1968 sync_stack_slots(2);
1969
1970 // Compiled code's Frame Pointer
1971 frame_pointer(RSP);
1972
1973 // Interpreter stores its frame pointer in a register which is
1974 // stored to the stack by I2CAdaptors.
1975 // I2CAdaptors convert from interpreted java to compiled java.
1976 interpreter_frame_pointer(RBP);
1977
1978 // Stack alignment requirement
1979 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
1980
1981 // Number of outgoing stack slots killed above the out_preserve_stack_slots
1982 // for calls to C. Supports the var-args backing area for register parms.
1983 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
1984
1985 // The after-PROLOG location of the return address. Location of
1986 // return address specifies a type (REG or STACK) and a number
1987 // representing the register number (i.e. - use a register name) or
1988 // stack slot.
1989 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
1990 // Otherwise, it is above the locks and verification slot and alignment word
1991 return_addr(STACK - 2 +
1992 align_up((Compile::current()->in_preserve_stack_slots() +
1993 Compile::current()->fixed_slots()),
1994 stack_alignment_in_slots()));
1995
1996 // Location of compiled Java return values. Same as C for now.
1997 return_value
1998 %{
1999 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2000 "only return normal values");
2001
2002 static const int lo[Op_RegL + 1] = {
2003 0,
2004 0,
2005 RAX_num, // Op_RegN
2006 RAX_num, // Op_RegI
2007 RAX_num, // Op_RegP
2008 XMM0_num, // Op_RegF
2009 XMM0_num, // Op_RegD
2010 RAX_num // Op_RegL
2011 };
2012 static const int hi[Op_RegL + 1] = {
2013 0,
2014 0,
2015 OptoReg::Bad, // Op_RegN
2016 OptoReg::Bad, // Op_RegI
2017 RAX_H_num, // Op_RegP
2018 OptoReg::Bad, // Op_RegF
2019 XMM0b_num, // Op_RegD
2020 RAX_H_num // Op_RegL
2021 };
2022 // Excluded flags and vector registers.
2023 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 8, "missing type");
2024 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2025 %}
2026 %}
2027
2028 //----------ATTRIBUTES---------------------------------------------------------
2029 //----------Operand Attributes-------------------------------------------------
2030 op_attrib op_cost(0); // Required cost attribute
2031
2032 //----------Instruction Attributes---------------------------------------------
2033 ins_attrib ins_cost(100); // Required cost attribute
2034 ins_attrib ins_size(8); // Required size attribute (in bits)
2035 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2036 // a non-matching short branch variant
2037 // of some long branch?
2038 ins_attrib ins_alignment(1); // Required alignment attribute (must
2039 // be a power of 2) specifies the
2040 // alignment that some part of the
2041 // instruction (not necessarily the
2042 // start) requires. If > 1, a
2043 // compute_padding() function must be
2044 // provided for the instruction
2045
2046 //----------OPERANDS-----------------------------------------------------------
2047 // Operand definitions must precede instruction definitions for correct parsing
2048 // in the ADLC because operands constitute user defined types which are used in
2049 // instruction definitions.
2050
2051 //----------Simple Operands----------------------------------------------------
2052 // Immediate Operands
2053 // Integer Immediate
2054 operand immI()
2055 %{
2056 match(ConI);
2057
2058 op_cost(10);
2059 format %{ %}
2060 interface(CONST_INTER);
2061 %}
2062
2063 // Constant for test vs zero
2064 operand immI_0()
2065 %{
2066 predicate(n->get_int() == 0);
2067 match(ConI);
2068
2069 op_cost(0);
2070 format %{ %}
2071 interface(CONST_INTER);
2072 %}
2073
2074 // Constant for increment
2075 operand immI_1()
2076 %{
2077 predicate(n->get_int() == 1);
2078 match(ConI);
2079
2080 op_cost(0);
2081 format %{ %}
2082 interface(CONST_INTER);
2083 %}
2084
2085 // Constant for decrement
2086 operand immI_M1()
2087 %{
2088 predicate(n->get_int() == -1);
2089 match(ConI);
2090
2091 op_cost(0);
2092 format %{ %}
2093 interface(CONST_INTER);
2094 %}
2095
2096 operand immI_2()
2097 %{
2098 predicate(n->get_int() == 2);
2099 match(ConI);
2100
2101 op_cost(0);
2102 format %{ %}
2103 interface(CONST_INTER);
2104 %}
2105
2106 operand immI_4()
2107 %{
2108 predicate(n->get_int() == 4);
2109 match(ConI);
2110
2111 op_cost(0);
2112 format %{ %}
2113 interface(CONST_INTER);
2114 %}
2115
2116 operand immI_8()
2117 %{
2118 predicate(n->get_int() == 8);
2119 match(ConI);
2120
2121 op_cost(0);
2122 format %{ %}
2123 interface(CONST_INTER);
2124 %}
2125
2126 // Valid scale values for addressing modes
2127 operand immI2()
2128 %{
2129 predicate(0 <= n->get_int() && (n->get_int() <= 3));
2130 match(ConI);
2131
2132 format %{ %}
2133 interface(CONST_INTER);
2134 %}
2135
2136 operand immU7()
2137 %{
2138 predicate((0 <= n->get_int()) && (n->get_int() <= 0x7F));
2139 match(ConI);
2140
2141 op_cost(5);
2142 format %{ %}
2143 interface(CONST_INTER);
2144 %}
2145
2146 operand immI8()
2147 %{
2148 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2149 match(ConI);
2150
2151 op_cost(5);
2152 format %{ %}
2153 interface(CONST_INTER);
2154 %}
2155
2156 operand immU8()
2157 %{
2158 predicate((0 <= n->get_int()) && (n->get_int() <= 255));
2159 match(ConI);
2160
2161 op_cost(5);
2162 format %{ %}
2163 interface(CONST_INTER);
2164 %}
2165
2166 operand immI16()
2167 %{
2168 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
2169 match(ConI);
2170
2171 op_cost(10);
2172 format %{ %}
2173 interface(CONST_INTER);
2174 %}
2175
2176 // Int Immediate non-negative
2177 operand immU31()
2178 %{
2179 predicate(n->get_int() >= 0);
2180 match(ConI);
2181
2182 op_cost(0);
2183 format %{ %}
2184 interface(CONST_INTER);
2185 %}
2186
2187 // Pointer Immediate
2188 operand immP()
2189 %{
2190 match(ConP);
2191
2192 op_cost(10);
2193 format %{ %}
2194 interface(CONST_INTER);
2195 %}
2196
2197 // Null Pointer Immediate
2198 operand immP0()
2199 %{
2200 predicate(n->get_ptr() == 0);
2201 match(ConP);
2202
2203 op_cost(5);
2204 format %{ %}
2205 interface(CONST_INTER);
2206 %}
2207
2208 // Pointer Immediate
2209 operand immN() %{
2210 match(ConN);
2211
2212 op_cost(10);
2213 format %{ %}
2214 interface(CONST_INTER);
2215 %}
2216
2217 operand immNKlass() %{
2218 match(ConNKlass);
2219
2220 op_cost(10);
2221 format %{ %}
2222 interface(CONST_INTER);
2223 %}
2224
2225 // Null Pointer Immediate
2226 operand immN0() %{
2227 predicate(n->get_narrowcon() == 0);
2228 match(ConN);
2229
2230 op_cost(5);
2231 format %{ %}
2232 interface(CONST_INTER);
2233 %}
2234
2235 operand immP31()
2236 %{
2237 predicate(n->as_Type()->type()->reloc() == relocInfo::none
2238 && (n->get_ptr() >> 31) == 0);
2239 match(ConP);
2240
2241 op_cost(5);
2242 format %{ %}
2243 interface(CONST_INTER);
2244 %}
2245
2246
2247 // Long Immediate
2248 operand immL()
2249 %{
2250 match(ConL);
2251
2252 op_cost(20);
2253 format %{ %}
2254 interface(CONST_INTER);
2255 %}
2256
2257 // Long Immediate 8-bit
2258 operand immL8()
2259 %{
2260 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
2261 match(ConL);
2262
2263 op_cost(5);
2264 format %{ %}
2265 interface(CONST_INTER);
2266 %}
2267
2268 // Long Immediate 32-bit unsigned
2269 operand immUL32()
2270 %{
2271 predicate(n->get_long() == (unsigned int) (n->get_long()));
2272 match(ConL);
2273
2274 op_cost(10);
2275 format %{ %}
2276 interface(CONST_INTER);
2277 %}
2278
2279 // Long Immediate 32-bit signed
2280 operand immL32()
2281 %{
2282 predicate(n->get_long() == (int) (n->get_long()));
2283 match(ConL);
2284
2285 op_cost(15);
2286 format %{ %}
2287 interface(CONST_INTER);
2288 %}
2289
2290 operand immL_Pow2()
2291 %{
2292 predicate(is_power_of_2((julong)n->get_long()));
2293 match(ConL);
2294
2295 op_cost(15);
2296 format %{ %}
2297 interface(CONST_INTER);
2298 %}
2299
2300 operand immL_NotPow2()
2301 %{
2302 predicate(is_power_of_2((julong)~n->get_long()));
2303 match(ConL);
2304
2305 op_cost(15);
2306 format %{ %}
2307 interface(CONST_INTER);
2308 %}
2309
2310 // Long Immediate zero
2311 operand immL0()
2312 %{
2313 predicate(n->get_long() == 0L);
2314 match(ConL);
2315
2316 op_cost(10);
2317 format %{ %}
2318 interface(CONST_INTER);
2319 %}
2320
2321 // Constant for increment
2322 operand immL1()
2323 %{
2324 predicate(n->get_long() == 1);
2325 match(ConL);
2326
2327 format %{ %}
2328 interface(CONST_INTER);
2329 %}
2330
2331 // Constant for decrement
2332 operand immL_M1()
2333 %{
2334 predicate(n->get_long() == -1);
2335 match(ConL);
2336
2337 format %{ %}
2338 interface(CONST_INTER);
2339 %}
2340
2341 // Long Immediate: low 32-bit mask
2342 operand immL_32bits()
2343 %{
2344 predicate(n->get_long() == 0xFFFFFFFFL);
2345 match(ConL);
2346 op_cost(20);
2347
2348 format %{ %}
2349 interface(CONST_INTER);
2350 %}
2351
2352 // Int Immediate: 2^n-1, positive
2353 operand immI_Pow2M1()
2354 %{
2355 predicate((n->get_int() > 0)
2356 && is_power_of_2((juint)n->get_int() + 1));
2357 match(ConI);
2358
2359 op_cost(20);
2360 format %{ %}
2361 interface(CONST_INTER);
2362 %}
2363
2364 // Float Immediate zero
2365 operand immF0()
2366 %{
2367 predicate(jint_cast(n->getf()) == 0);
2368 match(ConF);
2369
2370 op_cost(5);
2371 format %{ %}
2372 interface(CONST_INTER);
2373 %}
2374
2375 // Float Immediate
2376 operand immF()
2377 %{
2378 match(ConF);
2379
2380 op_cost(15);
2381 format %{ %}
2382 interface(CONST_INTER);
2383 %}
2384
2385 // Double Immediate zero
2386 operand immD0()
2387 %{
2388 predicate(jlong_cast(n->getd()) == 0);
2389 match(ConD);
2390
2391 op_cost(5);
2392 format %{ %}
2393 interface(CONST_INTER);
2394 %}
2395
2396 // Double Immediate
2397 operand immD()
2398 %{
2399 match(ConD);
2400
2401 op_cost(15);
2402 format %{ %}
2403 interface(CONST_INTER);
2404 %}
2405
2406 // Immediates for special shifts (sign extend)
2407
2408 // Constants for increment
2409 operand immI_16()
2410 %{
2411 predicate(n->get_int() == 16);
2412 match(ConI);
2413
2414 format %{ %}
2415 interface(CONST_INTER);
2416 %}
2417
2418 operand immI_24()
2419 %{
2420 predicate(n->get_int() == 24);
2421 match(ConI);
2422
2423 format %{ %}
2424 interface(CONST_INTER);
2425 %}
2426
2427 // Constant for byte-wide masking
2428 operand immI_255()
2429 %{
2430 predicate(n->get_int() == 255);
2431 match(ConI);
2432
2433 format %{ %}
2434 interface(CONST_INTER);
2435 %}
2436
2437 // Constant for short-wide masking
2438 operand immI_65535()
2439 %{
2440 predicate(n->get_int() == 65535);
2441 match(ConI);
2442
2443 format %{ %}
2444 interface(CONST_INTER);
2445 %}
2446
2447 // Constant for byte-wide masking
2448 operand immL_255()
2449 %{
2450 predicate(n->get_long() == 255);
2451 match(ConL);
2452
2453 format %{ %}
2454 interface(CONST_INTER);
2455 %}
2456
2457 // Constant for short-wide masking
2458 operand immL_65535()
2459 %{
2460 predicate(n->get_long() == 65535);
2461 match(ConL);
2462
2463 format %{ %}
2464 interface(CONST_INTER);
2465 %}
2466
2467 operand kReg()
2468 %{
2469 constraint(ALLOC_IN_RC(vectmask_reg));
2470 match(RegVectMask);
2471 format %{%}
2472 interface(REG_INTER);
2473 %}
2474
2475 // Register Operands
2476 // Integer Register
2477 operand rRegI()
2478 %{
2479 constraint(ALLOC_IN_RC(int_reg));
2480 match(RegI);
2481
2482 match(rax_RegI);
2483 match(rbx_RegI);
2484 match(rcx_RegI);
2485 match(rdx_RegI);
2486 match(rdi_RegI);
2487
2488 format %{ %}
2489 interface(REG_INTER);
2490 %}
2491
2492 // Special Registers
2493 operand rax_RegI()
2494 %{
2495 constraint(ALLOC_IN_RC(int_rax_reg));
2496 match(RegI);
2497 match(rRegI);
2498
2499 format %{ "RAX" %}
2500 interface(REG_INTER);
2501 %}
2502
2503 // Special Registers
2504 operand rbx_RegI()
2505 %{
2506 constraint(ALLOC_IN_RC(int_rbx_reg));
2507 match(RegI);
2508 match(rRegI);
2509
2510 format %{ "RBX" %}
2511 interface(REG_INTER);
2512 %}
2513
2514 operand rcx_RegI()
2515 %{
2516 constraint(ALLOC_IN_RC(int_rcx_reg));
2517 match(RegI);
2518 match(rRegI);
2519
2520 format %{ "RCX" %}
2521 interface(REG_INTER);
2522 %}
2523
2524 operand rdx_RegI()
2525 %{
2526 constraint(ALLOC_IN_RC(int_rdx_reg));
2527 match(RegI);
2528 match(rRegI);
2529
2530 format %{ "RDX" %}
2531 interface(REG_INTER);
2532 %}
2533
2534 operand rdi_RegI()
2535 %{
2536 constraint(ALLOC_IN_RC(int_rdi_reg));
2537 match(RegI);
2538 match(rRegI);
2539
2540 format %{ "RDI" %}
2541 interface(REG_INTER);
2542 %}
2543
2544 operand no_rax_rdx_RegI()
2545 %{
2546 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
2547 match(RegI);
2548 match(rbx_RegI);
2549 match(rcx_RegI);
2550 match(rdi_RegI);
2551
2552 format %{ %}
2553 interface(REG_INTER);
2554 %}
2555
2556 operand no_rbp_r13_RegI()
2557 %{
2558 constraint(ALLOC_IN_RC(int_no_rbp_r13_reg));
2559 match(RegI);
2560 match(rRegI);
2561 match(rax_RegI);
2562 match(rbx_RegI);
2563 match(rcx_RegI);
2564 match(rdx_RegI);
2565 match(rdi_RegI);
2566
2567 format %{ %}
2568 interface(REG_INTER);
2569 %}
2570
2571 // Pointer Register
2572 operand any_RegP()
2573 %{
2574 constraint(ALLOC_IN_RC(any_reg));
2575 match(RegP);
2576 match(rax_RegP);
2577 match(rbx_RegP);
2578 match(rdi_RegP);
2579 match(rsi_RegP);
2580 match(rbp_RegP);
2581 match(r15_RegP);
2582 match(rRegP);
2583
2584 format %{ %}
2585 interface(REG_INTER);
2586 %}
2587
2588 operand rRegP()
2589 %{
2590 constraint(ALLOC_IN_RC(ptr_reg));
2591 match(RegP);
2592 match(rax_RegP);
2593 match(rbx_RegP);
2594 match(rdi_RegP);
2595 match(rsi_RegP);
2596 match(rbp_RegP); // See Q&A below about
2597 match(r15_RegP); // r15_RegP and rbp_RegP.
2598
2599 format %{ %}
2600 interface(REG_INTER);
2601 %}
2602
2603 operand rRegN() %{
2604 constraint(ALLOC_IN_RC(int_reg));
2605 match(RegN);
2606
2607 format %{ %}
2608 interface(REG_INTER);
2609 %}
2610
2611 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
2612 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
2613 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
2614 // The output of an instruction is controlled by the allocator, which respects
2615 // register class masks, not match rules. Unless an instruction mentions
2616 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
2617 // by the allocator as an input.
2618 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
2619 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
2620 // result, RBP is not included in the output of the instruction either.
2621
2622 // This operand is not allowed to use RBP even if
2623 // RBP is not used to hold the frame pointer.
2624 operand no_rbp_RegP()
2625 %{
2626 constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
2627 match(RegP);
2628 match(rbx_RegP);
2629 match(rsi_RegP);
2630 match(rdi_RegP);
2631
2632 format %{ %}
2633 interface(REG_INTER);
2634 %}
2635
2636 // Special Registers
2637 // Return a pointer value
2638 operand rax_RegP()
2639 %{
2640 constraint(ALLOC_IN_RC(ptr_rax_reg));
2641 match(RegP);
2642 match(rRegP);
2643
2644 format %{ %}
2645 interface(REG_INTER);
2646 %}
2647
2648 // Special Registers
2649 // Return a compressed pointer value
2650 operand rax_RegN()
2651 %{
2652 constraint(ALLOC_IN_RC(int_rax_reg));
2653 match(RegN);
2654 match(rRegN);
2655
2656 format %{ %}
2657 interface(REG_INTER);
2658 %}
2659
2660 // Used in AtomicAdd
2661 operand rbx_RegP()
2662 %{
2663 constraint(ALLOC_IN_RC(ptr_rbx_reg));
2664 match(RegP);
2665 match(rRegP);
2666
2667 format %{ %}
2668 interface(REG_INTER);
2669 %}
2670
2671 operand rsi_RegP()
2672 %{
2673 constraint(ALLOC_IN_RC(ptr_rsi_reg));
2674 match(RegP);
2675 match(rRegP);
2676
2677 format %{ %}
2678 interface(REG_INTER);
2679 %}
2680
2681 operand rbp_RegP()
2682 %{
2683 constraint(ALLOC_IN_RC(ptr_rbp_reg));
2684 match(RegP);
2685 match(rRegP);
2686
2687 format %{ %}
2688 interface(REG_INTER);
2689 %}
2690
2691 // Used in rep stosq
2692 operand rdi_RegP()
2693 %{
2694 constraint(ALLOC_IN_RC(ptr_rdi_reg));
2695 match(RegP);
2696 match(rRegP);
2697
2698 format %{ %}
2699 interface(REG_INTER);
2700 %}
2701
2702 operand r15_RegP()
2703 %{
2704 constraint(ALLOC_IN_RC(ptr_r15_reg));
2705 match(RegP);
2706 match(rRegP);
2707
2708 format %{ %}
2709 interface(REG_INTER);
2710 %}
2711
2712 operand rRegL()
2713 %{
2714 constraint(ALLOC_IN_RC(long_reg));
2715 match(RegL);
2716 match(rax_RegL);
2717 match(rdx_RegL);
2718
2719 format %{ %}
2720 interface(REG_INTER);
2721 %}
2722
2723 // Special Registers
2724 operand no_rax_rdx_RegL()
2725 %{
2726 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
2727 match(RegL);
2728 match(rRegL);
2729
2730 format %{ %}
2731 interface(REG_INTER);
2732 %}
2733
2734 operand rax_RegL()
2735 %{
2736 constraint(ALLOC_IN_RC(long_rax_reg));
2737 match(RegL);
2738 match(rRegL);
2739
2740 format %{ "RAX" %}
2741 interface(REG_INTER);
2742 %}
2743
2744 operand rcx_RegL()
2745 %{
2746 constraint(ALLOC_IN_RC(long_rcx_reg));
2747 match(RegL);
2748 match(rRegL);
2749
2750 format %{ %}
2751 interface(REG_INTER);
2752 %}
2753
2754 operand rdx_RegL()
2755 %{
2756 constraint(ALLOC_IN_RC(long_rdx_reg));
2757 match(RegL);
2758 match(rRegL);
2759
2760 format %{ %}
2761 interface(REG_INTER);
2762 %}
2763
2764 operand r11_RegL()
2765 %{
2766 constraint(ALLOC_IN_RC(long_r11_reg));
2767 match(RegL);
2768 match(rRegL);
2769
2770 format %{ %}
2771 interface(REG_INTER);
2772 %}
2773
2774 operand no_rbp_r13_RegL()
2775 %{
2776 constraint(ALLOC_IN_RC(long_no_rbp_r13_reg));
2777 match(RegL);
2778 match(rRegL);
2779 match(rax_RegL);
2780 match(rcx_RegL);
2781 match(rdx_RegL);
2782
2783 format %{ %}
2784 interface(REG_INTER);
2785 %}
2786
2787 // Flags register, used as output of compare instructions
2788 operand rFlagsReg()
2789 %{
2790 constraint(ALLOC_IN_RC(int_flags));
2791 match(RegFlags);
2792
2793 format %{ "RFLAGS" %}
2794 interface(REG_INTER);
2795 %}
2796
2797 // Flags register, used as output of FLOATING POINT compare instructions
2798 operand rFlagsRegU()
2799 %{
2800 constraint(ALLOC_IN_RC(int_flags));
2801 match(RegFlags);
2802
2803 format %{ "RFLAGS_U" %}
2804 interface(REG_INTER);
2805 %}
2806
2807 operand rFlagsRegUCF() %{
2808 constraint(ALLOC_IN_RC(int_flags));
2809 match(RegFlags);
2810 predicate(false);
2811
2812 format %{ "RFLAGS_U_CF" %}
2813 interface(REG_INTER);
2814 %}
2815
2816 // Float register operands
2817 operand regF() %{
2818 constraint(ALLOC_IN_RC(float_reg));
2819 match(RegF);
2820
2821 format %{ %}
2822 interface(REG_INTER);
2823 %}
2824
2825 // Float register operands
2826 operand legRegF() %{
2827 constraint(ALLOC_IN_RC(float_reg_legacy));
2828 match(RegF);
2829
2830 format %{ %}
2831 interface(REG_INTER);
2832 %}
2833
2834 // Float register operands
2835 operand vlRegF() %{
2836 constraint(ALLOC_IN_RC(float_reg_vl));
2837 match(RegF);
2838
2839 format %{ %}
2840 interface(REG_INTER);
2841 %}
2842
2843 // Double register operands
2844 operand regD() %{
2845 constraint(ALLOC_IN_RC(double_reg));
2846 match(RegD);
2847
2848 format %{ %}
2849 interface(REG_INTER);
2850 %}
2851
2852 // Double register operands
2853 operand legRegD() %{
2854 constraint(ALLOC_IN_RC(double_reg_legacy));
2855 match(RegD);
2856
2857 format %{ %}
2858 interface(REG_INTER);
2859 %}
2860
2861 // Double register operands
2862 operand vlRegD() %{
2863 constraint(ALLOC_IN_RC(double_reg_vl));
2864 match(RegD);
2865
2866 format %{ %}
2867 interface(REG_INTER);
2868 %}
2869
2870 //----------Memory Operands----------------------------------------------------
2871 // Direct Memory Operand
2872 // operand direct(immP addr)
2873 // %{
2874 // match(addr);
2875
2876 // format %{ "[$addr]" %}
2877 // interface(MEMORY_INTER) %{
2878 // base(0xFFFFFFFF);
2879 // index(0x4);
2880 // scale(0x0);
2881 // disp($addr);
2882 // %}
2883 // %}
2884
2885 // Indirect Memory Operand
2886 operand indirect(any_RegP reg)
2887 %{
2888 constraint(ALLOC_IN_RC(ptr_reg));
2889 match(reg);
2890
2891 format %{ "[$reg]" %}
2892 interface(MEMORY_INTER) %{
2893 base($reg);
2894 index(0x4);
2895 scale(0x0);
2896 disp(0x0);
2897 %}
2898 %}
2899
2900 // Indirect Memory Plus Short Offset Operand
2901 operand indOffset8(any_RegP reg, immL8 off)
2902 %{
2903 constraint(ALLOC_IN_RC(ptr_reg));
2904 match(AddP reg off);
2905
2906 format %{ "[$reg + $off (8-bit)]" %}
2907 interface(MEMORY_INTER) %{
2908 base($reg);
2909 index(0x4);
2910 scale(0x0);
2911 disp($off);
2912 %}
2913 %}
2914
2915 // Indirect Memory Plus Long Offset Operand
2916 operand indOffset32(any_RegP reg, immL32 off)
2917 %{
2918 constraint(ALLOC_IN_RC(ptr_reg));
2919 match(AddP reg off);
2920
2921 format %{ "[$reg + $off (32-bit)]" %}
2922 interface(MEMORY_INTER) %{
2923 base($reg);
2924 index(0x4);
2925 scale(0x0);
2926 disp($off);
2927 %}
2928 %}
2929
2930 // Indirect Memory Plus Index Register Plus Offset Operand
2931 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
2932 %{
2933 constraint(ALLOC_IN_RC(ptr_reg));
2934 match(AddP (AddP reg lreg) off);
2935
2936 op_cost(10);
2937 format %{"[$reg + $off + $lreg]" %}
2938 interface(MEMORY_INTER) %{
2939 base($reg);
2940 index($lreg);
2941 scale(0x0);
2942 disp($off);
2943 %}
2944 %}
2945
2946 // Indirect Memory Plus Index Register Plus Offset Operand
2947 operand indIndex(any_RegP reg, rRegL lreg)
2948 %{
2949 constraint(ALLOC_IN_RC(ptr_reg));
2950 match(AddP reg lreg);
2951
2952 op_cost(10);
2953 format %{"[$reg + $lreg]" %}
2954 interface(MEMORY_INTER) %{
2955 base($reg);
2956 index($lreg);
2957 scale(0x0);
2958 disp(0x0);
2959 %}
2960 %}
2961
2962 // Indirect Memory Times Scale Plus Index Register
2963 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
2964 %{
2965 constraint(ALLOC_IN_RC(ptr_reg));
2966 match(AddP reg (LShiftL lreg scale));
2967
2968 op_cost(10);
2969 format %{"[$reg + $lreg << $scale]" %}
2970 interface(MEMORY_INTER) %{
2971 base($reg);
2972 index($lreg);
2973 scale($scale);
2974 disp(0x0);
2975 %}
2976 %}
2977
2978 operand indPosIndexScale(any_RegP reg, rRegI idx, immI2 scale)
2979 %{
2980 constraint(ALLOC_IN_RC(ptr_reg));
2981 predicate(n->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
2982 match(AddP reg (LShiftL (ConvI2L idx) scale));
2983
2984 op_cost(10);
2985 format %{"[$reg + pos $idx << $scale]" %}
2986 interface(MEMORY_INTER) %{
2987 base($reg);
2988 index($idx);
2989 scale($scale);
2990 disp(0x0);
2991 %}
2992 %}
2993
2994 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
2995 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
2996 %{
2997 constraint(ALLOC_IN_RC(ptr_reg));
2998 match(AddP (AddP reg (LShiftL lreg scale)) off);
2999
3000 op_cost(10);
3001 format %{"[$reg + $off + $lreg << $scale]" %}
3002 interface(MEMORY_INTER) %{
3003 base($reg);
3004 index($lreg);
3005 scale($scale);
3006 disp($off);
3007 %}
3008 %}
3009
3010 // Indirect Memory Plus Positive Index Register Plus Offset Operand
3011 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
3012 %{
3013 constraint(ALLOC_IN_RC(ptr_reg));
3014 predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3015 match(AddP (AddP reg (ConvI2L idx)) off);
3016
3017 op_cost(10);
3018 format %{"[$reg + $off + $idx]" %}
3019 interface(MEMORY_INTER) %{
3020 base($reg);
3021 index($idx);
3022 scale(0x0);
3023 disp($off);
3024 %}
3025 %}
3026
3027 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3028 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3029 %{
3030 constraint(ALLOC_IN_RC(ptr_reg));
3031 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3032 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3033
3034 op_cost(10);
3035 format %{"[$reg + $off + $idx << $scale]" %}
3036 interface(MEMORY_INTER) %{
3037 base($reg);
3038 index($idx);
3039 scale($scale);
3040 disp($off);
3041 %}
3042 %}
3043
3044 // Indirect Narrow Oop Plus Offset Operand
3045 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3046 // we can't free r12 even with CompressedOops::base() == nullptr.
3047 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3048 predicate(UseCompressedOops && (CompressedOops::shift() == Address::times_8));
3049 constraint(ALLOC_IN_RC(ptr_reg));
3050 match(AddP (DecodeN reg) off);
3051
3052 op_cost(10);
3053 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3054 interface(MEMORY_INTER) %{
3055 base(0xc); // R12
3056 index($reg);
3057 scale(0x3);
3058 disp($off);
3059 %}
3060 %}
3061
3062 // Indirect Memory Operand
3063 operand indirectNarrow(rRegN reg)
3064 %{
3065 predicate(CompressedOops::shift() == 0);
3066 constraint(ALLOC_IN_RC(ptr_reg));
3067 match(DecodeN reg);
3068
3069 format %{ "[$reg]" %}
3070 interface(MEMORY_INTER) %{
3071 base($reg);
3072 index(0x4);
3073 scale(0x0);
3074 disp(0x0);
3075 %}
3076 %}
3077
3078 // Indirect Memory Plus Short Offset Operand
3079 operand indOffset8Narrow(rRegN reg, immL8 off)
3080 %{
3081 predicate(CompressedOops::shift() == 0);
3082 constraint(ALLOC_IN_RC(ptr_reg));
3083 match(AddP (DecodeN reg) off);
3084
3085 format %{ "[$reg + $off (8-bit)]" %}
3086 interface(MEMORY_INTER) %{
3087 base($reg);
3088 index(0x4);
3089 scale(0x0);
3090 disp($off);
3091 %}
3092 %}
3093
3094 // Indirect Memory Plus Long Offset Operand
3095 operand indOffset32Narrow(rRegN reg, immL32 off)
3096 %{
3097 predicate(CompressedOops::shift() == 0);
3098 constraint(ALLOC_IN_RC(ptr_reg));
3099 match(AddP (DecodeN reg) off);
3100
3101 format %{ "[$reg + $off (32-bit)]" %}
3102 interface(MEMORY_INTER) %{
3103 base($reg);
3104 index(0x4);
3105 scale(0x0);
3106 disp($off);
3107 %}
3108 %}
3109
3110 // Indirect Memory Plus Index Register Plus Offset Operand
3111 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
3112 %{
3113 predicate(CompressedOops::shift() == 0);
3114 constraint(ALLOC_IN_RC(ptr_reg));
3115 match(AddP (AddP (DecodeN reg) lreg) off);
3116
3117 op_cost(10);
3118 format %{"[$reg + $off + $lreg]" %}
3119 interface(MEMORY_INTER) %{
3120 base($reg);
3121 index($lreg);
3122 scale(0x0);
3123 disp($off);
3124 %}
3125 %}
3126
3127 // Indirect Memory Plus Index Register Plus Offset Operand
3128 operand indIndexNarrow(rRegN reg, rRegL lreg)
3129 %{
3130 predicate(CompressedOops::shift() == 0);
3131 constraint(ALLOC_IN_RC(ptr_reg));
3132 match(AddP (DecodeN reg) lreg);
3133
3134 op_cost(10);
3135 format %{"[$reg + $lreg]" %}
3136 interface(MEMORY_INTER) %{
3137 base($reg);
3138 index($lreg);
3139 scale(0x0);
3140 disp(0x0);
3141 %}
3142 %}
3143
3144 // Indirect Memory Times Scale Plus Index Register
3145 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
3146 %{
3147 predicate(CompressedOops::shift() == 0);
3148 constraint(ALLOC_IN_RC(ptr_reg));
3149 match(AddP (DecodeN reg) (LShiftL lreg scale));
3150
3151 op_cost(10);
3152 format %{"[$reg + $lreg << $scale]" %}
3153 interface(MEMORY_INTER) %{
3154 base($reg);
3155 index($lreg);
3156 scale($scale);
3157 disp(0x0);
3158 %}
3159 %}
3160
3161 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3162 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
3163 %{
3164 predicate(CompressedOops::shift() == 0);
3165 constraint(ALLOC_IN_RC(ptr_reg));
3166 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
3167
3168 op_cost(10);
3169 format %{"[$reg + $off + $lreg << $scale]" %}
3170 interface(MEMORY_INTER) %{
3171 base($reg);
3172 index($lreg);
3173 scale($scale);
3174 disp($off);
3175 %}
3176 %}
3177
3178 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
3179 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
3180 %{
3181 constraint(ALLOC_IN_RC(ptr_reg));
3182 predicate(CompressedOops::shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3183 match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
3184
3185 op_cost(10);
3186 format %{"[$reg + $off + $idx]" %}
3187 interface(MEMORY_INTER) %{
3188 base($reg);
3189 index($idx);
3190 scale(0x0);
3191 disp($off);
3192 %}
3193 %}
3194
3195 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3196 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
3197 %{
3198 constraint(ALLOC_IN_RC(ptr_reg));
3199 predicate(CompressedOops::shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3200 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
3201
3202 op_cost(10);
3203 format %{"[$reg + $off + $idx << $scale]" %}
3204 interface(MEMORY_INTER) %{
3205 base($reg);
3206 index($idx);
3207 scale($scale);
3208 disp($off);
3209 %}
3210 %}
3211
3212 //----------Special Memory Operands--------------------------------------------
3213 // Stack Slot Operand - This operand is used for loading and storing temporary
3214 // values on the stack where a match requires a value to
3215 // flow through memory.
3216 operand stackSlotP(sRegP reg)
3217 %{
3218 constraint(ALLOC_IN_RC(stack_slots));
3219 // No match rule because this operand is only generated in matching
3220
3221 format %{ "[$reg]" %}
3222 interface(MEMORY_INTER) %{
3223 base(0x4); // RSP
3224 index(0x4); // No Index
3225 scale(0x0); // No Scale
3226 disp($reg); // Stack Offset
3227 %}
3228 %}
3229
3230 operand stackSlotI(sRegI reg)
3231 %{
3232 constraint(ALLOC_IN_RC(stack_slots));
3233 // No match rule because this operand is only generated in matching
3234
3235 format %{ "[$reg]" %}
3236 interface(MEMORY_INTER) %{
3237 base(0x4); // RSP
3238 index(0x4); // No Index
3239 scale(0x0); // No Scale
3240 disp($reg); // Stack Offset
3241 %}
3242 %}
3243
3244 operand stackSlotF(sRegF reg)
3245 %{
3246 constraint(ALLOC_IN_RC(stack_slots));
3247 // No match rule because this operand is only generated in matching
3248
3249 format %{ "[$reg]" %}
3250 interface(MEMORY_INTER) %{
3251 base(0x4); // RSP
3252 index(0x4); // No Index
3253 scale(0x0); // No Scale
3254 disp($reg); // Stack Offset
3255 %}
3256 %}
3257
3258 operand stackSlotD(sRegD reg)
3259 %{
3260 constraint(ALLOC_IN_RC(stack_slots));
3261 // No match rule because this operand is only generated in matching
3262
3263 format %{ "[$reg]" %}
3264 interface(MEMORY_INTER) %{
3265 base(0x4); // RSP
3266 index(0x4); // No Index
3267 scale(0x0); // No Scale
3268 disp($reg); // Stack Offset
3269 %}
3270 %}
3271 operand stackSlotL(sRegL reg)
3272 %{
3273 constraint(ALLOC_IN_RC(stack_slots));
3274 // No match rule because this operand is only generated in matching
3275
3276 format %{ "[$reg]" %}
3277 interface(MEMORY_INTER) %{
3278 base(0x4); // RSP
3279 index(0x4); // No Index
3280 scale(0x0); // No Scale
3281 disp($reg); // Stack Offset
3282 %}
3283 %}
3284
3285 //----------Conditional Branch Operands----------------------------------------
3286 // Comparison Op - This is the operation of the comparison, and is limited to
3287 // the following set of codes:
3288 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3289 //
3290 // Other attributes of the comparison, such as unsignedness, are specified
3291 // by the comparison instruction that sets a condition code flags register.
3292 // That result is represented by a flags operand whose subtype is appropriate
3293 // to the unsignedness (etc.) of the comparison.
3294 //
3295 // Later, the instruction which matches both the Comparison Op (a Bool) and
3296 // the flags (produced by the Cmp) specifies the coding of the comparison op
3297 // by matching a specific subtype of Bool operand below, such as cmpOpU.
3298
3299 // Comparison Code
3300 operand cmpOp()
3301 %{
3302 match(Bool);
3303
3304 format %{ "" %}
3305 interface(COND_INTER) %{
3306 equal(0x4, "e");
3307 not_equal(0x5, "ne");
3308 less(0xC, "l");
3309 greater_equal(0xD, "ge");
3310 less_equal(0xE, "le");
3311 greater(0xF, "g");
3312 overflow(0x0, "o");
3313 no_overflow(0x1, "no");
3314 %}
3315 %}
3316
3317 // Comparison Code, unsigned compare. Used by FP also, with
3318 // C2 (unordered) turned into GT or LT already. The other bits
3319 // C0 and C3 are turned into Carry & Zero flags.
3320 operand cmpOpU()
3321 %{
3322 match(Bool);
3323
3324 format %{ "" %}
3325 interface(COND_INTER) %{
3326 equal(0x4, "e");
3327 not_equal(0x5, "ne");
3328 less(0x2, "b");
3329 greater_equal(0x3, "ae");
3330 less_equal(0x6, "be");
3331 greater(0x7, "a");
3332 overflow(0x0, "o");
3333 no_overflow(0x1, "no");
3334 %}
3335 %}
3336
3337
3338 // Floating comparisons that don't require any fixup for the unordered case,
3339 // If both inputs of the comparison are the same, ZF is always set so we
3340 // don't need to use cmpOpUCF2 for eq/ne
3341 operand cmpOpUCF() %{
3342 match(Bool);
3343 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
3344 n->as_Bool()->_test._test == BoolTest::ge ||
3345 n->as_Bool()->_test._test == BoolTest::le ||
3346 n->as_Bool()->_test._test == BoolTest::gt ||
3347 n->in(1)->in(1) == n->in(1)->in(2));
3348 format %{ "" %}
3349 interface(COND_INTER) %{
3350 equal(0xb, "np");
3351 not_equal(0xa, "p");
3352 less(0x2, "b");
3353 greater_equal(0x3, "ae");
3354 less_equal(0x6, "be");
3355 greater(0x7, "a");
3356 overflow(0x0, "o");
3357 no_overflow(0x1, "no");
3358 %}
3359 %}
3360
3361
3362 // Floating comparisons that can be fixed up with extra conditional jumps
3363 operand cmpOpUCF2() %{
3364 match(Bool);
3365 predicate((n->as_Bool()->_test._test == BoolTest::ne ||
3366 n->as_Bool()->_test._test == BoolTest::eq) &&
3367 n->in(1)->in(1) != n->in(1)->in(2));
3368 format %{ "" %}
3369 interface(COND_INTER) %{
3370 equal(0x4, "e");
3371 not_equal(0x5, "ne");
3372 less(0x2, "b");
3373 greater_equal(0x3, "ae");
3374 less_equal(0x6, "be");
3375 greater(0x7, "a");
3376 overflow(0x0, "o");
3377 no_overflow(0x1, "no");
3378 %}
3379 %}
3380
3381 //----------OPERAND CLASSES----------------------------------------------------
3382 // Operand Classes are groups of operands that are used as to simplify
3383 // instruction definitions by not requiring the AD writer to specify separate
3384 // instructions for every form of operand when the instruction accepts
3385 // multiple operand types with the same basic encoding and format. The classic
3386 // case of this is memory operands.
3387
3388 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
3389 indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
3390 indCompressedOopOffset,
3391 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
3392 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
3393 indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
3394
3395 //----------PIPELINE-----------------------------------------------------------
3396 // Rules which define the behavior of the target architectures pipeline.
3397 pipeline %{
3398
3399 //----------ATTRIBUTES---------------------------------------------------------
3400 attributes %{
3401 variable_size_instructions; // Fixed size instructions
3402 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
3403 instruction_unit_size = 1; // An instruction is 1 bytes long
3404 instruction_fetch_unit_size = 16; // The processor fetches one line
3405 instruction_fetch_units = 1; // of 16 bytes
3406
3407 // List of nop instructions
3408 nops( MachNop );
3409 %}
3410
3411 //----------RESOURCES----------------------------------------------------------
3412 // Resources are the functional units available to the machine
3413
3414 // Generic P2/P3 pipeline
3415 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
3416 // 3 instructions decoded per cycle.
3417 // 2 load/store ops per cycle, 1 branch, 1 FPU,
3418 // 3 ALU op, only ALU0 handles mul instructions.
3419 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
3420 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
3421 BR, FPU,
3422 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
3423
3424 //----------PIPELINE DESCRIPTION-----------------------------------------------
3425 // Pipeline Description specifies the stages in the machine's pipeline
3426
3427 // Generic P2/P3 pipeline
3428 pipe_desc(S0, S1, S2, S3, S4, S5);
3429
3430 //----------PIPELINE CLASSES---------------------------------------------------
3431 // Pipeline Classes describe the stages in which input and output are
3432 // referenced by the hardware pipeline.
3433
3434 // Naming convention: ialu or fpu
3435 // Then: _reg
3436 // Then: _reg if there is a 2nd register
3437 // Then: _long if it's a pair of instructions implementing a long
3438 // Then: _fat if it requires the big decoder
3439 // Or: _mem if it requires the big decoder and a memory unit.
3440
3441 // Integer ALU reg operation
3442 pipe_class ialu_reg(rRegI dst)
3443 %{
3444 single_instruction;
3445 dst : S4(write);
3446 dst : S3(read);
3447 DECODE : S0; // any decoder
3448 ALU : S3; // any alu
3449 %}
3450
3451 // Long ALU reg operation
3452 pipe_class ialu_reg_long(rRegL dst)
3453 %{
3454 instruction_count(2);
3455 dst : S4(write);
3456 dst : S3(read);
3457 DECODE : S0(2); // any 2 decoders
3458 ALU : S3(2); // both alus
3459 %}
3460
3461 // Integer ALU reg operation using big decoder
3462 pipe_class ialu_reg_fat(rRegI dst)
3463 %{
3464 single_instruction;
3465 dst : S4(write);
3466 dst : S3(read);
3467 D0 : S0; // big decoder only
3468 ALU : S3; // any alu
3469 %}
3470
3471 // Integer ALU reg-reg operation
3472 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
3473 %{
3474 single_instruction;
3475 dst : S4(write);
3476 src : S3(read);
3477 DECODE : S0; // any decoder
3478 ALU : S3; // any alu
3479 %}
3480
3481 // Integer ALU reg-reg operation
3482 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
3483 %{
3484 single_instruction;
3485 dst : S4(write);
3486 src : S3(read);
3487 D0 : S0; // big decoder only
3488 ALU : S3; // any alu
3489 %}
3490
3491 // Integer ALU reg-mem operation
3492 pipe_class ialu_reg_mem(rRegI dst, memory mem)
3493 %{
3494 single_instruction;
3495 dst : S5(write);
3496 mem : S3(read);
3497 D0 : S0; // big decoder only
3498 ALU : S4; // any alu
3499 MEM : S3; // any mem
3500 %}
3501
3502 // Integer mem operation (prefetch)
3503 pipe_class ialu_mem(memory mem)
3504 %{
3505 single_instruction;
3506 mem : S3(read);
3507 D0 : S0; // big decoder only
3508 MEM : S3; // any mem
3509 %}
3510
3511 // Integer Store to Memory
3512 pipe_class ialu_mem_reg(memory mem, rRegI src)
3513 %{
3514 single_instruction;
3515 mem : S3(read);
3516 src : S5(read);
3517 D0 : S0; // big decoder only
3518 ALU : S4; // any alu
3519 MEM : S3;
3520 %}
3521
3522 // // Long Store to Memory
3523 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
3524 // %{
3525 // instruction_count(2);
3526 // mem : S3(read);
3527 // src : S5(read);
3528 // D0 : S0(2); // big decoder only; twice
3529 // ALU : S4(2); // any 2 alus
3530 // MEM : S3(2); // Both mems
3531 // %}
3532
3533 // Integer Store to Memory
3534 pipe_class ialu_mem_imm(memory mem)
3535 %{
3536 single_instruction;
3537 mem : S3(read);
3538 D0 : S0; // big decoder only
3539 ALU : S4; // any alu
3540 MEM : S3;
3541 %}
3542
3543 // Integer ALU0 reg-reg operation
3544 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
3545 %{
3546 single_instruction;
3547 dst : S4(write);
3548 src : S3(read);
3549 D0 : S0; // Big decoder only
3550 ALU0 : S3; // only alu0
3551 %}
3552
3553 // Integer ALU0 reg-mem operation
3554 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
3555 %{
3556 single_instruction;
3557 dst : S5(write);
3558 mem : S3(read);
3559 D0 : S0; // big decoder only
3560 ALU0 : S4; // ALU0 only
3561 MEM : S3; // any mem
3562 %}
3563
3564 // Integer ALU reg-reg operation
3565 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
3566 %{
3567 single_instruction;
3568 cr : S4(write);
3569 src1 : S3(read);
3570 src2 : S3(read);
3571 DECODE : S0; // any decoder
3572 ALU : S3; // any alu
3573 %}
3574
3575 // Integer ALU reg-imm operation
3576 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
3577 %{
3578 single_instruction;
3579 cr : S4(write);
3580 src1 : S3(read);
3581 DECODE : S0; // any decoder
3582 ALU : S3; // any alu
3583 %}
3584
3585 // Integer ALU reg-mem operation
3586 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
3587 %{
3588 single_instruction;
3589 cr : S4(write);
3590 src1 : S3(read);
3591 src2 : S3(read);
3592 D0 : S0; // big decoder only
3593 ALU : S4; // any alu
3594 MEM : S3;
3595 %}
3596
3597 // Conditional move reg-reg
3598 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
3599 %{
3600 instruction_count(4);
3601 y : S4(read);
3602 q : S3(read);
3603 p : S3(read);
3604 DECODE : S0(4); // any decoder
3605 %}
3606
3607 // Conditional move reg-reg
3608 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
3609 %{
3610 single_instruction;
3611 dst : S4(write);
3612 src : S3(read);
3613 cr : S3(read);
3614 DECODE : S0; // any decoder
3615 %}
3616
3617 // Conditional move reg-mem
3618 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
3619 %{
3620 single_instruction;
3621 dst : S4(write);
3622 src : S3(read);
3623 cr : S3(read);
3624 DECODE : S0; // any decoder
3625 MEM : S3;
3626 %}
3627
3628 // Conditional move reg-reg long
3629 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
3630 %{
3631 single_instruction;
3632 dst : S4(write);
3633 src : S3(read);
3634 cr : S3(read);
3635 DECODE : S0(2); // any 2 decoders
3636 %}
3637
3638 // Float reg-reg operation
3639 pipe_class fpu_reg(regD dst)
3640 %{
3641 instruction_count(2);
3642 dst : S3(read);
3643 DECODE : S0(2); // any 2 decoders
3644 FPU : S3;
3645 %}
3646
3647 // Float reg-reg operation
3648 pipe_class fpu_reg_reg(regD dst, regD src)
3649 %{
3650 instruction_count(2);
3651 dst : S4(write);
3652 src : S3(read);
3653 DECODE : S0(2); // any 2 decoders
3654 FPU : S3;
3655 %}
3656
3657 // Float reg-reg operation
3658 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
3659 %{
3660 instruction_count(3);
3661 dst : S4(write);
3662 src1 : S3(read);
3663 src2 : S3(read);
3664 DECODE : S0(3); // any 3 decoders
3665 FPU : S3(2);
3666 %}
3667
3668 // Float reg-reg operation
3669 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
3670 %{
3671 instruction_count(4);
3672 dst : S4(write);
3673 src1 : S3(read);
3674 src2 : S3(read);
3675 src3 : S3(read);
3676 DECODE : S0(4); // any 3 decoders
3677 FPU : S3(2);
3678 %}
3679
3680 // Float reg-reg operation
3681 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
3682 %{
3683 instruction_count(4);
3684 dst : S4(write);
3685 src1 : S3(read);
3686 src2 : S3(read);
3687 src3 : S3(read);
3688 DECODE : S1(3); // any 3 decoders
3689 D0 : S0; // Big decoder only
3690 FPU : S3(2);
3691 MEM : S3;
3692 %}
3693
3694 // Float reg-mem operation
3695 pipe_class fpu_reg_mem(regD dst, memory mem)
3696 %{
3697 instruction_count(2);
3698 dst : S5(write);
3699 mem : S3(read);
3700 D0 : S0; // big decoder only
3701 DECODE : S1; // any decoder for FPU POP
3702 FPU : S4;
3703 MEM : S3; // any mem
3704 %}
3705
3706 // Float reg-mem operation
3707 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
3708 %{
3709 instruction_count(3);
3710 dst : S5(write);
3711 src1 : S3(read);
3712 mem : S3(read);
3713 D0 : S0; // big decoder only
3714 DECODE : S1(2); // any decoder for FPU POP
3715 FPU : S4;
3716 MEM : S3; // any mem
3717 %}
3718
3719 // Float mem-reg operation
3720 pipe_class fpu_mem_reg(memory mem, regD src)
3721 %{
3722 instruction_count(2);
3723 src : S5(read);
3724 mem : S3(read);
3725 DECODE : S0; // any decoder for FPU PUSH
3726 D0 : S1; // big decoder only
3727 FPU : S4;
3728 MEM : S3; // any mem
3729 %}
3730
3731 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
3732 %{
3733 instruction_count(3);
3734 src1 : S3(read);
3735 src2 : S3(read);
3736 mem : S3(read);
3737 DECODE : S0(2); // any decoder for FPU PUSH
3738 D0 : S1; // big decoder only
3739 FPU : S4;
3740 MEM : S3; // any mem
3741 %}
3742
3743 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
3744 %{
3745 instruction_count(3);
3746 src1 : S3(read);
3747 src2 : S3(read);
3748 mem : S4(read);
3749 DECODE : S0; // any decoder for FPU PUSH
3750 D0 : S0(2); // big decoder only
3751 FPU : S4;
3752 MEM : S3(2); // any mem
3753 %}
3754
3755 pipe_class fpu_mem_mem(memory dst, memory src1)
3756 %{
3757 instruction_count(2);
3758 src1 : S3(read);
3759 dst : S4(read);
3760 D0 : S0(2); // big decoder only
3761 MEM : S3(2); // any mem
3762 %}
3763
3764 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
3765 %{
3766 instruction_count(3);
3767 src1 : S3(read);
3768 src2 : S3(read);
3769 dst : S4(read);
3770 D0 : S0(3); // big decoder only
3771 FPU : S4;
3772 MEM : S3(3); // any mem
3773 %}
3774
3775 pipe_class fpu_mem_reg_con(memory mem, regD src1)
3776 %{
3777 instruction_count(3);
3778 src1 : S4(read);
3779 mem : S4(read);
3780 DECODE : S0; // any decoder for FPU PUSH
3781 D0 : S0(2); // big decoder only
3782 FPU : S4;
3783 MEM : S3(2); // any mem
3784 %}
3785
3786 // Float load constant
3787 pipe_class fpu_reg_con(regD dst)
3788 %{
3789 instruction_count(2);
3790 dst : S5(write);
3791 D0 : S0; // big decoder only for the load
3792 DECODE : S1; // any decoder for FPU POP
3793 FPU : S4;
3794 MEM : S3; // any mem
3795 %}
3796
3797 // Float load constant
3798 pipe_class fpu_reg_reg_con(regD dst, regD src)
3799 %{
3800 instruction_count(3);
3801 dst : S5(write);
3802 src : S3(read);
3803 D0 : S0; // big decoder only for the load
3804 DECODE : S1(2); // any decoder for FPU POP
3805 FPU : S4;
3806 MEM : S3; // any mem
3807 %}
3808
3809 // UnConditional branch
3810 pipe_class pipe_jmp(label labl)
3811 %{
3812 single_instruction;
3813 BR : S3;
3814 %}
3815
3816 // Conditional branch
3817 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
3818 %{
3819 single_instruction;
3820 cr : S1(read);
3821 BR : S3;
3822 %}
3823
3824 // Allocation idiom
3825 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
3826 %{
3827 instruction_count(1); force_serialization;
3828 fixed_latency(6);
3829 heap_ptr : S3(read);
3830 DECODE : S0(3);
3831 D0 : S2;
3832 MEM : S3;
3833 ALU : S3(2);
3834 dst : S5(write);
3835 BR : S5;
3836 %}
3837
3838 // Generic big/slow expanded idiom
3839 pipe_class pipe_slow()
3840 %{
3841 instruction_count(10); multiple_bundles; force_serialization;
3842 fixed_latency(100);
3843 D0 : S0(2);
3844 MEM : S3(2);
3845 %}
3846
3847 // The real do-nothing guy
3848 pipe_class empty()
3849 %{
3850 instruction_count(0);
3851 %}
3852
3853 // Define the class for the Nop node
3854 define
3855 %{
3856 MachNop = empty;
3857 %}
3858
3859 %}
3860
3861 //----------INSTRUCTIONS-------------------------------------------------------
3862 //
3863 // match -- States which machine-independent subtree may be replaced
3864 // by this instruction.
3865 // ins_cost -- The estimated cost of this instruction is used by instruction
3866 // selection to identify a minimum cost tree of machine
3867 // instructions that matches a tree of machine-independent
3868 // instructions.
3869 // format -- A string providing the disassembly for this instruction.
3870 // The value of an instruction's operand may be inserted
3871 // by referring to it with a '$' prefix.
3872 // opcode -- Three instruction opcodes may be provided. These are referred
3873 // to within an encode class as $primary, $secondary, and $tertiary
3874 // rrspectively. The primary opcode is commonly used to
3875 // indicate the type of machine instruction, while secondary
3876 // and tertiary are often used for prefix options or addressing
3877 // modes.
3878 // ins_encode -- A list of encode classes with parameters. The encode class
3879 // name must have been defined in an 'enc_class' specification
3880 // in the encode section of the architecture description.
3881
3882 // Dummy reg-to-reg vector moves. Removed during post-selection cleanup.
3883 // Load Float
3884 instruct MoveF2VL(vlRegF dst, regF src) %{
3885 match(Set dst src);
3886 format %{ "movss $dst,$src\t! load float (4 bytes)" %}
3887 ins_encode %{
3888 ShouldNotReachHere();
3889 %}
3890 ins_pipe( fpu_reg_reg );
3891 %}
3892
3893 // Load Float
3894 instruct MoveF2LEG(legRegF dst, regF src) %{
3895 match(Set dst src);
3896 format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
3897 ins_encode %{
3898 ShouldNotReachHere();
3899 %}
3900 ins_pipe( fpu_reg_reg );
3901 %}
3902
3903 // Load Float
3904 instruct MoveVL2F(regF dst, vlRegF src) %{
3905 match(Set dst src);
3906 format %{ "movss $dst,$src\t! load float (4 bytes)" %}
3907 ins_encode %{
3908 ShouldNotReachHere();
3909 %}
3910 ins_pipe( fpu_reg_reg );
3911 %}
3912
3913 // Load Float
3914 instruct MoveLEG2F(regF dst, legRegF src) %{
3915 match(Set dst src);
3916 format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
3917 ins_encode %{
3918 ShouldNotReachHere();
3919 %}
3920 ins_pipe( fpu_reg_reg );
3921 %}
3922
3923 // Load Double
3924 instruct MoveD2VL(vlRegD dst, regD src) %{
3925 match(Set dst src);
3926 format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
3927 ins_encode %{
3928 ShouldNotReachHere();
3929 %}
3930 ins_pipe( fpu_reg_reg );
3931 %}
3932
3933 // Load Double
3934 instruct MoveD2LEG(legRegD dst, regD src) %{
3935 match(Set dst src);
3936 format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
3937 ins_encode %{
3938 ShouldNotReachHere();
3939 %}
3940 ins_pipe( fpu_reg_reg );
3941 %}
3942
3943 // Load Double
3944 instruct MoveVL2D(regD dst, vlRegD src) %{
3945 match(Set dst src);
3946 format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
3947 ins_encode %{
3948 ShouldNotReachHere();
3949 %}
3950 ins_pipe( fpu_reg_reg );
3951 %}
3952
3953 // Load Double
3954 instruct MoveLEG2D(regD dst, legRegD src) %{
3955 match(Set dst src);
3956 format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
3957 ins_encode %{
3958 ShouldNotReachHere();
3959 %}
3960 ins_pipe( fpu_reg_reg );
3961 %}
3962
3963 //----------Load/Store/Move Instructions---------------------------------------
3964 //----------Load Instructions--------------------------------------------------
3965
3966 // Load Byte (8 bit signed)
3967 instruct loadB(rRegI dst, memory mem)
3968 %{
3969 match(Set dst (LoadB mem));
3970
3971 ins_cost(125);
3972 format %{ "movsbl $dst, $mem\t# byte" %}
3973
3974 ins_encode %{
3975 __ movsbl($dst$$Register, $mem$$Address);
3976 %}
3977
3978 ins_pipe(ialu_reg_mem);
3979 %}
3980
3981 // Load Byte (8 bit signed) into Long Register
3982 instruct loadB2L(rRegL dst, memory mem)
3983 %{
3984 match(Set dst (ConvI2L (LoadB mem)));
3985
3986 ins_cost(125);
3987 format %{ "movsbq $dst, $mem\t# byte -> long" %}
3988
3989 ins_encode %{
3990 __ movsbq($dst$$Register, $mem$$Address);
3991 %}
3992
3993 ins_pipe(ialu_reg_mem);
3994 %}
3995
3996 // Load Unsigned Byte (8 bit UNsigned)
3997 instruct loadUB(rRegI dst, memory mem)
3998 %{
3999 match(Set dst (LoadUB mem));
4000
4001 ins_cost(125);
4002 format %{ "movzbl $dst, $mem\t# ubyte" %}
4003
4004 ins_encode %{
4005 __ movzbl($dst$$Register, $mem$$Address);
4006 %}
4007
4008 ins_pipe(ialu_reg_mem);
4009 %}
4010
4011 // Load Unsigned Byte (8 bit UNsigned) into Long Register
4012 instruct loadUB2L(rRegL dst, memory mem)
4013 %{
4014 match(Set dst (ConvI2L (LoadUB mem)));
4015
4016 ins_cost(125);
4017 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
4018
4019 ins_encode %{
4020 __ movzbq($dst$$Register, $mem$$Address);
4021 %}
4022
4023 ins_pipe(ialu_reg_mem);
4024 %}
4025
4026 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
4027 instruct loadUB2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4028 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
4029 effect(KILL cr);
4030
4031 format %{ "movzbq $dst, $mem\t# ubyte & 32-bit mask -> long\n\t"
4032 "andl $dst, right_n_bits($mask, 8)" %}
4033 ins_encode %{
4034 Register Rdst = $dst$$Register;
4035 __ movzbq(Rdst, $mem$$Address);
4036 __ andl(Rdst, $mask$$constant & right_n_bits(8));
4037 %}
4038 ins_pipe(ialu_reg_mem);
4039 %}
4040
4041 // Load Short (16 bit signed)
4042 instruct loadS(rRegI dst, memory mem)
4043 %{
4044 match(Set dst (LoadS mem));
4045
4046 ins_cost(125);
4047 format %{ "movswl $dst, $mem\t# short" %}
4048
4049 ins_encode %{
4050 __ movswl($dst$$Register, $mem$$Address);
4051 %}
4052
4053 ins_pipe(ialu_reg_mem);
4054 %}
4055
4056 // Load Short (16 bit signed) to Byte (8 bit signed)
4057 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4058 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
4059
4060 ins_cost(125);
4061 format %{ "movsbl $dst, $mem\t# short -> byte" %}
4062 ins_encode %{
4063 __ movsbl($dst$$Register, $mem$$Address);
4064 %}
4065 ins_pipe(ialu_reg_mem);
4066 %}
4067
4068 // Load Short (16 bit signed) into Long Register
4069 instruct loadS2L(rRegL dst, memory mem)
4070 %{
4071 match(Set dst (ConvI2L (LoadS mem)));
4072
4073 ins_cost(125);
4074 format %{ "movswq $dst, $mem\t# short -> long" %}
4075
4076 ins_encode %{
4077 __ movswq($dst$$Register, $mem$$Address);
4078 %}
4079
4080 ins_pipe(ialu_reg_mem);
4081 %}
4082
4083 // Load Unsigned Short/Char (16 bit UNsigned)
4084 instruct loadUS(rRegI dst, memory mem)
4085 %{
4086 match(Set dst (LoadUS mem));
4087
4088 ins_cost(125);
4089 format %{ "movzwl $dst, $mem\t# ushort/char" %}
4090
4091 ins_encode %{
4092 __ movzwl($dst$$Register, $mem$$Address);
4093 %}
4094
4095 ins_pipe(ialu_reg_mem);
4096 %}
4097
4098 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
4099 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4100 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
4101
4102 ins_cost(125);
4103 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
4104 ins_encode %{
4105 __ movsbl($dst$$Register, $mem$$Address);
4106 %}
4107 ins_pipe(ialu_reg_mem);
4108 %}
4109
4110 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
4111 instruct loadUS2L(rRegL dst, memory mem)
4112 %{
4113 match(Set dst (ConvI2L (LoadUS mem)));
4114
4115 ins_cost(125);
4116 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
4117
4118 ins_encode %{
4119 __ movzwq($dst$$Register, $mem$$Address);
4120 %}
4121
4122 ins_pipe(ialu_reg_mem);
4123 %}
4124
4125 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
4126 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4127 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4128
4129 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
4130 ins_encode %{
4131 __ movzbq($dst$$Register, $mem$$Address);
4132 %}
4133 ins_pipe(ialu_reg_mem);
4134 %}
4135
4136 // Load Unsigned Short/Char (16 bit UNsigned) with 32-bit mask into Long Register
4137 instruct loadUS2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4138 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4139 effect(KILL cr);
4140
4141 format %{ "movzwq $dst, $mem\t# ushort/char & 32-bit mask -> long\n\t"
4142 "andl $dst, right_n_bits($mask, 16)" %}
4143 ins_encode %{
4144 Register Rdst = $dst$$Register;
4145 __ movzwq(Rdst, $mem$$Address);
4146 __ andl(Rdst, $mask$$constant & right_n_bits(16));
4147 %}
4148 ins_pipe(ialu_reg_mem);
4149 %}
4150
4151 // Load Integer
4152 instruct loadI(rRegI dst, memory mem)
4153 %{
4154 match(Set dst (LoadI mem));
4155
4156 ins_cost(125);
4157 format %{ "movl $dst, $mem\t# int" %}
4158
4159 ins_encode %{
4160 __ movl($dst$$Register, $mem$$Address);
4161 %}
4162
4163 ins_pipe(ialu_reg_mem);
4164 %}
4165
4166 // Load Integer (32 bit signed) to Byte (8 bit signed)
4167 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4168 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
4169
4170 ins_cost(125);
4171 format %{ "movsbl $dst, $mem\t# int -> byte" %}
4172 ins_encode %{
4173 __ movsbl($dst$$Register, $mem$$Address);
4174 %}
4175 ins_pipe(ialu_reg_mem);
4176 %}
4177
4178 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
4179 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
4180 match(Set dst (AndI (LoadI mem) mask));
4181
4182 ins_cost(125);
4183 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
4184 ins_encode %{
4185 __ movzbl($dst$$Register, $mem$$Address);
4186 %}
4187 ins_pipe(ialu_reg_mem);
4188 %}
4189
4190 // Load Integer (32 bit signed) to Short (16 bit signed)
4191 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
4192 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
4193
4194 ins_cost(125);
4195 format %{ "movswl $dst, $mem\t# int -> short" %}
4196 ins_encode %{
4197 __ movswl($dst$$Register, $mem$$Address);
4198 %}
4199 ins_pipe(ialu_reg_mem);
4200 %}
4201
4202 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
4203 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
4204 match(Set dst (AndI (LoadI mem) mask));
4205
4206 ins_cost(125);
4207 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
4208 ins_encode %{
4209 __ movzwl($dst$$Register, $mem$$Address);
4210 %}
4211 ins_pipe(ialu_reg_mem);
4212 %}
4213
4214 // Load Integer into Long Register
4215 instruct loadI2L(rRegL dst, memory mem)
4216 %{
4217 match(Set dst (ConvI2L (LoadI mem)));
4218
4219 ins_cost(125);
4220 format %{ "movslq $dst, $mem\t# int -> long" %}
4221
4222 ins_encode %{
4223 __ movslq($dst$$Register, $mem$$Address);
4224 %}
4225
4226 ins_pipe(ialu_reg_mem);
4227 %}
4228
4229 // Load Integer with mask 0xFF into Long Register
4230 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4231 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4232
4233 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
4234 ins_encode %{
4235 __ movzbq($dst$$Register, $mem$$Address);
4236 %}
4237 ins_pipe(ialu_reg_mem);
4238 %}
4239
4240 // Load Integer with mask 0xFFFF into Long Register
4241 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
4242 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4243
4244 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
4245 ins_encode %{
4246 __ movzwq($dst$$Register, $mem$$Address);
4247 %}
4248 ins_pipe(ialu_reg_mem);
4249 %}
4250
4251 // Load Integer with a 31-bit mask into Long Register
4252 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
4253 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4254 effect(KILL cr);
4255
4256 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t"
4257 "andl $dst, $mask" %}
4258 ins_encode %{
4259 Register Rdst = $dst$$Register;
4260 __ movl(Rdst, $mem$$Address);
4261 __ andl(Rdst, $mask$$constant);
4262 %}
4263 ins_pipe(ialu_reg_mem);
4264 %}
4265
4266 // Load Unsigned Integer into Long Register
4267 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
4268 %{
4269 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
4270
4271 ins_cost(125);
4272 format %{ "movl $dst, $mem\t# uint -> long" %}
4273
4274 ins_encode %{
4275 __ movl($dst$$Register, $mem$$Address);
4276 %}
4277
4278 ins_pipe(ialu_reg_mem);
4279 %}
4280
4281 // Load Long
4282 instruct loadL(rRegL dst, memory mem)
4283 %{
4284 match(Set dst (LoadL mem));
4285
4286 ins_cost(125);
4287 format %{ "movq $dst, $mem\t# long" %}
4288
4289 ins_encode %{
4290 __ movq($dst$$Register, $mem$$Address);
4291 %}
4292
4293 ins_pipe(ialu_reg_mem); // XXX
4294 %}
4295
4296 // Load Range
4297 instruct loadRange(rRegI dst, memory mem)
4298 %{
4299 match(Set dst (LoadRange mem));
4300
4301 ins_cost(125); // XXX
4302 format %{ "movl $dst, $mem\t# range" %}
4303 ins_encode %{
4304 __ movl($dst$$Register, $mem$$Address);
4305 %}
4306 ins_pipe(ialu_reg_mem);
4307 %}
4308
4309 // Load Pointer
4310 instruct loadP(rRegP dst, memory mem)
4311 %{
4312 match(Set dst (LoadP mem));
4313 predicate(n->as_Load()->barrier_data() == 0);
4314
4315 ins_cost(125); // XXX
4316 format %{ "movq $dst, $mem\t# ptr" %}
4317 ins_encode %{
4318 __ movq($dst$$Register, $mem$$Address);
4319 %}
4320 ins_pipe(ialu_reg_mem); // XXX
4321 %}
4322
4323 // Load Compressed Pointer
4324 instruct loadN(rRegN dst, memory mem)
4325 %{
4326 predicate(n->as_Load()->barrier_data() == 0);
4327 match(Set dst (LoadN mem));
4328
4329 ins_cost(125); // XXX
4330 format %{ "movl $dst, $mem\t# compressed ptr" %}
4331 ins_encode %{
4332 __ movl($dst$$Register, $mem$$Address);
4333 %}
4334 ins_pipe(ialu_reg_mem); // XXX
4335 %}
4336
4337
4338 // Load Klass Pointer
4339 instruct loadKlass(rRegP dst, memory mem)
4340 %{
4341 match(Set dst (LoadKlass mem));
4342
4343 ins_cost(125); // XXX
4344 format %{ "movq $dst, $mem\t# class" %}
4345 ins_encode %{
4346 __ movq($dst$$Register, $mem$$Address);
4347 %}
4348 ins_pipe(ialu_reg_mem); // XXX
4349 %}
4350
4351 // Load narrow Klass Pointer
4352 instruct loadNKlass(rRegN dst, memory mem)
4353 %{
4354 match(Set dst (LoadNKlass mem));
4355
4356 ins_cost(125); // XXX
4357 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
4358 ins_encode %{
4359 __ movl($dst$$Register, $mem$$Address);
4360 %}
4361 ins_pipe(ialu_reg_mem); // XXX
4362 %}
4363
4364 // Load Float
4365 instruct loadF(regF dst, memory mem)
4366 %{
4367 match(Set dst (LoadF mem));
4368
4369 ins_cost(145); // XXX
4370 format %{ "movss $dst, $mem\t# float" %}
4371 ins_encode %{
4372 __ movflt($dst$$XMMRegister, $mem$$Address);
4373 %}
4374 ins_pipe(pipe_slow); // XXX
4375 %}
4376
4377 // Load Double
4378 instruct loadD_partial(regD dst, memory mem)
4379 %{
4380 predicate(!UseXmmLoadAndClearUpper);
4381 match(Set dst (LoadD mem));
4382
4383 ins_cost(145); // XXX
4384 format %{ "movlpd $dst, $mem\t# double" %}
4385 ins_encode %{
4386 __ movdbl($dst$$XMMRegister, $mem$$Address);
4387 %}
4388 ins_pipe(pipe_slow); // XXX
4389 %}
4390
4391 instruct loadD(regD dst, memory mem)
4392 %{
4393 predicate(UseXmmLoadAndClearUpper);
4394 match(Set dst (LoadD mem));
4395
4396 ins_cost(145); // XXX
4397 format %{ "movsd $dst, $mem\t# double" %}
4398 ins_encode %{
4399 __ movdbl($dst$$XMMRegister, $mem$$Address);
4400 %}
4401 ins_pipe(pipe_slow); // XXX
4402 %}
4403
4404 // max = java.lang.Math.max(float a, float b)
4405 instruct maxF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
4406 predicate(UseAVX > 0 && !VLoopReductions::is_reduction(n));
4407 match(Set dst (MaxF a b));
4408 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
4409 format %{ "maxF $dst, $a, $b \t! using tmp, atmp and btmp as TEMP" %}
4410 ins_encode %{
4411 __ vminmax_fp(Op_MaxV, T_FLOAT, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
4412 %}
4413 ins_pipe( pipe_slow );
4414 %}
4415
4416 instruct maxF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{
4417 predicate(UseAVX > 0 && VLoopReductions::is_reduction(n));
4418 match(Set dst (MaxF a b));
4419 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
4420
4421 format %{ "$dst = max($a, $b)\t# intrinsic (float)" %}
4422 ins_encode %{
4423 emit_fp_min_max(masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
4424 false /*min*/, true /*single*/);
4425 %}
4426 ins_pipe( pipe_slow );
4427 %}
4428
4429 // max = java.lang.Math.max(double a, double b)
4430 instruct maxD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
4431 predicate(UseAVX > 0 && !VLoopReductions::is_reduction(n));
4432 match(Set dst (MaxD a b));
4433 effect(USE a, USE b, TEMP atmp, TEMP btmp, TEMP tmp);
4434 format %{ "maxD $dst, $a, $b \t! using tmp, atmp and btmp as TEMP" %}
4435 ins_encode %{
4436 __ vminmax_fp(Op_MaxV, T_DOUBLE, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
4437 %}
4438 ins_pipe( pipe_slow );
4439 %}
4440
4441 instruct maxD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{
4442 predicate(UseAVX > 0 && VLoopReductions::is_reduction(n));
4443 match(Set dst (MaxD a b));
4444 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
4445
4446 format %{ "$dst = max($a, $b)\t# intrinsic (double)" %}
4447 ins_encode %{
4448 emit_fp_min_max(masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
4449 false /*min*/, false /*single*/);
4450 %}
4451 ins_pipe( pipe_slow );
4452 %}
4453
4454 // min = java.lang.Math.min(float a, float b)
4455 instruct minF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
4456 predicate(UseAVX > 0 && !VLoopReductions::is_reduction(n));
4457 match(Set dst (MinF a b));
4458 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
4459 format %{ "minF $dst, $a, $b \t! using tmp, atmp and btmp as TEMP" %}
4460 ins_encode %{
4461 __ vminmax_fp(Op_MinV, T_FLOAT, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
4462 %}
4463 ins_pipe( pipe_slow );
4464 %}
4465
4466 instruct minF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{
4467 predicate(UseAVX > 0 && VLoopReductions::is_reduction(n));
4468 match(Set dst (MinF a b));
4469 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
4470
4471 format %{ "$dst = min($a, $b)\t# intrinsic (float)" %}
4472 ins_encode %{
4473 emit_fp_min_max(masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
4474 true /*min*/, true /*single*/);
4475 %}
4476 ins_pipe( pipe_slow );
4477 %}
4478
4479 // min = java.lang.Math.min(double a, double b)
4480 instruct minD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
4481 predicate(UseAVX > 0 && !VLoopReductions::is_reduction(n));
4482 match(Set dst (MinD a b));
4483 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
4484 format %{ "minD $dst, $a, $b \t! using tmp, atmp and btmp as TEMP" %}
4485 ins_encode %{
4486 __ vminmax_fp(Op_MinV, T_DOUBLE, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
4487 %}
4488 ins_pipe( pipe_slow );
4489 %}
4490
4491 instruct minD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{
4492 predicate(UseAVX > 0 && VLoopReductions::is_reduction(n));
4493 match(Set dst (MinD a b));
4494 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
4495
4496 format %{ "$dst = min($a, $b)\t# intrinsic (double)" %}
4497 ins_encode %{
4498 emit_fp_min_max(masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
4499 true /*min*/, false /*single*/);
4500 %}
4501 ins_pipe( pipe_slow );
4502 %}
4503
4504 // Load Effective Address
4505 instruct leaP8(rRegP dst, indOffset8 mem)
4506 %{
4507 match(Set dst mem);
4508
4509 ins_cost(110); // XXX
4510 format %{ "leaq $dst, $mem\t# ptr 8" %}
4511 ins_encode %{
4512 __ leaq($dst$$Register, $mem$$Address);
4513 %}
4514 ins_pipe(ialu_reg_reg_fat);
4515 %}
4516
4517 instruct leaP32(rRegP dst, indOffset32 mem)
4518 %{
4519 match(Set dst mem);
4520
4521 ins_cost(110);
4522 format %{ "leaq $dst, $mem\t# ptr 32" %}
4523 ins_encode %{
4524 __ leaq($dst$$Register, $mem$$Address);
4525 %}
4526 ins_pipe(ialu_reg_reg_fat);
4527 %}
4528
4529 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
4530 %{
4531 match(Set dst mem);
4532
4533 ins_cost(110);
4534 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
4535 ins_encode %{
4536 __ leaq($dst$$Register, $mem$$Address);
4537 %}
4538 ins_pipe(ialu_reg_reg_fat);
4539 %}
4540
4541 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
4542 %{
4543 match(Set dst mem);
4544
4545 ins_cost(110);
4546 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
4547 ins_encode %{
4548 __ leaq($dst$$Register, $mem$$Address);
4549 %}
4550 ins_pipe(ialu_reg_reg_fat);
4551 %}
4552
4553 instruct leaPPosIdxScale(rRegP dst, indPosIndexScale mem)
4554 %{
4555 match(Set dst mem);
4556
4557 ins_cost(110);
4558 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
4559 ins_encode %{
4560 __ leaq($dst$$Register, $mem$$Address);
4561 %}
4562 ins_pipe(ialu_reg_reg_fat);
4563 %}
4564
4565 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
4566 %{
4567 match(Set dst mem);
4568
4569 ins_cost(110);
4570 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
4571 ins_encode %{
4572 __ leaq($dst$$Register, $mem$$Address);
4573 %}
4574 ins_pipe(ialu_reg_reg_fat);
4575 %}
4576
4577 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
4578 %{
4579 match(Set dst mem);
4580
4581 ins_cost(110);
4582 format %{ "leaq $dst, $mem\t# ptr posidxoff" %}
4583 ins_encode %{
4584 __ leaq($dst$$Register, $mem$$Address);
4585 %}
4586 ins_pipe(ialu_reg_reg_fat);
4587 %}
4588
4589 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
4590 %{
4591 match(Set dst mem);
4592
4593 ins_cost(110);
4594 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
4595 ins_encode %{
4596 __ leaq($dst$$Register, $mem$$Address);
4597 %}
4598 ins_pipe(ialu_reg_reg_fat);
4599 %}
4600
4601 // Load Effective Address which uses Narrow (32-bits) oop
4602 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
4603 %{
4604 predicate(UseCompressedOops && (CompressedOops::shift() != 0));
4605 match(Set dst mem);
4606
4607 ins_cost(110);
4608 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
4609 ins_encode %{
4610 __ leaq($dst$$Register, $mem$$Address);
4611 %}
4612 ins_pipe(ialu_reg_reg_fat);
4613 %}
4614
4615 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
4616 %{
4617 predicate(CompressedOops::shift() == 0);
4618 match(Set dst mem);
4619
4620 ins_cost(110); // XXX
4621 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
4622 ins_encode %{
4623 __ leaq($dst$$Register, $mem$$Address);
4624 %}
4625 ins_pipe(ialu_reg_reg_fat);
4626 %}
4627
4628 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
4629 %{
4630 predicate(CompressedOops::shift() == 0);
4631 match(Set dst mem);
4632
4633 ins_cost(110);
4634 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
4635 ins_encode %{
4636 __ leaq($dst$$Register, $mem$$Address);
4637 %}
4638 ins_pipe(ialu_reg_reg_fat);
4639 %}
4640
4641 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
4642 %{
4643 predicate(CompressedOops::shift() == 0);
4644 match(Set dst mem);
4645
4646 ins_cost(110);
4647 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
4648 ins_encode %{
4649 __ leaq($dst$$Register, $mem$$Address);
4650 %}
4651 ins_pipe(ialu_reg_reg_fat);
4652 %}
4653
4654 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
4655 %{
4656 predicate(CompressedOops::shift() == 0);
4657 match(Set dst mem);
4658
4659 ins_cost(110);
4660 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
4661 ins_encode %{
4662 __ leaq($dst$$Register, $mem$$Address);
4663 %}
4664 ins_pipe(ialu_reg_reg_fat);
4665 %}
4666
4667 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
4668 %{
4669 predicate(CompressedOops::shift() == 0);
4670 match(Set dst mem);
4671
4672 ins_cost(110);
4673 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
4674 ins_encode %{
4675 __ leaq($dst$$Register, $mem$$Address);
4676 %}
4677 ins_pipe(ialu_reg_reg_fat);
4678 %}
4679
4680 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
4681 %{
4682 predicate(CompressedOops::shift() == 0);
4683 match(Set dst mem);
4684
4685 ins_cost(110);
4686 format %{ "leaq $dst, $mem\t# ptr posidxoffnarrow" %}
4687 ins_encode %{
4688 __ leaq($dst$$Register, $mem$$Address);
4689 %}
4690 ins_pipe(ialu_reg_reg_fat);
4691 %}
4692
4693 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
4694 %{
4695 predicate(CompressedOops::shift() == 0);
4696 match(Set dst mem);
4697
4698 ins_cost(110);
4699 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
4700 ins_encode %{
4701 __ leaq($dst$$Register, $mem$$Address);
4702 %}
4703 ins_pipe(ialu_reg_reg_fat);
4704 %}
4705
4706 instruct loadConI(rRegI dst, immI src)
4707 %{
4708 match(Set dst src);
4709
4710 format %{ "movl $dst, $src\t# int" %}
4711 ins_encode %{
4712 __ movl($dst$$Register, $src$$constant);
4713 %}
4714 ins_pipe(ialu_reg_fat); // XXX
4715 %}
4716
4717 instruct loadConI0(rRegI dst, immI_0 src, rFlagsReg cr)
4718 %{
4719 match(Set dst src);
4720 effect(KILL cr);
4721
4722 ins_cost(50);
4723 format %{ "xorl $dst, $dst\t# int" %}
4724 ins_encode %{
4725 __ xorl($dst$$Register, $dst$$Register);
4726 %}
4727 ins_pipe(ialu_reg);
4728 %}
4729
4730 instruct loadConL(rRegL dst, immL src)
4731 %{
4732 match(Set dst src);
4733
4734 ins_cost(150);
4735 format %{ "movq $dst, $src\t# long" %}
4736 ins_encode %{
4737 __ mov64($dst$$Register, $src$$constant);
4738 %}
4739 ins_pipe(ialu_reg);
4740 %}
4741
4742 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
4743 %{
4744 match(Set dst src);
4745 effect(KILL cr);
4746
4747 ins_cost(50);
4748 format %{ "xorl $dst, $dst\t# long" %}
4749 ins_encode %{
4750 __ xorl($dst$$Register, $dst$$Register);
4751 %}
4752 ins_pipe(ialu_reg); // XXX
4753 %}
4754
4755 instruct loadConUL32(rRegL dst, immUL32 src)
4756 %{
4757 match(Set dst src);
4758
4759 ins_cost(60);
4760 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
4761 ins_encode %{
4762 __ movl($dst$$Register, $src$$constant);
4763 %}
4764 ins_pipe(ialu_reg);
4765 %}
4766
4767 instruct loadConL32(rRegL dst, immL32 src)
4768 %{
4769 match(Set dst src);
4770
4771 ins_cost(70);
4772 format %{ "movq $dst, $src\t# long (32-bit)" %}
4773 ins_encode %{
4774 __ movq($dst$$Register, $src$$constant);
4775 %}
4776 ins_pipe(ialu_reg);
4777 %}
4778
4779 instruct loadConP(rRegP dst, immP con) %{
4780 match(Set dst con);
4781
4782 format %{ "movq $dst, $con\t# ptr" %}
4783 ins_encode %{
4784 __ mov64($dst$$Register, $con$$constant, $con->constant_reloc(), RELOC_IMM64);
4785 %}
4786 ins_pipe(ialu_reg_fat); // XXX
4787 %}
4788
4789 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
4790 %{
4791 match(Set dst src);
4792 effect(KILL cr);
4793
4794 ins_cost(50);
4795 format %{ "xorl $dst, $dst\t# ptr" %}
4796 ins_encode %{
4797 __ xorl($dst$$Register, $dst$$Register);
4798 %}
4799 ins_pipe(ialu_reg);
4800 %}
4801
4802 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
4803 %{
4804 match(Set dst src);
4805 effect(KILL cr);
4806
4807 ins_cost(60);
4808 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
4809 ins_encode %{
4810 __ movl($dst$$Register, $src$$constant);
4811 %}
4812 ins_pipe(ialu_reg);
4813 %}
4814
4815 instruct loadConF(regF dst, immF con) %{
4816 match(Set dst con);
4817 ins_cost(125);
4818 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
4819 ins_encode %{
4820 __ movflt($dst$$XMMRegister, $constantaddress($con));
4821 %}
4822 ins_pipe(pipe_slow);
4823 %}
4824
4825 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
4826 match(Set dst src);
4827 effect(KILL cr);
4828 format %{ "xorq $dst, $src\t# compressed null pointer" %}
4829 ins_encode %{
4830 __ xorq($dst$$Register, $dst$$Register);
4831 %}
4832 ins_pipe(ialu_reg);
4833 %}
4834
4835 instruct loadConN(rRegN dst, immN src) %{
4836 match(Set dst src);
4837
4838 ins_cost(125);
4839 format %{ "movl $dst, $src\t# compressed ptr" %}
4840 ins_encode %{
4841 address con = (address)$src$$constant;
4842 if (con == nullptr) {
4843 ShouldNotReachHere();
4844 } else {
4845 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
4846 }
4847 %}
4848 ins_pipe(ialu_reg_fat); // XXX
4849 %}
4850
4851 instruct loadConNKlass(rRegN dst, immNKlass src) %{
4852 match(Set dst src);
4853
4854 ins_cost(125);
4855 format %{ "movl $dst, $src\t# compressed klass ptr" %}
4856 ins_encode %{
4857 address con = (address)$src$$constant;
4858 if (con == nullptr) {
4859 ShouldNotReachHere();
4860 } else {
4861 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
4862 }
4863 %}
4864 ins_pipe(ialu_reg_fat); // XXX
4865 %}
4866
4867 instruct loadConF0(regF dst, immF0 src)
4868 %{
4869 match(Set dst src);
4870 ins_cost(100);
4871
4872 format %{ "xorps $dst, $dst\t# float 0.0" %}
4873 ins_encode %{
4874 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
4875 %}
4876 ins_pipe(pipe_slow);
4877 %}
4878
4879 // Use the same format since predicate() can not be used here.
4880 instruct loadConD(regD dst, immD con) %{
4881 match(Set dst con);
4882 ins_cost(125);
4883 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
4884 ins_encode %{
4885 __ movdbl($dst$$XMMRegister, $constantaddress($con));
4886 %}
4887 ins_pipe(pipe_slow);
4888 %}
4889
4890 instruct loadConD0(regD dst, immD0 src)
4891 %{
4892 match(Set dst src);
4893 ins_cost(100);
4894
4895 format %{ "xorpd $dst, $dst\t# double 0.0" %}
4896 ins_encode %{
4897 __ xorpd($dst$$XMMRegister, $dst$$XMMRegister);
4898 %}
4899 ins_pipe(pipe_slow);
4900 %}
4901
4902 instruct loadSSI(rRegI dst, stackSlotI src)
4903 %{
4904 match(Set dst src);
4905
4906 ins_cost(125);
4907 format %{ "movl $dst, $src\t# int stk" %}
4908 ins_encode %{
4909 __ movl($dst$$Register, $src$$Address);
4910 %}
4911 ins_pipe(ialu_reg_mem);
4912 %}
4913
4914 instruct loadSSL(rRegL dst, stackSlotL src)
4915 %{
4916 match(Set dst src);
4917
4918 ins_cost(125);
4919 format %{ "movq $dst, $src\t# long stk" %}
4920 ins_encode %{
4921 __ movq($dst$$Register, $src$$Address);
4922 %}
4923 ins_pipe(ialu_reg_mem);
4924 %}
4925
4926 instruct loadSSP(rRegP dst, stackSlotP src)
4927 %{
4928 match(Set dst src);
4929
4930 ins_cost(125);
4931 format %{ "movq $dst, $src\t# ptr stk" %}
4932 ins_encode %{
4933 __ movq($dst$$Register, $src$$Address);
4934 %}
4935 ins_pipe(ialu_reg_mem);
4936 %}
4937
4938 instruct loadSSF(regF dst, stackSlotF src)
4939 %{
4940 match(Set dst src);
4941
4942 ins_cost(125);
4943 format %{ "movss $dst, $src\t# float stk" %}
4944 ins_encode %{
4945 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
4946 %}
4947 ins_pipe(pipe_slow); // XXX
4948 %}
4949
4950 // Use the same format since predicate() can not be used here.
4951 instruct loadSSD(regD dst, stackSlotD src)
4952 %{
4953 match(Set dst src);
4954
4955 ins_cost(125);
4956 format %{ "movsd $dst, $src\t# double stk" %}
4957 ins_encode %{
4958 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
4959 %}
4960 ins_pipe(pipe_slow); // XXX
4961 %}
4962
4963 // Prefetch instructions for allocation.
4964 // Must be safe to execute with invalid address (cannot fault).
4965
4966 instruct prefetchAlloc( memory mem ) %{
4967 predicate(AllocatePrefetchInstr==3);
4968 match(PrefetchAllocation mem);
4969 ins_cost(125);
4970
4971 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
4972 ins_encode %{
4973 __ prefetchw($mem$$Address);
4974 %}
4975 ins_pipe(ialu_mem);
4976 %}
4977
4978 instruct prefetchAllocNTA( memory mem ) %{
4979 predicate(AllocatePrefetchInstr==0);
4980 match(PrefetchAllocation mem);
4981 ins_cost(125);
4982
4983 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
4984 ins_encode %{
4985 __ prefetchnta($mem$$Address);
4986 %}
4987 ins_pipe(ialu_mem);
4988 %}
4989
4990 instruct prefetchAllocT0( memory mem ) %{
4991 predicate(AllocatePrefetchInstr==1);
4992 match(PrefetchAllocation mem);
4993 ins_cost(125);
4994
4995 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
4996 ins_encode %{
4997 __ prefetcht0($mem$$Address);
4998 %}
4999 ins_pipe(ialu_mem);
5000 %}
5001
5002 instruct prefetchAllocT2( memory mem ) %{
5003 predicate(AllocatePrefetchInstr==2);
5004 match(PrefetchAllocation mem);
5005 ins_cost(125);
5006
5007 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
5008 ins_encode %{
5009 __ prefetcht2($mem$$Address);
5010 %}
5011 ins_pipe(ialu_mem);
5012 %}
5013
5014 //----------Store Instructions-------------------------------------------------
5015
5016 // Store Byte
5017 instruct storeB(memory mem, rRegI src)
5018 %{
5019 match(Set mem (StoreB mem src));
5020
5021 ins_cost(125); // XXX
5022 format %{ "movb $mem, $src\t# byte" %}
5023 ins_encode %{
5024 __ movb($mem$$Address, $src$$Register);
5025 %}
5026 ins_pipe(ialu_mem_reg);
5027 %}
5028
5029 // Store Char/Short
5030 instruct storeC(memory mem, rRegI src)
5031 %{
5032 match(Set mem (StoreC mem src));
5033
5034 ins_cost(125); // XXX
5035 format %{ "movw $mem, $src\t# char/short" %}
5036 ins_encode %{
5037 __ movw($mem$$Address, $src$$Register);
5038 %}
5039 ins_pipe(ialu_mem_reg);
5040 %}
5041
5042 // Store Integer
5043 instruct storeI(memory mem, rRegI src)
5044 %{
5045 match(Set mem (StoreI mem src));
5046
5047 ins_cost(125); // XXX
5048 format %{ "movl $mem, $src\t# int" %}
5049 ins_encode %{
5050 __ movl($mem$$Address, $src$$Register);
5051 %}
5052 ins_pipe(ialu_mem_reg);
5053 %}
5054
5055 // Store Long
5056 instruct storeL(memory mem, rRegL src)
5057 %{
5058 match(Set mem (StoreL mem src));
5059
5060 ins_cost(125); // XXX
5061 format %{ "movq $mem, $src\t# long" %}
5062 ins_encode %{
5063 __ movq($mem$$Address, $src$$Register);
5064 %}
5065 ins_pipe(ialu_mem_reg); // XXX
5066 %}
5067
5068 // Store Pointer
5069 instruct storeP(memory mem, any_RegP src)
5070 %{
5071 predicate(n->as_Store()->barrier_data() == 0);
5072 match(Set mem (StoreP mem src));
5073
5074 ins_cost(125); // XXX
5075 format %{ "movq $mem, $src\t# ptr" %}
5076 ins_encode %{
5077 __ movq($mem$$Address, $src$$Register);
5078 %}
5079 ins_pipe(ialu_mem_reg);
5080 %}
5081
5082 instruct storeImmP0(memory mem, immP0 zero)
5083 %{
5084 predicate(UseCompressedOops && (CompressedOops::base() == nullptr) && n->as_Store()->barrier_data() == 0);
5085 match(Set mem (StoreP mem zero));
5086
5087 ins_cost(125); // XXX
5088 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
5089 ins_encode %{
5090 __ movq($mem$$Address, r12);
5091 %}
5092 ins_pipe(ialu_mem_reg);
5093 %}
5094
5095 // Store Null Pointer, mark word, or other simple pointer constant.
5096 instruct storeImmP(memory mem, immP31 src)
5097 %{
5098 predicate(n->as_Store()->barrier_data() == 0);
5099 match(Set mem (StoreP mem src));
5100
5101 ins_cost(150); // XXX
5102 format %{ "movq $mem, $src\t# ptr" %}
5103 ins_encode %{
5104 __ movq($mem$$Address, $src$$constant);
5105 %}
5106 ins_pipe(ialu_mem_imm);
5107 %}
5108
5109 // Store Compressed Pointer
5110 instruct storeN(memory mem, rRegN src)
5111 %{
5112 predicate(n->as_Store()->barrier_data() == 0);
5113 match(Set mem (StoreN mem src));
5114
5115 ins_cost(125); // XXX
5116 format %{ "movl $mem, $src\t# compressed ptr" %}
5117 ins_encode %{
5118 __ movl($mem$$Address, $src$$Register);
5119 %}
5120 ins_pipe(ialu_mem_reg);
5121 %}
5122
5123 instruct storeNKlass(memory mem, rRegN src)
5124 %{
5125 match(Set mem (StoreNKlass mem src));
5126
5127 ins_cost(125); // XXX
5128 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5129 ins_encode %{
5130 __ movl($mem$$Address, $src$$Register);
5131 %}
5132 ins_pipe(ialu_mem_reg);
5133 %}
5134
5135 instruct storeImmN0(memory mem, immN0 zero)
5136 %{
5137 predicate(CompressedOops::base() == nullptr && n->as_Store()->barrier_data() == 0);
5138 match(Set mem (StoreN mem zero));
5139
5140 ins_cost(125); // XXX
5141 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
5142 ins_encode %{
5143 __ movl($mem$$Address, r12);
5144 %}
5145 ins_pipe(ialu_mem_reg);
5146 %}
5147
5148 instruct storeImmN(memory mem, immN src)
5149 %{
5150 predicate(n->as_Store()->barrier_data() == 0);
5151 match(Set mem (StoreN mem src));
5152
5153 ins_cost(150); // XXX
5154 format %{ "movl $mem, $src\t# compressed ptr" %}
5155 ins_encode %{
5156 address con = (address)$src$$constant;
5157 if (con == nullptr) {
5158 __ movl($mem$$Address, 0);
5159 } else {
5160 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
5161 }
5162 %}
5163 ins_pipe(ialu_mem_imm);
5164 %}
5165
5166 instruct storeImmNKlass(memory mem, immNKlass src)
5167 %{
5168 match(Set mem (StoreNKlass mem src));
5169
5170 ins_cost(150); // XXX
5171 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5172 ins_encode %{
5173 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
5174 %}
5175 ins_pipe(ialu_mem_imm);
5176 %}
5177
5178 // Store Integer Immediate
5179 instruct storeImmI0(memory mem, immI_0 zero)
5180 %{
5181 predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
5182 match(Set mem (StoreI mem zero));
5183
5184 ins_cost(125); // XXX
5185 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
5186 ins_encode %{
5187 __ movl($mem$$Address, r12);
5188 %}
5189 ins_pipe(ialu_mem_reg);
5190 %}
5191
5192 instruct storeImmI(memory mem, immI src)
5193 %{
5194 match(Set mem (StoreI mem src));
5195
5196 ins_cost(150);
5197 format %{ "movl $mem, $src\t# int" %}
5198 ins_encode %{
5199 __ movl($mem$$Address, $src$$constant);
5200 %}
5201 ins_pipe(ialu_mem_imm);
5202 %}
5203
5204 // Store Long Immediate
5205 instruct storeImmL0(memory mem, immL0 zero)
5206 %{
5207 predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
5208 match(Set mem (StoreL mem zero));
5209
5210 ins_cost(125); // XXX
5211 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
5212 ins_encode %{
5213 __ movq($mem$$Address, r12);
5214 %}
5215 ins_pipe(ialu_mem_reg);
5216 %}
5217
5218 instruct storeImmL(memory mem, immL32 src)
5219 %{
5220 match(Set mem (StoreL mem src));
5221
5222 ins_cost(150);
5223 format %{ "movq $mem, $src\t# long" %}
5224 ins_encode %{
5225 __ movq($mem$$Address, $src$$constant);
5226 %}
5227 ins_pipe(ialu_mem_imm);
5228 %}
5229
5230 // Store Short/Char Immediate
5231 instruct storeImmC0(memory mem, immI_0 zero)
5232 %{
5233 predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
5234 match(Set mem (StoreC mem zero));
5235
5236 ins_cost(125); // XXX
5237 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
5238 ins_encode %{
5239 __ movw($mem$$Address, r12);
5240 %}
5241 ins_pipe(ialu_mem_reg);
5242 %}
5243
5244 instruct storeImmI16(memory mem, immI16 src)
5245 %{
5246 predicate(UseStoreImmI16);
5247 match(Set mem (StoreC mem src));
5248
5249 ins_cost(150);
5250 format %{ "movw $mem, $src\t# short/char" %}
5251 ins_encode %{
5252 __ movw($mem$$Address, $src$$constant);
5253 %}
5254 ins_pipe(ialu_mem_imm);
5255 %}
5256
5257 // Store Byte Immediate
5258 instruct storeImmB0(memory mem, immI_0 zero)
5259 %{
5260 predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
5261 match(Set mem (StoreB mem zero));
5262
5263 ins_cost(125); // XXX
5264 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
5265 ins_encode %{
5266 __ movb($mem$$Address, r12);
5267 %}
5268 ins_pipe(ialu_mem_reg);
5269 %}
5270
5271 instruct storeImmB(memory mem, immI8 src)
5272 %{
5273 match(Set mem (StoreB mem src));
5274
5275 ins_cost(150); // XXX
5276 format %{ "movb $mem, $src\t# byte" %}
5277 ins_encode %{
5278 __ movb($mem$$Address, $src$$constant);
5279 %}
5280 ins_pipe(ialu_mem_imm);
5281 %}
5282
5283 // Store Float
5284 instruct storeF(memory mem, regF src)
5285 %{
5286 match(Set mem (StoreF mem src));
5287
5288 ins_cost(95); // XXX
5289 format %{ "movss $mem, $src\t# float" %}
5290 ins_encode %{
5291 __ movflt($mem$$Address, $src$$XMMRegister);
5292 %}
5293 ins_pipe(pipe_slow); // XXX
5294 %}
5295
5296 // Store immediate Float value (it is faster than store from XMM register)
5297 instruct storeF0(memory mem, immF0 zero)
5298 %{
5299 predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
5300 match(Set mem (StoreF mem zero));
5301
5302 ins_cost(25); // XXX
5303 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
5304 ins_encode %{
5305 __ movl($mem$$Address, r12);
5306 %}
5307 ins_pipe(ialu_mem_reg);
5308 %}
5309
5310 instruct storeF_imm(memory mem, immF src)
5311 %{
5312 match(Set mem (StoreF mem src));
5313
5314 ins_cost(50);
5315 format %{ "movl $mem, $src\t# float" %}
5316 ins_encode %{
5317 __ movl($mem$$Address, jint_cast($src$$constant));
5318 %}
5319 ins_pipe(ialu_mem_imm);
5320 %}
5321
5322 // Store Double
5323 instruct storeD(memory mem, regD src)
5324 %{
5325 match(Set mem (StoreD mem src));
5326
5327 ins_cost(95); // XXX
5328 format %{ "movsd $mem, $src\t# double" %}
5329 ins_encode %{
5330 __ movdbl($mem$$Address, $src$$XMMRegister);
5331 %}
5332 ins_pipe(pipe_slow); // XXX
5333 %}
5334
5335 // Store immediate double 0.0 (it is faster than store from XMM register)
5336 instruct storeD0_imm(memory mem, immD0 src)
5337 %{
5338 predicate(!UseCompressedOops || (CompressedOops::base() != nullptr));
5339 match(Set mem (StoreD mem src));
5340
5341 ins_cost(50);
5342 format %{ "movq $mem, $src\t# double 0." %}
5343 ins_encode %{
5344 __ movq($mem$$Address, $src$$constant);
5345 %}
5346 ins_pipe(ialu_mem_imm);
5347 %}
5348
5349 instruct storeD0(memory mem, immD0 zero)
5350 %{
5351 predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
5352 match(Set mem (StoreD mem zero));
5353
5354 ins_cost(25); // XXX
5355 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
5356 ins_encode %{
5357 __ movq($mem$$Address, r12);
5358 %}
5359 ins_pipe(ialu_mem_reg);
5360 %}
5361
5362 instruct storeSSI(stackSlotI dst, rRegI src)
5363 %{
5364 match(Set dst src);
5365
5366 ins_cost(100);
5367 format %{ "movl $dst, $src\t# int stk" %}
5368 ins_encode %{
5369 __ movl($dst$$Address, $src$$Register);
5370 %}
5371 ins_pipe( ialu_mem_reg );
5372 %}
5373
5374 instruct storeSSL(stackSlotL dst, rRegL src)
5375 %{
5376 match(Set dst src);
5377
5378 ins_cost(100);
5379 format %{ "movq $dst, $src\t# long stk" %}
5380 ins_encode %{
5381 __ movq($dst$$Address, $src$$Register);
5382 %}
5383 ins_pipe(ialu_mem_reg);
5384 %}
5385
5386 instruct storeSSP(stackSlotP dst, rRegP src)
5387 %{
5388 match(Set dst src);
5389
5390 ins_cost(100);
5391 format %{ "movq $dst, $src\t# ptr stk" %}
5392 ins_encode %{
5393 __ movq($dst$$Address, $src$$Register);
5394 %}
5395 ins_pipe(ialu_mem_reg);
5396 %}
5397
5398 instruct storeSSF(stackSlotF dst, regF src)
5399 %{
5400 match(Set dst src);
5401
5402 ins_cost(95); // XXX
5403 format %{ "movss $dst, $src\t# float stk" %}
5404 ins_encode %{
5405 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
5406 %}
5407 ins_pipe(pipe_slow); // XXX
5408 %}
5409
5410 instruct storeSSD(stackSlotD dst, regD src)
5411 %{
5412 match(Set dst src);
5413
5414 ins_cost(95); // XXX
5415 format %{ "movsd $dst, $src\t# double stk" %}
5416 ins_encode %{
5417 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
5418 %}
5419 ins_pipe(pipe_slow); // XXX
5420 %}
5421
5422 instruct cacheWB(indirect addr)
5423 %{
5424 predicate(VM_Version::supports_data_cache_line_flush());
5425 match(CacheWB addr);
5426
5427 ins_cost(100);
5428 format %{"cache wb $addr" %}
5429 ins_encode %{
5430 assert($addr->index_position() < 0, "should be");
5431 assert($addr$$disp == 0, "should be");
5432 __ cache_wb(Address($addr$$base$$Register, 0));
5433 %}
5434 ins_pipe(pipe_slow); // XXX
5435 %}
5436
5437 instruct cacheWBPreSync()
5438 %{
5439 predicate(VM_Version::supports_data_cache_line_flush());
5440 match(CacheWBPreSync);
5441
5442 ins_cost(100);
5443 format %{"cache wb presync" %}
5444 ins_encode %{
5445 __ cache_wbsync(true);
5446 %}
5447 ins_pipe(pipe_slow); // XXX
5448 %}
5449
5450 instruct cacheWBPostSync()
5451 %{
5452 predicate(VM_Version::supports_data_cache_line_flush());
5453 match(CacheWBPostSync);
5454
5455 ins_cost(100);
5456 format %{"cache wb postsync" %}
5457 ins_encode %{
5458 __ cache_wbsync(false);
5459 %}
5460 ins_pipe(pipe_slow); // XXX
5461 %}
5462
5463 //----------BSWAP Instructions-------------------------------------------------
5464 instruct bytes_reverse_int(rRegI dst) %{
5465 match(Set dst (ReverseBytesI dst));
5466
5467 format %{ "bswapl $dst" %}
5468 ins_encode %{
5469 __ bswapl($dst$$Register);
5470 %}
5471 ins_pipe( ialu_reg );
5472 %}
5473
5474 instruct bytes_reverse_long(rRegL dst) %{
5475 match(Set dst (ReverseBytesL dst));
5476
5477 format %{ "bswapq $dst" %}
5478 ins_encode %{
5479 __ bswapq($dst$$Register);
5480 %}
5481 ins_pipe( ialu_reg);
5482 %}
5483
5484 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
5485 match(Set dst (ReverseBytesUS dst));
5486 effect(KILL cr);
5487
5488 format %{ "bswapl $dst\n\t"
5489 "shrl $dst,16\n\t" %}
5490 ins_encode %{
5491 __ bswapl($dst$$Register);
5492 __ shrl($dst$$Register, 16);
5493 %}
5494 ins_pipe( ialu_reg );
5495 %}
5496
5497 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
5498 match(Set dst (ReverseBytesS dst));
5499 effect(KILL cr);
5500
5501 format %{ "bswapl $dst\n\t"
5502 "sar $dst,16\n\t" %}
5503 ins_encode %{
5504 __ bswapl($dst$$Register);
5505 __ sarl($dst$$Register, 16);
5506 %}
5507 ins_pipe( ialu_reg );
5508 %}
5509
5510 //---------- Zeros Count Instructions ------------------------------------------
5511
5512 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
5513 predicate(UseCountLeadingZerosInstruction);
5514 match(Set dst (CountLeadingZerosI src));
5515 effect(KILL cr);
5516
5517 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
5518 ins_encode %{
5519 __ lzcntl($dst$$Register, $src$$Register);
5520 %}
5521 ins_pipe(ialu_reg);
5522 %}
5523
5524 instruct countLeadingZerosI_mem(rRegI dst, memory src, rFlagsReg cr) %{
5525 predicate(UseCountLeadingZerosInstruction);
5526 match(Set dst (CountLeadingZerosI (LoadI src)));
5527 effect(KILL cr);
5528 ins_cost(175);
5529 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
5530 ins_encode %{
5531 __ lzcntl($dst$$Register, $src$$Address);
5532 %}
5533 ins_pipe(ialu_reg_mem);
5534 %}
5535
5536 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
5537 predicate(!UseCountLeadingZerosInstruction);
5538 match(Set dst (CountLeadingZerosI src));
5539 effect(KILL cr);
5540
5541 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
5542 "jnz skip\n\t"
5543 "movl $dst, -1\n"
5544 "skip:\n\t"
5545 "negl $dst\n\t"
5546 "addl $dst, 31" %}
5547 ins_encode %{
5548 Register Rdst = $dst$$Register;
5549 Register Rsrc = $src$$Register;
5550 Label skip;
5551 __ bsrl(Rdst, Rsrc);
5552 __ jccb(Assembler::notZero, skip);
5553 __ movl(Rdst, -1);
5554 __ bind(skip);
5555 __ negl(Rdst);
5556 __ addl(Rdst, BitsPerInt - 1);
5557 %}
5558 ins_pipe(ialu_reg);
5559 %}
5560
5561 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
5562 predicate(UseCountLeadingZerosInstruction);
5563 match(Set dst (CountLeadingZerosL src));
5564 effect(KILL cr);
5565
5566 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
5567 ins_encode %{
5568 __ lzcntq($dst$$Register, $src$$Register);
5569 %}
5570 ins_pipe(ialu_reg);
5571 %}
5572
5573 instruct countLeadingZerosL_mem(rRegI dst, memory src, rFlagsReg cr) %{
5574 predicate(UseCountLeadingZerosInstruction);
5575 match(Set dst (CountLeadingZerosL (LoadL src)));
5576 effect(KILL cr);
5577 ins_cost(175);
5578 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
5579 ins_encode %{
5580 __ lzcntq($dst$$Register, $src$$Address);
5581 %}
5582 ins_pipe(ialu_reg_mem);
5583 %}
5584
5585 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
5586 predicate(!UseCountLeadingZerosInstruction);
5587 match(Set dst (CountLeadingZerosL src));
5588 effect(KILL cr);
5589
5590 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
5591 "jnz skip\n\t"
5592 "movl $dst, -1\n"
5593 "skip:\n\t"
5594 "negl $dst\n\t"
5595 "addl $dst, 63" %}
5596 ins_encode %{
5597 Register Rdst = $dst$$Register;
5598 Register Rsrc = $src$$Register;
5599 Label skip;
5600 __ bsrq(Rdst, Rsrc);
5601 __ jccb(Assembler::notZero, skip);
5602 __ movl(Rdst, -1);
5603 __ bind(skip);
5604 __ negl(Rdst);
5605 __ addl(Rdst, BitsPerLong - 1);
5606 %}
5607 ins_pipe(ialu_reg);
5608 %}
5609
5610 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
5611 predicate(UseCountTrailingZerosInstruction);
5612 match(Set dst (CountTrailingZerosI src));
5613 effect(KILL cr);
5614
5615 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
5616 ins_encode %{
5617 __ tzcntl($dst$$Register, $src$$Register);
5618 %}
5619 ins_pipe(ialu_reg);
5620 %}
5621
5622 instruct countTrailingZerosI_mem(rRegI dst, memory src, rFlagsReg cr) %{
5623 predicate(UseCountTrailingZerosInstruction);
5624 match(Set dst (CountTrailingZerosI (LoadI src)));
5625 effect(KILL cr);
5626 ins_cost(175);
5627 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
5628 ins_encode %{
5629 __ tzcntl($dst$$Register, $src$$Address);
5630 %}
5631 ins_pipe(ialu_reg_mem);
5632 %}
5633
5634 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
5635 predicate(!UseCountTrailingZerosInstruction);
5636 match(Set dst (CountTrailingZerosI src));
5637 effect(KILL cr);
5638
5639 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
5640 "jnz done\n\t"
5641 "movl $dst, 32\n"
5642 "done:" %}
5643 ins_encode %{
5644 Register Rdst = $dst$$Register;
5645 Label done;
5646 __ bsfl(Rdst, $src$$Register);
5647 __ jccb(Assembler::notZero, done);
5648 __ movl(Rdst, BitsPerInt);
5649 __ bind(done);
5650 %}
5651 ins_pipe(ialu_reg);
5652 %}
5653
5654 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
5655 predicate(UseCountTrailingZerosInstruction);
5656 match(Set dst (CountTrailingZerosL src));
5657 effect(KILL cr);
5658
5659 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
5660 ins_encode %{
5661 __ tzcntq($dst$$Register, $src$$Register);
5662 %}
5663 ins_pipe(ialu_reg);
5664 %}
5665
5666 instruct countTrailingZerosL_mem(rRegI dst, memory src, rFlagsReg cr) %{
5667 predicate(UseCountTrailingZerosInstruction);
5668 match(Set dst (CountTrailingZerosL (LoadL src)));
5669 effect(KILL cr);
5670 ins_cost(175);
5671 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
5672 ins_encode %{
5673 __ tzcntq($dst$$Register, $src$$Address);
5674 %}
5675 ins_pipe(ialu_reg_mem);
5676 %}
5677
5678 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
5679 predicate(!UseCountTrailingZerosInstruction);
5680 match(Set dst (CountTrailingZerosL src));
5681 effect(KILL cr);
5682
5683 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
5684 "jnz done\n\t"
5685 "movl $dst, 64\n"
5686 "done:" %}
5687 ins_encode %{
5688 Register Rdst = $dst$$Register;
5689 Label done;
5690 __ bsfq(Rdst, $src$$Register);
5691 __ jccb(Assembler::notZero, done);
5692 __ movl(Rdst, BitsPerLong);
5693 __ bind(done);
5694 %}
5695 ins_pipe(ialu_reg);
5696 %}
5697
5698 //--------------- Reverse Operation Instructions ----------------
5699 instruct bytes_reversebit_int(rRegI dst, rRegI src, rRegI rtmp, rFlagsReg cr) %{
5700 predicate(!VM_Version::supports_gfni());
5701 match(Set dst (ReverseI src));
5702 effect(TEMP dst, TEMP rtmp, KILL cr);
5703 format %{ "reverse_int $dst $src\t! using $rtmp as TEMP" %}
5704 ins_encode %{
5705 __ reverseI($dst$$Register, $src$$Register, xnoreg, xnoreg, $rtmp$$Register);
5706 %}
5707 ins_pipe( ialu_reg );
5708 %}
5709
5710 instruct bytes_reversebit_int_gfni(rRegI dst, rRegI src, vlRegF xtmp1, vlRegF xtmp2, rRegL rtmp, rFlagsReg cr) %{
5711 predicate(VM_Version::supports_gfni());
5712 match(Set dst (ReverseI src));
5713 effect(TEMP dst, TEMP xtmp1, TEMP xtmp2, TEMP rtmp, KILL cr);
5714 format %{ "reverse_int $dst $src\t! using $rtmp, $xtmp1 and $xtmp2 as TEMP" %}
5715 ins_encode %{
5716 __ reverseI($dst$$Register, $src$$Register, $xtmp1$$XMMRegister, $xtmp2$$XMMRegister, $rtmp$$Register);
5717 %}
5718 ins_pipe( ialu_reg );
5719 %}
5720
5721 instruct bytes_reversebit_long(rRegL dst, rRegL src, rRegL rtmp1, rRegL rtmp2, rFlagsReg cr) %{
5722 predicate(!VM_Version::supports_gfni());
5723 match(Set dst (ReverseL src));
5724 effect(TEMP dst, TEMP rtmp1, TEMP rtmp2, KILL cr);
5725 format %{ "reverse_long $dst $src\t! using $rtmp1 and $rtmp2 as TEMP" %}
5726 ins_encode %{
5727 __ reverseL($dst$$Register, $src$$Register, xnoreg, xnoreg, $rtmp1$$Register, $rtmp2$$Register);
5728 %}
5729 ins_pipe( ialu_reg );
5730 %}
5731
5732 instruct bytes_reversebit_long_gfni(rRegL dst, rRegL src, vlRegD xtmp1, vlRegD xtmp2, rRegL rtmp, rFlagsReg cr) %{
5733 predicate(VM_Version::supports_gfni());
5734 match(Set dst (ReverseL src));
5735 effect(TEMP dst, TEMP xtmp1, TEMP xtmp2, TEMP rtmp, KILL cr);
5736 format %{ "reverse_long $dst $src\t! using $rtmp, $xtmp1 and $xtmp2 as TEMP" %}
5737 ins_encode %{
5738 __ reverseL($dst$$Register, $src$$Register, $xtmp1$$XMMRegister, $xtmp2$$XMMRegister, $rtmp$$Register, noreg);
5739 %}
5740 ins_pipe( ialu_reg );
5741 %}
5742
5743 //---------- Population Count Instructions -------------------------------------
5744
5745 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
5746 predicate(UsePopCountInstruction);
5747 match(Set dst (PopCountI src));
5748 effect(KILL cr);
5749
5750 format %{ "popcnt $dst, $src" %}
5751 ins_encode %{
5752 __ popcntl($dst$$Register, $src$$Register);
5753 %}
5754 ins_pipe(ialu_reg);
5755 %}
5756
5757 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
5758 predicate(UsePopCountInstruction);
5759 match(Set dst (PopCountI (LoadI mem)));
5760 effect(KILL cr);
5761
5762 format %{ "popcnt $dst, $mem" %}
5763 ins_encode %{
5764 __ popcntl($dst$$Register, $mem$$Address);
5765 %}
5766 ins_pipe(ialu_reg);
5767 %}
5768
5769 // Note: Long.bitCount(long) returns an int.
5770 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
5771 predicate(UsePopCountInstruction);
5772 match(Set dst (PopCountL src));
5773 effect(KILL cr);
5774
5775 format %{ "popcnt $dst, $src" %}
5776 ins_encode %{
5777 __ popcntq($dst$$Register, $src$$Register);
5778 %}
5779 ins_pipe(ialu_reg);
5780 %}
5781
5782 // Note: Long.bitCount(long) returns an int.
5783 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
5784 predicate(UsePopCountInstruction);
5785 match(Set dst (PopCountL (LoadL mem)));
5786 effect(KILL cr);
5787
5788 format %{ "popcnt $dst, $mem" %}
5789 ins_encode %{
5790 __ popcntq($dst$$Register, $mem$$Address);
5791 %}
5792 ins_pipe(ialu_reg);
5793 %}
5794
5795
5796 //----------MemBar Instructions-----------------------------------------------
5797 // Memory barrier flavors
5798
5799 instruct membar_acquire()
5800 %{
5801 match(MemBarAcquire);
5802 match(LoadFence);
5803 ins_cost(0);
5804
5805 size(0);
5806 format %{ "MEMBAR-acquire ! (empty encoding)" %}
5807 ins_encode();
5808 ins_pipe(empty);
5809 %}
5810
5811 instruct membar_acquire_lock()
5812 %{
5813 match(MemBarAcquireLock);
5814 ins_cost(0);
5815
5816 size(0);
5817 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
5818 ins_encode();
5819 ins_pipe(empty);
5820 %}
5821
5822 instruct membar_release()
5823 %{
5824 match(MemBarRelease);
5825 match(StoreFence);
5826 ins_cost(0);
5827
5828 size(0);
5829 format %{ "MEMBAR-release ! (empty encoding)" %}
5830 ins_encode();
5831 ins_pipe(empty);
5832 %}
5833
5834 instruct membar_release_lock()
5835 %{
5836 match(MemBarReleaseLock);
5837 ins_cost(0);
5838
5839 size(0);
5840 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
5841 ins_encode();
5842 ins_pipe(empty);
5843 %}
5844
5845 instruct membar_volatile(rFlagsReg cr) %{
5846 match(MemBarVolatile);
5847 effect(KILL cr);
5848 ins_cost(400);
5849
5850 format %{
5851 $$template
5852 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
5853 %}
5854 ins_encode %{
5855 __ membar(Assembler::StoreLoad);
5856 %}
5857 ins_pipe(pipe_slow);
5858 %}
5859
5860 instruct unnecessary_membar_volatile()
5861 %{
5862 match(MemBarVolatile);
5863 predicate(Matcher::post_store_load_barrier(n));
5864 ins_cost(0);
5865
5866 size(0);
5867 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
5868 ins_encode();
5869 ins_pipe(empty);
5870 %}
5871
5872 instruct membar_storestore() %{
5873 match(MemBarStoreStore);
5874 match(StoreStoreFence);
5875 ins_cost(0);
5876
5877 size(0);
5878 format %{ "MEMBAR-storestore (empty encoding)" %}
5879 ins_encode( );
5880 ins_pipe(empty);
5881 %}
5882
5883 //----------Move Instructions--------------------------------------------------
5884
5885 instruct castX2P(rRegP dst, rRegL src)
5886 %{
5887 match(Set dst (CastX2P src));
5888
5889 format %{ "movq $dst, $src\t# long->ptr" %}
5890 ins_encode %{
5891 if ($dst$$reg != $src$$reg) {
5892 __ movptr($dst$$Register, $src$$Register);
5893 }
5894 %}
5895 ins_pipe(ialu_reg_reg); // XXX
5896 %}
5897
5898 instruct castP2X(rRegL dst, rRegP src)
5899 %{
5900 match(Set dst (CastP2X src));
5901
5902 format %{ "movq $dst, $src\t# ptr -> long" %}
5903 ins_encode %{
5904 if ($dst$$reg != $src$$reg) {
5905 __ movptr($dst$$Register, $src$$Register);
5906 }
5907 %}
5908 ins_pipe(ialu_reg_reg); // XXX
5909 %}
5910
5911 // Convert oop into int for vectors alignment masking
5912 instruct convP2I(rRegI dst, rRegP src)
5913 %{
5914 match(Set dst (ConvL2I (CastP2X src)));
5915
5916 format %{ "movl $dst, $src\t# ptr -> int" %}
5917 ins_encode %{
5918 __ movl($dst$$Register, $src$$Register);
5919 %}
5920 ins_pipe(ialu_reg_reg); // XXX
5921 %}
5922
5923 // Convert compressed oop into int for vectors alignment masking
5924 // in case of 32bit oops (heap < 4Gb).
5925 instruct convN2I(rRegI dst, rRegN src)
5926 %{
5927 predicate(CompressedOops::shift() == 0);
5928 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
5929
5930 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
5931 ins_encode %{
5932 __ movl($dst$$Register, $src$$Register);
5933 %}
5934 ins_pipe(ialu_reg_reg); // XXX
5935 %}
5936
5937 // Convert oop pointer into compressed form
5938 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
5939 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
5940 match(Set dst (EncodeP src));
5941 effect(KILL cr);
5942 format %{ "encode_heap_oop $dst,$src" %}
5943 ins_encode %{
5944 Register s = $src$$Register;
5945 Register d = $dst$$Register;
5946 if (s != d) {
5947 __ movq(d, s);
5948 }
5949 __ encode_heap_oop(d);
5950 %}
5951 ins_pipe(ialu_reg_long);
5952 %}
5953
5954 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
5955 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
5956 match(Set dst (EncodeP src));
5957 effect(KILL cr);
5958 format %{ "encode_heap_oop_not_null $dst,$src" %}
5959 ins_encode %{
5960 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
5961 %}
5962 ins_pipe(ialu_reg_long);
5963 %}
5964
5965 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
5966 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
5967 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
5968 match(Set dst (DecodeN src));
5969 effect(KILL cr);
5970 format %{ "decode_heap_oop $dst,$src" %}
5971 ins_encode %{
5972 Register s = $src$$Register;
5973 Register d = $dst$$Register;
5974 if (s != d) {
5975 __ movq(d, s);
5976 }
5977 __ decode_heap_oop(d);
5978 %}
5979 ins_pipe(ialu_reg_long);
5980 %}
5981
5982 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
5983 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
5984 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
5985 match(Set dst (DecodeN src));
5986 effect(KILL cr);
5987 format %{ "decode_heap_oop_not_null $dst,$src" %}
5988 ins_encode %{
5989 Register s = $src$$Register;
5990 Register d = $dst$$Register;
5991 if (s != d) {
5992 __ decode_heap_oop_not_null(d, s);
5993 } else {
5994 __ decode_heap_oop_not_null(d);
5995 }
5996 %}
5997 ins_pipe(ialu_reg_long);
5998 %}
5999
6000 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6001 match(Set dst (EncodePKlass src));
6002 effect(TEMP dst, KILL cr);
6003 format %{ "encode_and_move_klass_not_null $dst,$src" %}
6004 ins_encode %{
6005 __ encode_and_move_klass_not_null($dst$$Register, $src$$Register);
6006 %}
6007 ins_pipe(ialu_reg_long);
6008 %}
6009
6010 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6011 match(Set dst (DecodeNKlass src));
6012 effect(TEMP dst, KILL cr);
6013 format %{ "decode_and_move_klass_not_null $dst,$src" %}
6014 ins_encode %{
6015 __ decode_and_move_klass_not_null($dst$$Register, $src$$Register);
6016 %}
6017 ins_pipe(ialu_reg_long);
6018 %}
6019
6020 //----------Conditional Move---------------------------------------------------
6021 // Jump
6022 // dummy instruction for generating temp registers
6023 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6024 match(Jump (LShiftL switch_val shift));
6025 ins_cost(350);
6026 predicate(false);
6027 effect(TEMP dest);
6028
6029 format %{ "leaq $dest, [$constantaddress]\n\t"
6030 "jmp [$dest + $switch_val << $shift]\n\t" %}
6031 ins_encode %{
6032 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6033 // to do that and the compiler is using that register as one it can allocate.
6034 // So we build it all by hand.
6035 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6036 // ArrayAddress dispatch(table, index);
6037 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6038 __ lea($dest$$Register, $constantaddress);
6039 __ jmp(dispatch);
6040 %}
6041 ins_pipe(pipe_jmp);
6042 %}
6043
6044 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6045 match(Jump (AddL (LShiftL switch_val shift) offset));
6046 ins_cost(350);
6047 effect(TEMP dest);
6048
6049 format %{ "leaq $dest, [$constantaddress]\n\t"
6050 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
6051 ins_encode %{
6052 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6053 // to do that and the compiler is using that register as one it can allocate.
6054 // So we build it all by hand.
6055 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6056 // ArrayAddress dispatch(table, index);
6057 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6058 __ lea($dest$$Register, $constantaddress);
6059 __ jmp(dispatch);
6060 %}
6061 ins_pipe(pipe_jmp);
6062 %}
6063
6064 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
6065 match(Jump switch_val);
6066 ins_cost(350);
6067 effect(TEMP dest);
6068
6069 format %{ "leaq $dest, [$constantaddress]\n\t"
6070 "jmp [$dest + $switch_val]\n\t" %}
6071 ins_encode %{
6072 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6073 // to do that and the compiler is using that register as one it can allocate.
6074 // So we build it all by hand.
6075 // Address index(noreg, switch_reg, Address::times_1);
6076 // ArrayAddress dispatch(table, index);
6077 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
6078 __ lea($dest$$Register, $constantaddress);
6079 __ jmp(dispatch);
6080 %}
6081 ins_pipe(pipe_jmp);
6082 %}
6083
6084 // Conditional move
6085 instruct cmovI_imm_01(rRegI dst, immI_1 src, rFlagsReg cr, cmpOp cop)
6086 %{
6087 predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_int() == 0);
6088 match(Set dst (CMoveI (Binary cop cr) (Binary src dst)));
6089
6090 ins_cost(100); // XXX
6091 format %{ "setbn$cop $dst\t# signed, int" %}
6092 ins_encode %{
6093 Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
6094 __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
6095 %}
6096 ins_pipe(ialu_reg);
6097 %}
6098
6099 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
6100 %{
6101 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6102
6103 ins_cost(200); // XXX
6104 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6105 ins_encode %{
6106 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6107 %}
6108 ins_pipe(pipe_cmov_reg);
6109 %}
6110
6111 instruct cmovI_imm_01U(rRegI dst, immI_1 src, rFlagsRegU cr, cmpOpU cop)
6112 %{
6113 predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_int() == 0);
6114 match(Set dst (CMoveI (Binary cop cr) (Binary src dst)));
6115
6116 ins_cost(100); // XXX
6117 format %{ "setbn$cop $dst\t# unsigned, int" %}
6118 ins_encode %{
6119 Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
6120 __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
6121 %}
6122 ins_pipe(ialu_reg);
6123 %}
6124
6125 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
6126 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6127
6128 ins_cost(200); // XXX
6129 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6130 ins_encode %{
6131 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6132 %}
6133 ins_pipe(pipe_cmov_reg);
6134 %}
6135
6136 instruct cmovI_imm_01UCF(rRegI dst, immI_1 src, rFlagsRegUCF cr, cmpOpUCF cop)
6137 %{
6138 predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_int() == 0);
6139 match(Set dst (CMoveI (Binary cop cr) (Binary src dst)));
6140
6141 ins_cost(100); // XXX
6142 format %{ "setbn$cop $dst\t# unsigned, int" %}
6143 ins_encode %{
6144 Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
6145 __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
6146 %}
6147 ins_pipe(ialu_reg);
6148 %}
6149
6150 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6151 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6152 ins_cost(200);
6153 expand %{
6154 cmovI_regU(cop, cr, dst, src);
6155 %}
6156 %}
6157
6158 instruct cmovI_regUCF2_ne(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6159 predicate(n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
6160 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6161
6162 ins_cost(200); // XXX
6163 format %{ "cmovpl $dst, $src\n\t"
6164 "cmovnel $dst, $src" %}
6165 ins_encode %{
6166 __ cmovl(Assembler::parity, $dst$$Register, $src$$Register);
6167 __ cmovl(Assembler::notEqual, $dst$$Register, $src$$Register);
6168 %}
6169 ins_pipe(pipe_cmov_reg);
6170 %}
6171
6172 // Since (x == y) == !(x != y), we can flip the sense of the test by flipping the
6173 // inputs of the CMove
6174 instruct cmovI_regUCF2_eq(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6175 predicate(n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
6176 match(Set dst (CMoveI (Binary cop cr) (Binary src dst)));
6177
6178 ins_cost(200); // XXX
6179 format %{ "cmovpl $dst, $src\n\t"
6180 "cmovnel $dst, $src" %}
6181 ins_encode %{
6182 __ cmovl(Assembler::parity, $dst$$Register, $src$$Register);
6183 __ cmovl(Assembler::notEqual, $dst$$Register, $src$$Register);
6184 %}
6185 ins_pipe(pipe_cmov_reg);
6186 %}
6187
6188 // Conditional move
6189 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
6190 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6191
6192 ins_cost(250); // XXX
6193 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6194 ins_encode %{
6195 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
6196 %}
6197 ins_pipe(pipe_cmov_mem);
6198 %}
6199
6200 // Conditional move
6201 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
6202 %{
6203 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6204
6205 ins_cost(250); // XXX
6206 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6207 ins_encode %{
6208 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
6209 %}
6210 ins_pipe(pipe_cmov_mem);
6211 %}
6212
6213 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
6214 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6215 ins_cost(250);
6216 expand %{
6217 cmovI_memU(cop, cr, dst, src);
6218 %}
6219 %}
6220
6221 // Conditional move
6222 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
6223 %{
6224 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6225
6226 ins_cost(200); // XXX
6227 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
6228 ins_encode %{
6229 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6230 %}
6231 ins_pipe(pipe_cmov_reg);
6232 %}
6233
6234 // Conditional move
6235 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
6236 %{
6237 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6238
6239 ins_cost(200); // XXX
6240 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
6241 ins_encode %{
6242 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6243 %}
6244 ins_pipe(pipe_cmov_reg);
6245 %}
6246
6247 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6248 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6249 ins_cost(200);
6250 expand %{
6251 cmovN_regU(cop, cr, dst, src);
6252 %}
6253 %}
6254
6255 instruct cmovN_regUCF2_ne(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6256 predicate(n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
6257 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6258
6259 ins_cost(200); // XXX
6260 format %{ "cmovpl $dst, $src\n\t"
6261 "cmovnel $dst, $src" %}
6262 ins_encode %{
6263 __ cmovl(Assembler::parity, $dst$$Register, $src$$Register);
6264 __ cmovl(Assembler::notEqual, $dst$$Register, $src$$Register);
6265 %}
6266 ins_pipe(pipe_cmov_reg);
6267 %}
6268
6269 // Since (x == y) == !(x != y), we can flip the sense of the test by flipping the
6270 // inputs of the CMove
6271 instruct cmovN_regUCF2_eq(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6272 predicate(n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
6273 match(Set dst (CMoveN (Binary cop cr) (Binary src dst)));
6274
6275 ins_cost(200); // XXX
6276 format %{ "cmovpl $dst, $src\n\t"
6277 "cmovnel $dst, $src" %}
6278 ins_encode %{
6279 __ cmovl(Assembler::parity, $dst$$Register, $src$$Register);
6280 __ cmovl(Assembler::notEqual, $dst$$Register, $src$$Register);
6281 %}
6282 ins_pipe(pipe_cmov_reg);
6283 %}
6284
6285 // Conditional move
6286 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
6287 %{
6288 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6289
6290 ins_cost(200); // XXX
6291 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
6292 ins_encode %{
6293 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6294 %}
6295 ins_pipe(pipe_cmov_reg); // XXX
6296 %}
6297
6298 // Conditional move
6299 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
6300 %{
6301 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6302
6303 ins_cost(200); // XXX
6304 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
6305 ins_encode %{
6306 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6307 %}
6308 ins_pipe(pipe_cmov_reg); // XXX
6309 %}
6310
6311 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6312 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6313 ins_cost(200);
6314 expand %{
6315 cmovP_regU(cop, cr, dst, src);
6316 %}
6317 %}
6318
6319 instruct cmovP_regUCF2_ne(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6320 predicate(n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
6321 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6322
6323 ins_cost(200); // XXX
6324 format %{ "cmovpq $dst, $src\n\t"
6325 "cmovneq $dst, $src" %}
6326 ins_encode %{
6327 __ cmovq(Assembler::parity, $dst$$Register, $src$$Register);
6328 __ cmovq(Assembler::notEqual, $dst$$Register, $src$$Register);
6329 %}
6330 ins_pipe(pipe_cmov_reg);
6331 %}
6332
6333 // Since (x == y) == !(x != y), we can flip the sense of the test by flipping the
6334 // inputs of the CMove
6335 instruct cmovP_regUCF2_eq(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6336 predicate(n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
6337 match(Set dst (CMoveP (Binary cop cr) (Binary src dst)));
6338
6339 ins_cost(200); // XXX
6340 format %{ "cmovpq $dst, $src\n\t"
6341 "cmovneq $dst, $src" %}
6342 ins_encode %{
6343 __ cmovq(Assembler::parity, $dst$$Register, $src$$Register);
6344 __ cmovq(Assembler::notEqual, $dst$$Register, $src$$Register);
6345 %}
6346 ins_pipe(pipe_cmov_reg);
6347 %}
6348
6349 instruct cmovL_imm_01(rRegL dst, immL1 src, rFlagsReg cr, cmpOp cop)
6350 %{
6351 predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_long() == 0);
6352 match(Set dst (CMoveL (Binary cop cr) (Binary src dst)));
6353
6354 ins_cost(100); // XXX
6355 format %{ "setbn$cop $dst\t# signed, long" %}
6356 ins_encode %{
6357 Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
6358 __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
6359 %}
6360 ins_pipe(ialu_reg);
6361 %}
6362
6363 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
6364 %{
6365 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6366
6367 ins_cost(200); // XXX
6368 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6369 ins_encode %{
6370 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6371 %}
6372 ins_pipe(pipe_cmov_reg); // XXX
6373 %}
6374
6375 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
6376 %{
6377 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6378
6379 ins_cost(200); // XXX
6380 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6381 ins_encode %{
6382 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
6383 %}
6384 ins_pipe(pipe_cmov_mem); // XXX
6385 %}
6386
6387 instruct cmovL_imm_01U(rRegL dst, immL1 src, rFlagsRegU cr, cmpOpU cop)
6388 %{
6389 predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_long() == 0);
6390 match(Set dst (CMoveL (Binary cop cr) (Binary src dst)));
6391
6392 ins_cost(100); // XXX
6393 format %{ "setbn$cop $dst\t# unsigned, long" %}
6394 ins_encode %{
6395 Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
6396 __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
6397 %}
6398 ins_pipe(ialu_reg);
6399 %}
6400
6401 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
6402 %{
6403 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6404
6405 ins_cost(200); // XXX
6406 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6407 ins_encode %{
6408 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6409 %}
6410 ins_pipe(pipe_cmov_reg); // XXX
6411 %}
6412
6413 instruct cmovL_imm_01UCF(rRegL dst, immL1 src, rFlagsRegUCF cr, cmpOpUCF cop)
6414 %{
6415 predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_long() == 0);
6416 match(Set dst (CMoveL (Binary cop cr) (Binary src dst)));
6417
6418 ins_cost(100); // XXX
6419 format %{ "setbn$cop $dst\t# unsigned, long" %}
6420 ins_encode %{
6421 Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
6422 __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
6423 %}
6424 ins_pipe(ialu_reg);
6425 %}
6426
6427 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
6428 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6429 ins_cost(200);
6430 expand %{
6431 cmovL_regU(cop, cr, dst, src);
6432 %}
6433 %}
6434
6435 instruct cmovL_regUCF2_ne(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
6436 predicate(n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
6437 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6438
6439 ins_cost(200); // XXX
6440 format %{ "cmovpq $dst, $src\n\t"
6441 "cmovneq $dst, $src" %}
6442 ins_encode %{
6443 __ cmovq(Assembler::parity, $dst$$Register, $src$$Register);
6444 __ cmovq(Assembler::notEqual, $dst$$Register, $src$$Register);
6445 %}
6446 ins_pipe(pipe_cmov_reg);
6447 %}
6448
6449 // Since (x == y) == !(x != y), we can flip the sense of the test by flipping the
6450 // inputs of the CMove
6451 instruct cmovL_regUCF2_eq(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
6452 predicate(n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
6453 match(Set dst (CMoveL (Binary cop cr) (Binary src dst)));
6454
6455 ins_cost(200); // XXX
6456 format %{ "cmovpq $dst, $src\n\t"
6457 "cmovneq $dst, $src" %}
6458 ins_encode %{
6459 __ cmovq(Assembler::parity, $dst$$Register, $src$$Register);
6460 __ cmovq(Assembler::notEqual, $dst$$Register, $src$$Register);
6461 %}
6462 ins_pipe(pipe_cmov_reg);
6463 %}
6464
6465 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
6466 %{
6467 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6468
6469 ins_cost(200); // XXX
6470 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6471 ins_encode %{
6472 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
6473 %}
6474 ins_pipe(pipe_cmov_mem); // XXX
6475 %}
6476
6477 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
6478 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6479 ins_cost(200);
6480 expand %{
6481 cmovL_memU(cop, cr, dst, src);
6482 %}
6483 %}
6484
6485 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
6486 %{
6487 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6488
6489 ins_cost(200); // XXX
6490 format %{ "jn$cop skip\t# signed cmove float\n\t"
6491 "movss $dst, $src\n"
6492 "skip:" %}
6493 ins_encode %{
6494 Label Lskip;
6495 // Invert sense of branch from sense of CMOV
6496 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6497 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6498 __ bind(Lskip);
6499 %}
6500 ins_pipe(pipe_slow);
6501 %}
6502
6503 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
6504 %{
6505 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6506
6507 ins_cost(200); // XXX
6508 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
6509 "movss $dst, $src\n"
6510 "skip:" %}
6511 ins_encode %{
6512 Label Lskip;
6513 // Invert sense of branch from sense of CMOV
6514 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6515 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6516 __ bind(Lskip);
6517 %}
6518 ins_pipe(pipe_slow);
6519 %}
6520
6521 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
6522 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6523 ins_cost(200);
6524 expand %{
6525 cmovF_regU(cop, cr, dst, src);
6526 %}
6527 %}
6528
6529 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
6530 %{
6531 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6532
6533 ins_cost(200); // XXX
6534 format %{ "jn$cop skip\t# signed cmove double\n\t"
6535 "movsd $dst, $src\n"
6536 "skip:" %}
6537 ins_encode %{
6538 Label Lskip;
6539 // Invert sense of branch from sense of CMOV
6540 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6541 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6542 __ bind(Lskip);
6543 %}
6544 ins_pipe(pipe_slow);
6545 %}
6546
6547 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
6548 %{
6549 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6550
6551 ins_cost(200); // XXX
6552 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
6553 "movsd $dst, $src\n"
6554 "skip:" %}
6555 ins_encode %{
6556 Label Lskip;
6557 // Invert sense of branch from sense of CMOV
6558 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6559 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6560 __ bind(Lskip);
6561 %}
6562 ins_pipe(pipe_slow);
6563 %}
6564
6565 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
6566 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6567 ins_cost(200);
6568 expand %{
6569 cmovD_regU(cop, cr, dst, src);
6570 %}
6571 %}
6572
6573 //----------Arithmetic Instructions--------------------------------------------
6574 //----------Addition Instructions----------------------------------------------
6575
6576 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
6577 %{
6578 match(Set dst (AddI dst src));
6579 effect(KILL cr);
6580 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
6581 format %{ "addl $dst, $src\t# int" %}
6582 ins_encode %{
6583 __ addl($dst$$Register, $src$$Register);
6584 %}
6585 ins_pipe(ialu_reg_reg);
6586 %}
6587
6588 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
6589 %{
6590 match(Set dst (AddI dst src));
6591 effect(KILL cr);
6592 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
6593
6594 format %{ "addl $dst, $src\t# int" %}
6595 ins_encode %{
6596 __ addl($dst$$Register, $src$$constant);
6597 %}
6598 ins_pipe( ialu_reg );
6599 %}
6600
6601 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
6602 %{
6603 match(Set dst (AddI dst (LoadI src)));
6604 effect(KILL cr);
6605 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
6606
6607 ins_cost(150); // XXX
6608 format %{ "addl $dst, $src\t# int" %}
6609 ins_encode %{
6610 __ addl($dst$$Register, $src$$Address);
6611 %}
6612 ins_pipe(ialu_reg_mem);
6613 %}
6614
6615 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
6616 %{
6617 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6618 effect(KILL cr);
6619 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
6620
6621 ins_cost(150); // XXX
6622 format %{ "addl $dst, $src\t# int" %}
6623 ins_encode %{
6624 __ addl($dst$$Address, $src$$Register);
6625 %}
6626 ins_pipe(ialu_mem_reg);
6627 %}
6628
6629 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
6630 %{
6631 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6632 effect(KILL cr);
6633 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
6634
6635
6636 ins_cost(125); // XXX
6637 format %{ "addl $dst, $src\t# int" %}
6638 ins_encode %{
6639 __ addl($dst$$Address, $src$$constant);
6640 %}
6641 ins_pipe(ialu_mem_imm);
6642 %}
6643
6644 instruct incI_rReg(rRegI dst, immI_1 src, rFlagsReg cr)
6645 %{
6646 predicate(UseIncDec);
6647 match(Set dst (AddI dst src));
6648 effect(KILL cr);
6649
6650 format %{ "incl $dst\t# int" %}
6651 ins_encode %{
6652 __ incrementl($dst$$Register);
6653 %}
6654 ins_pipe(ialu_reg);
6655 %}
6656
6657 instruct incI_mem(memory dst, immI_1 src, rFlagsReg cr)
6658 %{
6659 predicate(UseIncDec);
6660 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6661 effect(KILL cr);
6662
6663 ins_cost(125); // XXX
6664 format %{ "incl $dst\t# int" %}
6665 ins_encode %{
6666 __ incrementl($dst$$Address);
6667 %}
6668 ins_pipe(ialu_mem_imm);
6669 %}
6670
6671 // XXX why does that use AddI
6672 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
6673 %{
6674 predicate(UseIncDec);
6675 match(Set dst (AddI dst src));
6676 effect(KILL cr);
6677
6678 format %{ "decl $dst\t# int" %}
6679 ins_encode %{
6680 __ decrementl($dst$$Register);
6681 %}
6682 ins_pipe(ialu_reg);
6683 %}
6684
6685 // XXX why does that use AddI
6686 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
6687 %{
6688 predicate(UseIncDec);
6689 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6690 effect(KILL cr);
6691
6692 ins_cost(125); // XXX
6693 format %{ "decl $dst\t# int" %}
6694 ins_encode %{
6695 __ decrementl($dst$$Address);
6696 %}
6697 ins_pipe(ialu_mem_imm);
6698 %}
6699
6700 instruct leaI_rReg_immI2_immI(rRegI dst, rRegI index, immI2 scale, immI disp)
6701 %{
6702 predicate(VM_Version::supports_fast_2op_lea());
6703 match(Set dst (AddI (LShiftI index scale) disp));
6704
6705 format %{ "leal $dst, [$index << $scale + $disp]\t# int" %}
6706 ins_encode %{
6707 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
6708 __ leal($dst$$Register, Address(noreg, $index$$Register, scale, $disp$$constant));
6709 %}
6710 ins_pipe(ialu_reg_reg);
6711 %}
6712
6713 instruct leaI_rReg_rReg_immI(rRegI dst, rRegI base, rRegI index, immI disp)
6714 %{
6715 predicate(VM_Version::supports_fast_3op_lea());
6716 match(Set dst (AddI (AddI base index) disp));
6717
6718 format %{ "leal $dst, [$base + $index + $disp]\t# int" %}
6719 ins_encode %{
6720 __ leal($dst$$Register, Address($base$$Register, $index$$Register, Address::times_1, $disp$$constant));
6721 %}
6722 ins_pipe(ialu_reg_reg);
6723 %}
6724
6725 instruct leaI_rReg_rReg_immI2(rRegI dst, no_rbp_r13_RegI base, rRegI index, immI2 scale)
6726 %{
6727 predicate(VM_Version::supports_fast_2op_lea());
6728 match(Set dst (AddI base (LShiftI index scale)));
6729
6730 format %{ "leal $dst, [$base + $index << $scale]\t# int" %}
6731 ins_encode %{
6732 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
6733 __ leal($dst$$Register, Address($base$$Register, $index$$Register, scale));
6734 %}
6735 ins_pipe(ialu_reg_reg);
6736 %}
6737
6738 instruct leaI_rReg_rReg_immI2_immI(rRegI dst, rRegI base, rRegI index, immI2 scale, immI disp)
6739 %{
6740 predicate(VM_Version::supports_fast_3op_lea());
6741 match(Set dst (AddI (AddI base (LShiftI index scale)) disp));
6742
6743 format %{ "leal $dst, [$base + $index << $scale + $disp]\t# int" %}
6744 ins_encode %{
6745 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
6746 __ leal($dst$$Register, Address($base$$Register, $index$$Register, scale, $disp$$constant));
6747 %}
6748 ins_pipe(ialu_reg_reg);
6749 %}
6750
6751 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
6752 %{
6753 match(Set dst (AddL dst src));
6754 effect(KILL cr);
6755 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
6756
6757 format %{ "addq $dst, $src\t# long" %}
6758 ins_encode %{
6759 __ addq($dst$$Register, $src$$Register);
6760 %}
6761 ins_pipe(ialu_reg_reg);
6762 %}
6763
6764 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
6765 %{
6766 match(Set dst (AddL dst src));
6767 effect(KILL cr);
6768 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
6769
6770 format %{ "addq $dst, $src\t# long" %}
6771 ins_encode %{
6772 __ addq($dst$$Register, $src$$constant);
6773 %}
6774 ins_pipe( ialu_reg );
6775 %}
6776
6777 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
6778 %{
6779 match(Set dst (AddL dst (LoadL src)));
6780 effect(KILL cr);
6781 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
6782
6783 ins_cost(150); // XXX
6784 format %{ "addq $dst, $src\t# long" %}
6785 ins_encode %{
6786 __ addq($dst$$Register, $src$$Address);
6787 %}
6788 ins_pipe(ialu_reg_mem);
6789 %}
6790
6791 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
6792 %{
6793 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
6794 effect(KILL cr);
6795 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
6796
6797 ins_cost(150); // XXX
6798 format %{ "addq $dst, $src\t# long" %}
6799 ins_encode %{
6800 __ addq($dst$$Address, $src$$Register);
6801 %}
6802 ins_pipe(ialu_mem_reg);
6803 %}
6804
6805 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
6806 %{
6807 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
6808 effect(KILL cr);
6809 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
6810
6811 ins_cost(125); // XXX
6812 format %{ "addq $dst, $src\t# long" %}
6813 ins_encode %{
6814 __ addq($dst$$Address, $src$$constant);
6815 %}
6816 ins_pipe(ialu_mem_imm);
6817 %}
6818
6819 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
6820 %{
6821 predicate(UseIncDec);
6822 match(Set dst (AddL dst src));
6823 effect(KILL cr);
6824
6825 format %{ "incq $dst\t# long" %}
6826 ins_encode %{
6827 __ incrementq($dst$$Register);
6828 %}
6829 ins_pipe(ialu_reg);
6830 %}
6831
6832 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
6833 %{
6834 predicate(UseIncDec);
6835 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
6836 effect(KILL cr);
6837
6838 ins_cost(125); // XXX
6839 format %{ "incq $dst\t# long" %}
6840 ins_encode %{
6841 __ incrementq($dst$$Address);
6842 %}
6843 ins_pipe(ialu_mem_imm);
6844 %}
6845
6846 // XXX why does that use AddL
6847 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
6848 %{
6849 predicate(UseIncDec);
6850 match(Set dst (AddL dst src));
6851 effect(KILL cr);
6852
6853 format %{ "decq $dst\t# long" %}
6854 ins_encode %{
6855 __ decrementq($dst$$Register);
6856 %}
6857 ins_pipe(ialu_reg);
6858 %}
6859
6860 // XXX why does that use AddL
6861 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
6862 %{
6863 predicate(UseIncDec);
6864 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
6865 effect(KILL cr);
6866
6867 ins_cost(125); // XXX
6868 format %{ "decq $dst\t# long" %}
6869 ins_encode %{
6870 __ decrementq($dst$$Address);
6871 %}
6872 ins_pipe(ialu_mem_imm);
6873 %}
6874
6875 instruct leaL_rReg_immI2_immL32(rRegL dst, rRegL index, immI2 scale, immL32 disp)
6876 %{
6877 predicate(VM_Version::supports_fast_2op_lea());
6878 match(Set dst (AddL (LShiftL index scale) disp));
6879
6880 format %{ "leaq $dst, [$index << $scale + $disp]\t# long" %}
6881 ins_encode %{
6882 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
6883 __ leaq($dst$$Register, Address(noreg, $index$$Register, scale, $disp$$constant));
6884 %}
6885 ins_pipe(ialu_reg_reg);
6886 %}
6887
6888 instruct leaL_rReg_rReg_immL32(rRegL dst, rRegL base, rRegL index, immL32 disp)
6889 %{
6890 predicate(VM_Version::supports_fast_3op_lea());
6891 match(Set dst (AddL (AddL base index) disp));
6892
6893 format %{ "leaq $dst, [$base + $index + $disp]\t# long" %}
6894 ins_encode %{
6895 __ leaq($dst$$Register, Address($base$$Register, $index$$Register, Address::times_1, $disp$$constant));
6896 %}
6897 ins_pipe(ialu_reg_reg);
6898 %}
6899
6900 instruct leaL_rReg_rReg_immI2(rRegL dst, no_rbp_r13_RegL base, rRegL index, immI2 scale)
6901 %{
6902 predicate(VM_Version::supports_fast_2op_lea());
6903 match(Set dst (AddL base (LShiftL index scale)));
6904
6905 format %{ "leaq $dst, [$base + $index << $scale]\t# long" %}
6906 ins_encode %{
6907 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
6908 __ leaq($dst$$Register, Address($base$$Register, $index$$Register, scale));
6909 %}
6910 ins_pipe(ialu_reg_reg);
6911 %}
6912
6913 instruct leaL_rReg_rReg_immI2_immL32(rRegL dst, rRegL base, rRegL index, immI2 scale, immL32 disp)
6914 %{
6915 predicate(VM_Version::supports_fast_3op_lea());
6916 match(Set dst (AddL (AddL base (LShiftL index scale)) disp));
6917
6918 format %{ "leaq $dst, [$base + $index << $scale + $disp]\t# long" %}
6919 ins_encode %{
6920 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
6921 __ leaq($dst$$Register, Address($base$$Register, $index$$Register, scale, $disp$$constant));
6922 %}
6923 ins_pipe(ialu_reg_reg);
6924 %}
6925
6926 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
6927 %{
6928 match(Set dst (AddP dst src));
6929 effect(KILL cr);
6930 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
6931
6932 format %{ "addq $dst, $src\t# ptr" %}
6933 ins_encode %{
6934 __ addq($dst$$Register, $src$$Register);
6935 %}
6936 ins_pipe(ialu_reg_reg);
6937 %}
6938
6939 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
6940 %{
6941 match(Set dst (AddP dst src));
6942 effect(KILL cr);
6943 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
6944
6945 format %{ "addq $dst, $src\t# ptr" %}
6946 ins_encode %{
6947 __ addq($dst$$Register, $src$$constant);
6948 %}
6949 ins_pipe( ialu_reg );
6950 %}
6951
6952 // XXX addP mem ops ????
6953
6954 instruct checkCastPP(rRegP dst)
6955 %{
6956 match(Set dst (CheckCastPP dst));
6957
6958 size(0);
6959 format %{ "# checkcastPP of $dst" %}
6960 ins_encode(/* empty encoding */);
6961 ins_pipe(empty);
6962 %}
6963
6964 instruct castPP(rRegP dst)
6965 %{
6966 match(Set dst (CastPP dst));
6967
6968 size(0);
6969 format %{ "# castPP of $dst" %}
6970 ins_encode(/* empty encoding */);
6971 ins_pipe(empty);
6972 %}
6973
6974 instruct castII(rRegI dst)
6975 %{
6976 match(Set dst (CastII dst));
6977
6978 size(0);
6979 format %{ "# castII of $dst" %}
6980 ins_encode(/* empty encoding */);
6981 ins_cost(0);
6982 ins_pipe(empty);
6983 %}
6984
6985 instruct castLL(rRegL dst)
6986 %{
6987 match(Set dst (CastLL dst));
6988
6989 size(0);
6990 format %{ "# castLL of $dst" %}
6991 ins_encode(/* empty encoding */);
6992 ins_cost(0);
6993 ins_pipe(empty);
6994 %}
6995
6996 instruct castFF(regF dst)
6997 %{
6998 match(Set dst (CastFF dst));
6999
7000 size(0);
7001 format %{ "# castFF of $dst" %}
7002 ins_encode(/* empty encoding */);
7003 ins_cost(0);
7004 ins_pipe(empty);
7005 %}
7006
7007 instruct castDD(regD dst)
7008 %{
7009 match(Set dst (CastDD dst));
7010
7011 size(0);
7012 format %{ "# castDD of $dst" %}
7013 ins_encode(/* empty encoding */);
7014 ins_cost(0);
7015 ins_pipe(empty);
7016 %}
7017
7018 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7019 instruct compareAndSwapP(rRegI res,
7020 memory mem_ptr,
7021 rax_RegP oldval, rRegP newval,
7022 rFlagsReg cr)
7023 %{
7024 predicate(n->as_LoadStore()->barrier_data() == 0);
7025 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7026 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval)));
7027 effect(KILL cr, KILL oldval);
7028
7029 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7030 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7031 "setcc $res \t# emits sete + movzbl or setzue for APX" %}
7032 ins_encode %{
7033 __ lock();
7034 __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
7035 __ setcc(Assembler::equal, $res$$Register);
7036 %}
7037 ins_pipe( pipe_cmpxchg );
7038 %}
7039
7040 instruct compareAndSwapL(rRegI res,
7041 memory mem_ptr,
7042 rax_RegL oldval, rRegL newval,
7043 rFlagsReg cr)
7044 %{
7045 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7046 match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval)));
7047 effect(KILL cr, KILL oldval);
7048
7049 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7050 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7051 "setcc $res \t# emits sete + movzbl or setzue for APX" %}
7052 ins_encode %{
7053 __ lock();
7054 __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
7055 __ setcc(Assembler::equal, $res$$Register);
7056 %}
7057 ins_pipe( pipe_cmpxchg );
7058 %}
7059
7060 instruct compareAndSwapI(rRegI res,
7061 memory mem_ptr,
7062 rax_RegI oldval, rRegI newval,
7063 rFlagsReg cr)
7064 %{
7065 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7066 match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval)));
7067 effect(KILL cr, KILL oldval);
7068
7069 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7070 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7071 "setcc $res \t# emits sete + movzbl or setzue for APX" %}
7072 ins_encode %{
7073 __ lock();
7074 __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
7075 __ setcc(Assembler::equal, $res$$Register);
7076 %}
7077 ins_pipe( pipe_cmpxchg );
7078 %}
7079
7080 instruct compareAndSwapB(rRegI res,
7081 memory mem_ptr,
7082 rax_RegI oldval, rRegI newval,
7083 rFlagsReg cr)
7084 %{
7085 match(Set res (CompareAndSwapB mem_ptr (Binary oldval newval)));
7086 match(Set res (WeakCompareAndSwapB mem_ptr (Binary oldval newval)));
7087 effect(KILL cr, KILL oldval);
7088
7089 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7090 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7091 "setcc $res \t# emits sete + movzbl or setzue for APX" %}
7092 ins_encode %{
7093 __ lock();
7094 __ cmpxchgb($newval$$Register, $mem_ptr$$Address);
7095 __ setcc(Assembler::equal, $res$$Register);
7096 %}
7097 ins_pipe( pipe_cmpxchg );
7098 %}
7099
7100 instruct compareAndSwapS(rRegI res,
7101 memory mem_ptr,
7102 rax_RegI oldval, rRegI newval,
7103 rFlagsReg cr)
7104 %{
7105 match(Set res (CompareAndSwapS mem_ptr (Binary oldval newval)));
7106 match(Set res (WeakCompareAndSwapS mem_ptr (Binary oldval newval)));
7107 effect(KILL cr, KILL oldval);
7108
7109 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7110 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7111 "setcc $res \t# emits sete + movzbl or setzue for APX" %}
7112 ins_encode %{
7113 __ lock();
7114 __ cmpxchgw($newval$$Register, $mem_ptr$$Address);
7115 __ setcc(Assembler::equal, $res$$Register);
7116 %}
7117 ins_pipe( pipe_cmpxchg );
7118 %}
7119
7120 instruct compareAndSwapN(rRegI res,
7121 memory mem_ptr,
7122 rax_RegN oldval, rRegN newval,
7123 rFlagsReg cr) %{
7124 predicate(n->as_LoadStore()->barrier_data() == 0);
7125 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7126 match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval)));
7127 effect(KILL cr, KILL oldval);
7128
7129 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7130 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7131 "setcc $res \t# emits sete + movzbl or setzue for APX" %}
7132 ins_encode %{
7133 __ lock();
7134 __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
7135 __ setcc(Assembler::equal, $res$$Register);
7136 %}
7137 ins_pipe( pipe_cmpxchg );
7138 %}
7139
7140 instruct compareAndExchangeB(
7141 memory mem_ptr,
7142 rax_RegI oldval, rRegI newval,
7143 rFlagsReg cr)
7144 %{
7145 match(Set oldval (CompareAndExchangeB mem_ptr (Binary oldval newval)));
7146 effect(KILL cr);
7147
7148 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7149 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7150 ins_encode %{
7151 __ lock();
7152 __ cmpxchgb($newval$$Register, $mem_ptr$$Address);
7153 %}
7154 ins_pipe( pipe_cmpxchg );
7155 %}
7156
7157 instruct compareAndExchangeS(
7158 memory mem_ptr,
7159 rax_RegI oldval, rRegI newval,
7160 rFlagsReg cr)
7161 %{
7162 match(Set oldval (CompareAndExchangeS mem_ptr (Binary oldval newval)));
7163 effect(KILL cr);
7164
7165 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7166 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7167 ins_encode %{
7168 __ lock();
7169 __ cmpxchgw($newval$$Register, $mem_ptr$$Address);
7170 %}
7171 ins_pipe( pipe_cmpxchg );
7172 %}
7173
7174 instruct compareAndExchangeI(
7175 memory mem_ptr,
7176 rax_RegI oldval, rRegI newval,
7177 rFlagsReg cr)
7178 %{
7179 match(Set oldval (CompareAndExchangeI mem_ptr (Binary oldval newval)));
7180 effect(KILL cr);
7181
7182 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7183 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7184 ins_encode %{
7185 __ lock();
7186 __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
7187 %}
7188 ins_pipe( pipe_cmpxchg );
7189 %}
7190
7191 instruct compareAndExchangeL(
7192 memory mem_ptr,
7193 rax_RegL oldval, rRegL newval,
7194 rFlagsReg cr)
7195 %{
7196 match(Set oldval (CompareAndExchangeL mem_ptr (Binary oldval newval)));
7197 effect(KILL cr);
7198
7199 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7200 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7201 ins_encode %{
7202 __ lock();
7203 __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
7204 %}
7205 ins_pipe( pipe_cmpxchg );
7206 %}
7207
7208 instruct compareAndExchangeN(
7209 memory mem_ptr,
7210 rax_RegN oldval, rRegN newval,
7211 rFlagsReg cr) %{
7212 predicate(n->as_LoadStore()->barrier_data() == 0);
7213 match(Set oldval (CompareAndExchangeN mem_ptr (Binary oldval newval)));
7214 effect(KILL cr);
7215
7216 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7217 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7218 ins_encode %{
7219 __ lock();
7220 __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
7221 %}
7222 ins_pipe( pipe_cmpxchg );
7223 %}
7224
7225 instruct compareAndExchangeP(
7226 memory mem_ptr,
7227 rax_RegP oldval, rRegP newval,
7228 rFlagsReg cr)
7229 %{
7230 predicate(n->as_LoadStore()->barrier_data() == 0);
7231 match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval)));
7232 effect(KILL cr);
7233
7234 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7235 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7236 ins_encode %{
7237 __ lock();
7238 __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
7239 %}
7240 ins_pipe( pipe_cmpxchg );
7241 %}
7242
7243 instruct xaddB_reg_no_res(memory mem, Universe dummy, rRegI add, rFlagsReg cr) %{
7244 predicate(n->as_LoadStore()->result_not_used());
7245 match(Set dummy (GetAndAddB mem add));
7246 effect(KILL cr);
7247 format %{ "addb_lock $mem, $add" %}
7248 ins_encode %{
7249 __ lock();
7250 __ addb($mem$$Address, $add$$Register);
7251 %}
7252 ins_pipe(pipe_cmpxchg);
7253 %}
7254
7255 instruct xaddB_imm_no_res(memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7256 predicate(n->as_LoadStore()->result_not_used());
7257 match(Set dummy (GetAndAddB mem add));
7258 effect(KILL cr);
7259 format %{ "addb_lock $mem, $add" %}
7260 ins_encode %{
7261 __ lock();
7262 __ addb($mem$$Address, $add$$constant);
7263 %}
7264 ins_pipe(pipe_cmpxchg);
7265 %}
7266
7267 instruct xaddB(memory mem, rRegI newval, rFlagsReg cr) %{
7268 predicate(!n->as_LoadStore()->result_not_used());
7269 match(Set newval (GetAndAddB mem newval));
7270 effect(KILL cr);
7271 format %{ "xaddb_lock $mem, $newval" %}
7272 ins_encode %{
7273 __ lock();
7274 __ xaddb($mem$$Address, $newval$$Register);
7275 %}
7276 ins_pipe(pipe_cmpxchg);
7277 %}
7278
7279 instruct xaddS_reg_no_res(memory mem, Universe dummy, rRegI add, rFlagsReg cr) %{
7280 predicate(n->as_LoadStore()->result_not_used());
7281 match(Set dummy (GetAndAddS mem add));
7282 effect(KILL cr);
7283 format %{ "addw_lock $mem, $add" %}
7284 ins_encode %{
7285 __ lock();
7286 __ addw($mem$$Address, $add$$Register);
7287 %}
7288 ins_pipe(pipe_cmpxchg);
7289 %}
7290
7291 instruct xaddS_imm_no_res(memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7292 predicate(UseStoreImmI16 && n->as_LoadStore()->result_not_used());
7293 match(Set dummy (GetAndAddS mem add));
7294 effect(KILL cr);
7295 format %{ "addw_lock $mem, $add" %}
7296 ins_encode %{
7297 __ lock();
7298 __ addw($mem$$Address, $add$$constant);
7299 %}
7300 ins_pipe(pipe_cmpxchg);
7301 %}
7302
7303 instruct xaddS(memory mem, rRegI newval, rFlagsReg cr) %{
7304 predicate(!n->as_LoadStore()->result_not_used());
7305 match(Set newval (GetAndAddS mem newval));
7306 effect(KILL cr);
7307 format %{ "xaddw_lock $mem, $newval" %}
7308 ins_encode %{
7309 __ lock();
7310 __ xaddw($mem$$Address, $newval$$Register);
7311 %}
7312 ins_pipe(pipe_cmpxchg);
7313 %}
7314
7315 instruct xaddI_reg_no_res(memory mem, Universe dummy, rRegI add, rFlagsReg cr) %{
7316 predicate(n->as_LoadStore()->result_not_used());
7317 match(Set dummy (GetAndAddI mem add));
7318 effect(KILL cr);
7319 format %{ "addl_lock $mem, $add" %}
7320 ins_encode %{
7321 __ lock();
7322 __ addl($mem$$Address, $add$$Register);
7323 %}
7324 ins_pipe(pipe_cmpxchg);
7325 %}
7326
7327 instruct xaddI_imm_no_res(memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7328 predicate(n->as_LoadStore()->result_not_used());
7329 match(Set dummy (GetAndAddI mem add));
7330 effect(KILL cr);
7331 format %{ "addl_lock $mem, $add" %}
7332 ins_encode %{
7333 __ lock();
7334 __ addl($mem$$Address, $add$$constant);
7335 %}
7336 ins_pipe(pipe_cmpxchg);
7337 %}
7338
7339 instruct xaddI(memory mem, rRegI newval, rFlagsReg cr) %{
7340 predicate(!n->as_LoadStore()->result_not_used());
7341 match(Set newval (GetAndAddI mem newval));
7342 effect(KILL cr);
7343 format %{ "xaddl_lock $mem, $newval" %}
7344 ins_encode %{
7345 __ lock();
7346 __ xaddl($mem$$Address, $newval$$Register);
7347 %}
7348 ins_pipe(pipe_cmpxchg);
7349 %}
7350
7351 instruct xaddL_reg_no_res(memory mem, Universe dummy, rRegL add, rFlagsReg cr) %{
7352 predicate(n->as_LoadStore()->result_not_used());
7353 match(Set dummy (GetAndAddL mem add));
7354 effect(KILL cr);
7355 format %{ "addq_lock $mem, $add" %}
7356 ins_encode %{
7357 __ lock();
7358 __ addq($mem$$Address, $add$$Register);
7359 %}
7360 ins_pipe(pipe_cmpxchg);
7361 %}
7362
7363 instruct xaddL_imm_no_res(memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
7364 predicate(n->as_LoadStore()->result_not_used());
7365 match(Set dummy (GetAndAddL mem add));
7366 effect(KILL cr);
7367 format %{ "addq_lock $mem, $add" %}
7368 ins_encode %{
7369 __ lock();
7370 __ addq($mem$$Address, $add$$constant);
7371 %}
7372 ins_pipe(pipe_cmpxchg);
7373 %}
7374
7375 instruct xaddL(memory mem, rRegL newval, rFlagsReg cr) %{
7376 predicate(!n->as_LoadStore()->result_not_used());
7377 match(Set newval (GetAndAddL mem newval));
7378 effect(KILL cr);
7379 format %{ "xaddq_lock $mem, $newval" %}
7380 ins_encode %{
7381 __ lock();
7382 __ xaddq($mem$$Address, $newval$$Register);
7383 %}
7384 ins_pipe(pipe_cmpxchg);
7385 %}
7386
7387 instruct xchgB( memory mem, rRegI newval) %{
7388 match(Set newval (GetAndSetB mem newval));
7389 format %{ "XCHGB $newval,[$mem]" %}
7390 ins_encode %{
7391 __ xchgb($newval$$Register, $mem$$Address);
7392 %}
7393 ins_pipe( pipe_cmpxchg );
7394 %}
7395
7396 instruct xchgS( memory mem, rRegI newval) %{
7397 match(Set newval (GetAndSetS mem newval));
7398 format %{ "XCHGW $newval,[$mem]" %}
7399 ins_encode %{
7400 __ xchgw($newval$$Register, $mem$$Address);
7401 %}
7402 ins_pipe( pipe_cmpxchg );
7403 %}
7404
7405 instruct xchgI( memory mem, rRegI newval) %{
7406 match(Set newval (GetAndSetI mem newval));
7407 format %{ "XCHGL $newval,[$mem]" %}
7408 ins_encode %{
7409 __ xchgl($newval$$Register, $mem$$Address);
7410 %}
7411 ins_pipe( pipe_cmpxchg );
7412 %}
7413
7414 instruct xchgL( memory mem, rRegL newval) %{
7415 match(Set newval (GetAndSetL mem newval));
7416 format %{ "XCHGL $newval,[$mem]" %}
7417 ins_encode %{
7418 __ xchgq($newval$$Register, $mem$$Address);
7419 %}
7420 ins_pipe( pipe_cmpxchg );
7421 %}
7422
7423 instruct xchgP( memory mem, rRegP newval) %{
7424 match(Set newval (GetAndSetP mem newval));
7425 predicate(n->as_LoadStore()->barrier_data() == 0);
7426 format %{ "XCHGQ $newval,[$mem]" %}
7427 ins_encode %{
7428 __ xchgq($newval$$Register, $mem$$Address);
7429 %}
7430 ins_pipe( pipe_cmpxchg );
7431 %}
7432
7433 instruct xchgN( memory mem, rRegN newval) %{
7434 predicate(n->as_LoadStore()->barrier_data() == 0);
7435 match(Set newval (GetAndSetN mem newval));
7436 format %{ "XCHGL $newval,$mem]" %}
7437 ins_encode %{
7438 __ xchgl($newval$$Register, $mem$$Address);
7439 %}
7440 ins_pipe( pipe_cmpxchg );
7441 %}
7442
7443 //----------Abs Instructions-------------------------------------------
7444
7445 // Integer Absolute Instructions
7446 instruct absI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7447 %{
7448 match(Set dst (AbsI src));
7449 effect(TEMP dst, KILL cr);
7450 format %{ "xorl $dst, $dst\t# abs int\n\t"
7451 "subl $dst, $src\n\t"
7452 "cmovll $dst, $src" %}
7453 ins_encode %{
7454 __ xorl($dst$$Register, $dst$$Register);
7455 __ subl($dst$$Register, $src$$Register);
7456 __ cmovl(Assembler::less, $dst$$Register, $src$$Register);
7457 %}
7458
7459 ins_pipe(ialu_reg_reg);
7460 %}
7461
7462 // Long Absolute Instructions
7463 instruct absL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7464 %{
7465 match(Set dst (AbsL src));
7466 effect(TEMP dst, KILL cr);
7467 format %{ "xorl $dst, $dst\t# abs long\n\t"
7468 "subq $dst, $src\n\t"
7469 "cmovlq $dst, $src" %}
7470 ins_encode %{
7471 __ xorl($dst$$Register, $dst$$Register);
7472 __ subq($dst$$Register, $src$$Register);
7473 __ cmovq(Assembler::less, $dst$$Register, $src$$Register);
7474 %}
7475
7476 ins_pipe(ialu_reg_reg);
7477 %}
7478
7479 //----------Subtraction Instructions-------------------------------------------
7480
7481 // Integer Subtraction Instructions
7482 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7483 %{
7484 match(Set dst (SubI dst src));
7485 effect(KILL cr);
7486 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7487
7488 format %{ "subl $dst, $src\t# int" %}
7489 ins_encode %{
7490 __ subl($dst$$Register, $src$$Register);
7491 %}
7492 ins_pipe(ialu_reg_reg);
7493 %}
7494
7495 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7496 %{
7497 match(Set dst (SubI dst (LoadI src)));
7498 effect(KILL cr);
7499 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7500
7501 ins_cost(150);
7502 format %{ "subl $dst, $src\t# int" %}
7503 ins_encode %{
7504 __ subl($dst$$Register, $src$$Address);
7505 %}
7506 ins_pipe(ialu_reg_mem);
7507 %}
7508
7509 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7510 %{
7511 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7512 effect(KILL cr);
7513 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7514
7515 ins_cost(150);
7516 format %{ "subl $dst, $src\t# int" %}
7517 ins_encode %{
7518 __ subl($dst$$Address, $src$$Register);
7519 %}
7520 ins_pipe(ialu_mem_reg);
7521 %}
7522
7523 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7524 %{
7525 match(Set dst (SubL dst src));
7526 effect(KILL cr);
7527 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7528
7529 format %{ "subq $dst, $src\t# long" %}
7530 ins_encode %{
7531 __ subq($dst$$Register, $src$$Register);
7532 %}
7533 ins_pipe(ialu_reg_reg);
7534 %}
7535
7536 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7537 %{
7538 match(Set dst (SubL dst (LoadL src)));
7539 effect(KILL cr);
7540 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7541
7542 ins_cost(150);
7543 format %{ "subq $dst, $src\t# long" %}
7544 ins_encode %{
7545 __ subq($dst$$Register, $src$$Address);
7546 %}
7547 ins_pipe(ialu_reg_mem);
7548 %}
7549
7550 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7551 %{
7552 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7553 effect(KILL cr);
7554 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7555
7556 ins_cost(150);
7557 format %{ "subq $dst, $src\t# long" %}
7558 ins_encode %{
7559 __ subq($dst$$Address, $src$$Register);
7560 %}
7561 ins_pipe(ialu_mem_reg);
7562 %}
7563
7564 // Subtract from a pointer
7565 // XXX hmpf???
7566 instruct subP_rReg(rRegP dst, rRegI src, immI_0 zero, rFlagsReg cr)
7567 %{
7568 match(Set dst (AddP dst (SubI zero src)));
7569 effect(KILL cr);
7570
7571 format %{ "subq $dst, $src\t# ptr - int" %}
7572 ins_encode %{
7573 __ subq($dst$$Register, $src$$Register);
7574 %}
7575 ins_pipe(ialu_reg_reg);
7576 %}
7577
7578 instruct negI_rReg(rRegI dst, immI_0 zero, rFlagsReg cr)
7579 %{
7580 match(Set dst (SubI zero dst));
7581 effect(KILL cr);
7582 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
7583
7584 format %{ "negl $dst\t# int" %}
7585 ins_encode %{
7586 __ negl($dst$$Register);
7587 %}
7588 ins_pipe(ialu_reg);
7589 %}
7590
7591 instruct negI_rReg_2(rRegI dst, rFlagsReg cr)
7592 %{
7593 match(Set dst (NegI dst));
7594 effect(KILL cr);
7595 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
7596
7597 format %{ "negl $dst\t# int" %}
7598 ins_encode %{
7599 __ negl($dst$$Register);
7600 %}
7601 ins_pipe(ialu_reg);
7602 %}
7603
7604 instruct negI_mem(memory dst, immI_0 zero, rFlagsReg cr)
7605 %{
7606 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
7607 effect(KILL cr);
7608 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
7609
7610 format %{ "negl $dst\t# int" %}
7611 ins_encode %{
7612 __ negl($dst$$Address);
7613 %}
7614 ins_pipe(ialu_reg);
7615 %}
7616
7617 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
7618 %{
7619 match(Set dst (SubL zero dst));
7620 effect(KILL cr);
7621 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
7622
7623 format %{ "negq $dst\t# long" %}
7624 ins_encode %{
7625 __ negq($dst$$Register);
7626 %}
7627 ins_pipe(ialu_reg);
7628 %}
7629
7630 instruct negL_rReg_2(rRegL dst, rFlagsReg cr)
7631 %{
7632 match(Set dst (NegL dst));
7633 effect(KILL cr);
7634 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
7635
7636 format %{ "negq $dst\t# int" %}
7637 ins_encode %{
7638 __ negq($dst$$Register);
7639 %}
7640 ins_pipe(ialu_reg);
7641 %}
7642
7643 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
7644 %{
7645 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
7646 effect(KILL cr);
7647 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
7648
7649 format %{ "negq $dst\t# long" %}
7650 ins_encode %{
7651 __ negq($dst$$Address);
7652 %}
7653 ins_pipe(ialu_reg);
7654 %}
7655
7656 //----------Multiplication/Division Instructions-------------------------------
7657 // Integer Multiplication Instructions
7658 // Multiply Register
7659
7660 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7661 %{
7662 match(Set dst (MulI dst src));
7663 effect(KILL cr);
7664
7665 ins_cost(300);
7666 format %{ "imull $dst, $src\t# int" %}
7667 ins_encode %{
7668 __ imull($dst$$Register, $src$$Register);
7669 %}
7670 ins_pipe(ialu_reg_reg_alu0);
7671 %}
7672
7673 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
7674 %{
7675 match(Set dst (MulI src imm));
7676 effect(KILL cr);
7677
7678 ins_cost(300);
7679 format %{ "imull $dst, $src, $imm\t# int" %}
7680 ins_encode %{
7681 __ imull($dst$$Register, $src$$Register, $imm$$constant);
7682 %}
7683 ins_pipe(ialu_reg_reg_alu0);
7684 %}
7685
7686 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
7687 %{
7688 match(Set dst (MulI dst (LoadI src)));
7689 effect(KILL cr);
7690
7691 ins_cost(350);
7692 format %{ "imull $dst, $src\t# int" %}
7693 ins_encode %{
7694 __ imull($dst$$Register, $src$$Address);
7695 %}
7696 ins_pipe(ialu_reg_mem_alu0);
7697 %}
7698
7699 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
7700 %{
7701 match(Set dst (MulI (LoadI src) imm));
7702 effect(KILL cr);
7703
7704 ins_cost(300);
7705 format %{ "imull $dst, $src, $imm\t# int" %}
7706 ins_encode %{
7707 __ imull($dst$$Register, $src$$Address, $imm$$constant);
7708 %}
7709 ins_pipe(ialu_reg_mem_alu0);
7710 %}
7711
7712 instruct mulAddS2I_rReg(rRegI dst, rRegI src1, rRegI src2, rRegI src3, rFlagsReg cr)
7713 %{
7714 match(Set dst (MulAddS2I (Binary dst src1) (Binary src2 src3)));
7715 effect(KILL cr, KILL src2);
7716
7717 expand %{ mulI_rReg(dst, src1, cr);
7718 mulI_rReg(src2, src3, cr);
7719 addI_rReg(dst, src2, cr); %}
7720 %}
7721
7722 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7723 %{
7724 match(Set dst (MulL dst src));
7725 effect(KILL cr);
7726
7727 ins_cost(300);
7728 format %{ "imulq $dst, $src\t# long" %}
7729 ins_encode %{
7730 __ imulq($dst$$Register, $src$$Register);
7731 %}
7732 ins_pipe(ialu_reg_reg_alu0);
7733 %}
7734
7735 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
7736 %{
7737 match(Set dst (MulL src imm));
7738 effect(KILL cr);
7739
7740 ins_cost(300);
7741 format %{ "imulq $dst, $src, $imm\t# long" %}
7742 ins_encode %{
7743 __ imulq($dst$$Register, $src$$Register, $imm$$constant);
7744 %}
7745 ins_pipe(ialu_reg_reg_alu0);
7746 %}
7747
7748 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
7749 %{
7750 match(Set dst (MulL dst (LoadL src)));
7751 effect(KILL cr);
7752
7753 ins_cost(350);
7754 format %{ "imulq $dst, $src\t# long" %}
7755 ins_encode %{
7756 __ imulq($dst$$Register, $src$$Address);
7757 %}
7758 ins_pipe(ialu_reg_mem_alu0);
7759 %}
7760
7761 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
7762 %{
7763 match(Set dst (MulL (LoadL src) imm));
7764 effect(KILL cr);
7765
7766 ins_cost(300);
7767 format %{ "imulq $dst, $src, $imm\t# long" %}
7768 ins_encode %{
7769 __ imulq($dst$$Register, $src$$Address, $imm$$constant);
7770 %}
7771 ins_pipe(ialu_reg_mem_alu0);
7772 %}
7773
7774 instruct mulHiL_rReg(rdx_RegL dst, rRegL src, rax_RegL rax, rFlagsReg cr)
7775 %{
7776 match(Set dst (MulHiL src rax));
7777 effect(USE_KILL rax, KILL cr);
7778
7779 ins_cost(300);
7780 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
7781 ins_encode %{
7782 __ imulq($src$$Register);
7783 %}
7784 ins_pipe(ialu_reg_reg_alu0);
7785 %}
7786
7787 instruct umulHiL_rReg(rdx_RegL dst, rRegL src, rax_RegL rax, rFlagsReg cr)
7788 %{
7789 match(Set dst (UMulHiL src rax));
7790 effect(USE_KILL rax, KILL cr);
7791
7792 ins_cost(300);
7793 format %{ "mulq RDX:RAX, RAX, $src\t# umulhi" %}
7794 ins_encode %{
7795 __ mulq($src$$Register);
7796 %}
7797 ins_pipe(ialu_reg_reg_alu0);
7798 %}
7799
7800 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
7801 rFlagsReg cr)
7802 %{
7803 match(Set rax (DivI rax div));
7804 effect(KILL rdx, KILL cr);
7805
7806 ins_cost(30*100+10*100); // XXX
7807 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
7808 "jne,s normal\n\t"
7809 "xorl rdx, rdx\n\t"
7810 "cmpl $div, -1\n\t"
7811 "je,s done\n"
7812 "normal: cdql\n\t"
7813 "idivl $div\n"
7814 "done:" %}
7815 ins_encode(cdql_enc(div));
7816 ins_pipe(ialu_reg_reg_alu0);
7817 %}
7818
7819 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
7820 rFlagsReg cr)
7821 %{
7822 match(Set rax (DivL rax div));
7823 effect(KILL rdx, KILL cr);
7824
7825 ins_cost(30*100+10*100); // XXX
7826 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
7827 "cmpq rax, rdx\n\t"
7828 "jne,s normal\n\t"
7829 "xorl rdx, rdx\n\t"
7830 "cmpq $div, -1\n\t"
7831 "je,s done\n"
7832 "normal: cdqq\n\t"
7833 "idivq $div\n"
7834 "done:" %}
7835 ins_encode(cdqq_enc(div));
7836 ins_pipe(ialu_reg_reg_alu0);
7837 %}
7838
7839 instruct udivI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, rFlagsReg cr)
7840 %{
7841 match(Set rax (UDivI rax div));
7842 effect(KILL rdx, KILL cr);
7843
7844 ins_cost(300);
7845 format %{ "udivl $rax,$rax,$div\t# UDivI\n" %}
7846 ins_encode %{
7847 __ udivI($rax$$Register, $div$$Register, $rdx$$Register);
7848 %}
7849 ins_pipe(ialu_reg_reg_alu0);
7850 %}
7851
7852 instruct udivL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, rFlagsReg cr)
7853 %{
7854 match(Set rax (UDivL rax div));
7855 effect(KILL rdx, KILL cr);
7856
7857 ins_cost(300);
7858 format %{ "udivq $rax,$rax,$div\t# UDivL\n" %}
7859 ins_encode %{
7860 __ udivL($rax$$Register, $div$$Register, $rdx$$Register);
7861 %}
7862 ins_pipe(ialu_reg_reg_alu0);
7863 %}
7864
7865 // Integer DIVMOD with Register, both quotient and mod results
7866 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
7867 rFlagsReg cr)
7868 %{
7869 match(DivModI rax div);
7870 effect(KILL cr);
7871
7872 ins_cost(30*100+10*100); // XXX
7873 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
7874 "jne,s normal\n\t"
7875 "xorl rdx, rdx\n\t"
7876 "cmpl $div, -1\n\t"
7877 "je,s done\n"
7878 "normal: cdql\n\t"
7879 "idivl $div\n"
7880 "done:" %}
7881 ins_encode(cdql_enc(div));
7882 ins_pipe(pipe_slow);
7883 %}
7884
7885 // Long DIVMOD with Register, both quotient and mod results
7886 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
7887 rFlagsReg cr)
7888 %{
7889 match(DivModL rax div);
7890 effect(KILL cr);
7891
7892 ins_cost(30*100+10*100); // XXX
7893 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
7894 "cmpq rax, rdx\n\t"
7895 "jne,s normal\n\t"
7896 "xorl rdx, rdx\n\t"
7897 "cmpq $div, -1\n\t"
7898 "je,s done\n"
7899 "normal: cdqq\n\t"
7900 "idivq $div\n"
7901 "done:" %}
7902 ins_encode(cdqq_enc(div));
7903 ins_pipe(pipe_slow);
7904 %}
7905
7906 // Unsigned integer DIVMOD with Register, both quotient and mod results
7907 instruct udivModI_rReg_divmod(rax_RegI rax, no_rax_rdx_RegI tmp, rdx_RegI rdx,
7908 no_rax_rdx_RegI div, rFlagsReg cr)
7909 %{
7910 match(UDivModI rax div);
7911 effect(TEMP tmp, KILL cr);
7912
7913 ins_cost(300);
7914 format %{ "udivl $rax,$rax,$div\t# begin UDivModI\n\t"
7915 "umodl $rdx,$rax,$div\t! using $tmp as TEMP # end UDivModI\n"
7916 %}
7917 ins_encode %{
7918 __ udivmodI($rax$$Register, $div$$Register, $rdx$$Register, $tmp$$Register);
7919 %}
7920 ins_pipe(pipe_slow);
7921 %}
7922
7923 // Unsigned long DIVMOD with Register, both quotient and mod results
7924 instruct udivModL_rReg_divmod(rax_RegL rax, no_rax_rdx_RegL tmp, rdx_RegL rdx,
7925 no_rax_rdx_RegL div, rFlagsReg cr)
7926 %{
7927 match(UDivModL rax div);
7928 effect(TEMP tmp, KILL cr);
7929
7930 ins_cost(300);
7931 format %{ "udivq $rax,$rax,$div\t# begin UDivModL\n\t"
7932 "umodq $rdx,$rax,$div\t! using $tmp as TEMP # end UDivModL\n"
7933 %}
7934 ins_encode %{
7935 __ udivmodL($rax$$Register, $div$$Register, $rdx$$Register, $tmp$$Register);
7936 %}
7937 ins_pipe(pipe_slow);
7938 %}
7939
7940 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
7941 rFlagsReg cr)
7942 %{
7943 match(Set rdx (ModI rax div));
7944 effect(KILL rax, KILL cr);
7945
7946 ins_cost(300); // XXX
7947 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
7948 "jne,s normal\n\t"
7949 "xorl rdx, rdx\n\t"
7950 "cmpl $div, -1\n\t"
7951 "je,s done\n"
7952 "normal: cdql\n\t"
7953 "idivl $div\n"
7954 "done:" %}
7955 ins_encode(cdql_enc(div));
7956 ins_pipe(ialu_reg_reg_alu0);
7957 %}
7958
7959 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
7960 rFlagsReg cr)
7961 %{
7962 match(Set rdx (ModL rax div));
7963 effect(KILL rax, KILL cr);
7964
7965 ins_cost(300); // XXX
7966 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
7967 "cmpq rax, rdx\n\t"
7968 "jne,s normal\n\t"
7969 "xorl rdx, rdx\n\t"
7970 "cmpq $div, -1\n\t"
7971 "je,s done\n"
7972 "normal: cdqq\n\t"
7973 "idivq $div\n"
7974 "done:" %}
7975 ins_encode(cdqq_enc(div));
7976 ins_pipe(ialu_reg_reg_alu0);
7977 %}
7978
7979 instruct umodI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div, rFlagsReg cr)
7980 %{
7981 match(Set rdx (UModI rax div));
7982 effect(KILL rax, KILL cr);
7983
7984 ins_cost(300);
7985 format %{ "umodl $rdx,$rax,$div\t# UModI\n" %}
7986 ins_encode %{
7987 __ umodI($rax$$Register, $div$$Register, $rdx$$Register);
7988 %}
7989 ins_pipe(ialu_reg_reg_alu0);
7990 %}
7991
7992 instruct umodL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div, rFlagsReg cr)
7993 %{
7994 match(Set rdx (UModL rax div));
7995 effect(KILL rax, KILL cr);
7996
7997 ins_cost(300);
7998 format %{ "umodq $rdx,$rax,$div\t# UModL\n" %}
7999 ins_encode %{
8000 __ umodL($rax$$Register, $div$$Register, $rdx$$Register);
8001 %}
8002 ins_pipe(ialu_reg_reg_alu0);
8003 %}
8004
8005 // Integer Shift Instructions
8006 // Shift Left by one, two, three
8007 instruct salI_rReg_immI2(rRegI dst, immI2 shift, rFlagsReg cr)
8008 %{
8009 match(Set dst (LShiftI dst shift));
8010 effect(KILL cr);
8011
8012 format %{ "sall $dst, $shift" %}
8013 ins_encode %{
8014 __ sall($dst$$Register, $shift$$constant);
8015 %}
8016 ins_pipe(ialu_reg);
8017 %}
8018
8019 // Shift Left by 8-bit immediate
8020 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8021 %{
8022 match(Set dst (LShiftI dst shift));
8023 effect(KILL cr);
8024
8025 format %{ "sall $dst, $shift" %}
8026 ins_encode %{
8027 __ sall($dst$$Register, $shift$$constant);
8028 %}
8029 ins_pipe(ialu_reg);
8030 %}
8031
8032 // Shift Left by 8-bit immediate
8033 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8034 %{
8035 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8036 effect(KILL cr);
8037
8038 format %{ "sall $dst, $shift" %}
8039 ins_encode %{
8040 __ sall($dst$$Address, $shift$$constant);
8041 %}
8042 ins_pipe(ialu_mem_imm);
8043 %}
8044
8045 // Shift Left by variable
8046 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8047 %{
8048 predicate(!VM_Version::supports_bmi2());
8049 match(Set dst (LShiftI dst shift));
8050 effect(KILL cr);
8051
8052 format %{ "sall $dst, $shift" %}
8053 ins_encode %{
8054 __ sall($dst$$Register);
8055 %}
8056 ins_pipe(ialu_reg_reg);
8057 %}
8058
8059 // Shift Left by variable
8060 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8061 %{
8062 predicate(!VM_Version::supports_bmi2());
8063 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8064 effect(KILL cr);
8065
8066 format %{ "sall $dst, $shift" %}
8067 ins_encode %{
8068 __ sall($dst$$Address);
8069 %}
8070 ins_pipe(ialu_mem_reg);
8071 %}
8072
8073 instruct salI_rReg_rReg(rRegI dst, rRegI src, rRegI shift)
8074 %{
8075 predicate(VM_Version::supports_bmi2());
8076 match(Set dst (LShiftI src shift));
8077
8078 format %{ "shlxl $dst, $src, $shift" %}
8079 ins_encode %{
8080 __ shlxl($dst$$Register, $src$$Register, $shift$$Register);
8081 %}
8082 ins_pipe(ialu_reg_reg);
8083 %}
8084
8085 instruct salI_mem_rReg(rRegI dst, memory src, rRegI shift)
8086 %{
8087 predicate(VM_Version::supports_bmi2());
8088 match(Set dst (LShiftI (LoadI src) shift));
8089 ins_cost(175);
8090 format %{ "shlxl $dst, $src, $shift" %}
8091 ins_encode %{
8092 __ shlxl($dst$$Register, $src$$Address, $shift$$Register);
8093 %}
8094 ins_pipe(ialu_reg_mem);
8095 %}
8096
8097 // Arithmetic Shift Right by 8-bit immediate
8098 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8099 %{
8100 match(Set dst (RShiftI dst shift));
8101 effect(KILL cr);
8102
8103 format %{ "sarl $dst, $shift" %}
8104 ins_encode %{
8105 __ sarl($dst$$Register, $shift$$constant);
8106 %}
8107 ins_pipe(ialu_mem_imm);
8108 %}
8109
8110 // Arithmetic Shift Right by 8-bit immediate
8111 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8112 %{
8113 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8114 effect(KILL cr);
8115
8116 format %{ "sarl $dst, $shift" %}
8117 ins_encode %{
8118 __ sarl($dst$$Address, $shift$$constant);
8119 %}
8120 ins_pipe(ialu_mem_imm);
8121 %}
8122
8123 // Arithmetic Shift Right by variable
8124 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8125 %{
8126 predicate(!VM_Version::supports_bmi2());
8127 match(Set dst (RShiftI dst shift));
8128 effect(KILL cr);
8129
8130 format %{ "sarl $dst, $shift" %}
8131 ins_encode %{
8132 __ sarl($dst$$Register);
8133 %}
8134 ins_pipe(ialu_reg_reg);
8135 %}
8136
8137 // Arithmetic Shift Right by variable
8138 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8139 %{
8140 predicate(!VM_Version::supports_bmi2());
8141 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8142 effect(KILL cr);
8143
8144 format %{ "sarl $dst, $shift" %}
8145 ins_encode %{
8146 __ sarl($dst$$Address);
8147 %}
8148 ins_pipe(ialu_mem_reg);
8149 %}
8150
8151 instruct sarI_rReg_rReg(rRegI dst, rRegI src, rRegI shift)
8152 %{
8153 predicate(VM_Version::supports_bmi2());
8154 match(Set dst (RShiftI src shift));
8155
8156 format %{ "sarxl $dst, $src, $shift" %}
8157 ins_encode %{
8158 __ sarxl($dst$$Register, $src$$Register, $shift$$Register);
8159 %}
8160 ins_pipe(ialu_reg_reg);
8161 %}
8162
8163 instruct sarI_mem_rReg(rRegI dst, memory src, rRegI shift)
8164 %{
8165 predicate(VM_Version::supports_bmi2());
8166 match(Set dst (RShiftI (LoadI src) shift));
8167 ins_cost(175);
8168 format %{ "sarxl $dst, $src, $shift" %}
8169 ins_encode %{
8170 __ sarxl($dst$$Register, $src$$Address, $shift$$Register);
8171 %}
8172 ins_pipe(ialu_reg_mem);
8173 %}
8174
8175 // Logical Shift Right by 8-bit immediate
8176 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8177 %{
8178 match(Set dst (URShiftI dst shift));
8179 effect(KILL cr);
8180
8181 format %{ "shrl $dst, $shift" %}
8182 ins_encode %{
8183 __ shrl($dst$$Register, $shift$$constant);
8184 %}
8185 ins_pipe(ialu_reg);
8186 %}
8187
8188 // Logical Shift Right by 8-bit immediate
8189 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8190 %{
8191 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8192 effect(KILL cr);
8193
8194 format %{ "shrl $dst, $shift" %}
8195 ins_encode %{
8196 __ shrl($dst$$Address, $shift$$constant);
8197 %}
8198 ins_pipe(ialu_mem_imm);
8199 %}
8200
8201 // Logical Shift Right by variable
8202 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8203 %{
8204 predicate(!VM_Version::supports_bmi2());
8205 match(Set dst (URShiftI dst shift));
8206 effect(KILL cr);
8207
8208 format %{ "shrl $dst, $shift" %}
8209 ins_encode %{
8210 __ shrl($dst$$Register);
8211 %}
8212 ins_pipe(ialu_reg_reg);
8213 %}
8214
8215 // Logical Shift Right by variable
8216 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8217 %{
8218 predicate(!VM_Version::supports_bmi2());
8219 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8220 effect(KILL cr);
8221
8222 format %{ "shrl $dst, $shift" %}
8223 ins_encode %{
8224 __ shrl($dst$$Address);
8225 %}
8226 ins_pipe(ialu_mem_reg);
8227 %}
8228
8229 instruct shrI_rReg_rReg(rRegI dst, rRegI src, rRegI shift)
8230 %{
8231 predicate(VM_Version::supports_bmi2());
8232 match(Set dst (URShiftI src shift));
8233
8234 format %{ "shrxl $dst, $src, $shift" %}
8235 ins_encode %{
8236 __ shrxl($dst$$Register, $src$$Register, $shift$$Register);
8237 %}
8238 ins_pipe(ialu_reg_reg);
8239 %}
8240
8241 instruct shrI_mem_rReg(rRegI dst, memory src, rRegI shift)
8242 %{
8243 predicate(VM_Version::supports_bmi2());
8244 match(Set dst (URShiftI (LoadI src) shift));
8245 ins_cost(175);
8246 format %{ "shrxl $dst, $src, $shift" %}
8247 ins_encode %{
8248 __ shrxl($dst$$Register, $src$$Address, $shift$$Register);
8249 %}
8250 ins_pipe(ialu_reg_mem);
8251 %}
8252
8253 // Long Shift Instructions
8254 // Shift Left by one, two, three
8255 instruct salL_rReg_immI2(rRegL dst, immI2 shift, rFlagsReg cr)
8256 %{
8257 match(Set dst (LShiftL dst shift));
8258 effect(KILL cr);
8259
8260 format %{ "salq $dst, $shift" %}
8261 ins_encode %{
8262 __ salq($dst$$Register, $shift$$constant);
8263 %}
8264 ins_pipe(ialu_reg);
8265 %}
8266
8267 // Shift Left by 8-bit immediate
8268 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8269 %{
8270 match(Set dst (LShiftL dst shift));
8271 effect(KILL cr);
8272
8273 format %{ "salq $dst, $shift" %}
8274 ins_encode %{
8275 __ salq($dst$$Register, $shift$$constant);
8276 %}
8277 ins_pipe(ialu_reg);
8278 %}
8279
8280 // Shift Left by 8-bit immediate
8281 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8282 %{
8283 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8284 effect(KILL cr);
8285
8286 format %{ "salq $dst, $shift" %}
8287 ins_encode %{
8288 __ salq($dst$$Address, $shift$$constant);
8289 %}
8290 ins_pipe(ialu_mem_imm);
8291 %}
8292
8293 // Shift Left by variable
8294 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8295 %{
8296 predicate(!VM_Version::supports_bmi2());
8297 match(Set dst (LShiftL dst shift));
8298 effect(KILL cr);
8299
8300 format %{ "salq $dst, $shift" %}
8301 ins_encode %{
8302 __ salq($dst$$Register);
8303 %}
8304 ins_pipe(ialu_reg_reg);
8305 %}
8306
8307 // Shift Left by variable
8308 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8309 %{
8310 predicate(!VM_Version::supports_bmi2());
8311 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8312 effect(KILL cr);
8313
8314 format %{ "salq $dst, $shift" %}
8315 ins_encode %{
8316 __ salq($dst$$Address);
8317 %}
8318 ins_pipe(ialu_mem_reg);
8319 %}
8320
8321 instruct salL_rReg_rReg(rRegL dst, rRegL src, rRegI shift)
8322 %{
8323 predicate(VM_Version::supports_bmi2());
8324 match(Set dst (LShiftL src shift));
8325
8326 format %{ "shlxq $dst, $src, $shift" %}
8327 ins_encode %{
8328 __ shlxq($dst$$Register, $src$$Register, $shift$$Register);
8329 %}
8330 ins_pipe(ialu_reg_reg);
8331 %}
8332
8333 instruct salL_mem_rReg(rRegL dst, memory src, rRegI shift)
8334 %{
8335 predicate(VM_Version::supports_bmi2());
8336 match(Set dst (LShiftL (LoadL src) shift));
8337 ins_cost(175);
8338 format %{ "shlxq $dst, $src, $shift" %}
8339 ins_encode %{
8340 __ shlxq($dst$$Register, $src$$Address, $shift$$Register);
8341 %}
8342 ins_pipe(ialu_reg_mem);
8343 %}
8344
8345 // Arithmetic Shift Right by 8-bit immediate
8346 instruct sarL_rReg_imm(rRegL dst, immI shift, rFlagsReg cr)
8347 %{
8348 match(Set dst (RShiftL dst shift));
8349 effect(KILL cr);
8350
8351 format %{ "sarq $dst, $shift" %}
8352 ins_encode %{
8353 __ sarq($dst$$Register, (unsigned char)($shift$$constant & 0x3F));
8354 %}
8355 ins_pipe(ialu_mem_imm);
8356 %}
8357
8358 // Arithmetic Shift Right by 8-bit immediate
8359 instruct sarL_mem_imm(memory dst, immI shift, rFlagsReg cr)
8360 %{
8361 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8362 effect(KILL cr);
8363
8364 format %{ "sarq $dst, $shift" %}
8365 ins_encode %{
8366 __ sarq($dst$$Address, (unsigned char)($shift$$constant & 0x3F));
8367 %}
8368 ins_pipe(ialu_mem_imm);
8369 %}
8370
8371 // Arithmetic Shift Right by variable
8372 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8373 %{
8374 predicate(!VM_Version::supports_bmi2());
8375 match(Set dst (RShiftL dst shift));
8376 effect(KILL cr);
8377
8378 format %{ "sarq $dst, $shift" %}
8379 ins_encode %{
8380 __ sarq($dst$$Register);
8381 %}
8382 ins_pipe(ialu_reg_reg);
8383 %}
8384
8385 // Arithmetic Shift Right by variable
8386 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8387 %{
8388 predicate(!VM_Version::supports_bmi2());
8389 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8390 effect(KILL cr);
8391
8392 format %{ "sarq $dst, $shift" %}
8393 ins_encode %{
8394 __ sarq($dst$$Address);
8395 %}
8396 ins_pipe(ialu_mem_reg);
8397 %}
8398
8399 instruct sarL_rReg_rReg(rRegL dst, rRegL src, rRegI shift)
8400 %{
8401 predicate(VM_Version::supports_bmi2());
8402 match(Set dst (RShiftL src shift));
8403
8404 format %{ "sarxq $dst, $src, $shift" %}
8405 ins_encode %{
8406 __ sarxq($dst$$Register, $src$$Register, $shift$$Register);
8407 %}
8408 ins_pipe(ialu_reg_reg);
8409 %}
8410
8411 instruct sarL_mem_rReg(rRegL dst, memory src, rRegI shift)
8412 %{
8413 predicate(VM_Version::supports_bmi2());
8414 match(Set dst (RShiftL (LoadL src) shift));
8415 ins_cost(175);
8416 format %{ "sarxq $dst, $src, $shift" %}
8417 ins_encode %{
8418 __ sarxq($dst$$Register, $src$$Address, $shift$$Register);
8419 %}
8420 ins_pipe(ialu_reg_mem);
8421 %}
8422
8423 // Logical Shift Right by 8-bit immediate
8424 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8425 %{
8426 match(Set dst (URShiftL dst shift));
8427 effect(KILL cr);
8428
8429 format %{ "shrq $dst, $shift" %}
8430 ins_encode %{
8431 __ shrq($dst$$Register, $shift$$constant);
8432 %}
8433 ins_pipe(ialu_reg);
8434 %}
8435
8436 // Logical Shift Right by 8-bit immediate
8437 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8438 %{
8439 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8440 effect(KILL cr);
8441
8442 format %{ "shrq $dst, $shift" %}
8443 ins_encode %{
8444 __ shrq($dst$$Address, $shift$$constant);
8445 %}
8446 ins_pipe(ialu_mem_imm);
8447 %}
8448
8449 // Logical Shift Right by variable
8450 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8451 %{
8452 predicate(!VM_Version::supports_bmi2());
8453 match(Set dst (URShiftL dst shift));
8454 effect(KILL cr);
8455
8456 format %{ "shrq $dst, $shift" %}
8457 ins_encode %{
8458 __ shrq($dst$$Register);
8459 %}
8460 ins_pipe(ialu_reg_reg);
8461 %}
8462
8463 // Logical Shift Right by variable
8464 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8465 %{
8466 predicate(!VM_Version::supports_bmi2());
8467 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8468 effect(KILL cr);
8469
8470 format %{ "shrq $dst, $shift" %}
8471 ins_encode %{
8472 __ shrq($dst$$Address);
8473 %}
8474 ins_pipe(ialu_mem_reg);
8475 %}
8476
8477 instruct shrL_rReg_rReg(rRegL dst, rRegL src, rRegI shift)
8478 %{
8479 predicate(VM_Version::supports_bmi2());
8480 match(Set dst (URShiftL src shift));
8481
8482 format %{ "shrxq $dst, $src, $shift" %}
8483 ins_encode %{
8484 __ shrxq($dst$$Register, $src$$Register, $shift$$Register);
8485 %}
8486 ins_pipe(ialu_reg_reg);
8487 %}
8488
8489 instruct shrL_mem_rReg(rRegL dst, memory src, rRegI shift)
8490 %{
8491 predicate(VM_Version::supports_bmi2());
8492 match(Set dst (URShiftL (LoadL src) shift));
8493 ins_cost(175);
8494 format %{ "shrxq $dst, $src, $shift" %}
8495 ins_encode %{
8496 __ shrxq($dst$$Register, $src$$Address, $shift$$Register);
8497 %}
8498 ins_pipe(ialu_reg_mem);
8499 %}
8500
8501 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8502 // This idiom is used by the compiler for the i2b bytecode.
8503 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
8504 %{
8505 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8506
8507 format %{ "movsbl $dst, $src\t# i2b" %}
8508 ins_encode %{
8509 __ movsbl($dst$$Register, $src$$Register);
8510 %}
8511 ins_pipe(ialu_reg_reg);
8512 %}
8513
8514 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8515 // This idiom is used by the compiler the i2s bytecode.
8516 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
8517 %{
8518 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8519
8520 format %{ "movswl $dst, $src\t# i2s" %}
8521 ins_encode %{
8522 __ movswl($dst$$Register, $src$$Register);
8523 %}
8524 ins_pipe(ialu_reg_reg);
8525 %}
8526
8527 // ROL/ROR instructions
8528
8529 // Rotate left by constant.
8530 instruct rolI_immI8_legacy(rRegI dst, immI8 shift, rFlagsReg cr)
8531 %{
8532 predicate(!VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
8533 match(Set dst (RotateLeft dst shift));
8534 effect(KILL cr);
8535 format %{ "roll $dst, $shift" %}
8536 ins_encode %{
8537 __ roll($dst$$Register, $shift$$constant);
8538 %}
8539 ins_pipe(ialu_reg);
8540 %}
8541
8542 instruct rolI_immI8(rRegI dst, rRegI src, immI8 shift)
8543 %{
8544 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
8545 match(Set dst (RotateLeft src shift));
8546 format %{ "rolxl $dst, $src, $shift" %}
8547 ins_encode %{
8548 int shift = 32 - ($shift$$constant & 31);
8549 __ rorxl($dst$$Register, $src$$Register, shift);
8550 %}
8551 ins_pipe(ialu_reg_reg);
8552 %}
8553
8554 instruct rolI_mem_immI8(rRegI dst, memory src, immI8 shift)
8555 %{
8556 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
8557 match(Set dst (RotateLeft (LoadI src) shift));
8558 ins_cost(175);
8559 format %{ "rolxl $dst, $src, $shift" %}
8560 ins_encode %{
8561 int shift = 32 - ($shift$$constant & 31);
8562 __ rorxl($dst$$Register, $src$$Address, shift);
8563 %}
8564 ins_pipe(ialu_reg_mem);
8565 %}
8566
8567 // Rotate Left by variable
8568 instruct rolI_rReg_Var(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8569 %{
8570 predicate(n->bottom_type()->basic_type() == T_INT);
8571 match(Set dst (RotateLeft dst shift));
8572 effect(KILL cr);
8573 format %{ "roll $dst, $shift" %}
8574 ins_encode %{
8575 __ roll($dst$$Register);
8576 %}
8577 ins_pipe(ialu_reg_reg);
8578 %}
8579
8580 // Rotate Right by constant.
8581 instruct rorI_immI8_legacy(rRegI dst, immI8 shift, rFlagsReg cr)
8582 %{
8583 predicate(!VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
8584 match(Set dst (RotateRight dst shift));
8585 effect(KILL cr);
8586 format %{ "rorl $dst, $shift" %}
8587 ins_encode %{
8588 __ rorl($dst$$Register, $shift$$constant);
8589 %}
8590 ins_pipe(ialu_reg);
8591 %}
8592
8593 // Rotate Right by constant.
8594 instruct rorI_immI8(rRegI dst, rRegI src, immI8 shift)
8595 %{
8596 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
8597 match(Set dst (RotateRight src shift));
8598 format %{ "rorxl $dst, $src, $shift" %}
8599 ins_encode %{
8600 __ rorxl($dst$$Register, $src$$Register, $shift$$constant);
8601 %}
8602 ins_pipe(ialu_reg_reg);
8603 %}
8604
8605 instruct rorI_mem_immI8(rRegI dst, memory src, immI8 shift)
8606 %{
8607 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
8608 match(Set dst (RotateRight (LoadI src) shift));
8609 ins_cost(175);
8610 format %{ "rorxl $dst, $src, $shift" %}
8611 ins_encode %{
8612 __ rorxl($dst$$Register, $src$$Address, $shift$$constant);
8613 %}
8614 ins_pipe(ialu_reg_mem);
8615 %}
8616
8617 // Rotate Right by variable
8618 instruct rorI_rReg_Var(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8619 %{
8620 predicate(n->bottom_type()->basic_type() == T_INT);
8621 match(Set dst (RotateRight dst shift));
8622 effect(KILL cr);
8623 format %{ "rorl $dst, $shift" %}
8624 ins_encode %{
8625 __ rorl($dst$$Register);
8626 %}
8627 ins_pipe(ialu_reg_reg);
8628 %}
8629
8630 // Rotate Left by constant.
8631 instruct rolL_immI8_legacy(rRegL dst, immI8 shift, rFlagsReg cr)
8632 %{
8633 predicate(!VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
8634 match(Set dst (RotateLeft dst shift));
8635 effect(KILL cr);
8636 format %{ "rolq $dst, $shift" %}
8637 ins_encode %{
8638 __ rolq($dst$$Register, $shift$$constant);
8639 %}
8640 ins_pipe(ialu_reg);
8641 %}
8642
8643 instruct rolL_immI8(rRegL dst, rRegL src, immI8 shift)
8644 %{
8645 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
8646 match(Set dst (RotateLeft src shift));
8647 format %{ "rolxq $dst, $src, $shift" %}
8648 ins_encode %{
8649 int shift = 64 - ($shift$$constant & 63);
8650 __ rorxq($dst$$Register, $src$$Register, shift);
8651 %}
8652 ins_pipe(ialu_reg_reg);
8653 %}
8654
8655 instruct rolL_mem_immI8(rRegL dst, memory src, immI8 shift)
8656 %{
8657 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
8658 match(Set dst (RotateLeft (LoadL src) shift));
8659 ins_cost(175);
8660 format %{ "rolxq $dst, $src, $shift" %}
8661 ins_encode %{
8662 int shift = 64 - ($shift$$constant & 63);
8663 __ rorxq($dst$$Register, $src$$Address, shift);
8664 %}
8665 ins_pipe(ialu_reg_mem);
8666 %}
8667
8668 // Rotate Left by variable
8669 instruct rolL_rReg_Var(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8670 %{
8671 predicate(n->bottom_type()->basic_type() == T_LONG);
8672 match(Set dst (RotateLeft dst shift));
8673 effect(KILL cr);
8674 format %{ "rolq $dst, $shift" %}
8675 ins_encode %{
8676 __ rolq($dst$$Register);
8677 %}
8678 ins_pipe(ialu_reg_reg);
8679 %}
8680
8681 // Rotate Right by constant.
8682 instruct rorL_immI8_legacy(rRegL dst, immI8 shift, rFlagsReg cr)
8683 %{
8684 predicate(!VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
8685 match(Set dst (RotateRight dst shift));
8686 effect(KILL cr);
8687 format %{ "rorq $dst, $shift" %}
8688 ins_encode %{
8689 __ rorq($dst$$Register, $shift$$constant);
8690 %}
8691 ins_pipe(ialu_reg);
8692 %}
8693
8694 // Rotate Right by constant
8695 instruct rorL_immI8(rRegL dst, rRegL src, immI8 shift)
8696 %{
8697 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
8698 match(Set dst (RotateRight src shift));
8699 format %{ "rorxq $dst, $src, $shift" %}
8700 ins_encode %{
8701 __ rorxq($dst$$Register, $src$$Register, $shift$$constant);
8702 %}
8703 ins_pipe(ialu_reg_reg);
8704 %}
8705
8706 instruct rorL_mem_immI8(rRegL dst, memory src, immI8 shift)
8707 %{
8708 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
8709 match(Set dst (RotateRight (LoadL src) shift));
8710 ins_cost(175);
8711 format %{ "rorxq $dst, $src, $shift" %}
8712 ins_encode %{
8713 __ rorxq($dst$$Register, $src$$Address, $shift$$constant);
8714 %}
8715 ins_pipe(ialu_reg_mem);
8716 %}
8717
8718 // Rotate Right by variable
8719 instruct rorL_rReg_Var(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8720 %{
8721 predicate(n->bottom_type()->basic_type() == T_LONG);
8722 match(Set dst (RotateRight dst shift));
8723 effect(KILL cr);
8724 format %{ "rorq $dst, $shift" %}
8725 ins_encode %{
8726 __ rorq($dst$$Register);
8727 %}
8728 ins_pipe(ialu_reg_reg);
8729 %}
8730
8731 //----------------------------- CompressBits/ExpandBits ------------------------
8732
8733 instruct compressBitsL_reg(rRegL dst, rRegL src, rRegL mask) %{
8734 predicate(n->bottom_type()->isa_long());
8735 match(Set dst (CompressBits src mask));
8736 format %{ "pextq $dst, $src, $mask\t! parallel bit extract" %}
8737 ins_encode %{
8738 __ pextq($dst$$Register, $src$$Register, $mask$$Register);
8739 %}
8740 ins_pipe( pipe_slow );
8741 %}
8742
8743 instruct expandBitsL_reg(rRegL dst, rRegL src, rRegL mask) %{
8744 predicate(n->bottom_type()->isa_long());
8745 match(Set dst (ExpandBits src mask));
8746 format %{ "pdepq $dst, $src, $mask\t! parallel bit deposit" %}
8747 ins_encode %{
8748 __ pdepq($dst$$Register, $src$$Register, $mask$$Register);
8749 %}
8750 ins_pipe( pipe_slow );
8751 %}
8752
8753 instruct compressBitsL_mem(rRegL dst, rRegL src, memory mask) %{
8754 predicate(n->bottom_type()->isa_long());
8755 match(Set dst (CompressBits src (LoadL mask)));
8756 format %{ "pextq $dst, $src, $mask\t! parallel bit extract" %}
8757 ins_encode %{
8758 __ pextq($dst$$Register, $src$$Register, $mask$$Address);
8759 %}
8760 ins_pipe( pipe_slow );
8761 %}
8762
8763 instruct expandBitsL_mem(rRegL dst, rRegL src, memory mask) %{
8764 predicate(n->bottom_type()->isa_long());
8765 match(Set dst (ExpandBits src (LoadL mask)));
8766 format %{ "pdepq $dst, $src, $mask\t! parallel bit deposit" %}
8767 ins_encode %{
8768 __ pdepq($dst$$Register, $src$$Register, $mask$$Address);
8769 %}
8770 ins_pipe( pipe_slow );
8771 %}
8772
8773
8774 // Logical Instructions
8775
8776 // Integer Logical Instructions
8777
8778 // And Instructions
8779 // And Register with Register
8780 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8781 %{
8782 match(Set dst (AndI dst src));
8783 effect(KILL cr);
8784 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
8785
8786 format %{ "andl $dst, $src\t# int" %}
8787 ins_encode %{
8788 __ andl($dst$$Register, $src$$Register);
8789 %}
8790 ins_pipe(ialu_reg_reg);
8791 %}
8792
8793 // And Register with Immediate 255
8794 instruct andI_rReg_imm255(rRegI dst, rRegI src, immI_255 mask)
8795 %{
8796 match(Set dst (AndI src mask));
8797
8798 format %{ "movzbl $dst, $src\t# int & 0xFF" %}
8799 ins_encode %{
8800 __ movzbl($dst$$Register, $src$$Register);
8801 %}
8802 ins_pipe(ialu_reg);
8803 %}
8804
8805 // And Register with Immediate 255 and promote to long
8806 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
8807 %{
8808 match(Set dst (ConvI2L (AndI src mask)));
8809
8810 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
8811 ins_encode %{
8812 __ movzbl($dst$$Register, $src$$Register);
8813 %}
8814 ins_pipe(ialu_reg);
8815 %}
8816
8817 // And Register with Immediate 65535
8818 instruct andI_rReg_imm65535(rRegI dst, rRegI src, immI_65535 mask)
8819 %{
8820 match(Set dst (AndI src mask));
8821
8822 format %{ "movzwl $dst, $src\t# int & 0xFFFF" %}
8823 ins_encode %{
8824 __ movzwl($dst$$Register, $src$$Register);
8825 %}
8826 ins_pipe(ialu_reg);
8827 %}
8828
8829 // And Register with Immediate 65535 and promote to long
8830 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
8831 %{
8832 match(Set dst (ConvI2L (AndI src mask)));
8833
8834 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
8835 ins_encode %{
8836 __ movzwl($dst$$Register, $src$$Register);
8837 %}
8838 ins_pipe(ialu_reg);
8839 %}
8840
8841 // Can skip int2long conversions after AND with small bitmask
8842 instruct convI2LAndI_reg_immIbitmask(rRegL dst, rRegI src, immI_Pow2M1 mask, rRegI tmp, rFlagsReg cr)
8843 %{
8844 predicate(VM_Version::supports_bmi2());
8845 ins_cost(125);
8846 effect(TEMP tmp, KILL cr);
8847 match(Set dst (ConvI2L (AndI src mask)));
8848 format %{ "bzhiq $dst, $src, $mask \t# using $tmp as TEMP, int & immI_Pow2M1 -> long" %}
8849 ins_encode %{
8850 __ movl($tmp$$Register, exact_log2($mask$$constant + 1));
8851 __ bzhiq($dst$$Register, $src$$Register, $tmp$$Register);
8852 %}
8853 ins_pipe(ialu_reg_reg);
8854 %}
8855
8856 // And Register with Immediate
8857 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8858 %{
8859 match(Set dst (AndI dst src));
8860 effect(KILL cr);
8861 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
8862
8863 format %{ "andl $dst, $src\t# int" %}
8864 ins_encode %{
8865 __ andl($dst$$Register, $src$$constant);
8866 %}
8867 ins_pipe(ialu_reg);
8868 %}
8869
8870 // And Register with Memory
8871 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8872 %{
8873 match(Set dst (AndI dst (LoadI src)));
8874 effect(KILL cr);
8875 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
8876
8877 ins_cost(150);
8878 format %{ "andl $dst, $src\t# int" %}
8879 ins_encode %{
8880 __ andl($dst$$Register, $src$$Address);
8881 %}
8882 ins_pipe(ialu_reg_mem);
8883 %}
8884
8885 // And Memory with Register
8886 instruct andB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8887 %{
8888 match(Set dst (StoreB dst (AndI (LoadB dst) src)));
8889 effect(KILL cr);
8890 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
8891
8892 ins_cost(150);
8893 format %{ "andb $dst, $src\t# byte" %}
8894 ins_encode %{
8895 __ andb($dst$$Address, $src$$Register);
8896 %}
8897 ins_pipe(ialu_mem_reg);
8898 %}
8899
8900 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8901 %{
8902 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8903 effect(KILL cr);
8904 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
8905
8906 ins_cost(150);
8907 format %{ "andl $dst, $src\t# int" %}
8908 ins_encode %{
8909 __ andl($dst$$Address, $src$$Register);
8910 %}
8911 ins_pipe(ialu_mem_reg);
8912 %}
8913
8914 // And Memory with Immediate
8915 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
8916 %{
8917 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8918 effect(KILL cr);
8919 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
8920
8921 ins_cost(125);
8922 format %{ "andl $dst, $src\t# int" %}
8923 ins_encode %{
8924 __ andl($dst$$Address, $src$$constant);
8925 %}
8926 ins_pipe(ialu_mem_imm);
8927 %}
8928
8929 // BMI1 instructions
8930 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
8931 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
8932 predicate(UseBMI1Instructions);
8933 effect(KILL cr);
8934 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
8935
8936 ins_cost(125);
8937 format %{ "andnl $dst, $src1, $src2" %}
8938
8939 ins_encode %{
8940 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
8941 %}
8942 ins_pipe(ialu_reg_mem);
8943 %}
8944
8945 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
8946 match(Set dst (AndI (XorI src1 minus_1) src2));
8947 predicate(UseBMI1Instructions);
8948 effect(KILL cr);
8949 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
8950
8951 format %{ "andnl $dst, $src1, $src2" %}
8952
8953 ins_encode %{
8954 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
8955 %}
8956 ins_pipe(ialu_reg);
8957 %}
8958
8959 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI_0 imm_zero, rFlagsReg cr) %{
8960 match(Set dst (AndI (SubI imm_zero src) src));
8961 predicate(UseBMI1Instructions);
8962 effect(KILL cr);
8963 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
8964
8965 format %{ "blsil $dst, $src" %}
8966
8967 ins_encode %{
8968 __ blsil($dst$$Register, $src$$Register);
8969 %}
8970 ins_pipe(ialu_reg);
8971 %}
8972
8973 instruct blsiI_rReg_mem(rRegI dst, memory src, immI_0 imm_zero, rFlagsReg cr) %{
8974 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
8975 predicate(UseBMI1Instructions);
8976 effect(KILL cr);
8977 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
8978
8979 ins_cost(125);
8980 format %{ "blsil $dst, $src" %}
8981
8982 ins_encode %{
8983 __ blsil($dst$$Register, $src$$Address);
8984 %}
8985 ins_pipe(ialu_reg_mem);
8986 %}
8987
8988 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
8989 %{
8990 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
8991 predicate(UseBMI1Instructions);
8992 effect(KILL cr);
8993 flag(PD::Flag_sets_sign_flag, PD::Flag_clears_zero_flag, PD::Flag_clears_overflow_flag);
8994
8995 ins_cost(125);
8996 format %{ "blsmskl $dst, $src" %}
8997
8998 ins_encode %{
8999 __ blsmskl($dst$$Register, $src$$Address);
9000 %}
9001 ins_pipe(ialu_reg_mem);
9002 %}
9003
9004 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9005 %{
9006 match(Set dst (XorI (AddI src minus_1) src));
9007 predicate(UseBMI1Instructions);
9008 effect(KILL cr);
9009 flag(PD::Flag_sets_sign_flag, PD::Flag_clears_zero_flag, PD::Flag_clears_overflow_flag);
9010
9011 format %{ "blsmskl $dst, $src" %}
9012
9013 ins_encode %{
9014 __ blsmskl($dst$$Register, $src$$Register);
9015 %}
9016
9017 ins_pipe(ialu_reg);
9018 %}
9019
9020 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9021 %{
9022 match(Set dst (AndI (AddI src minus_1) src) );
9023 predicate(UseBMI1Instructions);
9024 effect(KILL cr);
9025 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
9026
9027 format %{ "blsrl $dst, $src" %}
9028
9029 ins_encode %{
9030 __ blsrl($dst$$Register, $src$$Register);
9031 %}
9032
9033 ins_pipe(ialu_reg_mem);
9034 %}
9035
9036 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9037 %{
9038 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
9039 predicate(UseBMI1Instructions);
9040 effect(KILL cr);
9041 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
9042
9043 ins_cost(125);
9044 format %{ "blsrl $dst, $src" %}
9045
9046 ins_encode %{
9047 __ blsrl($dst$$Register, $src$$Address);
9048 %}
9049
9050 ins_pipe(ialu_reg);
9051 %}
9052
9053 // Or Instructions
9054 // Or Register with Register
9055 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9056 %{
9057 match(Set dst (OrI dst src));
9058 effect(KILL cr);
9059 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9060
9061 format %{ "orl $dst, $src\t# int" %}
9062 ins_encode %{
9063 __ orl($dst$$Register, $src$$Register);
9064 %}
9065 ins_pipe(ialu_reg_reg);
9066 %}
9067
9068 // Or Register with Immediate
9069 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9070 %{
9071 match(Set dst (OrI dst src));
9072 effect(KILL cr);
9073 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9074
9075 format %{ "orl $dst, $src\t# int" %}
9076 ins_encode %{
9077 __ orl($dst$$Register, $src$$constant);
9078 %}
9079 ins_pipe(ialu_reg);
9080 %}
9081
9082 // Or Register with Memory
9083 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9084 %{
9085 match(Set dst (OrI dst (LoadI src)));
9086 effect(KILL cr);
9087 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9088
9089 ins_cost(150);
9090 format %{ "orl $dst, $src\t# int" %}
9091 ins_encode %{
9092 __ orl($dst$$Register, $src$$Address);
9093 %}
9094 ins_pipe(ialu_reg_mem);
9095 %}
9096
9097 // Or Memory with Register
9098 instruct orB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9099 %{
9100 match(Set dst (StoreB dst (OrI (LoadB dst) src)));
9101 effect(KILL cr);
9102 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9103
9104 ins_cost(150);
9105 format %{ "orb $dst, $src\t# byte" %}
9106 ins_encode %{
9107 __ orb($dst$$Address, $src$$Register);
9108 %}
9109 ins_pipe(ialu_mem_reg);
9110 %}
9111
9112 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9113 %{
9114 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9115 effect(KILL cr);
9116 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9117
9118 ins_cost(150);
9119 format %{ "orl $dst, $src\t# int" %}
9120 ins_encode %{
9121 __ orl($dst$$Address, $src$$Register);
9122 %}
9123 ins_pipe(ialu_mem_reg);
9124 %}
9125
9126 // Or Memory with Immediate
9127 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
9128 %{
9129 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9130 effect(KILL cr);
9131 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9132
9133 ins_cost(125);
9134 format %{ "orl $dst, $src\t# int" %}
9135 ins_encode %{
9136 __ orl($dst$$Address, $src$$constant);
9137 %}
9138 ins_pipe(ialu_mem_imm);
9139 %}
9140
9141 // Xor Instructions
9142 // Xor Register with Register
9143 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9144 %{
9145 match(Set dst (XorI dst src));
9146 effect(KILL cr);
9147 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9148
9149 format %{ "xorl $dst, $src\t# int" %}
9150 ins_encode %{
9151 __ xorl($dst$$Register, $src$$Register);
9152 %}
9153 ins_pipe(ialu_reg_reg);
9154 %}
9155
9156 // Xor Register with Immediate -1
9157 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
9158 match(Set dst (XorI dst imm));
9159
9160 format %{ "not $dst" %}
9161 ins_encode %{
9162 __ notl($dst$$Register);
9163 %}
9164 ins_pipe(ialu_reg);
9165 %}
9166
9167 // Xor Register with Immediate
9168 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9169 %{
9170 match(Set dst (XorI dst src));
9171 effect(KILL cr);
9172 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9173
9174 format %{ "xorl $dst, $src\t# int" %}
9175 ins_encode %{
9176 __ xorl($dst$$Register, $src$$constant);
9177 %}
9178 ins_pipe(ialu_reg);
9179 %}
9180
9181 // Xor Register with Memory
9182 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9183 %{
9184 match(Set dst (XorI dst (LoadI src)));
9185 effect(KILL cr);
9186 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9187
9188 ins_cost(150);
9189 format %{ "xorl $dst, $src\t# int" %}
9190 ins_encode %{
9191 __ xorl($dst$$Register, $src$$Address);
9192 %}
9193 ins_pipe(ialu_reg_mem);
9194 %}
9195
9196 // Xor Memory with Register
9197 instruct xorB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9198 %{
9199 match(Set dst (StoreB dst (XorI (LoadB dst) src)));
9200 effect(KILL cr);
9201 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9202
9203 ins_cost(150);
9204 format %{ "xorb $dst, $src\t# byte" %}
9205 ins_encode %{
9206 __ xorb($dst$$Address, $src$$Register);
9207 %}
9208 ins_pipe(ialu_mem_reg);
9209 %}
9210
9211 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9212 %{
9213 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9214 effect(KILL cr);
9215 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9216
9217 ins_cost(150);
9218 format %{ "xorl $dst, $src\t# int" %}
9219 ins_encode %{
9220 __ xorl($dst$$Address, $src$$Register);
9221 %}
9222 ins_pipe(ialu_mem_reg);
9223 %}
9224
9225 // Xor Memory with Immediate
9226 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
9227 %{
9228 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9229 effect(KILL cr);
9230 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9231
9232 ins_cost(125);
9233 format %{ "xorl $dst, $src\t# int" %}
9234 ins_encode %{
9235 __ xorl($dst$$Address, $src$$constant);
9236 %}
9237 ins_pipe(ialu_mem_imm);
9238 %}
9239
9240
9241 // Long Logical Instructions
9242
9243 // And Instructions
9244 // And Register with Register
9245 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9246 %{
9247 match(Set dst (AndL dst src));
9248 effect(KILL cr);
9249 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9250
9251 format %{ "andq $dst, $src\t# long" %}
9252 ins_encode %{
9253 __ andq($dst$$Register, $src$$Register);
9254 %}
9255 ins_pipe(ialu_reg_reg);
9256 %}
9257
9258 // And Register with Immediate 255
9259 instruct andL_rReg_imm255(rRegL dst, rRegL src, immL_255 mask)
9260 %{
9261 match(Set dst (AndL src mask));
9262
9263 format %{ "movzbl $dst, $src\t# long & 0xFF" %}
9264 ins_encode %{
9265 // movzbl zeroes out the upper 32-bit and does not need REX.W
9266 __ movzbl($dst$$Register, $src$$Register);
9267 %}
9268 ins_pipe(ialu_reg);
9269 %}
9270
9271 // And Register with Immediate 65535
9272 instruct andL_rReg_imm65535(rRegL dst, rRegL src, immL_65535 mask)
9273 %{
9274 match(Set dst (AndL src mask));
9275
9276 format %{ "movzwl $dst, $src\t# long & 0xFFFF" %}
9277 ins_encode %{
9278 // movzwl zeroes out the upper 32-bit and does not need REX.W
9279 __ movzwl($dst$$Register, $src$$Register);
9280 %}
9281 ins_pipe(ialu_reg);
9282 %}
9283
9284 // And Register with Immediate
9285 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9286 %{
9287 match(Set dst (AndL dst src));
9288 effect(KILL cr);
9289 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9290
9291 format %{ "andq $dst, $src\t# long" %}
9292 ins_encode %{
9293 __ andq($dst$$Register, $src$$constant);
9294 %}
9295 ins_pipe(ialu_reg);
9296 %}
9297
9298 // And Register with Memory
9299 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9300 %{
9301 match(Set dst (AndL dst (LoadL src)));
9302 effect(KILL cr);
9303 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9304
9305 ins_cost(150);
9306 format %{ "andq $dst, $src\t# long" %}
9307 ins_encode %{
9308 __ andq($dst$$Register, $src$$Address);
9309 %}
9310 ins_pipe(ialu_reg_mem);
9311 %}
9312
9313 // And Memory with Register
9314 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9315 %{
9316 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9317 effect(KILL cr);
9318 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9319
9320 ins_cost(150);
9321 format %{ "andq $dst, $src\t# long" %}
9322 ins_encode %{
9323 __ andq($dst$$Address, $src$$Register);
9324 %}
9325 ins_pipe(ialu_mem_reg);
9326 %}
9327
9328 // And Memory with Immediate
9329 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9330 %{
9331 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9332 effect(KILL cr);
9333 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9334
9335 ins_cost(125);
9336 format %{ "andq $dst, $src\t# long" %}
9337 ins_encode %{
9338 __ andq($dst$$Address, $src$$constant);
9339 %}
9340 ins_pipe(ialu_mem_imm);
9341 %}
9342
9343 instruct btrL_mem_imm(memory dst, immL_NotPow2 con, rFlagsReg cr)
9344 %{
9345 // con should be a pure 64-bit immediate given that not(con) is a power of 2
9346 // because AND/OR works well enough for 8/32-bit values.
9347 predicate(log2i_graceful(~n->in(3)->in(2)->get_long()) > 30);
9348
9349 match(Set dst (StoreL dst (AndL (LoadL dst) con)));
9350 effect(KILL cr);
9351
9352 ins_cost(125);
9353 format %{ "btrq $dst, log2(not($con))\t# long" %}
9354 ins_encode %{
9355 __ btrq($dst$$Address, log2i_exact((julong)~$con$$constant));
9356 %}
9357 ins_pipe(ialu_mem_imm);
9358 %}
9359
9360 // BMI1 instructions
9361 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
9362 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
9363 predicate(UseBMI1Instructions);
9364 effect(KILL cr);
9365 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9366
9367 ins_cost(125);
9368 format %{ "andnq $dst, $src1, $src2" %}
9369
9370 ins_encode %{
9371 __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
9372 %}
9373 ins_pipe(ialu_reg_mem);
9374 %}
9375
9376 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
9377 match(Set dst (AndL (XorL src1 minus_1) src2));
9378 predicate(UseBMI1Instructions);
9379 effect(KILL cr);
9380 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9381
9382 format %{ "andnq $dst, $src1, $src2" %}
9383
9384 ins_encode %{
9385 __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
9386 %}
9387 ins_pipe(ialu_reg_mem);
9388 %}
9389
9390 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
9391 match(Set dst (AndL (SubL imm_zero src) src));
9392 predicate(UseBMI1Instructions);
9393 effect(KILL cr);
9394 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
9395
9396 format %{ "blsiq $dst, $src" %}
9397
9398 ins_encode %{
9399 __ blsiq($dst$$Register, $src$$Register);
9400 %}
9401 ins_pipe(ialu_reg);
9402 %}
9403
9404 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
9405 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
9406 predicate(UseBMI1Instructions);
9407 effect(KILL cr);
9408 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
9409
9410 ins_cost(125);
9411 format %{ "blsiq $dst, $src" %}
9412
9413 ins_encode %{
9414 __ blsiq($dst$$Register, $src$$Address);
9415 %}
9416 ins_pipe(ialu_reg_mem);
9417 %}
9418
9419 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9420 %{
9421 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
9422 predicate(UseBMI1Instructions);
9423 effect(KILL cr);
9424 flag(PD::Flag_sets_sign_flag, PD::Flag_clears_zero_flag, PD::Flag_clears_overflow_flag);
9425
9426 ins_cost(125);
9427 format %{ "blsmskq $dst, $src" %}
9428
9429 ins_encode %{
9430 __ blsmskq($dst$$Register, $src$$Address);
9431 %}
9432 ins_pipe(ialu_reg_mem);
9433 %}
9434
9435 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9436 %{
9437 match(Set dst (XorL (AddL src minus_1) src));
9438 predicate(UseBMI1Instructions);
9439 effect(KILL cr);
9440 flag(PD::Flag_sets_sign_flag, PD::Flag_clears_zero_flag, PD::Flag_clears_overflow_flag);
9441
9442 format %{ "blsmskq $dst, $src" %}
9443
9444 ins_encode %{
9445 __ blsmskq($dst$$Register, $src$$Register);
9446 %}
9447
9448 ins_pipe(ialu_reg);
9449 %}
9450
9451 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9452 %{
9453 match(Set dst (AndL (AddL src minus_1) src) );
9454 predicate(UseBMI1Instructions);
9455 effect(KILL cr);
9456 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
9457
9458 format %{ "blsrq $dst, $src" %}
9459
9460 ins_encode %{
9461 __ blsrq($dst$$Register, $src$$Register);
9462 %}
9463
9464 ins_pipe(ialu_reg);
9465 %}
9466
9467 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9468 %{
9469 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
9470 predicate(UseBMI1Instructions);
9471 effect(KILL cr);
9472 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
9473
9474 ins_cost(125);
9475 format %{ "blsrq $dst, $src" %}
9476
9477 ins_encode %{
9478 __ blsrq($dst$$Register, $src$$Address);
9479 %}
9480
9481 ins_pipe(ialu_reg);
9482 %}
9483
9484 // Or Instructions
9485 // Or Register with Register
9486 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9487 %{
9488 match(Set dst (OrL dst src));
9489 effect(KILL cr);
9490 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9491
9492 format %{ "orq $dst, $src\t# long" %}
9493 ins_encode %{
9494 __ orq($dst$$Register, $src$$Register);
9495 %}
9496 ins_pipe(ialu_reg_reg);
9497 %}
9498
9499 // Use any_RegP to match R15 (TLS register) without spilling.
9500 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
9501 match(Set dst (OrL dst (CastP2X src)));
9502 effect(KILL cr);
9503 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9504
9505 format %{ "orq $dst, $src\t# long" %}
9506 ins_encode %{
9507 __ orq($dst$$Register, $src$$Register);
9508 %}
9509 ins_pipe(ialu_reg_reg);
9510 %}
9511
9512
9513 // Or Register with Immediate
9514 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9515 %{
9516 match(Set dst (OrL dst src));
9517 effect(KILL cr);
9518 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9519
9520 format %{ "orq $dst, $src\t# long" %}
9521 ins_encode %{
9522 __ orq($dst$$Register, $src$$constant);
9523 %}
9524 ins_pipe(ialu_reg);
9525 %}
9526
9527 // Or Register with Memory
9528 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9529 %{
9530 match(Set dst (OrL dst (LoadL src)));
9531 effect(KILL cr);
9532 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9533
9534 ins_cost(150);
9535 format %{ "orq $dst, $src\t# long" %}
9536 ins_encode %{
9537 __ orq($dst$$Register, $src$$Address);
9538 %}
9539 ins_pipe(ialu_reg_mem);
9540 %}
9541
9542 // Or Memory with Register
9543 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9544 %{
9545 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9546 effect(KILL cr);
9547 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9548
9549 ins_cost(150);
9550 format %{ "orq $dst, $src\t# long" %}
9551 ins_encode %{
9552 __ orq($dst$$Address, $src$$Register);
9553 %}
9554 ins_pipe(ialu_mem_reg);
9555 %}
9556
9557 // Or Memory with Immediate
9558 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9559 %{
9560 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9561 effect(KILL cr);
9562 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9563
9564 ins_cost(125);
9565 format %{ "orq $dst, $src\t# long" %}
9566 ins_encode %{
9567 __ orq($dst$$Address, $src$$constant);
9568 %}
9569 ins_pipe(ialu_mem_imm);
9570 %}
9571
9572 instruct btsL_mem_imm(memory dst, immL_Pow2 con, rFlagsReg cr)
9573 %{
9574 // con should be a pure 64-bit power of 2 immediate
9575 // because AND/OR works well enough for 8/32-bit values.
9576 predicate(log2i_graceful(n->in(3)->in(2)->get_long()) > 31);
9577
9578 match(Set dst (StoreL dst (OrL (LoadL dst) con)));
9579 effect(KILL cr);
9580
9581 ins_cost(125);
9582 format %{ "btsq $dst, log2($con)\t# long" %}
9583 ins_encode %{
9584 __ btsq($dst$$Address, log2i_exact((julong)$con$$constant));
9585 %}
9586 ins_pipe(ialu_mem_imm);
9587 %}
9588
9589 // Xor Instructions
9590 // Xor Register with Register
9591 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9592 %{
9593 match(Set dst (XorL dst src));
9594 effect(KILL cr);
9595 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9596
9597 format %{ "xorq $dst, $src\t# long" %}
9598 ins_encode %{
9599 __ xorq($dst$$Register, $src$$Register);
9600 %}
9601 ins_pipe(ialu_reg_reg);
9602 %}
9603
9604 // Xor Register with Immediate -1
9605 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
9606 match(Set dst (XorL dst imm));
9607
9608 format %{ "notq $dst" %}
9609 ins_encode %{
9610 __ notq($dst$$Register);
9611 %}
9612 ins_pipe(ialu_reg);
9613 %}
9614
9615 // Xor Register with Immediate
9616 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9617 %{
9618 match(Set dst (XorL dst src));
9619 effect(KILL cr);
9620 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9621
9622 format %{ "xorq $dst, $src\t# long" %}
9623 ins_encode %{
9624 __ xorq($dst$$Register, $src$$constant);
9625 %}
9626 ins_pipe(ialu_reg);
9627 %}
9628
9629 // Xor Register with Memory
9630 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9631 %{
9632 match(Set dst (XorL dst (LoadL src)));
9633 effect(KILL cr);
9634 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9635
9636 ins_cost(150);
9637 format %{ "xorq $dst, $src\t# long" %}
9638 ins_encode %{
9639 __ xorq($dst$$Register, $src$$Address);
9640 %}
9641 ins_pipe(ialu_reg_mem);
9642 %}
9643
9644 // Xor Memory with Register
9645 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9646 %{
9647 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9648 effect(KILL cr);
9649 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9650
9651 ins_cost(150);
9652 format %{ "xorq $dst, $src\t# long" %}
9653 ins_encode %{
9654 __ xorq($dst$$Address, $src$$Register);
9655 %}
9656 ins_pipe(ialu_mem_reg);
9657 %}
9658
9659 // Xor Memory with Immediate
9660 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9661 %{
9662 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9663 effect(KILL cr);
9664 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9665
9666 ins_cost(125);
9667 format %{ "xorq $dst, $src\t# long" %}
9668 ins_encode %{
9669 __ xorq($dst$$Address, $src$$constant);
9670 %}
9671 ins_pipe(ialu_mem_imm);
9672 %}
9673
9674 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
9675 %{
9676 match(Set dst (CmpLTMask p q));
9677 effect(KILL cr);
9678
9679 ins_cost(400);
9680 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
9681 "setcc $dst \t# emits setlt + movzbl or setzul for APX"
9682 "negl $dst" %}
9683 ins_encode %{
9684 __ cmpl($p$$Register, $q$$Register);
9685 __ setcc(Assembler::less, $dst$$Register);
9686 __ negl($dst$$Register);
9687 %}
9688 ins_pipe(pipe_slow);
9689 %}
9690
9691 instruct cmpLTMask0(rRegI dst, immI_0 zero, rFlagsReg cr)
9692 %{
9693 match(Set dst (CmpLTMask dst zero));
9694 effect(KILL cr);
9695
9696 ins_cost(100);
9697 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
9698 ins_encode %{
9699 __ sarl($dst$$Register, 31);
9700 %}
9701 ins_pipe(ialu_reg);
9702 %}
9703
9704 /* Better to save a register than avoid a branch */
9705 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
9706 %{
9707 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9708 effect(KILL cr);
9709 ins_cost(300);
9710 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t"
9711 "jge done\n\t"
9712 "addl $p,$y\n"
9713 "done: " %}
9714 ins_encode %{
9715 Register Rp = $p$$Register;
9716 Register Rq = $q$$Register;
9717 Register Ry = $y$$Register;
9718 Label done;
9719 __ subl(Rp, Rq);
9720 __ jccb(Assembler::greaterEqual, done);
9721 __ addl(Rp, Ry);
9722 __ bind(done);
9723 %}
9724 ins_pipe(pipe_cmplt);
9725 %}
9726
9727 /* Better to save a register than avoid a branch */
9728 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
9729 %{
9730 match(Set y (AndI (CmpLTMask p q) y));
9731 effect(KILL cr);
9732
9733 ins_cost(300);
9734
9735 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t"
9736 "jlt done\n\t"
9737 "xorl $y, $y\n"
9738 "done: " %}
9739 ins_encode %{
9740 Register Rp = $p$$Register;
9741 Register Rq = $q$$Register;
9742 Register Ry = $y$$Register;
9743 Label done;
9744 __ cmpl(Rp, Rq);
9745 __ jccb(Assembler::less, done);
9746 __ xorl(Ry, Ry);
9747 __ bind(done);
9748 %}
9749 ins_pipe(pipe_cmplt);
9750 %}
9751
9752
9753 //---------- FP Instructions------------------------------------------------
9754
9755 // Really expensive, avoid
9756 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
9757 %{
9758 match(Set cr (CmpF src1 src2));
9759
9760 ins_cost(500);
9761 format %{ "ucomiss $src1, $src2\n\t"
9762 "jnp,s exit\n\t"
9763 "pushfq\t# saw NaN, set CF\n\t"
9764 "andq [rsp], #0xffffff2b\n\t"
9765 "popfq\n"
9766 "exit:" %}
9767 ins_encode %{
9768 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9769 emit_cmpfp_fixup(masm);
9770 %}
9771 ins_pipe(pipe_slow);
9772 %}
9773
9774 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
9775 match(Set cr (CmpF src1 src2));
9776
9777 ins_cost(100);
9778 format %{ "ucomiss $src1, $src2" %}
9779 ins_encode %{
9780 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9781 %}
9782 ins_pipe(pipe_slow);
9783 %}
9784
9785 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
9786 match(Set cr (CmpF src1 (LoadF src2)));
9787
9788 ins_cost(100);
9789 format %{ "ucomiss $src1, $src2" %}
9790 ins_encode %{
9791 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9792 %}
9793 ins_pipe(pipe_slow);
9794 %}
9795
9796 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
9797 match(Set cr (CmpF src con));
9798 ins_cost(100);
9799 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
9800 ins_encode %{
9801 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9802 %}
9803 ins_pipe(pipe_slow);
9804 %}
9805
9806 // Really expensive, avoid
9807 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
9808 %{
9809 match(Set cr (CmpD src1 src2));
9810
9811 ins_cost(500);
9812 format %{ "ucomisd $src1, $src2\n\t"
9813 "jnp,s exit\n\t"
9814 "pushfq\t# saw NaN, set CF\n\t"
9815 "andq [rsp], #0xffffff2b\n\t"
9816 "popfq\n"
9817 "exit:" %}
9818 ins_encode %{
9819 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9820 emit_cmpfp_fixup(masm);
9821 %}
9822 ins_pipe(pipe_slow);
9823 %}
9824
9825 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
9826 match(Set cr (CmpD src1 src2));
9827
9828 ins_cost(100);
9829 format %{ "ucomisd $src1, $src2 test" %}
9830 ins_encode %{
9831 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9832 %}
9833 ins_pipe(pipe_slow);
9834 %}
9835
9836 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
9837 match(Set cr (CmpD src1 (LoadD src2)));
9838
9839 ins_cost(100);
9840 format %{ "ucomisd $src1, $src2" %}
9841 ins_encode %{
9842 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9843 %}
9844 ins_pipe(pipe_slow);
9845 %}
9846
9847 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
9848 match(Set cr (CmpD src con));
9849 ins_cost(100);
9850 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
9851 ins_encode %{
9852 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9853 %}
9854 ins_pipe(pipe_slow);
9855 %}
9856
9857 // Compare into -1,0,1
9858 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
9859 %{
9860 match(Set dst (CmpF3 src1 src2));
9861 effect(KILL cr);
9862
9863 ins_cost(275);
9864 format %{ "ucomiss $src1, $src2\n\t"
9865 "movl $dst, #-1\n\t"
9866 "jp,s done\n\t"
9867 "jb,s done\n\t"
9868 "setne $dst\n\t"
9869 "movzbl $dst, $dst\n"
9870 "done:" %}
9871 ins_encode %{
9872 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9873 emit_cmpfp3(masm, $dst$$Register);
9874 %}
9875 ins_pipe(pipe_slow);
9876 %}
9877
9878 // Compare into -1,0,1
9879 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
9880 %{
9881 match(Set dst (CmpF3 src1 (LoadF src2)));
9882 effect(KILL cr);
9883
9884 ins_cost(275);
9885 format %{ "ucomiss $src1, $src2\n\t"
9886 "movl $dst, #-1\n\t"
9887 "jp,s done\n\t"
9888 "jb,s done\n\t"
9889 "setne $dst\n\t"
9890 "movzbl $dst, $dst\n"
9891 "done:" %}
9892 ins_encode %{
9893 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9894 emit_cmpfp3(masm, $dst$$Register);
9895 %}
9896 ins_pipe(pipe_slow);
9897 %}
9898
9899 // Compare into -1,0,1
9900 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
9901 match(Set dst (CmpF3 src con));
9902 effect(KILL cr);
9903
9904 ins_cost(275);
9905 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9906 "movl $dst, #-1\n\t"
9907 "jp,s done\n\t"
9908 "jb,s done\n\t"
9909 "setne $dst\n\t"
9910 "movzbl $dst, $dst\n"
9911 "done:" %}
9912 ins_encode %{
9913 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9914 emit_cmpfp3(masm, $dst$$Register);
9915 %}
9916 ins_pipe(pipe_slow);
9917 %}
9918
9919 // Compare into -1,0,1
9920 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
9921 %{
9922 match(Set dst (CmpD3 src1 src2));
9923 effect(KILL cr);
9924
9925 ins_cost(275);
9926 format %{ "ucomisd $src1, $src2\n\t"
9927 "movl $dst, #-1\n\t"
9928 "jp,s done\n\t"
9929 "jb,s done\n\t"
9930 "setne $dst\n\t"
9931 "movzbl $dst, $dst\n"
9932 "done:" %}
9933 ins_encode %{
9934 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9935 emit_cmpfp3(masm, $dst$$Register);
9936 %}
9937 ins_pipe(pipe_slow);
9938 %}
9939
9940 // Compare into -1,0,1
9941 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
9942 %{
9943 match(Set dst (CmpD3 src1 (LoadD src2)));
9944 effect(KILL cr);
9945
9946 ins_cost(275);
9947 format %{ "ucomisd $src1, $src2\n\t"
9948 "movl $dst, #-1\n\t"
9949 "jp,s done\n\t"
9950 "jb,s done\n\t"
9951 "setne $dst\n\t"
9952 "movzbl $dst, $dst\n"
9953 "done:" %}
9954 ins_encode %{
9955 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9956 emit_cmpfp3(masm, $dst$$Register);
9957 %}
9958 ins_pipe(pipe_slow);
9959 %}
9960
9961 // Compare into -1,0,1
9962 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
9963 match(Set dst (CmpD3 src con));
9964 effect(KILL cr);
9965
9966 ins_cost(275);
9967 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
9968 "movl $dst, #-1\n\t"
9969 "jp,s done\n\t"
9970 "jb,s done\n\t"
9971 "setne $dst\n\t"
9972 "movzbl $dst, $dst\n"
9973 "done:" %}
9974 ins_encode %{
9975 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9976 emit_cmpfp3(masm, $dst$$Register);
9977 %}
9978 ins_pipe(pipe_slow);
9979 %}
9980
9981 //----------Arithmetic Conversion Instructions---------------------------------
9982
9983 instruct convF2D_reg_reg(regD dst, regF src)
9984 %{
9985 match(Set dst (ConvF2D src));
9986
9987 format %{ "cvtss2sd $dst, $src" %}
9988 ins_encode %{
9989 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
9990 %}
9991 ins_pipe(pipe_slow); // XXX
9992 %}
9993
9994 instruct convF2D_reg_mem(regD dst, memory src)
9995 %{
9996 predicate(UseAVX == 0);
9997 match(Set dst (ConvF2D (LoadF src)));
9998
9999 format %{ "cvtss2sd $dst, $src" %}
10000 ins_encode %{
10001 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
10002 %}
10003 ins_pipe(pipe_slow); // XXX
10004 %}
10005
10006 instruct convD2F_reg_reg(regF dst, regD src)
10007 %{
10008 match(Set dst (ConvD2F src));
10009
10010 format %{ "cvtsd2ss $dst, $src" %}
10011 ins_encode %{
10012 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10013 %}
10014 ins_pipe(pipe_slow); // XXX
10015 %}
10016
10017 instruct convD2F_reg_mem(regF dst, memory src)
10018 %{
10019 predicate(UseAVX == 0);
10020 match(Set dst (ConvD2F (LoadD src)));
10021
10022 format %{ "cvtsd2ss $dst, $src" %}
10023 ins_encode %{
10024 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
10025 %}
10026 ins_pipe(pipe_slow); // XXX
10027 %}
10028
10029 // XXX do mem variants
10030 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
10031 %{
10032 match(Set dst (ConvF2I src));
10033 effect(KILL cr);
10034 format %{ "convert_f2i $dst, $src" %}
10035 ins_encode %{
10036 __ convertF2I(T_INT, T_FLOAT, $dst$$Register, $src$$XMMRegister);
10037 %}
10038 ins_pipe(pipe_slow);
10039 %}
10040
10041 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
10042 %{
10043 match(Set dst (ConvF2L src));
10044 effect(KILL cr);
10045 format %{ "convert_f2l $dst, $src"%}
10046 ins_encode %{
10047 __ convertF2I(T_LONG, T_FLOAT, $dst$$Register, $src$$XMMRegister);
10048 %}
10049 ins_pipe(pipe_slow);
10050 %}
10051
10052 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
10053 %{
10054 match(Set dst (ConvD2I src));
10055 effect(KILL cr);
10056 format %{ "convert_d2i $dst, $src"%}
10057 ins_encode %{
10058 __ convertF2I(T_INT, T_DOUBLE, $dst$$Register, $src$$XMMRegister);
10059 %}
10060 ins_pipe(pipe_slow);
10061 %}
10062
10063 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
10064 %{
10065 match(Set dst (ConvD2L src));
10066 effect(KILL cr);
10067 format %{ "convert_d2l $dst, $src"%}
10068 ins_encode %{
10069 __ convertF2I(T_LONG, T_DOUBLE, $dst$$Register, $src$$XMMRegister);
10070 %}
10071 ins_pipe(pipe_slow);
10072 %}
10073
10074 instruct round_double_reg(rRegL dst, regD src, rRegL rtmp, rcx_RegL rcx, rFlagsReg cr)
10075 %{
10076 match(Set dst (RoundD src));
10077 effect(TEMP dst, TEMP rtmp, TEMP rcx, KILL cr);
10078 format %{ "round_double $dst,$src \t! using $rtmp and $rcx as TEMP"%}
10079 ins_encode %{
10080 __ round_double($dst$$Register, $src$$XMMRegister, $rtmp$$Register, $rcx$$Register);
10081 %}
10082 ins_pipe(pipe_slow);
10083 %}
10084
10085 instruct round_float_reg(rRegI dst, regF src, rRegL rtmp, rcx_RegL rcx, rFlagsReg cr)
10086 %{
10087 match(Set dst (RoundF src));
10088 effect(TEMP dst, TEMP rtmp, TEMP rcx, KILL cr);
10089 format %{ "round_float $dst,$src" %}
10090 ins_encode %{
10091 __ round_float($dst$$Register, $src$$XMMRegister, $rtmp$$Register, $rcx$$Register);
10092 %}
10093 ins_pipe(pipe_slow);
10094 %}
10095
10096 instruct convI2F_reg_reg(vlRegF dst, rRegI src)
10097 %{
10098 predicate(!UseXmmI2F);
10099 match(Set dst (ConvI2F src));
10100
10101 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10102 ins_encode %{
10103 if (UseAVX > 0) {
10104 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
10105 }
10106 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
10107 %}
10108 ins_pipe(pipe_slow); // XXX
10109 %}
10110
10111 instruct convI2F_reg_mem(regF dst, memory src)
10112 %{
10113 predicate(UseAVX == 0);
10114 match(Set dst (ConvI2F (LoadI src)));
10115
10116 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10117 ins_encode %{
10118 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
10119 %}
10120 ins_pipe(pipe_slow); // XXX
10121 %}
10122
10123 instruct convI2D_reg_reg(vlRegD dst, rRegI src)
10124 %{
10125 predicate(!UseXmmI2D);
10126 match(Set dst (ConvI2D src));
10127
10128 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10129 ins_encode %{
10130 if (UseAVX > 0) {
10131 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
10132 }
10133 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10134 %}
10135 ins_pipe(pipe_slow); // XXX
10136 %}
10137
10138 instruct convI2D_reg_mem(regD dst, memory src)
10139 %{
10140 predicate(UseAVX == 0);
10141 match(Set dst (ConvI2D (LoadI src)));
10142
10143 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10144 ins_encode %{
10145 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
10146 %}
10147 ins_pipe(pipe_slow); // XXX
10148 %}
10149
10150 instruct convXI2F_reg(regF dst, rRegI src)
10151 %{
10152 predicate(UseXmmI2F);
10153 match(Set dst (ConvI2F src));
10154
10155 format %{ "movdl $dst, $src\n\t"
10156 "cvtdq2psl $dst, $dst\t# i2f" %}
10157 ins_encode %{
10158 __ movdl($dst$$XMMRegister, $src$$Register);
10159 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10160 %}
10161 ins_pipe(pipe_slow); // XXX
10162 %}
10163
10164 instruct convXI2D_reg(regD dst, rRegI src)
10165 %{
10166 predicate(UseXmmI2D);
10167 match(Set dst (ConvI2D src));
10168
10169 format %{ "movdl $dst, $src\n\t"
10170 "cvtdq2pdl $dst, $dst\t# i2d" %}
10171 ins_encode %{
10172 __ movdl($dst$$XMMRegister, $src$$Register);
10173 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10174 %}
10175 ins_pipe(pipe_slow); // XXX
10176 %}
10177
10178 instruct convL2F_reg_reg(vlRegF dst, rRegL src)
10179 %{
10180 match(Set dst (ConvL2F src));
10181
10182 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10183 ins_encode %{
10184 if (UseAVX > 0) {
10185 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
10186 }
10187 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
10188 %}
10189 ins_pipe(pipe_slow); // XXX
10190 %}
10191
10192 instruct convL2F_reg_mem(regF dst, memory src)
10193 %{
10194 predicate(UseAVX == 0);
10195 match(Set dst (ConvL2F (LoadL src)));
10196
10197 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10198 ins_encode %{
10199 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
10200 %}
10201 ins_pipe(pipe_slow); // XXX
10202 %}
10203
10204 instruct convL2D_reg_reg(vlRegD dst, rRegL src)
10205 %{
10206 match(Set dst (ConvL2D src));
10207
10208 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10209 ins_encode %{
10210 if (UseAVX > 0) {
10211 __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
10212 }
10213 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
10214 %}
10215 ins_pipe(pipe_slow); // XXX
10216 %}
10217
10218 instruct convL2D_reg_mem(regD dst, memory src)
10219 %{
10220 predicate(UseAVX == 0);
10221 match(Set dst (ConvL2D (LoadL src)));
10222
10223 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10224 ins_encode %{
10225 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
10226 %}
10227 ins_pipe(pipe_slow); // XXX
10228 %}
10229
10230 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10231 %{
10232 match(Set dst (ConvI2L src));
10233
10234 ins_cost(125);
10235 format %{ "movslq $dst, $src\t# i2l" %}
10236 ins_encode %{
10237 __ movslq($dst$$Register, $src$$Register);
10238 %}
10239 ins_pipe(ialu_reg_reg);
10240 %}
10241
10242 // Zero-extend convert int to long
10243 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10244 %{
10245 match(Set dst (AndL (ConvI2L src) mask));
10246
10247 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10248 ins_encode %{
10249 if ($dst$$reg != $src$$reg) {
10250 __ movl($dst$$Register, $src$$Register);
10251 }
10252 %}
10253 ins_pipe(ialu_reg_reg);
10254 %}
10255
10256 // Zero-extend convert int to long
10257 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10258 %{
10259 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10260
10261 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10262 ins_encode %{
10263 __ movl($dst$$Register, $src$$Address);
10264 %}
10265 ins_pipe(ialu_reg_mem);
10266 %}
10267
10268 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10269 %{
10270 match(Set dst (AndL src mask));
10271
10272 format %{ "movl $dst, $src\t# zero-extend long" %}
10273 ins_encode %{
10274 __ movl($dst$$Register, $src$$Register);
10275 %}
10276 ins_pipe(ialu_reg_reg);
10277 %}
10278
10279 instruct convL2I_reg_reg(rRegI dst, rRegL src)
10280 %{
10281 match(Set dst (ConvL2I src));
10282
10283 format %{ "movl $dst, $src\t# l2i" %}
10284 ins_encode %{
10285 __ movl($dst$$Register, $src$$Register);
10286 %}
10287 ins_pipe(ialu_reg_reg);
10288 %}
10289
10290
10291 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10292 match(Set dst (MoveF2I src));
10293 effect(DEF dst, USE src);
10294
10295 ins_cost(125);
10296 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
10297 ins_encode %{
10298 __ movl($dst$$Register, Address(rsp, $src$$disp));
10299 %}
10300 ins_pipe(ialu_reg_mem);
10301 %}
10302
10303 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
10304 match(Set dst (MoveI2F src));
10305 effect(DEF dst, USE src);
10306
10307 ins_cost(125);
10308 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
10309 ins_encode %{
10310 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
10311 %}
10312 ins_pipe(pipe_slow);
10313 %}
10314
10315 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
10316 match(Set dst (MoveD2L src));
10317 effect(DEF dst, USE src);
10318
10319 ins_cost(125);
10320 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
10321 ins_encode %{
10322 __ movq($dst$$Register, Address(rsp, $src$$disp));
10323 %}
10324 ins_pipe(ialu_reg_mem);
10325 %}
10326
10327 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
10328 predicate(!UseXmmLoadAndClearUpper);
10329 match(Set dst (MoveL2D src));
10330 effect(DEF dst, USE src);
10331
10332 ins_cost(125);
10333 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
10334 ins_encode %{
10335 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10336 %}
10337 ins_pipe(pipe_slow);
10338 %}
10339
10340 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
10341 predicate(UseXmmLoadAndClearUpper);
10342 match(Set dst (MoveL2D src));
10343 effect(DEF dst, USE src);
10344
10345 ins_cost(125);
10346 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
10347 ins_encode %{
10348 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10349 %}
10350 ins_pipe(pipe_slow);
10351 %}
10352
10353
10354 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
10355 match(Set dst (MoveF2I src));
10356 effect(DEF dst, USE src);
10357
10358 ins_cost(95); // XXX
10359 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
10360 ins_encode %{
10361 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
10362 %}
10363 ins_pipe(pipe_slow);
10364 %}
10365
10366 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10367 match(Set dst (MoveI2F src));
10368 effect(DEF dst, USE src);
10369
10370 ins_cost(100);
10371 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
10372 ins_encode %{
10373 __ movl(Address(rsp, $dst$$disp), $src$$Register);
10374 %}
10375 ins_pipe( ialu_mem_reg );
10376 %}
10377
10378 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
10379 match(Set dst (MoveD2L src));
10380 effect(DEF dst, USE src);
10381
10382 ins_cost(95); // XXX
10383 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
10384 ins_encode %{
10385 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
10386 %}
10387 ins_pipe(pipe_slow);
10388 %}
10389
10390 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
10391 match(Set dst (MoveL2D src));
10392 effect(DEF dst, USE src);
10393
10394 ins_cost(100);
10395 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
10396 ins_encode %{
10397 __ movq(Address(rsp, $dst$$disp), $src$$Register);
10398 %}
10399 ins_pipe(ialu_mem_reg);
10400 %}
10401
10402 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
10403 match(Set dst (MoveF2I src));
10404 effect(DEF dst, USE src);
10405 ins_cost(85);
10406 format %{ "movd $dst,$src\t# MoveF2I" %}
10407 ins_encode %{
10408 __ movdl($dst$$Register, $src$$XMMRegister);
10409 %}
10410 ins_pipe( pipe_slow );
10411 %}
10412
10413 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
10414 match(Set dst (MoveD2L src));
10415 effect(DEF dst, USE src);
10416 ins_cost(85);
10417 format %{ "movd $dst,$src\t# MoveD2L" %}
10418 ins_encode %{
10419 __ movdq($dst$$Register, $src$$XMMRegister);
10420 %}
10421 ins_pipe( pipe_slow );
10422 %}
10423
10424 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
10425 match(Set dst (MoveI2F src));
10426 effect(DEF dst, USE src);
10427 ins_cost(100);
10428 format %{ "movd $dst,$src\t# MoveI2F" %}
10429 ins_encode %{
10430 __ movdl($dst$$XMMRegister, $src$$Register);
10431 %}
10432 ins_pipe( pipe_slow );
10433 %}
10434
10435 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
10436 match(Set dst (MoveL2D src));
10437 effect(DEF dst, USE src);
10438 ins_cost(100);
10439 format %{ "movd $dst,$src\t# MoveL2D" %}
10440 ins_encode %{
10441 __ movdq($dst$$XMMRegister, $src$$Register);
10442 %}
10443 ins_pipe( pipe_slow );
10444 %}
10445
10446 // Fast clearing of an array
10447 // Small non-constant lenght ClearArray for non-AVX512 targets.
10448 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
10449 Universe dummy, rFlagsReg cr)
10450 %{
10451 predicate(!((ClearArrayNode*)n)->is_large() && (UseAVX <= 2));
10452 match(Set dummy (ClearArray cnt base));
10453 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
10454
10455 format %{ $$template
10456 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
10457 $$emit$$"cmp InitArrayShortSize,rcx\n\t"
10458 $$emit$$"jg LARGE\n\t"
10459 $$emit$$"dec rcx\n\t"
10460 $$emit$$"js DONE\t# Zero length\n\t"
10461 $$emit$$"mov rax,(rdi,rcx,8)\t# LOOP\n\t"
10462 $$emit$$"dec rcx\n\t"
10463 $$emit$$"jge LOOP\n\t"
10464 $$emit$$"jmp DONE\n\t"
10465 $$emit$$"# LARGE:\n\t"
10466 if (UseFastStosb) {
10467 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
10468 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--\n\t"
10469 } else if (UseXMMForObjInit) {
10470 $$emit$$"mov rdi,rax\n\t"
10471 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
10472 $$emit$$"jmpq L_zero_64_bytes\n\t"
10473 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
10474 $$emit$$"vmovdqu ymm0,(rax)\n\t"
10475 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
10476 $$emit$$"add 0x40,rax\n\t"
10477 $$emit$$"# L_zero_64_bytes:\n\t"
10478 $$emit$$"sub 0x8,rcx\n\t"
10479 $$emit$$"jge L_loop\n\t"
10480 $$emit$$"add 0x4,rcx\n\t"
10481 $$emit$$"jl L_tail\n\t"
10482 $$emit$$"vmovdqu ymm0,(rax)\n\t"
10483 $$emit$$"add 0x20,rax\n\t"
10484 $$emit$$"sub 0x4,rcx\n\t"
10485 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
10486 $$emit$$"add 0x4,rcx\n\t"
10487 $$emit$$"jle L_end\n\t"
10488 $$emit$$"dec rcx\n\t"
10489 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
10490 $$emit$$"vmovq xmm0,(rax)\n\t"
10491 $$emit$$"add 0x8,rax\n\t"
10492 $$emit$$"dec rcx\n\t"
10493 $$emit$$"jge L_sloop\n\t"
10494 $$emit$$"# L_end:\n\t"
10495 } else {
10496 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--\n\t"
10497 }
10498 $$emit$$"# DONE"
10499 %}
10500 ins_encode %{
10501 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
10502 $tmp$$XMMRegister, false, knoreg);
10503 %}
10504 ins_pipe(pipe_slow);
10505 %}
10506
10507 // Small non-constant length ClearArray for AVX512 targets.
10508 instruct rep_stos_evex(rcx_RegL cnt, rdi_RegP base, legRegD tmp, kReg ktmp, rax_RegI zero,
10509 Universe dummy, rFlagsReg cr)
10510 %{
10511 predicate(!((ClearArrayNode*)n)->is_large() && (UseAVX > 2));
10512 match(Set dummy (ClearArray cnt base));
10513 ins_cost(125);
10514 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, TEMP ktmp, KILL zero, KILL cr);
10515
10516 format %{ $$template
10517 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
10518 $$emit$$"cmp InitArrayShortSize,rcx\n\t"
10519 $$emit$$"jg LARGE\n\t"
10520 $$emit$$"dec rcx\n\t"
10521 $$emit$$"js DONE\t# Zero length\n\t"
10522 $$emit$$"mov rax,(rdi,rcx,8)\t# LOOP\n\t"
10523 $$emit$$"dec rcx\n\t"
10524 $$emit$$"jge LOOP\n\t"
10525 $$emit$$"jmp DONE\n\t"
10526 $$emit$$"# LARGE:\n\t"
10527 if (UseFastStosb) {
10528 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
10529 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--\n\t"
10530 } else if (UseXMMForObjInit) {
10531 $$emit$$"mov rdi,rax\n\t"
10532 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
10533 $$emit$$"jmpq L_zero_64_bytes\n\t"
10534 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
10535 $$emit$$"vmovdqu ymm0,(rax)\n\t"
10536 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
10537 $$emit$$"add 0x40,rax\n\t"
10538 $$emit$$"# L_zero_64_bytes:\n\t"
10539 $$emit$$"sub 0x8,rcx\n\t"
10540 $$emit$$"jge L_loop\n\t"
10541 $$emit$$"add 0x4,rcx\n\t"
10542 $$emit$$"jl L_tail\n\t"
10543 $$emit$$"vmovdqu ymm0,(rax)\n\t"
10544 $$emit$$"add 0x20,rax\n\t"
10545 $$emit$$"sub 0x4,rcx\n\t"
10546 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
10547 $$emit$$"add 0x4,rcx\n\t"
10548 $$emit$$"jle L_end\n\t"
10549 $$emit$$"dec rcx\n\t"
10550 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
10551 $$emit$$"vmovq xmm0,(rax)\n\t"
10552 $$emit$$"add 0x8,rax\n\t"
10553 $$emit$$"dec rcx\n\t"
10554 $$emit$$"jge L_sloop\n\t"
10555 $$emit$$"# L_end:\n\t"
10556 } else {
10557 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--\n\t"
10558 }
10559 $$emit$$"# DONE"
10560 %}
10561 ins_encode %{
10562 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
10563 $tmp$$XMMRegister, false, $ktmp$$KRegister);
10564 %}
10565 ins_pipe(pipe_slow);
10566 %}
10567
10568 // Large non-constant length ClearArray for non-AVX512 targets.
10569 instruct rep_stos_large(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
10570 Universe dummy, rFlagsReg cr)
10571 %{
10572 predicate((UseAVX <=2) && ((ClearArrayNode*)n)->is_large());
10573 match(Set dummy (ClearArray cnt base));
10574 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
10575
10576 format %{ $$template
10577 if (UseFastStosb) {
10578 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
10579 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
10580 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--"
10581 } else if (UseXMMForObjInit) {
10582 $$emit$$"mov rdi,rax\t# ClearArray:\n\t"
10583 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
10584 $$emit$$"jmpq L_zero_64_bytes\n\t"
10585 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
10586 $$emit$$"vmovdqu ymm0,(rax)\n\t"
10587 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
10588 $$emit$$"add 0x40,rax\n\t"
10589 $$emit$$"# L_zero_64_bytes:\n\t"
10590 $$emit$$"sub 0x8,rcx\n\t"
10591 $$emit$$"jge L_loop\n\t"
10592 $$emit$$"add 0x4,rcx\n\t"
10593 $$emit$$"jl L_tail\n\t"
10594 $$emit$$"vmovdqu ymm0,(rax)\n\t"
10595 $$emit$$"add 0x20,rax\n\t"
10596 $$emit$$"sub 0x4,rcx\n\t"
10597 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
10598 $$emit$$"add 0x4,rcx\n\t"
10599 $$emit$$"jle L_end\n\t"
10600 $$emit$$"dec rcx\n\t"
10601 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
10602 $$emit$$"vmovq xmm0,(rax)\n\t"
10603 $$emit$$"add 0x8,rax\n\t"
10604 $$emit$$"dec rcx\n\t"
10605 $$emit$$"jge L_sloop\n\t"
10606 $$emit$$"# L_end:\n\t"
10607 } else {
10608 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
10609 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--"
10610 }
10611 %}
10612 ins_encode %{
10613 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
10614 $tmp$$XMMRegister, true, knoreg);
10615 %}
10616 ins_pipe(pipe_slow);
10617 %}
10618
10619 // Large non-constant length ClearArray for AVX512 targets.
10620 instruct rep_stos_large_evex(rcx_RegL cnt, rdi_RegP base, legRegD tmp, kReg ktmp, rax_RegI zero,
10621 Universe dummy, rFlagsReg cr)
10622 %{
10623 predicate((UseAVX > 2) && ((ClearArrayNode*)n)->is_large());
10624 match(Set dummy (ClearArray cnt base));
10625 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, TEMP ktmp, KILL zero, KILL cr);
10626
10627 format %{ $$template
10628 if (UseFastStosb) {
10629 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
10630 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
10631 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--"
10632 } else if (UseXMMForObjInit) {
10633 $$emit$$"mov rdi,rax\t# ClearArray:\n\t"
10634 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
10635 $$emit$$"jmpq L_zero_64_bytes\n\t"
10636 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
10637 $$emit$$"vmovdqu ymm0,(rax)\n\t"
10638 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
10639 $$emit$$"add 0x40,rax\n\t"
10640 $$emit$$"# L_zero_64_bytes:\n\t"
10641 $$emit$$"sub 0x8,rcx\n\t"
10642 $$emit$$"jge L_loop\n\t"
10643 $$emit$$"add 0x4,rcx\n\t"
10644 $$emit$$"jl L_tail\n\t"
10645 $$emit$$"vmovdqu ymm0,(rax)\n\t"
10646 $$emit$$"add 0x20,rax\n\t"
10647 $$emit$$"sub 0x4,rcx\n\t"
10648 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
10649 $$emit$$"add 0x4,rcx\n\t"
10650 $$emit$$"jle L_end\n\t"
10651 $$emit$$"dec rcx\n\t"
10652 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
10653 $$emit$$"vmovq xmm0,(rax)\n\t"
10654 $$emit$$"add 0x8,rax\n\t"
10655 $$emit$$"dec rcx\n\t"
10656 $$emit$$"jge L_sloop\n\t"
10657 $$emit$$"# L_end:\n\t"
10658 } else {
10659 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
10660 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--"
10661 }
10662 %}
10663 ins_encode %{
10664 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
10665 $tmp$$XMMRegister, true, $ktmp$$KRegister);
10666 %}
10667 ins_pipe(pipe_slow);
10668 %}
10669
10670 // Small constant length ClearArray for AVX512 targets.
10671 instruct rep_stos_im(immL cnt, rRegP base, regD tmp, rRegI zero, kReg ktmp, Universe dummy, rFlagsReg cr)
10672 %{
10673 predicate(!((ClearArrayNode*)n)->is_large() && (MaxVectorSize >= 32) && VM_Version::supports_avx512vl());
10674 match(Set dummy (ClearArray cnt base));
10675 ins_cost(100);
10676 effect(TEMP tmp, TEMP zero, TEMP ktmp, KILL cr);
10677 format %{ "clear_mem_imm $base , $cnt \n\t" %}
10678 ins_encode %{
10679 __ clear_mem($base$$Register, $cnt$$constant, $zero$$Register, $tmp$$XMMRegister, $ktmp$$KRegister);
10680 %}
10681 ins_pipe(pipe_slow);
10682 %}
10683
10684 instruct string_compareL(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10685 rax_RegI result, legRegD tmp1, rFlagsReg cr)
10686 %{
10687 predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
10688 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10689 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10690
10691 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10692 ins_encode %{
10693 __ string_compare($str1$$Register, $str2$$Register,
10694 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10695 $tmp1$$XMMRegister, StrIntrinsicNode::LL, knoreg);
10696 %}
10697 ins_pipe( pipe_slow );
10698 %}
10699
10700 instruct string_compareL_evex(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10701 rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
10702 %{
10703 predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
10704 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10705 effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10706
10707 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10708 ins_encode %{
10709 __ string_compare($str1$$Register, $str2$$Register,
10710 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10711 $tmp1$$XMMRegister, StrIntrinsicNode::LL, $ktmp$$KRegister);
10712 %}
10713 ins_pipe( pipe_slow );
10714 %}
10715
10716 instruct string_compareU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10717 rax_RegI result, legRegD tmp1, rFlagsReg cr)
10718 %{
10719 predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
10720 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10721 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10722
10723 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10724 ins_encode %{
10725 __ string_compare($str1$$Register, $str2$$Register,
10726 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10727 $tmp1$$XMMRegister, StrIntrinsicNode::UU, knoreg);
10728 %}
10729 ins_pipe( pipe_slow );
10730 %}
10731
10732 instruct string_compareU_evex(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10733 rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
10734 %{
10735 predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
10736 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10737 effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10738
10739 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10740 ins_encode %{
10741 __ string_compare($str1$$Register, $str2$$Register,
10742 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10743 $tmp1$$XMMRegister, StrIntrinsicNode::UU, $ktmp$$KRegister);
10744 %}
10745 ins_pipe( pipe_slow );
10746 %}
10747
10748 instruct string_compareLU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10749 rax_RegI result, legRegD tmp1, rFlagsReg cr)
10750 %{
10751 predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
10752 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10753 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10754
10755 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10756 ins_encode %{
10757 __ string_compare($str1$$Register, $str2$$Register,
10758 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10759 $tmp1$$XMMRegister, StrIntrinsicNode::LU, knoreg);
10760 %}
10761 ins_pipe( pipe_slow );
10762 %}
10763
10764 instruct string_compareLU_evex(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10765 rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
10766 %{
10767 predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
10768 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10769 effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10770
10771 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10772 ins_encode %{
10773 __ string_compare($str1$$Register, $str2$$Register,
10774 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10775 $tmp1$$XMMRegister, StrIntrinsicNode::LU, $ktmp$$KRegister);
10776 %}
10777 ins_pipe( pipe_slow );
10778 %}
10779
10780 instruct string_compareUL(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
10781 rax_RegI result, legRegD tmp1, rFlagsReg cr)
10782 %{
10783 predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
10784 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10785 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10786
10787 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10788 ins_encode %{
10789 __ string_compare($str2$$Register, $str1$$Register,
10790 $cnt2$$Register, $cnt1$$Register, $result$$Register,
10791 $tmp1$$XMMRegister, StrIntrinsicNode::UL, knoreg);
10792 %}
10793 ins_pipe( pipe_slow );
10794 %}
10795
10796 instruct string_compareUL_evex(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
10797 rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
10798 %{
10799 predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
10800 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10801 effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10802
10803 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10804 ins_encode %{
10805 __ string_compare($str2$$Register, $str1$$Register,
10806 $cnt2$$Register, $cnt1$$Register, $result$$Register,
10807 $tmp1$$XMMRegister, StrIntrinsicNode::UL, $ktmp$$KRegister);
10808 %}
10809 ins_pipe( pipe_slow );
10810 %}
10811
10812 // fast search of substring with known size.
10813 instruct string_indexof_conL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
10814 rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
10815 %{
10816 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
10817 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10818 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
10819
10820 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
10821 ins_encode %{
10822 int icnt2 = (int)$int_cnt2$$constant;
10823 if (icnt2 >= 16) {
10824 // IndexOf for constant substrings with size >= 16 elements
10825 // which don't need to be loaded through stack.
10826 __ string_indexofC8($str1$$Register, $str2$$Register,
10827 $cnt1$$Register, $cnt2$$Register,
10828 icnt2, $result$$Register,
10829 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
10830 } else {
10831 // Small strings are loaded through stack if they cross page boundary.
10832 __ string_indexof($str1$$Register, $str2$$Register,
10833 $cnt1$$Register, $cnt2$$Register,
10834 icnt2, $result$$Register,
10835 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
10836 }
10837 %}
10838 ins_pipe( pipe_slow );
10839 %}
10840
10841 // fast search of substring with known size.
10842 instruct string_indexof_conU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
10843 rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
10844 %{
10845 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
10846 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10847 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
10848
10849 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
10850 ins_encode %{
10851 int icnt2 = (int)$int_cnt2$$constant;
10852 if (icnt2 >= 8) {
10853 // IndexOf for constant substrings with size >= 8 elements
10854 // which don't need to be loaded through stack.
10855 __ string_indexofC8($str1$$Register, $str2$$Register,
10856 $cnt1$$Register, $cnt2$$Register,
10857 icnt2, $result$$Register,
10858 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
10859 } else {
10860 // Small strings are loaded through stack if they cross page boundary.
10861 __ string_indexof($str1$$Register, $str2$$Register,
10862 $cnt1$$Register, $cnt2$$Register,
10863 icnt2, $result$$Register,
10864 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
10865 }
10866 %}
10867 ins_pipe( pipe_slow );
10868 %}
10869
10870 // fast search of substring with known size.
10871 instruct string_indexof_conUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
10872 rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
10873 %{
10874 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
10875 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10876 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
10877
10878 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
10879 ins_encode %{
10880 int icnt2 = (int)$int_cnt2$$constant;
10881 if (icnt2 >= 8) {
10882 // IndexOf for constant substrings with size >= 8 elements
10883 // which don't need to be loaded through stack.
10884 __ string_indexofC8($str1$$Register, $str2$$Register,
10885 $cnt1$$Register, $cnt2$$Register,
10886 icnt2, $result$$Register,
10887 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
10888 } else {
10889 // Small strings are loaded through stack if they cross page boundary.
10890 __ string_indexof($str1$$Register, $str2$$Register,
10891 $cnt1$$Register, $cnt2$$Register,
10892 icnt2, $result$$Register,
10893 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
10894 }
10895 %}
10896 ins_pipe( pipe_slow );
10897 %}
10898
10899 instruct string_indexofL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
10900 rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
10901 %{
10902 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
10903 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10904 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
10905
10906 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
10907 ins_encode %{
10908 __ string_indexof($str1$$Register, $str2$$Register,
10909 $cnt1$$Register, $cnt2$$Register,
10910 (-1), $result$$Register,
10911 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
10912 %}
10913 ins_pipe( pipe_slow );
10914 %}
10915
10916 instruct string_indexofU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
10917 rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
10918 %{
10919 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
10920 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10921 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
10922
10923 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
10924 ins_encode %{
10925 __ string_indexof($str1$$Register, $str2$$Register,
10926 $cnt1$$Register, $cnt2$$Register,
10927 (-1), $result$$Register,
10928 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
10929 %}
10930 ins_pipe( pipe_slow );
10931 %}
10932
10933 instruct string_indexofUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
10934 rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
10935 %{
10936 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
10937 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10938 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
10939
10940 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
10941 ins_encode %{
10942 __ string_indexof($str1$$Register, $str2$$Register,
10943 $cnt1$$Register, $cnt2$$Register,
10944 (-1), $result$$Register,
10945 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
10946 %}
10947 ins_pipe( pipe_slow );
10948 %}
10949
10950 instruct string_indexof_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
10951 rbx_RegI result, legRegD tmp_vec1, legRegD tmp_vec2, legRegD tmp_vec3, rcx_RegI tmp, rFlagsReg cr)
10952 %{
10953 predicate(UseSSE42Intrinsics && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U));
10954 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10955 effect(TEMP tmp_vec1, TEMP tmp_vec2, TEMP tmp_vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
10956 format %{ "StringUTF16 IndexOf char[] $str1,$cnt1,$ch -> $result // KILL all" %}
10957 ins_encode %{
10958 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
10959 $tmp_vec1$$XMMRegister, $tmp_vec2$$XMMRegister, $tmp_vec3$$XMMRegister, $tmp$$Register);
10960 %}
10961 ins_pipe( pipe_slow );
10962 %}
10963
10964 instruct stringL_indexof_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
10965 rbx_RegI result, legRegD tmp_vec1, legRegD tmp_vec2, legRegD tmp_vec3, rcx_RegI tmp, rFlagsReg cr)
10966 %{
10967 predicate(UseSSE42Intrinsics && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L));
10968 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10969 effect(TEMP tmp_vec1, TEMP tmp_vec2, TEMP tmp_vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
10970 format %{ "StringLatin1 IndexOf char[] $str1,$cnt1,$ch -> $result // KILL all" %}
10971 ins_encode %{
10972 __ stringL_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
10973 $tmp_vec1$$XMMRegister, $tmp_vec2$$XMMRegister, $tmp_vec3$$XMMRegister, $tmp$$Register);
10974 %}
10975 ins_pipe( pipe_slow );
10976 %}
10977
10978 // fast string equals
10979 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
10980 legRegD tmp1, legRegD tmp2, rbx_RegI tmp3, rFlagsReg cr)
10981 %{
10982 predicate(!VM_Version::supports_avx512vlbw());
10983 match(Set result (StrEquals (Binary str1 str2) cnt));
10984 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
10985
10986 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
10987 ins_encode %{
10988 __ arrays_equals(false, $str1$$Register, $str2$$Register,
10989 $cnt$$Register, $result$$Register, $tmp3$$Register,
10990 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, knoreg);
10991 %}
10992 ins_pipe( pipe_slow );
10993 %}
10994
10995 instruct string_equals_evex(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
10996 legRegD tmp1, legRegD tmp2, kReg ktmp, rbx_RegI tmp3, rFlagsReg cr)
10997 %{
10998 predicate(VM_Version::supports_avx512vlbw());
10999 match(Set result (StrEquals (Binary str1 str2) cnt));
11000 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11001
11002 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11003 ins_encode %{
11004 __ arrays_equals(false, $str1$$Register, $str2$$Register,
11005 $cnt$$Register, $result$$Register, $tmp3$$Register,
11006 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, $ktmp$$KRegister);
11007 %}
11008 ins_pipe( pipe_slow );
11009 %}
11010
11011 // fast array equals
11012 instruct array_equalsB(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11013 legRegD tmp1, legRegD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11014 %{
11015 predicate(!VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
11016 match(Set result (AryEq ary1 ary2));
11017 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11018
11019 format %{ "Array Equals byte[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11020 ins_encode %{
11021 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11022 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11023 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, knoreg);
11024 %}
11025 ins_pipe( pipe_slow );
11026 %}
11027
11028 instruct array_equalsB_evex(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11029 legRegD tmp1, legRegD tmp2, kReg ktmp, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11030 %{
11031 predicate(VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
11032 match(Set result (AryEq ary1 ary2));
11033 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11034
11035 format %{ "Array Equals byte[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11036 ins_encode %{
11037 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11038 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11039 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, $ktmp$$KRegister);
11040 %}
11041 ins_pipe( pipe_slow );
11042 %}
11043
11044 instruct array_equalsC(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11045 legRegD tmp1, legRegD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11046 %{
11047 predicate(!VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
11048 match(Set result (AryEq ary1 ary2));
11049 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11050
11051 format %{ "Array Equals char[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11052 ins_encode %{
11053 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11054 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11055 $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */, knoreg);
11056 %}
11057 ins_pipe( pipe_slow );
11058 %}
11059
11060 instruct array_equalsC_evex(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11061 legRegD tmp1, legRegD tmp2, kReg ktmp, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11062 %{
11063 predicate(VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
11064 match(Set result (AryEq ary1 ary2));
11065 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11066
11067 format %{ "Array Equals char[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11068 ins_encode %{
11069 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11070 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11071 $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */, $ktmp$$KRegister);
11072 %}
11073 ins_pipe( pipe_slow );
11074 %}
11075
11076 instruct arrays_hashcode(rdi_RegP ary1, rdx_RegI cnt1, rbx_RegI result, immU8 basic_type,
11077 legRegD tmp_vec1, legRegD tmp_vec2, legRegD tmp_vec3, legRegD tmp_vec4,
11078 legRegD tmp_vec5, legRegD tmp_vec6, legRegD tmp_vec7, legRegD tmp_vec8,
11079 legRegD tmp_vec9, legRegD tmp_vec10, legRegD tmp_vec11, legRegD tmp_vec12,
11080 legRegD tmp_vec13, rRegI tmp1, rRegI tmp2, rRegI tmp3, rFlagsReg cr)
11081 %{
11082 predicate(UseAVX >= 2);
11083 match(Set result (VectorizedHashCode (Binary ary1 cnt1) (Binary result basic_type)));
11084 effect(TEMP tmp_vec1, TEMP tmp_vec2, TEMP tmp_vec3, TEMP tmp_vec4, TEMP tmp_vec5, TEMP tmp_vec6,
11085 TEMP tmp_vec7, TEMP tmp_vec8, TEMP tmp_vec9, TEMP tmp_vec10, TEMP tmp_vec11, TEMP tmp_vec12,
11086 TEMP tmp_vec13, TEMP tmp1, TEMP tmp2, TEMP tmp3, USE_KILL ary1, USE_KILL cnt1,
11087 USE basic_type, KILL cr);
11088
11089 format %{ "Array HashCode array[] $ary1,$cnt1,$result,$basic_type -> $result // KILL all" %}
11090 ins_encode %{
11091 __ arrays_hashcode($ary1$$Register, $cnt1$$Register, $result$$Register,
11092 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11093 $tmp_vec1$$XMMRegister, $tmp_vec2$$XMMRegister, $tmp_vec3$$XMMRegister,
11094 $tmp_vec4$$XMMRegister, $tmp_vec5$$XMMRegister, $tmp_vec6$$XMMRegister,
11095 $tmp_vec7$$XMMRegister, $tmp_vec8$$XMMRegister, $tmp_vec9$$XMMRegister,
11096 $tmp_vec10$$XMMRegister, $tmp_vec11$$XMMRegister, $tmp_vec12$$XMMRegister,
11097 $tmp_vec13$$XMMRegister, (BasicType)$basic_type$$constant);
11098 %}
11099 ins_pipe( pipe_slow );
11100 %}
11101
11102 instruct count_positives(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
11103 legRegD tmp1, legRegD tmp2, rbx_RegI tmp3, rFlagsReg cr,)
11104 %{
11105 predicate(!VM_Version::supports_avx512vlbw() || !VM_Version::supports_bmi2());
11106 match(Set result (CountPositives ary1 len));
11107 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
11108
11109 format %{ "countPositives byte[] $ary1,$len -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11110 ins_encode %{
11111 __ count_positives($ary1$$Register, $len$$Register,
11112 $result$$Register, $tmp3$$Register,
11113 $tmp1$$XMMRegister, $tmp2$$XMMRegister, knoreg, knoreg);
11114 %}
11115 ins_pipe( pipe_slow );
11116 %}
11117
11118 instruct count_positives_evex(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
11119 legRegD tmp1, legRegD tmp2, kReg ktmp1, kReg ktmp2, rbx_RegI tmp3, rFlagsReg cr,)
11120 %{
11121 predicate(VM_Version::supports_avx512vlbw() && VM_Version::supports_bmi2());
11122 match(Set result (CountPositives ary1 len));
11123 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp1, TEMP ktmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
11124
11125 format %{ "countPositives byte[] $ary1,$len -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11126 ins_encode %{
11127 __ count_positives($ary1$$Register, $len$$Register,
11128 $result$$Register, $tmp3$$Register,
11129 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $ktmp1$$KRegister, $ktmp2$$KRegister);
11130 %}
11131 ins_pipe( pipe_slow );
11132 %}
11133
11134 // fast char[] to byte[] compression
11135 instruct string_compress(rsi_RegP src, rdi_RegP dst, rdx_RegI len, legRegD tmp1, legRegD tmp2, legRegD tmp3,
11136 legRegD tmp4, rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11137 predicate(!VM_Version::supports_avx512vlbw() || !VM_Version::supports_bmi2());
11138 match(Set result (StrCompressedCopy src (Binary dst len)));
11139 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst,
11140 USE_KILL len, KILL tmp5, KILL cr);
11141
11142 format %{ "String Compress $src,$dst -> $result // KILL RAX, RCX, RDX" %}
11143 ins_encode %{
11144 __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
11145 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11146 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register,
11147 knoreg, knoreg);
11148 %}
11149 ins_pipe( pipe_slow );
11150 %}
11151
11152 instruct string_compress_evex(rsi_RegP src, rdi_RegP dst, rdx_RegI len, legRegD tmp1, legRegD tmp2, legRegD tmp3,
11153 legRegD tmp4, kReg ktmp1, kReg ktmp2, rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11154 predicate(VM_Version::supports_avx512vlbw() && VM_Version::supports_bmi2());
11155 match(Set result (StrCompressedCopy src (Binary dst len)));
11156 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP ktmp1, TEMP ktmp2, USE_KILL src, USE_KILL dst,
11157 USE_KILL len, KILL tmp5, KILL cr);
11158
11159 format %{ "String Compress $src,$dst -> $result // KILL RAX, RCX, RDX" %}
11160 ins_encode %{
11161 __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
11162 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11163 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register,
11164 $ktmp1$$KRegister, $ktmp2$$KRegister);
11165 %}
11166 ins_pipe( pipe_slow );
11167 %}
11168 // fast byte[] to char[] inflation
11169 instruct string_inflate(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11170 legRegD tmp1, rcx_RegI tmp2, rFlagsReg cr) %{
11171 predicate(!VM_Version::supports_avx512vlbw() || !VM_Version::supports_bmi2());
11172 match(Set dummy (StrInflatedCopy src (Binary dst len)));
11173 effect(TEMP tmp1, TEMP tmp2, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
11174
11175 format %{ "String Inflate $src,$dst // KILL $tmp1, $tmp2" %}
11176 ins_encode %{
11177 __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
11178 $tmp1$$XMMRegister, $tmp2$$Register, knoreg);
11179 %}
11180 ins_pipe( pipe_slow );
11181 %}
11182
11183 instruct string_inflate_evex(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11184 legRegD tmp1, kReg ktmp, rcx_RegI tmp2, rFlagsReg cr) %{
11185 predicate(VM_Version::supports_avx512vlbw() && VM_Version::supports_bmi2());
11186 match(Set dummy (StrInflatedCopy src (Binary dst len)));
11187 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
11188
11189 format %{ "String Inflate $src,$dst // KILL $tmp1, $tmp2" %}
11190 ins_encode %{
11191 __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
11192 $tmp1$$XMMRegister, $tmp2$$Register, $ktmp$$KRegister);
11193 %}
11194 ins_pipe( pipe_slow );
11195 %}
11196
11197 // encode char[] to byte[] in ISO_8859_1
11198 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11199 legRegD tmp1, legRegD tmp2, legRegD tmp3, legRegD tmp4,
11200 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11201 predicate(!((EncodeISOArrayNode*)n)->is_ascii());
11202 match(Set result (EncodeISOArray src (Binary dst len)));
11203 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11204
11205 format %{ "Encode iso array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
11206 ins_encode %{
11207 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11208 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11209 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register, false);
11210 %}
11211 ins_pipe( pipe_slow );
11212 %}
11213
11214 // encode char[] to byte[] in ASCII
11215 instruct encode_ascii_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11216 legRegD tmp1, legRegD tmp2, legRegD tmp3, legRegD tmp4,
11217 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11218 predicate(((EncodeISOArrayNode*)n)->is_ascii());
11219 match(Set result (EncodeISOArray src (Binary dst len)));
11220 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11221
11222 format %{ "Encode ascii array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
11223 ins_encode %{
11224 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11225 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11226 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register, true);
11227 %}
11228 ins_pipe( pipe_slow );
11229 %}
11230
11231 //----------Overflow Math Instructions-----------------------------------------
11232
11233 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11234 %{
11235 match(Set cr (OverflowAddI op1 op2));
11236 effect(DEF cr, USE_KILL op1, USE op2);
11237
11238 format %{ "addl $op1, $op2\t# overflow check int" %}
11239
11240 ins_encode %{
11241 __ addl($op1$$Register, $op2$$Register);
11242 %}
11243 ins_pipe(ialu_reg_reg);
11244 %}
11245
11246 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
11247 %{
11248 match(Set cr (OverflowAddI op1 op2));
11249 effect(DEF cr, USE_KILL op1, USE op2);
11250
11251 format %{ "addl $op1, $op2\t# overflow check int" %}
11252
11253 ins_encode %{
11254 __ addl($op1$$Register, $op2$$constant);
11255 %}
11256 ins_pipe(ialu_reg_reg);
11257 %}
11258
11259 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11260 %{
11261 match(Set cr (OverflowAddL op1 op2));
11262 effect(DEF cr, USE_KILL op1, USE op2);
11263
11264 format %{ "addq $op1, $op2\t# overflow check long" %}
11265 ins_encode %{
11266 __ addq($op1$$Register, $op2$$Register);
11267 %}
11268 ins_pipe(ialu_reg_reg);
11269 %}
11270
11271 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
11272 %{
11273 match(Set cr (OverflowAddL op1 op2));
11274 effect(DEF cr, USE_KILL op1, USE op2);
11275
11276 format %{ "addq $op1, $op2\t# overflow check long" %}
11277 ins_encode %{
11278 __ addq($op1$$Register, $op2$$constant);
11279 %}
11280 ins_pipe(ialu_reg_reg);
11281 %}
11282
11283 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11284 %{
11285 match(Set cr (OverflowSubI op1 op2));
11286
11287 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11288 ins_encode %{
11289 __ cmpl($op1$$Register, $op2$$Register);
11290 %}
11291 ins_pipe(ialu_reg_reg);
11292 %}
11293
11294 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11295 %{
11296 match(Set cr (OverflowSubI op1 op2));
11297
11298 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11299 ins_encode %{
11300 __ cmpl($op1$$Register, $op2$$constant);
11301 %}
11302 ins_pipe(ialu_reg_reg);
11303 %}
11304
11305 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11306 %{
11307 match(Set cr (OverflowSubL op1 op2));
11308
11309 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11310 ins_encode %{
11311 __ cmpq($op1$$Register, $op2$$Register);
11312 %}
11313 ins_pipe(ialu_reg_reg);
11314 %}
11315
11316 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11317 %{
11318 match(Set cr (OverflowSubL op1 op2));
11319
11320 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11321 ins_encode %{
11322 __ cmpq($op1$$Register, $op2$$constant);
11323 %}
11324 ins_pipe(ialu_reg_reg);
11325 %}
11326
11327 instruct overflowNegI_rReg(rFlagsReg cr, immI_0 zero, rax_RegI op2)
11328 %{
11329 match(Set cr (OverflowSubI zero op2));
11330 effect(DEF cr, USE_KILL op2);
11331
11332 format %{ "negl $op2\t# overflow check int" %}
11333 ins_encode %{
11334 __ negl($op2$$Register);
11335 %}
11336 ins_pipe(ialu_reg_reg);
11337 %}
11338
11339 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
11340 %{
11341 match(Set cr (OverflowSubL zero op2));
11342 effect(DEF cr, USE_KILL op2);
11343
11344 format %{ "negq $op2\t# overflow check long" %}
11345 ins_encode %{
11346 __ negq($op2$$Register);
11347 %}
11348 ins_pipe(ialu_reg_reg);
11349 %}
11350
11351 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11352 %{
11353 match(Set cr (OverflowMulI op1 op2));
11354 effect(DEF cr, USE_KILL op1, USE op2);
11355
11356 format %{ "imull $op1, $op2\t# overflow check int" %}
11357 ins_encode %{
11358 __ imull($op1$$Register, $op2$$Register);
11359 %}
11360 ins_pipe(ialu_reg_reg_alu0);
11361 %}
11362
11363 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
11364 %{
11365 match(Set cr (OverflowMulI op1 op2));
11366 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11367
11368 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %}
11369 ins_encode %{
11370 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
11371 %}
11372 ins_pipe(ialu_reg_reg_alu0);
11373 %}
11374
11375 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11376 %{
11377 match(Set cr (OverflowMulL op1 op2));
11378 effect(DEF cr, USE_KILL op1, USE op2);
11379
11380 format %{ "imulq $op1, $op2\t# overflow check long" %}
11381 ins_encode %{
11382 __ imulq($op1$$Register, $op2$$Register);
11383 %}
11384 ins_pipe(ialu_reg_reg_alu0);
11385 %}
11386
11387 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
11388 %{
11389 match(Set cr (OverflowMulL op1 op2));
11390 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11391
11392 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %}
11393 ins_encode %{
11394 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
11395 %}
11396 ins_pipe(ialu_reg_reg_alu0);
11397 %}
11398
11399
11400 //----------Control Flow Instructions------------------------------------------
11401 // Signed compare Instructions
11402
11403 // XXX more variants!!
11404 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11405 %{
11406 match(Set cr (CmpI op1 op2));
11407 effect(DEF cr, USE op1, USE op2);
11408
11409 format %{ "cmpl $op1, $op2" %}
11410 ins_encode %{
11411 __ cmpl($op1$$Register, $op2$$Register);
11412 %}
11413 ins_pipe(ialu_cr_reg_reg);
11414 %}
11415
11416 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11417 %{
11418 match(Set cr (CmpI op1 op2));
11419
11420 format %{ "cmpl $op1, $op2" %}
11421 ins_encode %{
11422 __ cmpl($op1$$Register, $op2$$constant);
11423 %}
11424 ins_pipe(ialu_cr_reg_imm);
11425 %}
11426
11427 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
11428 %{
11429 match(Set cr (CmpI op1 (LoadI op2)));
11430
11431 ins_cost(500); // XXX
11432 format %{ "cmpl $op1, $op2" %}
11433 ins_encode %{
11434 __ cmpl($op1$$Register, $op2$$Address);
11435 %}
11436 ins_pipe(ialu_cr_reg_mem);
11437 %}
11438
11439 instruct testI_reg(rFlagsReg cr, rRegI src, immI_0 zero)
11440 %{
11441 match(Set cr (CmpI src zero));
11442
11443 format %{ "testl $src, $src" %}
11444 ins_encode %{
11445 __ testl($src$$Register, $src$$Register);
11446 %}
11447 ins_pipe(ialu_cr_reg_imm);
11448 %}
11449
11450 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI_0 zero)
11451 %{
11452 match(Set cr (CmpI (AndI src con) zero));
11453
11454 format %{ "testl $src, $con" %}
11455 ins_encode %{
11456 __ testl($src$$Register, $con$$constant);
11457 %}
11458 ins_pipe(ialu_cr_reg_imm);
11459 %}
11460
11461 instruct testI_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2, immI_0 zero)
11462 %{
11463 match(Set cr (CmpI (AndI src1 src2) zero));
11464
11465 format %{ "testl $src1, $src2" %}
11466 ins_encode %{
11467 __ testl($src1$$Register, $src2$$Register);
11468 %}
11469 ins_pipe(ialu_cr_reg_imm);
11470 %}
11471
11472 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI_0 zero)
11473 %{
11474 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
11475
11476 format %{ "testl $src, $mem" %}
11477 ins_encode %{
11478 __ testl($src$$Register, $mem$$Address);
11479 %}
11480 ins_pipe(ialu_cr_reg_mem);
11481 %}
11482
11483 // Unsigned compare Instructions; really, same as signed except they
11484 // produce an rFlagsRegU instead of rFlagsReg.
11485 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
11486 %{
11487 match(Set cr (CmpU op1 op2));
11488
11489 format %{ "cmpl $op1, $op2\t# unsigned" %}
11490 ins_encode %{
11491 __ cmpl($op1$$Register, $op2$$Register);
11492 %}
11493 ins_pipe(ialu_cr_reg_reg);
11494 %}
11495
11496 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
11497 %{
11498 match(Set cr (CmpU op1 op2));
11499
11500 format %{ "cmpl $op1, $op2\t# unsigned" %}
11501 ins_encode %{
11502 __ cmpl($op1$$Register, $op2$$constant);
11503 %}
11504 ins_pipe(ialu_cr_reg_imm);
11505 %}
11506
11507 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
11508 %{
11509 match(Set cr (CmpU op1 (LoadI op2)));
11510
11511 ins_cost(500); // XXX
11512 format %{ "cmpl $op1, $op2\t# unsigned" %}
11513 ins_encode %{
11514 __ cmpl($op1$$Register, $op2$$Address);
11515 %}
11516 ins_pipe(ialu_cr_reg_mem);
11517 %}
11518
11519 instruct testU_reg(rFlagsRegU cr, rRegI src, immI_0 zero)
11520 %{
11521 match(Set cr (CmpU src zero));
11522
11523 format %{ "testl $src, $src\t# unsigned" %}
11524 ins_encode %{
11525 __ testl($src$$Register, $src$$Register);
11526 %}
11527 ins_pipe(ialu_cr_reg_imm);
11528 %}
11529
11530 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
11531 %{
11532 match(Set cr (CmpP op1 op2));
11533
11534 format %{ "cmpq $op1, $op2\t# ptr" %}
11535 ins_encode %{
11536 __ cmpq($op1$$Register, $op2$$Register);
11537 %}
11538 ins_pipe(ialu_cr_reg_reg);
11539 %}
11540
11541 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
11542 %{
11543 match(Set cr (CmpP op1 (LoadP op2)));
11544 predicate(n->in(2)->as_Load()->barrier_data() == 0);
11545
11546 ins_cost(500); // XXX
11547 format %{ "cmpq $op1, $op2\t# ptr" %}
11548 ins_encode %{
11549 __ cmpq($op1$$Register, $op2$$Address);
11550 %}
11551 ins_pipe(ialu_cr_reg_mem);
11552 %}
11553
11554 // XXX this is generalized by compP_rReg_mem???
11555 // Compare raw pointer (used in out-of-heap check).
11556 // Only works because non-oop pointers must be raw pointers
11557 // and raw pointers have no anti-dependencies.
11558 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
11559 %{
11560 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none &&
11561 n->in(2)->as_Load()->barrier_data() == 0);
11562 match(Set cr (CmpP op1 (LoadP op2)));
11563
11564 format %{ "cmpq $op1, $op2\t# raw ptr" %}
11565 ins_encode %{
11566 __ cmpq($op1$$Register, $op2$$Address);
11567 %}
11568 ins_pipe(ialu_cr_reg_mem);
11569 %}
11570
11571 // This will generate a signed flags result. This should be OK since
11572 // any compare to a zero should be eq/neq.
11573 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
11574 %{
11575 match(Set cr (CmpP src zero));
11576
11577 format %{ "testq $src, $src\t# ptr" %}
11578 ins_encode %{
11579 __ testq($src$$Register, $src$$Register);
11580 %}
11581 ins_pipe(ialu_cr_reg_imm);
11582 %}
11583
11584 // This will generate a signed flags result. This should be OK since
11585 // any compare to a zero should be eq/neq.
11586 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
11587 %{
11588 predicate((!UseCompressedOops || (CompressedOops::base() != nullptr)) &&
11589 n->in(1)->as_Load()->barrier_data() == 0);
11590 match(Set cr (CmpP (LoadP op) zero));
11591
11592 ins_cost(500); // XXX
11593 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
11594 ins_encode %{
11595 __ testq($op$$Address, 0xFFFFFFFF);
11596 %}
11597 ins_pipe(ialu_cr_reg_imm);
11598 %}
11599
11600 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
11601 %{
11602 predicate(UseCompressedOops && (CompressedOops::base() == nullptr) &&
11603 n->in(1)->as_Load()->barrier_data() == 0);
11604 match(Set cr (CmpP (LoadP mem) zero));
11605
11606 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
11607 ins_encode %{
11608 __ cmpq(r12, $mem$$Address);
11609 %}
11610 ins_pipe(ialu_cr_reg_mem);
11611 %}
11612
11613 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
11614 %{
11615 match(Set cr (CmpN op1 op2));
11616
11617 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11618 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
11619 ins_pipe(ialu_cr_reg_reg);
11620 %}
11621
11622 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
11623 %{
11624 predicate(n->in(2)->as_Load()->barrier_data() == 0);
11625 match(Set cr (CmpN src (LoadN mem)));
11626
11627 format %{ "cmpl $src, $mem\t# compressed ptr" %}
11628 ins_encode %{
11629 __ cmpl($src$$Register, $mem$$Address);
11630 %}
11631 ins_pipe(ialu_cr_reg_mem);
11632 %}
11633
11634 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
11635 match(Set cr (CmpN op1 op2));
11636
11637 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11638 ins_encode %{
11639 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
11640 %}
11641 ins_pipe(ialu_cr_reg_imm);
11642 %}
11643
11644 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
11645 %{
11646 predicate(n->in(2)->as_Load()->barrier_data() == 0);
11647 match(Set cr (CmpN src (LoadN mem)));
11648
11649 format %{ "cmpl $mem, $src\t# compressed ptr" %}
11650 ins_encode %{
11651 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
11652 %}
11653 ins_pipe(ialu_cr_reg_mem);
11654 %}
11655
11656 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
11657 match(Set cr (CmpN op1 op2));
11658
11659 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %}
11660 ins_encode %{
11661 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
11662 %}
11663 ins_pipe(ialu_cr_reg_imm);
11664 %}
11665
11666 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
11667 %{
11668 match(Set cr (CmpN src (LoadNKlass mem)));
11669
11670 format %{ "cmpl $mem, $src\t# compressed klass ptr" %}
11671 ins_encode %{
11672 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
11673 %}
11674 ins_pipe(ialu_cr_reg_mem);
11675 %}
11676
11677 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
11678 match(Set cr (CmpN src zero));
11679
11680 format %{ "testl $src, $src\t# compressed ptr" %}
11681 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
11682 ins_pipe(ialu_cr_reg_imm);
11683 %}
11684
11685 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
11686 %{
11687 predicate(CompressedOops::base() != nullptr &&
11688 n->in(1)->as_Load()->barrier_data() == 0);
11689 match(Set cr (CmpN (LoadN mem) zero));
11690
11691 ins_cost(500); // XXX
11692 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
11693 ins_encode %{
11694 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
11695 %}
11696 ins_pipe(ialu_cr_reg_mem);
11697 %}
11698
11699 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
11700 %{
11701 predicate(CompressedOops::base() == nullptr &&
11702 n->in(1)->as_Load()->barrier_data() == 0);
11703 match(Set cr (CmpN (LoadN mem) zero));
11704
11705 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
11706 ins_encode %{
11707 __ cmpl(r12, $mem$$Address);
11708 %}
11709 ins_pipe(ialu_cr_reg_mem);
11710 %}
11711
11712 // Yanked all unsigned pointer compare operations.
11713 // Pointer compares are done with CmpP which is already unsigned.
11714
11715 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11716 %{
11717 match(Set cr (CmpL op1 op2));
11718
11719 format %{ "cmpq $op1, $op2" %}
11720 ins_encode %{
11721 __ cmpq($op1$$Register, $op2$$Register);
11722 %}
11723 ins_pipe(ialu_cr_reg_reg);
11724 %}
11725
11726 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11727 %{
11728 match(Set cr (CmpL op1 op2));
11729
11730 format %{ "cmpq $op1, $op2" %}
11731 ins_encode %{
11732 __ cmpq($op1$$Register, $op2$$constant);
11733 %}
11734 ins_pipe(ialu_cr_reg_imm);
11735 %}
11736
11737 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
11738 %{
11739 match(Set cr (CmpL op1 (LoadL op2)));
11740
11741 format %{ "cmpq $op1, $op2" %}
11742 ins_encode %{
11743 __ cmpq($op1$$Register, $op2$$Address);
11744 %}
11745 ins_pipe(ialu_cr_reg_mem);
11746 %}
11747
11748 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
11749 %{
11750 match(Set cr (CmpL src zero));
11751
11752 format %{ "testq $src, $src" %}
11753 ins_encode %{
11754 __ testq($src$$Register, $src$$Register);
11755 %}
11756 ins_pipe(ialu_cr_reg_imm);
11757 %}
11758
11759 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
11760 %{
11761 match(Set cr (CmpL (AndL src con) zero));
11762
11763 format %{ "testq $src, $con\t# long" %}
11764 ins_encode %{
11765 __ testq($src$$Register, $con$$constant);
11766 %}
11767 ins_pipe(ialu_cr_reg_imm);
11768 %}
11769
11770 instruct testL_reg_reg(rFlagsReg cr, rRegL src1, rRegL src2, immL0 zero)
11771 %{
11772 match(Set cr (CmpL (AndL src1 src2) zero));
11773
11774 format %{ "testq $src1, $src2\t# long" %}
11775 ins_encode %{
11776 __ testq($src1$$Register, $src2$$Register);
11777 %}
11778 ins_pipe(ialu_cr_reg_imm);
11779 %}
11780
11781 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
11782 %{
11783 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
11784
11785 format %{ "testq $src, $mem" %}
11786 ins_encode %{
11787 __ testq($src$$Register, $mem$$Address);
11788 %}
11789 ins_pipe(ialu_cr_reg_mem);
11790 %}
11791
11792 instruct testL_reg_mem2(rFlagsReg cr, rRegP src, memory mem, immL0 zero)
11793 %{
11794 match(Set cr (CmpL (AndL (CastP2X src) (LoadL mem)) zero));
11795
11796 format %{ "testq $src, $mem" %}
11797 ins_encode %{
11798 __ testq($src$$Register, $mem$$Address);
11799 %}
11800 ins_pipe(ialu_cr_reg_mem);
11801 %}
11802
11803 // Manifest a CmpU result in an integer register. Very painful.
11804 // This is the test to avoid.
11805 instruct cmpU3_reg_reg(rRegI dst, rRegI src1, rRegI src2, rFlagsReg flags)
11806 %{
11807 match(Set dst (CmpU3 src1 src2));
11808 effect(KILL flags);
11809
11810 ins_cost(275); // XXX
11811 format %{ "cmpl $src1, $src2\t# CmpL3\n\t"
11812 "movl $dst, -1\n\t"
11813 "jb,u done\n\t"
11814 "setcc $dst \t# emits setne + movzbl or setzune for APX"
11815 "done:" %}
11816 ins_encode %{
11817 Label done;
11818 __ cmpl($src1$$Register, $src2$$Register);
11819 __ movl($dst$$Register, -1);
11820 __ jccb(Assembler::below, done);
11821 __ setcc(Assembler::notZero, $dst$$Register);
11822 __ bind(done);
11823 %}
11824 ins_pipe(pipe_slow);
11825 %}
11826
11827 // Manifest a CmpL result in an integer register. Very painful.
11828 // This is the test to avoid.
11829 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
11830 %{
11831 match(Set dst (CmpL3 src1 src2));
11832 effect(KILL flags);
11833
11834 ins_cost(275); // XXX
11835 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
11836 "movl $dst, -1\n\t"
11837 "jl,s done\n\t"
11838 "setcc $dst \t# emits setne + movzbl or setzune for APX"
11839 "done:" %}
11840 ins_encode %{
11841 Label done;
11842 __ cmpq($src1$$Register, $src2$$Register);
11843 __ movl($dst$$Register, -1);
11844 __ jccb(Assembler::less, done);
11845 __ setcc(Assembler::notZero, $dst$$Register);
11846 __ bind(done);
11847 %}
11848 ins_pipe(pipe_slow);
11849 %}
11850
11851 // Manifest a CmpUL result in an integer register. Very painful.
11852 // This is the test to avoid.
11853 instruct cmpUL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
11854 %{
11855 match(Set dst (CmpUL3 src1 src2));
11856 effect(KILL flags);
11857
11858 ins_cost(275); // XXX
11859 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
11860 "movl $dst, -1\n\t"
11861 "jb,u done\n\t"
11862 "setcc $dst \t# emits setne + movzbl or setzune for APX"
11863 "done:" %}
11864 ins_encode %{
11865 Label done;
11866 __ cmpq($src1$$Register, $src2$$Register);
11867 __ movl($dst$$Register, -1);
11868 __ jccb(Assembler::below, done);
11869 __ setcc(Assembler::notZero, $dst$$Register);
11870 __ bind(done);
11871 %}
11872 ins_pipe(pipe_slow);
11873 %}
11874
11875 // Unsigned long compare Instructions; really, same as signed long except they
11876 // produce an rFlagsRegU instead of rFlagsReg.
11877 instruct compUL_rReg(rFlagsRegU cr, rRegL op1, rRegL op2)
11878 %{
11879 match(Set cr (CmpUL op1 op2));
11880
11881 format %{ "cmpq $op1, $op2\t# unsigned" %}
11882 ins_encode %{
11883 __ cmpq($op1$$Register, $op2$$Register);
11884 %}
11885 ins_pipe(ialu_cr_reg_reg);
11886 %}
11887
11888 instruct compUL_rReg_imm(rFlagsRegU cr, rRegL op1, immL32 op2)
11889 %{
11890 match(Set cr (CmpUL op1 op2));
11891
11892 format %{ "cmpq $op1, $op2\t# unsigned" %}
11893 ins_encode %{
11894 __ cmpq($op1$$Register, $op2$$constant);
11895 %}
11896 ins_pipe(ialu_cr_reg_imm);
11897 %}
11898
11899 instruct compUL_rReg_mem(rFlagsRegU cr, rRegL op1, memory op2)
11900 %{
11901 match(Set cr (CmpUL op1 (LoadL op2)));
11902
11903 format %{ "cmpq $op1, $op2\t# unsigned" %}
11904 ins_encode %{
11905 __ cmpq($op1$$Register, $op2$$Address);
11906 %}
11907 ins_pipe(ialu_cr_reg_mem);
11908 %}
11909
11910 instruct testUL_reg(rFlagsRegU cr, rRegL src, immL0 zero)
11911 %{
11912 match(Set cr (CmpUL src zero));
11913
11914 format %{ "testq $src, $src\t# unsigned" %}
11915 ins_encode %{
11916 __ testq($src$$Register, $src$$Register);
11917 %}
11918 ins_pipe(ialu_cr_reg_imm);
11919 %}
11920
11921 instruct compB_mem_imm(rFlagsReg cr, memory mem, immI8 imm)
11922 %{
11923 match(Set cr (CmpI (LoadB mem) imm));
11924
11925 ins_cost(125);
11926 format %{ "cmpb $mem, $imm" %}
11927 ins_encode %{ __ cmpb($mem$$Address, $imm$$constant); %}
11928 ins_pipe(ialu_cr_reg_mem);
11929 %}
11930
11931 instruct testUB_mem_imm(rFlagsReg cr, memory mem, immU7 imm, immI_0 zero)
11932 %{
11933 match(Set cr (CmpI (AndI (LoadUB mem) imm) zero));
11934
11935 ins_cost(125);
11936 format %{ "testb $mem, $imm\t# ubyte" %}
11937 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
11938 ins_pipe(ialu_cr_reg_mem);
11939 %}
11940
11941 instruct testB_mem_imm(rFlagsReg cr, memory mem, immI8 imm, immI_0 zero)
11942 %{
11943 match(Set cr (CmpI (AndI (LoadB mem) imm) zero));
11944
11945 ins_cost(125);
11946 format %{ "testb $mem, $imm\t# byte" %}
11947 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
11948 ins_pipe(ialu_cr_reg_mem);
11949 %}
11950
11951 //----------Max and Min--------------------------------------------------------
11952 // Min Instructions
11953
11954 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
11955 %{
11956 effect(USE_DEF dst, USE src, USE cr);
11957
11958 format %{ "cmovlgt $dst, $src\t# min" %}
11959 ins_encode %{
11960 __ cmovl(Assembler::greater, $dst$$Register, $src$$Register);
11961 %}
11962 ins_pipe(pipe_cmov_reg);
11963 %}
11964
11965
11966 instruct minI_rReg(rRegI dst, rRegI src)
11967 %{
11968 match(Set dst (MinI dst src));
11969
11970 ins_cost(200);
11971 expand %{
11972 rFlagsReg cr;
11973 compI_rReg(cr, dst, src);
11974 cmovI_reg_g(dst, src, cr);
11975 %}
11976 %}
11977
11978 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
11979 %{
11980 effect(USE_DEF dst, USE src, USE cr);
11981
11982 format %{ "cmovllt $dst, $src\t# max" %}
11983 ins_encode %{
11984 __ cmovl(Assembler::less, $dst$$Register, $src$$Register);
11985 %}
11986 ins_pipe(pipe_cmov_reg);
11987 %}
11988
11989
11990 instruct maxI_rReg(rRegI dst, rRegI src)
11991 %{
11992 match(Set dst (MaxI dst src));
11993
11994 ins_cost(200);
11995 expand %{
11996 rFlagsReg cr;
11997 compI_rReg(cr, dst, src);
11998 cmovI_reg_l(dst, src, cr);
11999 %}
12000 %}
12001
12002 // ============================================================================
12003 // Branch Instructions
12004
12005 // Jump Direct - Label defines a relative address from JMP+1
12006 instruct jmpDir(label labl)
12007 %{
12008 match(Goto);
12009 effect(USE labl);
12010
12011 ins_cost(300);
12012 format %{ "jmp $labl" %}
12013 size(5);
12014 ins_encode %{
12015 Label* L = $labl$$label;
12016 __ jmp(*L, false); // Always long jump
12017 %}
12018 ins_pipe(pipe_jmp);
12019 %}
12020
12021 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12022 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
12023 %{
12024 match(If cop cr);
12025 effect(USE labl);
12026
12027 ins_cost(300);
12028 format %{ "j$cop $labl" %}
12029 size(6);
12030 ins_encode %{
12031 Label* L = $labl$$label;
12032 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12033 %}
12034 ins_pipe(pipe_jcc);
12035 %}
12036
12037 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12038 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
12039 %{
12040 match(CountedLoopEnd cop cr);
12041 effect(USE labl);
12042
12043 ins_cost(300);
12044 format %{ "j$cop $labl\t# loop end" %}
12045 size(6);
12046 ins_encode %{
12047 Label* L = $labl$$label;
12048 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12049 %}
12050 ins_pipe(pipe_jcc);
12051 %}
12052
12053 // Jump Direct Conditional - using unsigned comparison
12054 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12055 match(If cop cmp);
12056 effect(USE labl);
12057
12058 ins_cost(300);
12059 format %{ "j$cop,u $labl" %}
12060 size(6);
12061 ins_encode %{
12062 Label* L = $labl$$label;
12063 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12064 %}
12065 ins_pipe(pipe_jcc);
12066 %}
12067
12068 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12069 match(If cop cmp);
12070 effect(USE labl);
12071
12072 ins_cost(200);
12073 format %{ "j$cop,u $labl" %}
12074 size(6);
12075 ins_encode %{
12076 Label* L = $labl$$label;
12077 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12078 %}
12079 ins_pipe(pipe_jcc);
12080 %}
12081
12082 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12083 match(If cop cmp);
12084 effect(USE labl);
12085
12086 ins_cost(200);
12087 format %{ $$template
12088 if ($cop$$cmpcode == Assembler::notEqual) {
12089 $$emit$$"jp,u $labl\n\t"
12090 $$emit$$"j$cop,u $labl"
12091 } else {
12092 $$emit$$"jp,u done\n\t"
12093 $$emit$$"j$cop,u $labl\n\t"
12094 $$emit$$"done:"
12095 }
12096 %}
12097 ins_encode %{
12098 Label* l = $labl$$label;
12099 if ($cop$$cmpcode == Assembler::notEqual) {
12100 __ jcc(Assembler::parity, *l, false);
12101 __ jcc(Assembler::notEqual, *l, false);
12102 } else if ($cop$$cmpcode == Assembler::equal) {
12103 Label done;
12104 __ jccb(Assembler::parity, done);
12105 __ jcc(Assembler::equal, *l, false);
12106 __ bind(done);
12107 } else {
12108 ShouldNotReachHere();
12109 }
12110 %}
12111 ins_pipe(pipe_jcc);
12112 %}
12113
12114 // ============================================================================
12115 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
12116 // superklass array for an instance of the superklass. Set a hidden
12117 // internal cache on a hit (cache is checked with exposed code in
12118 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
12119 // encoding ALSO sets flags.
12120
12121 instruct partialSubtypeCheck(rdi_RegP result,
12122 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12123 rFlagsReg cr)
12124 %{
12125 match(Set result (PartialSubtypeCheck sub super));
12126 predicate(!UseSecondarySupersTable);
12127 effect(KILL rcx, KILL cr);
12128
12129 ins_cost(1100); // slightly larger than the next version
12130 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12131 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12132 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12133 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
12134 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
12135 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12136 "xorq $result, $result\t\t Hit: rdi zero\n\t"
12137 "miss:\t" %}
12138
12139 ins_encode %{
12140 Label miss;
12141 // NB: Callers may assume that, when $result is a valid register,
12142 // check_klass_subtype_slow_path_linear sets it to a nonzero
12143 // value.
12144 __ check_klass_subtype_slow_path_linear($sub$$Register, $super$$Register,
12145 $rcx$$Register, $result$$Register,
12146 nullptr, &miss,
12147 /*set_cond_codes:*/ true);
12148 __ xorptr($result$$Register, $result$$Register);
12149 __ bind(miss);
12150 %}
12151
12152 ins_pipe(pipe_slow);
12153 %}
12154
12155 // ============================================================================
12156 // Two versions of hashtable-based partialSubtypeCheck, both used when
12157 // we need to search for a super class in the secondary supers array.
12158 // The first is used when we don't know _a priori_ the class being
12159 // searched for. The second, far more common, is used when we do know:
12160 // this is used for instanceof, checkcast, and any case where C2 can
12161 // determine it by constant propagation.
12162
12163 instruct partialSubtypeCheckVarSuper(rsi_RegP sub, rax_RegP super, rdi_RegP result,
12164 rdx_RegL temp1, rcx_RegL temp2, rbx_RegP temp3, r11_RegL temp4,
12165 rFlagsReg cr)
12166 %{
12167 match(Set result (PartialSubtypeCheck sub super));
12168 predicate(UseSecondarySupersTable);
12169 effect(KILL cr, TEMP temp1, TEMP temp2, TEMP temp3, TEMP temp4);
12170
12171 ins_cost(1000);
12172 format %{ "partialSubtypeCheck $result, $sub, $super" %}
12173
12174 ins_encode %{
12175 __ lookup_secondary_supers_table_var($sub$$Register, $super$$Register, $temp1$$Register, $temp2$$Register,
12176 $temp3$$Register, $temp4$$Register, $result$$Register);
12177 %}
12178
12179 ins_pipe(pipe_slow);
12180 %}
12181
12182 instruct partialSubtypeCheckConstSuper(rsi_RegP sub, rax_RegP super_reg, immP super_con, rdi_RegP result,
12183 rdx_RegL temp1, rcx_RegL temp2, rbx_RegP temp3, r11_RegL temp4,
12184 rFlagsReg cr)
12185 %{
12186 match(Set result (PartialSubtypeCheck sub (Binary super_reg super_con)));
12187 predicate(UseSecondarySupersTable);
12188 effect(KILL cr, TEMP temp1, TEMP temp2, TEMP temp3, TEMP temp4);
12189
12190 ins_cost(700); // smaller than the next version
12191 format %{ "partialSubtypeCheck $result, $sub, $super_reg, $super_con" %}
12192
12193 ins_encode %{
12194 u1 super_klass_slot = ((Klass*)$super_con$$constant)->hash_slot();
12195 if (InlineSecondarySupersTest) {
12196 __ lookup_secondary_supers_table_const($sub$$Register, $super_reg$$Register, $temp1$$Register, $temp2$$Register,
12197 $temp3$$Register, $temp4$$Register, $result$$Register,
12198 super_klass_slot);
12199 } else {
12200 __ call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_stub(super_klass_slot)));
12201 }
12202 %}
12203
12204 ins_pipe(pipe_slow);
12205 %}
12206
12207 // ============================================================================
12208 // Branch Instructions -- short offset versions
12209 //
12210 // These instructions are used to replace jumps of a long offset (the default
12211 // match) with jumps of a shorter offset. These instructions are all tagged
12212 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12213 // match rules in general matching. Instead, the ADLC generates a conversion
12214 // method in the MachNode which can be used to do in-place replacement of the
12215 // long variant with the shorter variant. The compiler will determine if a
12216 // branch can be taken by the is_short_branch_offset() predicate in the machine
12217 // specific code section of the file.
12218
12219 // Jump Direct - Label defines a relative address from JMP+1
12220 instruct jmpDir_short(label labl) %{
12221 match(Goto);
12222 effect(USE labl);
12223
12224 ins_cost(300);
12225 format %{ "jmp,s $labl" %}
12226 size(2);
12227 ins_encode %{
12228 Label* L = $labl$$label;
12229 __ jmpb(*L);
12230 %}
12231 ins_pipe(pipe_jmp);
12232 ins_short_branch(1);
12233 %}
12234
12235 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12236 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
12237 match(If cop cr);
12238 effect(USE labl);
12239
12240 ins_cost(300);
12241 format %{ "j$cop,s $labl" %}
12242 size(2);
12243 ins_encode %{
12244 Label* L = $labl$$label;
12245 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12246 %}
12247 ins_pipe(pipe_jcc);
12248 ins_short_branch(1);
12249 %}
12250
12251 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12252 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
12253 match(CountedLoopEnd cop cr);
12254 effect(USE labl);
12255
12256 ins_cost(300);
12257 format %{ "j$cop,s $labl\t# loop end" %}
12258 size(2);
12259 ins_encode %{
12260 Label* L = $labl$$label;
12261 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12262 %}
12263 ins_pipe(pipe_jcc);
12264 ins_short_branch(1);
12265 %}
12266
12267 // Jump Direct Conditional - using unsigned comparison
12268 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12269 match(If cop cmp);
12270 effect(USE labl);
12271
12272 ins_cost(300);
12273 format %{ "j$cop,us $labl" %}
12274 size(2);
12275 ins_encode %{
12276 Label* L = $labl$$label;
12277 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12278 %}
12279 ins_pipe(pipe_jcc);
12280 ins_short_branch(1);
12281 %}
12282
12283 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12284 match(If cop cmp);
12285 effect(USE labl);
12286
12287 ins_cost(300);
12288 format %{ "j$cop,us $labl" %}
12289 size(2);
12290 ins_encode %{
12291 Label* L = $labl$$label;
12292 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12293 %}
12294 ins_pipe(pipe_jcc);
12295 ins_short_branch(1);
12296 %}
12297
12298 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12299 match(If cop cmp);
12300 effect(USE labl);
12301
12302 ins_cost(300);
12303 format %{ $$template
12304 if ($cop$$cmpcode == Assembler::notEqual) {
12305 $$emit$$"jp,u,s $labl\n\t"
12306 $$emit$$"j$cop,u,s $labl"
12307 } else {
12308 $$emit$$"jp,u,s done\n\t"
12309 $$emit$$"j$cop,u,s $labl\n\t"
12310 $$emit$$"done:"
12311 }
12312 %}
12313 size(4);
12314 ins_encode %{
12315 Label* l = $labl$$label;
12316 if ($cop$$cmpcode == Assembler::notEqual) {
12317 __ jccb(Assembler::parity, *l);
12318 __ jccb(Assembler::notEqual, *l);
12319 } else if ($cop$$cmpcode == Assembler::equal) {
12320 Label done;
12321 __ jccb(Assembler::parity, done);
12322 __ jccb(Assembler::equal, *l);
12323 __ bind(done);
12324 } else {
12325 ShouldNotReachHere();
12326 }
12327 %}
12328 ins_pipe(pipe_jcc);
12329 ins_short_branch(1);
12330 %}
12331
12332 // ============================================================================
12333 // inlined locking and unlocking
12334
12335 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{
12336 predicate(LockingMode != LM_LIGHTWEIGHT);
12337 match(Set cr (FastLock object box));
12338 effect(TEMP tmp, TEMP scr, USE_KILL box);
12339 ins_cost(300);
12340 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
12341 ins_encode %{
12342 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12343 $scr$$Register, noreg, noreg, r15_thread, nullptr);
12344 %}
12345 ins_pipe(pipe_slow);
12346 %}
12347
12348 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
12349 predicate(LockingMode != LM_LIGHTWEIGHT);
12350 match(Set cr (FastUnlock object box));
12351 effect(TEMP tmp, USE_KILL box);
12352 ins_cost(300);
12353 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
12354 ins_encode %{
12355 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register);
12356 %}
12357 ins_pipe(pipe_slow);
12358 %}
12359
12360 instruct cmpFastLockLightweight(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI rax_reg, rRegP tmp) %{
12361 predicate(LockingMode == LM_LIGHTWEIGHT);
12362 match(Set cr (FastLock object box));
12363 effect(TEMP rax_reg, TEMP tmp, USE_KILL box);
12364 ins_cost(300);
12365 format %{ "fastlock $object,$box\t! kills $box,$rax_reg,$tmp" %}
12366 ins_encode %{
12367 __ fast_lock_lightweight($object$$Register, $box$$Register, $rax_reg$$Register, $tmp$$Register, r15_thread);
12368 %}
12369 ins_pipe(pipe_slow);
12370 %}
12371
12372 instruct cmpFastUnlockLightweight(rFlagsReg cr, rRegP object, rax_RegP rax_reg, rRegP tmp) %{
12373 predicate(LockingMode == LM_LIGHTWEIGHT);
12374 match(Set cr (FastUnlock object rax_reg));
12375 effect(TEMP tmp, USE_KILL rax_reg);
12376 ins_cost(300);
12377 format %{ "fastunlock $object,$rax_reg\t! kills $rax_reg,$tmp" %}
12378 ins_encode %{
12379 __ fast_unlock_lightweight($object$$Register, $rax_reg$$Register, $tmp$$Register, r15_thread);
12380 %}
12381 ins_pipe(pipe_slow);
12382 %}
12383
12384
12385 // ============================================================================
12386 // Safepoint Instructions
12387 instruct safePoint_poll_tls(rFlagsReg cr, rRegP poll)
12388 %{
12389 match(SafePoint poll);
12390 effect(KILL cr, USE poll);
12391
12392 format %{ "testl rax, [$poll]\t"
12393 "# Safepoint: poll for GC" %}
12394 ins_cost(125);
12395 ins_encode %{
12396 __ relocate(relocInfo::poll_type);
12397 address pre_pc = __ pc();
12398 __ testl(rax, Address($poll$$Register, 0));
12399 assert(nativeInstruction_at(pre_pc)->is_safepoint_poll(), "must emit test %%eax [reg]");
12400 %}
12401 ins_pipe(ialu_reg_mem);
12402 %}
12403
12404 instruct mask_all_evexL(kReg dst, rRegL src) %{
12405 match(Set dst (MaskAll src));
12406 format %{ "mask_all_evexL $dst, $src \t! mask all operation" %}
12407 ins_encode %{
12408 int mask_len = Matcher::vector_length(this);
12409 __ vector_maskall_operation($dst$$KRegister, $src$$Register, mask_len);
12410 %}
12411 ins_pipe( pipe_slow );
12412 %}
12413
12414 instruct mask_all_evexI_GT32(kReg dst, rRegI src, rRegL tmp) %{
12415 predicate(Matcher::vector_length(n) > 32);
12416 match(Set dst (MaskAll src));
12417 effect(TEMP tmp);
12418 format %{ "mask_all_evexI_GT32 $dst, $src \t! using $tmp as TEMP" %}
12419 ins_encode %{
12420 int mask_len = Matcher::vector_length(this);
12421 __ movslq($tmp$$Register, $src$$Register);
12422 __ vector_maskall_operation($dst$$KRegister, $tmp$$Register, mask_len);
12423 %}
12424 ins_pipe( pipe_slow );
12425 %}
12426
12427 // ============================================================================
12428 // Procedure Call/Return Instructions
12429 // Call Java Static Instruction
12430 // Note: If this code changes, the corresponding ret_addr_offset() and
12431 // compute_padding() functions will have to be adjusted.
12432 instruct CallStaticJavaDirect(method meth) %{
12433 match(CallStaticJava);
12434 effect(USE meth);
12435
12436 ins_cost(300);
12437 format %{ "call,static " %}
12438 opcode(0xE8); /* E8 cd */
12439 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
12440 ins_pipe(pipe_slow);
12441 ins_alignment(4);
12442 %}
12443
12444 // Call Java Dynamic Instruction
12445 // Note: If this code changes, the corresponding ret_addr_offset() and
12446 // compute_padding() functions will have to be adjusted.
12447 instruct CallDynamicJavaDirect(method meth)
12448 %{
12449 match(CallDynamicJava);
12450 effect(USE meth);
12451
12452 ins_cost(300);
12453 format %{ "movq rax, #Universe::non_oop_word()\n\t"
12454 "call,dynamic " %}
12455 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
12456 ins_pipe(pipe_slow);
12457 ins_alignment(4);
12458 %}
12459
12460 // Call Runtime Instruction
12461 instruct CallRuntimeDirect(method meth)
12462 %{
12463 match(CallRuntime);
12464 effect(USE meth);
12465
12466 ins_cost(300);
12467 format %{ "call,runtime " %}
12468 ins_encode(clear_avx, Java_To_Runtime(meth));
12469 ins_pipe(pipe_slow);
12470 %}
12471
12472 // Call runtime without safepoint
12473 instruct CallLeafDirect(method meth)
12474 %{
12475 match(CallLeaf);
12476 effect(USE meth);
12477
12478 ins_cost(300);
12479 format %{ "call_leaf,runtime " %}
12480 ins_encode(clear_avx, Java_To_Runtime(meth));
12481 ins_pipe(pipe_slow);
12482 %}
12483
12484 // Call runtime without safepoint and with vector arguments
12485 instruct CallLeafDirectVector(method meth)
12486 %{
12487 match(CallLeafVector);
12488 effect(USE meth);
12489
12490 ins_cost(300);
12491 format %{ "call_leaf,vector " %}
12492 ins_encode(Java_To_Runtime(meth));
12493 ins_pipe(pipe_slow);
12494 %}
12495
12496 // Call runtime without safepoint
12497 instruct CallLeafNoFPDirect(method meth)
12498 %{
12499 match(CallLeafNoFP);
12500 effect(USE meth);
12501
12502 ins_cost(300);
12503 format %{ "call_leaf_nofp,runtime " %}
12504 ins_encode(clear_avx, Java_To_Runtime(meth));
12505 ins_pipe(pipe_slow);
12506 %}
12507
12508 // Return Instruction
12509 // Remove the return address & jump to it.
12510 // Notice: We always emit a nop after a ret to make sure there is room
12511 // for safepoint patching
12512 instruct Ret()
12513 %{
12514 match(Return);
12515
12516 format %{ "ret" %}
12517 ins_encode %{
12518 __ ret(0);
12519 %}
12520 ins_pipe(pipe_jmp);
12521 %}
12522
12523 // Tail Call; Jump from runtime stub to Java code.
12524 // Also known as an 'interprocedural jump'.
12525 // Target of jump will eventually return to caller.
12526 // TailJump below removes the return address.
12527 // Don't use rbp for 'jump_target' because a MachEpilogNode has already been
12528 // emitted just above the TailCall which has reset rbp to the caller state.
12529 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_ptr)
12530 %{
12531 match(TailCall jump_target method_ptr);
12532
12533 ins_cost(300);
12534 format %{ "jmp $jump_target\t# rbx holds method" %}
12535 ins_encode %{
12536 __ jmp($jump_target$$Register);
12537 %}
12538 ins_pipe(pipe_jmp);
12539 %}
12540
12541 // Tail Jump; remove the return address; jump to target.
12542 // TailCall above leaves the return address around.
12543 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
12544 %{
12545 match(TailJump jump_target ex_oop);
12546
12547 ins_cost(300);
12548 format %{ "popq rdx\t# pop return address\n\t"
12549 "jmp $jump_target" %}
12550 ins_encode %{
12551 __ popq(as_Register(RDX_enc));
12552 __ jmp($jump_target$$Register);
12553 %}
12554 ins_pipe(pipe_jmp);
12555 %}
12556
12557 // Forward exception.
12558 instruct ForwardExceptionjmp()
12559 %{
12560 match(ForwardException);
12561
12562 format %{ "jmp forward_exception_stub" %}
12563 ins_encode %{
12564 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()), noreg);
12565 %}
12566 ins_pipe(pipe_jmp);
12567 %}
12568
12569 // Create exception oop: created by stack-crawling runtime code.
12570 // Created exception is now available to this handler, and is setup
12571 // just prior to jumping to this handler. No code emitted.
12572 instruct CreateException(rax_RegP ex_oop)
12573 %{
12574 match(Set ex_oop (CreateEx));
12575
12576 size(0);
12577 // use the following format syntax
12578 format %{ "# exception oop is in rax; no code emitted" %}
12579 ins_encode();
12580 ins_pipe(empty);
12581 %}
12582
12583 // Rethrow exception:
12584 // The exception oop will come in the first argument position.
12585 // Then JUMP (not call) to the rethrow stub code.
12586 instruct RethrowException()
12587 %{
12588 match(Rethrow);
12589
12590 // use the following format syntax
12591 format %{ "jmp rethrow_stub" %}
12592 ins_encode %{
12593 __ jump(RuntimeAddress(OptoRuntime::rethrow_stub()), noreg);
12594 %}
12595 ins_pipe(pipe_jmp);
12596 %}
12597
12598 // ============================================================================
12599 // This name is KNOWN by the ADLC and cannot be changed.
12600 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
12601 // for this guy.
12602 instruct tlsLoadP(r15_RegP dst) %{
12603 match(Set dst (ThreadLocal));
12604 effect(DEF dst);
12605
12606 size(0);
12607 format %{ "# TLS is in R15" %}
12608 ins_encode( /*empty encoding*/ );
12609 ins_pipe(ialu_reg_reg);
12610 %}
12611
12612
12613 //----------PEEPHOLE RULES-----------------------------------------------------
12614 // These must follow all instruction definitions as they use the names
12615 // defined in the instructions definitions.
12616 //
12617 // peeppredicate ( rule_predicate );
12618 // // the predicate unless which the peephole rule will be ignored
12619 //
12620 // peepmatch ( root_instr_name [preceding_instruction]* );
12621 //
12622 // peepprocedure ( procedure_name );
12623 // // provide a procedure name to perform the optimization, the procedure should
12624 // // reside in the architecture dependent peephole file, the method has the
12625 // // signature of MachNode* (Block*, int, PhaseRegAlloc*, (MachNode*)(*)(), int...)
12626 // // with the arguments being the basic block, the current node index inside the
12627 // // block, the register allocator, the functions upon invoked return a new node
12628 // // defined in peepreplace, and the rules of the nodes appearing in the
12629 // // corresponding peepmatch, the function return true if successful, else
12630 // // return false
12631 //
12632 // peepconstraint %{
12633 // (instruction_number.operand_name relational_op instruction_number.operand_name
12634 // [, ...] );
12635 // // instruction numbers are zero-based using left to right order in peepmatch
12636 //
12637 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12638 // // provide an instruction_number.operand_name for each operand that appears
12639 // // in the replacement instruction's match rule
12640 //
12641 // ---------VM FLAGS---------------------------------------------------------
12642 //
12643 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12644 //
12645 // Each peephole rule is given an identifying number starting with zero and
12646 // increasing by one in the order seen by the parser. An individual peephole
12647 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12648 // on the command-line.
12649 //
12650 // ---------CURRENT LIMITATIONS----------------------------------------------
12651 //
12652 // Only transformations inside a basic block (do we need more for peephole)
12653 //
12654 // ---------EXAMPLE----------------------------------------------------------
12655 //
12656 // // pertinent parts of existing instructions in architecture description
12657 // instruct movI(rRegI dst, rRegI src)
12658 // %{
12659 // match(Set dst (CopyI src));
12660 // %}
12661 //
12662 // instruct incI_rReg(rRegI dst, immI_1 src, rFlagsReg cr)
12663 // %{
12664 // match(Set dst (AddI dst src));
12665 // effect(KILL cr);
12666 // %}
12667 //
12668 // instruct leaI_rReg_immI(rRegI dst, immI_1 src)
12669 // %{
12670 // match(Set dst (AddI dst src));
12671 // %}
12672 //
12673 // 1. Simple replacement
12674 // - Only match adjacent instructions in same basic block
12675 // - Only equality constraints
12676 // - Only constraints between operands, not (0.dest_reg == RAX_enc)
12677 // - Only one replacement instruction
12678 //
12679 // // Change (inc mov) to lea
12680 // peephole %{
12681 // // lea should only be emitted when beneficial
12682 // peeppredicate( VM_Version::supports_fast_2op_lea() );
12683 // // increment preceded by register-register move
12684 // peepmatch ( incI_rReg movI );
12685 // // require that the destination register of the increment
12686 // // match the destination register of the move
12687 // peepconstraint ( 0.dst == 1.dst );
12688 // // construct a replacement instruction that sets
12689 // // the destination to ( move's source register + one )
12690 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
12691 // %}
12692 //
12693 // 2. Procedural replacement
12694 // - More flexible finding relevent nodes
12695 // - More flexible constraints
12696 // - More flexible transformations
12697 // - May utilise architecture-dependent API more effectively
12698 // - Currently only one replacement instruction due to adlc parsing capabilities
12699 //
12700 // // Change (inc mov) to lea
12701 // peephole %{
12702 // // lea should only be emitted when beneficial
12703 // peeppredicate( VM_Version::supports_fast_2op_lea() );
12704 // // the rule numbers of these nodes inside are passed into the function below
12705 // peepmatch ( incI_rReg movI );
12706 // // the method that takes the responsibility of transformation
12707 // peepprocedure ( inc_mov_to_lea );
12708 // // the replacement is a leaI_rReg_immI, a lambda upon invoked creating this
12709 // // node is passed into the function above
12710 // peepreplace ( leaI_rReg_immI() );
12711 // %}
12712
12713 // These instructions is not matched by the matcher but used by the peephole
12714 instruct leaI_rReg_rReg_peep(rRegI dst, rRegI src1, rRegI src2)
12715 %{
12716 predicate(false);
12717 match(Set dst (AddI src1 src2));
12718 format %{ "leal $dst, [$src1 + $src2]" %}
12719 ins_encode %{
12720 Register dst = $dst$$Register;
12721 Register src1 = $src1$$Register;
12722 Register src2 = $src2$$Register;
12723 if (src1 != rbp && src1 != r13) {
12724 __ leal(dst, Address(src1, src2, Address::times_1));
12725 } else {
12726 assert(src2 != rbp && src2 != r13, "");
12727 __ leal(dst, Address(src2, src1, Address::times_1));
12728 }
12729 %}
12730 ins_pipe(ialu_reg_reg);
12731 %}
12732
12733 instruct leaI_rReg_immI_peep(rRegI dst, rRegI src1, immI src2)
12734 %{
12735 predicate(false);
12736 match(Set dst (AddI src1 src2));
12737 format %{ "leal $dst, [$src1 + $src2]" %}
12738 ins_encode %{
12739 __ leal($dst$$Register, Address($src1$$Register, $src2$$constant));
12740 %}
12741 ins_pipe(ialu_reg_reg);
12742 %}
12743
12744 instruct leaI_rReg_immI2_peep(rRegI dst, rRegI src, immI2 shift)
12745 %{
12746 predicate(false);
12747 match(Set dst (LShiftI src shift));
12748 format %{ "leal $dst, [$src << $shift]" %}
12749 ins_encode %{
12750 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($shift$$constant);
12751 Register src = $src$$Register;
12752 if (scale == Address::times_2 && src != rbp && src != r13) {
12753 __ leal($dst$$Register, Address(src, src, Address::times_1));
12754 } else {
12755 __ leal($dst$$Register, Address(noreg, src, scale));
12756 }
12757 %}
12758 ins_pipe(ialu_reg_reg);
12759 %}
12760
12761 instruct leaL_rReg_rReg_peep(rRegL dst, rRegL src1, rRegL src2)
12762 %{
12763 predicate(false);
12764 match(Set dst (AddL src1 src2));
12765 format %{ "leaq $dst, [$src1 + $src2]" %}
12766 ins_encode %{
12767 Register dst = $dst$$Register;
12768 Register src1 = $src1$$Register;
12769 Register src2 = $src2$$Register;
12770 if (src1 != rbp && src1 != r13) {
12771 __ leaq(dst, Address(src1, src2, Address::times_1));
12772 } else {
12773 assert(src2 != rbp && src2 != r13, "");
12774 __ leaq(dst, Address(src2, src1, Address::times_1));
12775 }
12776 %}
12777 ins_pipe(ialu_reg_reg);
12778 %}
12779
12780 instruct leaL_rReg_immL32_peep(rRegL dst, rRegL src1, immL32 src2)
12781 %{
12782 predicate(false);
12783 match(Set dst (AddL src1 src2));
12784 format %{ "leaq $dst, [$src1 + $src2]" %}
12785 ins_encode %{
12786 __ leaq($dst$$Register, Address($src1$$Register, $src2$$constant));
12787 %}
12788 ins_pipe(ialu_reg_reg);
12789 %}
12790
12791 instruct leaL_rReg_immI2_peep(rRegL dst, rRegL src, immI2 shift)
12792 %{
12793 predicate(false);
12794 match(Set dst (LShiftL src shift));
12795 format %{ "leaq $dst, [$src << $shift]" %}
12796 ins_encode %{
12797 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($shift$$constant);
12798 Register src = $src$$Register;
12799 if (scale == Address::times_2 && src != rbp && src != r13) {
12800 __ leaq($dst$$Register, Address(src, src, Address::times_1));
12801 } else {
12802 __ leaq($dst$$Register, Address(noreg, src, scale));
12803 }
12804 %}
12805 ins_pipe(ialu_reg_reg);
12806 %}
12807
12808 // These peephole rules replace mov + I pairs (where I is one of {add, inc, dec,
12809 // sal}) with lea instructions. The {add, sal} rules are beneficial in
12810 // processors with at least partial ALU support for lea
12811 // (supports_fast_2op_lea()), whereas the {inc, dec} rules are only generally
12812 // beneficial for processors with full ALU support
12813 // (VM_Version::supports_fast_3op_lea()) and Intel Cascade Lake.
12814
12815 peephole
12816 %{
12817 peeppredicate(VM_Version::supports_fast_2op_lea());
12818 peepmatch (addI_rReg);
12819 peepprocedure (lea_coalesce_reg);
12820 peepreplace (leaI_rReg_rReg_peep());
12821 %}
12822
12823 peephole
12824 %{
12825 peeppredicate(VM_Version::supports_fast_2op_lea());
12826 peepmatch (addI_rReg_imm);
12827 peepprocedure (lea_coalesce_imm);
12828 peepreplace (leaI_rReg_immI_peep());
12829 %}
12830
12831 peephole
12832 %{
12833 peeppredicate(VM_Version::supports_fast_3op_lea() ||
12834 VM_Version::is_intel_cascade_lake());
12835 peepmatch (incI_rReg);
12836 peepprocedure (lea_coalesce_imm);
12837 peepreplace (leaI_rReg_immI_peep());
12838 %}
12839
12840 peephole
12841 %{
12842 peeppredicate(VM_Version::supports_fast_3op_lea() ||
12843 VM_Version::is_intel_cascade_lake());
12844 peepmatch (decI_rReg);
12845 peepprocedure (lea_coalesce_imm);
12846 peepreplace (leaI_rReg_immI_peep());
12847 %}
12848
12849 peephole
12850 %{
12851 peeppredicate(VM_Version::supports_fast_2op_lea());
12852 peepmatch (salI_rReg_immI2);
12853 peepprocedure (lea_coalesce_imm);
12854 peepreplace (leaI_rReg_immI2_peep());
12855 %}
12856
12857 peephole
12858 %{
12859 peeppredicate(VM_Version::supports_fast_2op_lea());
12860 peepmatch (addL_rReg);
12861 peepprocedure (lea_coalesce_reg);
12862 peepreplace (leaL_rReg_rReg_peep());
12863 %}
12864
12865 peephole
12866 %{
12867 peeppredicate(VM_Version::supports_fast_2op_lea());
12868 peepmatch (addL_rReg_imm);
12869 peepprocedure (lea_coalesce_imm);
12870 peepreplace (leaL_rReg_immL32_peep());
12871 %}
12872
12873 peephole
12874 %{
12875 peeppredicate(VM_Version::supports_fast_3op_lea() ||
12876 VM_Version::is_intel_cascade_lake());
12877 peepmatch (incL_rReg);
12878 peepprocedure (lea_coalesce_imm);
12879 peepreplace (leaL_rReg_immL32_peep());
12880 %}
12881
12882 peephole
12883 %{
12884 peeppredicate(VM_Version::supports_fast_3op_lea() ||
12885 VM_Version::is_intel_cascade_lake());
12886 peepmatch (decL_rReg);
12887 peepprocedure (lea_coalesce_imm);
12888 peepreplace (leaL_rReg_immL32_peep());
12889 %}
12890
12891 peephole
12892 %{
12893 peeppredicate(VM_Version::supports_fast_2op_lea());
12894 peepmatch (salL_rReg_immI2);
12895 peepprocedure (lea_coalesce_imm);
12896 peepreplace (leaL_rReg_immI2_peep());
12897 %}
12898
12899 // These peephole rules matches instructions which set flags and are followed by a testI/L_reg
12900 // The test instruction is redudanent in case the downstream instuctions (like JCC or CMOV) only use flags that are already set by the previous instruction
12901
12902 //int variant
12903 peephole
12904 %{
12905 peepmatch (testI_reg);
12906 peepprocedure (test_may_remove);
12907 %}
12908
12909 //long variant
12910 peephole
12911 %{
12912 peepmatch (testL_reg);
12913 peepprocedure (test_may_remove);
12914 %}
12915
12916
12917 //----------SMARTSPILL RULES---------------------------------------------------
12918 // These must follow all instruction definitions as they use the names
12919 // defined in the instructions definitions.